# Patent

## Title
Electronic ballast having a partially self-oscillating inverter circuit

## Abstract

An electronic ballast for driving a gas discharge lamp comprises an inverter circuit that operates in a partially self-oscillating manner. The inverter circuit comprises a push-pull converter having a main transformer having a primary winding for producing a high-frequency AC voltage, semiconductor switches electrically coupled to the primary winding of the main transformer for conducting current through the primary winding on an alternate basis, and gate drive circuits for controlling the semiconductor switches on a cycle-by-cycle basis. The drive circuits control (e.g., turn on) the semiconductor switches in response to first control signals derived from the main transformer, and control (e.g., turn off) the semiconductor switches in response to second control signals received from a control circuit. The control circuit controls the semiconductor switches in response to a peak value of an integral of an inverter current flowing through the inverter circuit.

## Background
CROSS REFERENCE TO RELATED APPLICATION
This application is a continuation of U.S. patent application Ser. No. 12/205,339, filed Sep. 5, 2008, by Robert C. Newman, Jr. and Mark S. Taipale entitled ELECTRONIC BALLAST HAVING A PARTIALLY SELF-OSCILLATING INVERTER CIRCUIT the entire contents of which is hereby incorporated by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic ballasts for gas discharge lamps, such as fluorescent lamps. More specifically, the present invention relates to a two-wire electronic dimming ballast for powering and controlling the intensity of a fluorescent lamp in response to a phase-controlled voltage.
2. Description of the Related Art
The use of gas discharge lamps, such as fluorescent lamps, as replacements for conventional incandescent lamps, has increased greatly over the last several years. Fluorescent lamps typically are more efficient and provide a longer operational life when compared to incandescent lamps. In certain areas, such as California, for example, state law requires certain areas of new construction to be outfitted for the use of fluorescent lamps exclusively.
A gas discharge lamp must be driven by a ballast in order to illuminate properly. The ballast receives an alternating-current (AC) voltage from an AC power source and generates an appropriate high-frequency current for driving the fluorescent lamp. Dimming ballasts, which can control the intensity of a connected fluorescent lamp, typically have at least three connections: to a switched-hot voltage from the AC power source, to a neutral side of the AC power source, and to a desired-intensity control signal, such as a phase-controlled voltage from a standard three-wire dimming circuit. Some electronic dimming ballasts, such as a fluorescent TuWire® dimmer circuit manufactured by Lutron Electronics Co., Inc., only require two connections, e.g., to the phase-controlled voltage from the dimmer circuit and to the neutral side of the AC power source.
Most prior art ballast circuits have typically been designed and intended for use in commercial applications. This has caused most prior art ballasts to be rather expensive and fairly difficult to install and service, and thus not suitable for residential installations. Thus, there is a need for a small, low-cost two-wire electronic dimming ballast, which can be used by the energy-conscious consumer in combination with a fluorescent lamp as a replacement for an incandescent lamp.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, an electronic ballast for driving a gas discharge lamp comprises a bus capacitor for producing a substantially DC bus voltage, an inverter circuit for converting the DC bus voltage to a high-frequency AC voltage for driving the lamp, and a control circuit. The inverter circuit comprises a main transformer having a primary winding for producing the high-frequency AC voltage, first and second semiconductor switches electrically coupled to the primary winding of the main transformer for conducting current through the primary winding on an alternate basis, and first and second drive circuits for controlling the first and second semiconductor switches, respectively, on a cycle-by-cycle basis. The control circuit is coupled to the first and second drive circuits of the inverter circuit for controlling the first and second semiconductor switches. The first and second drive circuits control the respective first and second semiconductor switches in response to first control signals derived from the main transformer and second control signals received from the control circuit.
A multi-switch power converter for an electronic ballast is also described herein. The power converter comprises a main transformer having a primary winding for producing an oscillating output voltage, and first and second semiconductor switches electrically coupled to the primary winding of the main transformer for conducting current through the primary winding on an alternate basis. The power converter further comprises a first drive circuit operable to control the first semiconductor switch on a cycle-by-cycle basis in response to a first control signal derived from the main transformer and a second control signal received from an external control circuit. Additionally, the first drive circuit may control the first semiconductor switch, and the power converter further may further comprise a second drive circuit for controlling the second semiconductor switch on a cycle-by-cycle basis in response to a third control signal derived from the main transformer and a fourth control signal received from the external control circuit.
According to another embodiment of the present invention, a multi-switch power converter comprises (1) a main transformer having a primary winding for producing an oscillating output voltage; (2) first and second semiconductor switches electrically coupled to the primary winding of the main transformer for conducting current through the primary winding on an alternate basis; and (3) first and second drive circuits for controlling the first and second semiconductor switches, respectively, on a cycle-by-cycle basis in response to first control signals derived from the main transformer and second control signals received from an external control circuit.
A method of driving a gas discharge lamp from an electronic ballast having an inverter circuit and a control circuit is also disclosed. The inverter circuit comprises a main transformer having a primary winding coupled across an output of the inverter circuit, first and second semiconductor switches electrically coupled to the primary winding of the main transformer, and first and second drive circuits coupled to the first and second semiconductor switches, respectively. The method comprises the steps of: (1) producing a high-frequency AC voltage across the primary winding of the main transformer; (2) deriving first control signals from the main transformer; (3) receiving second control signals from the control circuit; and (4) controlling the first and second semiconductor switches on a cycle-by-cycle basis to conduct current through the primary winding on an alternate basis in response to the first and second control signals.
In addition, an inverter circuit, which comprises a bus capacitor, a transformer, first and second controller switches and a control circuit, is described herein. The transformer has a primary winding comprising first and second winding portions connected at a center tap and having first and second terminals. The bus capacitor is connected across a DC bus voltage between the center tap and a common point. The first switch is coupled between the common point and the first terminal of the primary winding, while the second switch is coupled between the common point and the second terminal of the primary winding. The control circuit controls the conduction state of the first and second switches, such that a current flows from the bus capacitor alternately through the first and second winding portions thereby generating a substantially square-wave voltage having a magnitude approximately twice the DC bus voltage across the primary winding. The control circuit comprises first and second drive circuits, one for each switch, coupled to control inputs of the first and second switches, respectively. The first and second drive circuits receive respective first and second control signals. The transformer has first and second magnetically-coupled drive windings, one for each switch, which current into the first and second drive circuits, respectively, to alternately turn on the first and second switches. Additionally, the first and second control signals render the first and second switches non conductive prior to the currents from the first and second drive windings rendering the first and second switches, respectively, conductive.
According to another embodiment of the present invention, an electronic ballast for driving a gas discharge lamp comprises a bus capacitor for producing a substantially DC bus voltage, an inverter circuit for converting the DC bus voltage to a high-frequency AC voltage for driving the lamp, a lamp current measurement circuit operable to generate a lamp current control signal representative of the magnitude of a lamp current flowing through the lamp, and a control circuit operable to receive the lamp current control signal and to control the inverter circuit in response to the magnitude of the lamp current. The inverter circuit comprises a main transformer having a primary winding for producing the high-frequency AC voltage, first and second semiconductor switches electrically coupled to the primary winding of the main transformer for conducting current through the primary winding on an alternate basis, and first and second drive circuits controlling the first and second semiconductor switches, respectively, on a cycle-by-cycle basis. The control circuit is coupled to the first and second drive circuits of the inverter circuit for controlling the first and second semiconductor switches in response to the magnitude of the lamp current. The first and second drive circuits control the first and second semiconductor switches, respectively, in response to a first control signal derived from the main transformer and a second control signal received from the control circuit.
According to another aspect of the present invention, a switching power converter generates a high-frequency AC voltage from a substantially DC bus voltage produced across a bus capacitor. The switching power converter comprises a semiconductor switch adapted to conduct a converter current through the bus capacitor, and a control circuit operable to scale the converter current to produce a scaled current, integrate the scaled current to generate an integral control signal representative of the scaled current, compare the integral control signal to a threshold voltage, and render the semiconductor switch non conductive in response to the integral control signal reaching the threshold voltage.
A method of controlling a switching power converter for an electronic ballast is also described herein. The power converter has an energy storage capacitor and at least one semiconductor switch for conducting a converter current. The method comprises the steps of: (1) scaling the converter current to produce a scaled current; (2) integrating the scaled current to generate an integral control signal representative of the scaled current; (3) comparing the integral control signal to a threshold voltage; and (4) rendering the semiconductor switch non-conductive in response to the integral control signal reaching the threshold voltage.
According to another embodiment of the present invention, an electronic ballast for driving a gas discharge lamp comprises: (1) a bus capacitor for producing a substantially DC bus voltage; (2) an inverter circuit for converting the DC bus voltage to a high-frequency AC voltage for driving the lamp, the inverter circuit comprising a semiconductor switch adapted to conduct a converter current; and (3) a control circuit operable to scale the converter current to produce a scaled current, integrate the scaled current to generate an integral control signal representative of the scaled current, compare the integral control signal to a threshold voltage, and render the semiconductor switch non-conductive in response to the integral control signal reaching the threshold voltage.
According to yet another embodiment of the present invention, an inverter circuit for an electronic ballast comprises a transformer having a primary winding comprising first and second winding portions connected at a center tap and having first and second terminals, a bus capacitor connected across a DC bus voltage between the center tap and a common point, first and second controlled switches, and a control circuit for controlling the conduction state of the first and second switches. The first switch is coupled between the common point and the first terminal of the primary winding, while the second switch is coupled between the common point and the second terminal of the primary winding. The control circuit provides first and second control signals to control inputs of the respective switches, whereby the first and second switches are alternately rendered conductive to generate a substantially square wave voltage having a magnitude approximately twice the DC bus voltage across the primary winding. The control circuit scales the current drawn through the first and second switches to produce a scaled current signal, integrates the scaled current signal to produce an integrated signal, and renders the switches non conductive in response to the integrated signal reaching a threshold voltage.
According to another embodiment of the present invention, an electronic ballast for driving a gas discharge lamp comprises a bus capacitor connected across a DC bus voltage, an inverter circuit for receiving the DC bus voltage and for generating a substantially square-wave voltage having a magnitude approximately twice the DC bus voltage, and a resonant tank circuit for receiving the square-wave voltage and generating a sinusoidal voltage for driving the lamp. The inverter circuit comprises a transformer having a primary winding comprising first and second winding portions connected at a center tap and having first and second terminals. The bus capacitor is connected between the center tap and a common point. The inverter circuit further comprises first and second switches coupled between the common point and the respective first and second terminals of the primary winding, and a control circuit for controlling the conduction state of the first and second switches. The control circuit provides first and second control signals to control inputs of the respective switches, whereby the first and second switches are alternately rendered conductive to generate a substantially square wave voltage having a magnitude approximately twice the DC bus voltage across the primary winding. The control circuit scales the current drawn through the first and second switches to produce a scaled current signal, integrates the scaled current signal to produce an integrated signal, and renders the switches non conductive in response to the integrated signal reaching a threshold voltage.
Other features and advantages of the present invention will become apparent from the following description of the invention that refers to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified block diagram of a system including an electronic dimming ballast for driving a fluorescent lamp according to a first embodiment of the present invention;
FIG. 2 is a simplified block diagram showing the electronic dimming ballast of FIG. 1 in greater detail;
FIG. 3 is a simplified schematic diagram showing a bus capacitor, a sense resistor, an inverter circuit, and a resonant tank of the electronic dimming ballast of FIG. 2 in greater detail;
FIG. 4 is a simplified schematic diagram showing a current transformer of the resonant tank of FIG. 3 in greater detail;
FIG. 5 is a simplified schematic diagram showing in greater detail a push/pull converter, which includes the inverter circuit, the bus capacitor, and the sense resistor of FIG. 3;
FIG. 6 is a simplified diagram of waveforms showing the operation of the push/pull converter and the control circuit of the ballast of FIG. 2 during normal operation;
FIG. 7 is a simplified schematic diagram of a measurement circuit of the ballast of FIG. 2 for measuring a lamp voltage and a lamp current of the fluorescent lamp;
FIG. 8 is a simplified diagram showing the lamp voltage, a real component of the lamp current, and a reactive component of the lamp current of the fluorescent lamp;
FIG. 9 is a simplified block diagram of a control circuit of the ballast of FIG. 2;
FIGS. 10A and 10B are simplified schematic diagrams of the control circuit of FIG. 9;
FIG. 11 is a simplified flowchart of a target lamp current procedure executed periodically by a microcontroller of the control circuit of FIG. 9;
FIG. 12 is a simplified flowchart of a startup procedure executed by the microcontroller of the control circuit of FIG. 9;
FIG. 13 is a simplified block diagram of an electronic dimming ballast according to a second embodiment of the present invention;
FIG. 14 is a simplified schematic diagram showing a charge pump, an inverter circuit, and a resonant tank circuit of the ballast of FIG. 13 in greater detail; and
FIG. 15 is a simplified schematic diagram of a lamp current measurement circuit of the measurement circuit of FIG. 7 according to a third embodiment of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
The foregoing summary, as well as the following detailed description of the preferred embodiments, is better understood when read in conjunction with the appended drawings. For the purposes of illustrating the invention, there is shown in the drawings an embodiment that is presently preferred, in which like numerals represent similar parts throughout the several views of the drawings, it being understood, however, that the invention is not limited to the specific methods and instrumentalities disclosed.
FIG. 1 is a simplified block diagram of a system including an electronic dimming ballast 100 for driving a fluorescent lamp 102 according to a first embodiment of the present invention. The ballast 100 is coupled to the hot side of an alternating-current (AC) power source 104 (e.g., 120 VAC, 60 Hz) through a conventional two-wire dimmer switch 106. The dimmer switch 106 typically includes a bidirectional semiconductor switch (not shown), such as, for example, a triac or two field-effect transistors (FETs) coupled in anti-series connection, for providing a phase-controlled voltage VPC (i.e., a dimmed-hot voltage) to the ballast 100. Using a standard forward phase-control dimming technique, the bidirectional semiconductor switch is rendered conductive at a specific time each half-cycle of the AC power source and remains conductive for a conduction period TCON during each half-cycle. The dimmer switch 106 is operable to control the amount of power delivered to the ballast 100 by controlling the length of the conduction period TCON.
The ballast 100 of FIG. 1 only requires two connections: to the phase-controlled voltage VPC from the dimmer switch 106 and to the neutral side of the AC power source 104. The ballast 100 is operable to control the lamp 102 on and off and to adjust the intensity of the lamp from a low-end (i.e., a minimum intensity) to a high-end (i.e., a maximum intensity) in response to the conduction period TCON of the phase-controlled voltage VPC.
FIG. 2 is a simplified block diagram showing the electronic dimming ballast 100 in greater detail. The electronic ballast 100 comprises a “front-end” circuit 120 and a “back-end” circuit 130. The front-end circuit 120 includes a radio-frequency interference (RFI) filter 122 for minimizing the noise provided on the AC mains and a full-wave rectifier 124 for receiving the phase-controlled voltage VPC and generating a rectified voltage VRECT. The rectified voltage VRECT is coupled to a bus capacitor CBUS through a diode D126 for producing a substantially DC bus voltage VBUS across the bus capacitor CBUS. The negative terminal of the bus capacitor CBUS is coupled to a rectifier DC common connection (as shown in FIG. 2).
The ballast back-end circuit 130 includes a power converter, e.g., an inverter circuit 140, for converting the DC bus voltage VBUS to a high-frequency square-wave voltage VSQ. The high-frequency square-wave VSQ (i.e., a high-frequency AC voltage) is characterized by an operating frequency fOP (and an operating period TOP=1/fOP). The ballast back-end circuit 130 further comprises an output circuit, e.g., a “symmetric” resonant tank circuit 150, for filtering the square-wave voltage VSQ to produce a substantially sinusoidal high-frequency AC voltage VSIN, which is coupled to the electrodes of the lamp 102. The inverter circuit 140 is coupled to the negative input of the DC bus capacitor CBUS via a sense resistor RSENSE. A sense voltage VSENSE (which is referenced to a circuit common connection as shown in FIG. 2) is produced across the sense resistor RSENSE in response to an inverter current IINV generated through bus capacitor CBUS during the operation of the inverter circuit 140. The sense resistor RSENSE is coupled between the rectifier DC common connection and the circuit common connection and has, for example, a resistance of 1Ω.
The ballast 100 further comprises a control circuit 160, which controls the operation of the inverter circuit 140 and thus the intensity of the lamp 102. A power supply 162 generates a DC supply voltage VCC (e.g., 5 VDC) for powering the control circuit 160 and other low-voltage circuitry of the ballast 100.
The control circuit 160 is operable to determine a desired lighting intensity for the lamp 102 (specifically, a target lamp current ITARGET) in response to a zero-crossing detect circuit 164. The zero-crossing detect circuit 164 provides a zero-crossing control signal VZC representative of the zero-crossings of the phase-controlled voltage VPC to the control circuit 160. A zero-crossing is defined as the time at which the phase-controlled voltage VPC changes from having a magnitude of substantially zero volts to having a magnitude greater than a predetermined zero-crossing threshold VTH-ZC (and vice versa) each half-cycle. Specifically, the zero-crossing detect circuit 164 compares the magnitude of the rectified voltage to the predetermined zero-crossing threshold VTH-ZC (e.g., approximately 20 V), and drives the zero-crossing control signal VZC high (i.e., to a logic high level, such as, approximately the DC supply voltage VCC) when the magnitude of the rectified voltage VRECT is less than the predetermined zero-crossing threshold VTH-ZC. Further, the zero-crossing detect circuit 164 drives the zero-crossing control signal VZC low (i.e., to a logic low level, such as, approximately circuit common) when the magnitude of the rectified voltage VRECT is greater than the predetermined zero-crossing threshold VTH-ZC.
The control circuit 160 is operable to determine the target lamp current ITARGET of the lamp 102 in response to the conduction period TCON of the phase-controlled voltage VPC. The control circuit 160 is operable to control the peak value of the integral of the inverter current IINV flowing in the inverter circuit 140 to indirectly control the operating frequency fOP of the high-frequency square-wave voltage VSQ, and to thus control the intensity of the lamp 102 to the desired lighting intensity.
The ballast 100 further comprises a measurement circuit 170, which provides a lamp voltage control signal VLAMP—VLT and a lamp current control signal VLAMP—CUR to the control circuit 160. The measurement circuit 170 is responsive to the inverter circuit 140 and the resonant tank circuit 150, such that the lamp voltage control signal VLAMP—VLT is representative of the magnitude of a lamp voltage VLAMP measured across the electrodes of the lamp 102, while the lamp current control signal VLAMP—CUR is representative of the magnitude of a lamp current ILAMP flowing through the lamp.
The control circuit 160 is operable to control the operation of the inverter circuit 140 in response to the sense voltage VSENSE produced across the sense resistor RSENSE, the zero-crossing control signal VZC from the zero-crossing detect circuit 164, the lamp voltage control signal VLAMP—VLT, and the lamp current control signal VLAMP—CUR. Specifically, the control circuit 160 controls the operation of the inverter circuit 140, in order to control the lamp current ILAMP towards the target lamp current ITARGET.
FIG. 3 is a simplified schematic diagram showing the inverter circuit 140 and the resonant tank circuit 150 in greater detail. As shown in FIG. 3, the inverter circuit 140, the bus capacitor CBUS, and the sense resistor RSENSE form a push/pull converter. However, the present invention is not limited to electronic dimming ballasts having only push/pull converters. The inverter circuit 140 comprises a main transformer 210 having a center-tapped primary winding that is coupled across an output of the inverter circuit 140. The high-frequency square-wave voltage VSQ of the inverter circuit 140 is generated across the primary winding of the main transformer 210. The center tap of the primary winding of the main transformer 210 is coupled to the DC bus voltage VBUS.
The inverter circuit 140 further comprises first and second semiconductor switches, e.g., field-effect transistors (FETs) Q220, Q230, which are coupled between the terminal ends of the primary winding of the main transformer 210 and circuit common. The FETs Q220, Q230 have control inputs (i.e., gates), which are coupled to first and second gate drive circuits 222, 232, respectively, for rendering the FETs conductive and non-conductive. The gate drive circuits 222, 232 receive first and second FET drive signals VDRV—FET1 and VDRV—FET2 from the control circuit 160, respectively. The gate drive circuits 222, 232 are also electrically coupled to respective drive windings 224, 234 that are magnetically coupled to the primary winding of the main transformer 210.
The push/pull converter of the ballast 100 exhibits a partially self-oscillating behavior since the gate drive circuits 222, 232 are operable to control the operation of the FETs Q220, Q230 in response to control signals received from both the control circuit 160 and the main transformer 210. Specifically, the gate drive circuits 222, 232 are operable to turn on (i.e., render conductive) the FETs Q220, Q230 in response to the control signals from the drive windings 224, 234 of the main transformer 210, and to turn off (i.e., render non-conductive) the FETs in response to the control signals (i.e., the first and second FET drive signals VDRV—FET1 and VDRV—FET2) from the control circuit 160. The FETs Q220, Q230 may be rendered conductive on an alternate basis, i.e., such that the first FET Q220 is not conductive when the second FET Q230 is conductive, and vice versa.
When the first FET Q220 is conductive, the terminal end of the primary winding connected to the first FET Q220 is electrically coupled to circuit common. Accordingly, the DC bus voltage VBUS is provided across one-half of the primary winding of the main transformer 210, such that the high-frequency square-wave voltage VSQ at the output of the inverter circuit 140 (i.e., across the primary winding of the main transformer 210) has a magnitude of approximately twice the bus voltage (i.e., 2·VBUS) with a positive voltage potential present from node B to node A as shown on FIG. 3. When the second FET Q230 is conductive and the first FET Q230 is not conductive, the terminal end of the primary winding connected to the second FET Q220 is electrically coupled to circuit common. The high-frequency square-wave voltage VSQ at the output of the inverter circuit 140 has an opposite polarity than when the first FET Q220 is conductive (i.e., a positive voltage potential is now present from node A to node B). Accordingly, the high-frequency square-wave voltage VSQ has a magnitude of twice the bus voltage VBUS that changes polarity at the operating frequency of the inverter circuit (as shown in FIG. 6).
As shown in FIG. 3, the drive windings 224, 234 of the main transformer 210 are also coupled to the power supply 162, such that the power supply is operable to draw current to generate the DC supply voltage VCC from the drive windings during normal operation of the ballast 110. When the ballast 100 is first powered up, the power supply 162 draws current from the output of the rectifier 124 through a high impedance path (e.g., approximately 50 kΩ) to generate an unregulated supply voltage VUNREG. The power supply 162 does not generate the DC supply voltage VCC until the magnitude of the unregulated supply voltage VUNREG has increased to a predetermined level (e.g., 12 V) to allow the power supply to draw a small amount of current to charge properly during startup of the ballast 100. During normal operation of the ballast 100 (i.e., when the inverter circuit 140 is operating normally), the power supply 162 draws current to generate the unregulated supply voltage VUNREG and the DC supply voltage VCC from the drive windings 224, 234 of the inverter circuit 140. The unregulated supply voltage VUNREG has a peak voltage of approximately 15 V and a ripple of approximately 3 V during normal operation. The power supply 162 also generates a second DC supply voltage VCC2, which has a magnitude greater than the DC supply voltage VCC (e.g., approximately 15 VDC).
The high-frequency square-wave voltage VSQ is provided to the resonant tank circuit 150, which draws a tank current ITANK (FIG. 4) from the inverter circuit 140. The resonant tank circuit 150 includes a “split” resonant inductor 240, which has first and second windings that are magnetically coupled together around a common magnetic core (i.e., an inductor assemblage). The first winding is directly electrically coupled to node A at the output of the inverter circuit 140, while the second winding is directly electrically coupled to node B at the output of the inverter circuit. A “split” resonant capacitor, which is formed by the series combination of two capacitors C250A, C250B (i.e., a capacitor assemblage), is coupled between the first and second windings of the split resonant inductor 240. The junction of the two capacitors C250A, 250B is coupled to the bus voltage VBUS, i.e., to the junction of the diode D126, the bus capacitor CBUS, and the center tap of the transformer 210. The split resonant inductor 240 and the capacitors C250A, C250B operate to filter the high-frequency square-wave voltage VSQ to produce the substantially sinusoidal voltage VSIN (between node X and node Y) for driving the lamp 102. The sinusoidal voltage VSIN is coupled to the lamp 102 through a DC-blocking capacitor C255, which prevents any DC lamp characteristics from adversely affecting the inverter.
The symmetric (or split) topology of the resonant tank circuit 150 minimizes the RFI noise produced at the electrodes of the lamp 102. The first and second windings of the split resonant inductor 240 are each characterized by parasitic capacitances coupled between the leads of the windings. These parasitic capacitances form capacitive dividers with the capacitors C250A, C250B, such that the RFI noise generated by the high-frequency square-wave voltage VSQ of the inverter circuit 140 is attenuated at the output of the resonant tank circuit 150, thereby improving the RFI performance of the ballast 100.
The first and second windings of the split resonant inductor 240 are also magnetically coupled to two filament windings 242, which are electrically coupled to the filaments of the lamp 102. Before the lamp 102 is turned on, the filaments of the lamp must be heated in order to extend the life of the lamp. Specifically, during a preheat mode before striking the lamp 102, the operating frequency fOP of the inverter circuit 140 is controlled to a preheat frequency fPRE, such that the magnitude of the voltage generated across the first and second windings of the split resonant inductor 240 is substantially greater than the magnitude of the voltage produced across the capacitors C250A, C250B. Accordingly, at this time, the filament windings 242 provide filament voltages to the filaments of the lamp 102 for heating the filaments. After the filaments are heated appropriately, the operating frequency fOP of the inverter circuit 140 is controlled such that the magnitude of the voltage across the capacitors C250A, C250B increases until the lamp 102 strikes and the lamp current ILAMP begins to flow through the lamp.
The measurement circuit 170 is electrically coupled to a first auxiliary winding 260 (which is magnetically coupled to the primary winding of the main transformer 210) and to a second auxiliary winding 262 (which is magnetically coupled to the first and second windings of the split resonant inductor 240). The voltage generated across the first auxiliary winding 260 is representative of the magnitude of the high-frequency square-wave voltage VSQ of the inverter circuit 140, while the voltage generated across the second auxiliary winding 262 is representative of the magnitude of the voltage across the first and second windings of the split resonant inductor 240. Since the magnitude of the lamp voltage VLAMP is approximately equal to the sum of the high-frequency square-wave voltage VSQ and the voltage across the first and second windings of the split resonant inductor 240, the measurement circuit 170 is operable to generate the lamp voltage control signal VLAMP—VLT in response to the voltages across the first and second auxiliary windings 260, 262.
The high-frequency sinusoidal voltage VSIN generated by the resonant tank circuit 150 is coupled to the electrodes of the lamp 102 via a current transformer 270. Specifically, the current transformer 270 has two primary windings which are coupled in series with each of the electrodes of the lamp 102. The current transformer 270 also has two secondary windings 270A, 270B that are magnetically coupled to the two primary windings, and electrically coupled to the measurement circuit 170. The measurement circuit 170 is operable to generate the lamp current ILAMP control signal in response to the currents generated through the secondary windings 270A, 270B of the current transformer 270.
FIG. 4 is a simplified schematic diagram showing the current transformer 270 and the connections of the current transformer to the components of the resonant tank circuit 150 and the electrodes of the lamp 102 in greater detail. The lamp 102 is typically characterized by a capacitive coupling CE1, CE2 between each of the electrodes and earth ground, e.g., the junction box in which the ballast 100 is mounted or the fixture in which the lamp 102 is installed (i.e., a conductive housing of the ballast 100 that is connected to earth ground). These capacitive couplings CE1, CE2 generate common-mode currents flowing through the primary windings of the current transformer 270. The differential-mode currents flowing through the primary windings of the current transformer 270 are representative of the magnitude of the lamp current ILAMP flowing through the lamp 102 and thus the intensity of the lamp. Therefore, the primary windings of the current transformer 270 are coupled in series with each of the electrodes of the lamp 102 as shown in FIG. 4, such that differential-mode currents in the electrodes of the lamp are added and common-mode currents in the electrodes are subtracted. While current transformer 270 is shown having two primary windings and two secondary windings, the current transformer could alternatively be implemented as two separate transformers, each having one primary winding and one secondary winding.
The operation of the measurement circuit 170 to generate the lamp voltage control signal VLAMP—VLT and the lamp current control signal VLAMP—CUR in response to the currents through the secondary windings 270A, 270B of the current transformer 270 is described in greater detail below with reference to FIG. 7.
FIG. 5 is a simplified schematic diagram of the push/pull converter (i.e., the inverter circuit 140, the bus capacitor CBUS, and the sense resistor RSENSE) showing the gate drive circuits 222, 232 in greater detail. FIG. 6 is a simplified diagram of waveforms showing the operation of the push/pull converter during normal operation of the ballast 100.
As previously mentioned, the first and second FETs Q220, Q230 are rendered conductive in response to the control signals provided from the first and second drive windings 224, 234 of the main transformer 210, respectively. The first and second gate drive circuits 222, 232 are operable to render the FETs Q220, Q230 non-conductive in response to the first and second FET drive signals VDRV—FET1, VDRV—FET2 generated by the control circuit 160, respectively. The control circuit 160 drives the first and second FET drive signals VDRV—FET1, VDRV—FET2 high and low simultaneously, such that the first and second FET drive signals are the same. Accordingly, the FETs Q220, Q230 are non-conductive at the same time, but are conductive on an alternate basis, such that the square-wave voltage is generated with the appropriate operating frequency fOP.
When the second FET Q230 is conductive, the tank current ITANK flows through a first half of the primary winding of the main transformer 210 to the resonant tank circuit 150 (i.e., from the bus capacitor CBUS to node A as shown in FIG. 5). At the same time, a current IINV2 (which has a magnitude equal to the magnitude of the tank current) flows through a second half of the primary winding (as shown in FIG. 5). Similarly, when the first FET Q220 is conductive, the tank current ITANK flows through the second half of the primary winding of the main transformer 210, and a current IINV1 (which has a magnitude equal to the magnitude of the tank current) flows through the first half of the primary winding. Accordingly, the inverter current IINV has a magnitude equal to approximately twice the magnitude of the tank current ITANK.
When the first FET Q220 is conductive, the magnitude of the high-frequency square wave voltage VSQ is approximately twice the bus voltage VBUS as measured from node B to node A. As previously mentioned, the tank current ITANK flows through the second half of the primary winding of the main transformer 210, and the current IINV1 flows through the first half of the primary winding. The sense voltage VSENSE is generated across the sense resistor RSENSE and is representative of the magnitude of the inverter current IINV. Note that the sense voltage VSENSE is a negative voltage when the inverter current IINV flows through the sense resistor RSENSE in the direction of the inverter current IINV shown in FIG. 5.
The control circuit 160 generates an integral control signal VINT, which is representative of the integral of the sense voltage VSENSE, and is operable to turn off the first FET Q220 in response to the integral control signal VINT reaching a threshold voltage VTH (as will be described in greater detail with reference to FIG. 9). The first FET drive signal VDRV—FET1 is coupled to the gate of an NPN bipolar junction transistor Q320 via the parallel combination of a resistor R321 (e.g., having a resistance of 10 kΩ) and a capacitor C323 (e.g., having a capacitance of 100 pF). To turn off the first FET Q220, the control circuit 160 drives the first FET drive signal VDRV—FET1 high (i.e., to approximately the DC supply voltage VCC). Accordingly, the transistor Q320 becomes conductive and conducts a current through the base of a PNP bipolar junction transistor Q322. The transistor Q322 becomes conductive pulling the gate of the first FET Q220 down towards circuit common, such that the first FET Q220 is rendered non-conductive.
After the FET Q220 is rendered non-conductive, the inverter current IINV continues to flow and charges a drain capacitance of the FET Q220. The high-frequency square-wave voltage VSQ changes polarity, such that the magnitude of the square-wave voltage VSQ is approximately twice the bus voltage VBUS as measured from node A to node B and the tank current ITANK is conducted through the first half of the primary winding of the main transformer 210. Eventually, the drain capacitance of the first FET Q220 charges to a point at which circuit common is at a greater magnitude than node B of the main transformer, and the body diode of the second FET Q230 begins to conduct, such that the sense voltage VSENSE briefly is a positive voltage.
The control circuit 160 drives the second FET drive signal VDRV—FET2 low to allow the second FET Q230 to become conductive after a “dead time”, and while the body diode of the second FET Q230 is conductive and there is substantially no voltage developed across the second FET Q230 (i.e., only a “diode drop” or approximately 0.5-0.7V). The control circuit 160 waits for a dead time period TD (e.g., approximately 0.5 μsec) after driving the first and second FET drive signals VDRV—FET1, VDRV—FET2 high before the control circuit 160 drives the first and second FET drive signals VDRV—FET1, VDRV—FET2 low in order to render the second FET Q230 conductive while there is substantially no voltage developed across the second FET (i.e., during the dead time). The magnetizing current of the main transformer 210 provides additional current for charging the drain capacitance of the FET Q220 to ensure that the switching transition occurs during the dead time.
Specifically, the second FET Q230 is rendered conductive in response to the control signal provided from the second drive winding 234 of the main transformer 210 after the first and second FET drive signals VDRV—FET1, VDRV—FET2 are driven low. The second drive winding 234 is magnetically coupled to the primary winding of the main transformer 210, such that the second drive winding 234 is operable to conduct a current into the second gate drive circuit 232 through a diode D334 when the square-wave voltage VSQ has a positive voltage potential from node A to node B. Thus, when the first and second FET drive signals VDRV—FET1, VDRV—FET2 are driven low by the control circuit 160, the second drive winding 234 conducts current through the diode D334 and resistors R335, R336, R337, and an NPN bipolar junction transistor Q333 is rendered conductive, thus, rendering the second FET Q230 conductive. The resistors R335, R336, R337 have, for example, resistances of 50Ω, 1.5 kΩ, and 33 kΩ, respectively. A zener diode Z338 has a breakover voltage of 15 V, for example, and is coupled to the transistors Q332, Q333 to prevent the voltage at the bases of the transistors Q332, Q333 from exceeding approximately 15 V.
Since the square-wave voltage VSQ has a positive voltage potential from node A to node B, the body diode of the second FET Q230 eventually becomes non-conductive. The current IINV2 flows through the second half of the primary winding and through the drain-source connection of the second FET Q230. Accordingly, the polarity of the sense voltage VSENSE changes from positive to negative as shown in FIG. 6. When the integral control signal VINT reaches the voltage threshold VTH, the control circuit 160 once again renders both of the FETs Q220, Q230 non-conductive. Similar to the operation of the first gate drive circuit 222, the gate of the second FET Q230 is then pulled down through two transistors Q330, Q332 in response to the second FET drive signal VDRV—FET2. After the second FET Q230 becomes non-conductive, the tank current ITANK and the magnetizing current of the main transformer 210 charge the drain capacitance of the second FET Q230 and the square-wave voltage VSQ changes polarity. When the first FET drive signal VDRV—FET1 is driven low, the first drive winding 224 conducts current through a diode D324 and three resistors R325, R326, R327 (e.g., having resistances of 50Ω, 1.5 kΩ, and 33 kΩ, respectively). Accordingly, an NPN bipolar junction transistor Q323 is rendered conductive, such that the first FET Q220 becomes conductive. The push/pull converter continues to operate in the partially self-oscillating fashion in response to the first and second drive signals VDRV—FET1, VDRV—FET2 from the control circuit 160 and the first and second drive windings 224, 234.
During startup of the ballast 100, the control circuit 160 is operable to enable a current path to conduct a startup current ISTRT through the resistors R336, R337 of the second gate drive circuit 232. In response to the startup current ISTRT, the second FET Q230 is rendered conductive and the inverter current IINV1 begins to flow. The second gate drive circuit 232 comprises a PNP bipolar junction transistor Q340, which is operable to conduct the startup current ISTRT from the unregulated supply voltage VUNREG through a resistor R342 (e.g., having a resistance of 100Ω). The base of the transistor Q340 is coupled to the unregulated supply voltage VUNREG through a resistor R344 (e.g., having a resistance of 330Ω).
The control circuit 160 generates a FET enable control signal VDRV—ENBL and an inverter startup control signal VDRV—STRT, which are both provided to the inverter circuit 140 in order to control the startup current ISTRT. The FET enable control signal VDRV—ENBL is coupled to the base of an NPN bipolar junction transistor Q346 through a resistor R348 (e.g., having a resistance of 1 kΩ). The inverter startup control signal VDRV—STRT is coupled to the emitter of the transistor Q346 through a resistor R350 (e.g., having a resistance of 220Ω). The inverter startup control signal VDRV—STRT is driven low by the control circuit 160 at startup of the ballast 100. The FET enable control signal VDRV—ENBL is the complement of the first and second drive signals VDRV—FET1, VDRV—FET2, i.e., the FET enable control signal VDRV—ENBL is driven high when the first and second drive signals VDRV—FET1, VDRV—FET2 are low (i.e., the FETs Q220, Q230 are conductive). Accordingly, when the inverter startup control signal VDRV—STRT is driven low during startup and the FET enable control signal VDRV—ENBL is driven high, the transistor Q340 is rendered conductive and conducts the startup current ISTRT through the resistors R336, R337 and the inverter current IINV begins to flow. Once the push/pull converter is operating in the partially self-oscillating fashion described above, the control circuit 160 disables the current path that provides the startup current ISTRT.
Another NPN transistor Q352 is coupled to the base of the transistor Q346 for preventing the transistor Q346 from being rendered conductive when the first FET Q220 is conductive. The base of the transistor Q352 is coupled to the junction of the resistors R325, R326 and the transistor Q323 of the first gate drive circuit 222 through a resistor R354 (e.g., having a resistance of 10 kΩ). Accordingly, if the first drive winding 224 is conducting current through the diodes D324 to render the first FET Q220 conductive, the transistor Q340 is prevented from conducting the startup current ISTRT.
FIG. 7 is a simplified schematic diagram of the measurement circuit 170, which comprises a lamp voltage measurement circuit 400 and a lamp current measurement circuit 420. The lamp voltage measurement circuit 400 is coupled to the series combination of the first and second auxiliary windings 260, 262, such that the magnitude of the voltage across the series combination of the auxiliary windings is representative of the magnitude of the lamp voltage VLAMP. The lamp voltage measurement circuit 400 generates the lamp voltage control signal VLAMP—VLT, such that the lamp voltage control signal has a magnitude approximately equal to the peak of the lamp voltage VLAMP. The control circuit 160 determines when an overvoltage condition exits across the lamp 102, i.e., when the voltage across the auxiliary windings 260, 262 exceeds a predetermined overvoltage threshold VOVP, in response to the lamp voltage control signal VLAMP—VLT. The control circuit 160 then causes the inverter circuit 140 to stop generating the high-frequency square-wave voltage VSQ in response to the lamp voltage control signal VLAMP—VLT to provide overvoltage protection (OVP) for the resonant tank circuit 150.
The lamp voltage measurement circuit 400 comprises two resistors R402, R404, which are coupled in series across the series combination of the auxiliary windings 260, 262, and have, for example, resistances of 320 kΩ and 4.3 kΩ, respectively. The junction of the resistors R402, R404 is coupled to the base of an NPN bipolar junction transistor Q406 through a diode D408. When the voltage across the series-combination of the auxiliary windings 260, 262 rises above the overvoltage threshold VOVP, the transistor Q406 conducts current through two resistors R410, R412, and charges a capacitor C414 to generate the lamp voltage control signal VLAMP—VLT across the parallel combination of the resistor R412 and the capacitor C414. For example, the resistors R410, R412 have resistances of 100Ω and 47Ω, respectively, and the capacitor C414 has a capacitance of 0.01 μF.
The lamp current measurement circuit 420 is coupled to the secondary windings 270A, 270B of the current transformer 270. As shown in FIG. 4, the lamp 102 is characterized by a parasitic capacitance CL coupled between the electrodes, which causes the lamp current ILAMP to have a reactive component IREACTIVE, such that

ILAMP=IREAL+IREACTIVE,  (Equation 1)

where IREAL is the real component of the lamp current. FIG. 8 is a simplified diagram showing the lamp voltage VLAMP, the real component IREAL of the lamp current ILAMP, and the reactive component IREACTIVE of the lamp current. The reactive component IREACTIVE of the lamp current ILAMP is 90° out of phase with the real component IREAL. Since the real component IREAL is representative of the intensity of the lamp 102, the lamp current measurement circuit 420 integrates the currents generated through the secondary windings of the current transformer 270 during every other half-cycle of the lamp voltage VLAMP to determine the magnitude of the real component IREAL of the lamp current ILAMP. Because the real component IREAL is in phase with the lamp voltage VLAMP and the reactive component IREACTIVE is 90° out of phase with the real lamp voltage VLAMP, the integral of the reactive component IREACTIVE during a half-cycle of the lamp voltage VLAMP is equal to approximately zero amps. Thus, the lamp current control signal VLAMP—CUR generated by the lamp current measurement circuit 420 is representative of only the real component IREAL of the lamp current ILAMP.

Since the currents through the secondary windings 270A, 270B of the current transformer 270 are integrated during every other half-cycle of the lamp voltage VLAMP, the lamp current measurement circuit 420 is also coupled to the series-combination of the auxiliary windings 260, 262. Specifically, the first auxiliary winding 260 is coupled to the base of an NPN bipolar junction transistor Q422 through a resistor R424, such when the voltage at the base of the transistor Q422 exceeds approximately 1.4 V during the positive half-cycles of the lamp voltage VLAMP, the transistor Q422 is rendered conductive. The transistor Q422 then conducts current from the DC supply voltage VCC through resistors R426, R428 and a diode D430 to circuit common. In response to the voltage produced across the resistor R428 and the diode D430, a NPN bipolar junction Q432 conducts current through a diode D434 to limit the current in the transistor Q422. A diode D436 coupled between circuit common and the base of the transistor Q422 prevents the lamp current measurement circuit 420 from being responsive to the lamp current ILAMP during the negative half-cycles of the lamp voltage VLAMP.
The first secondary winding 270A of the current transformer 270 is coupled across the base-emitter junction of a PNP bipolar junction transistor Q438. The junction of the base of the transistor Q438 and the secondary winding 270A of the current transformer 270 is coupled to the junction of the diode D426 and the DC supply voltage VCC. The secondary winding 270A of the current transformer 270 is electrically coupled such that the transistor Q438 is rendered conductive when the lamp current ILAMP (and thus the current through the winding 270A) has a positive magnitude. When the transistor Q422 is rendered conductive (i.e., during the positive half-cycles of the lamp voltage VLAMP) and the transistor Q438 is conductive (i.e., the current through the winding 270A has a positive magnitude), a PNP bipolar junction transistor Q440 is rendered conductive and conducts the current from the secondary winding 270A of the current transformer 270. A diode D442 prevents the voltage at the base of the transistor Q440 from dropping too low, i.e., more than a diode drop (e.g., 0.7 V) below the DC supply voltage VCC. When the transistor Q422 is non-conductive, the base of the transistor Q440 is pulled up towards the DC supply voltage VCC through the resistor R426 and the transistor Q440 is rendered non-conductive.
Similarly, the second secondary winding 270B of the current transformer 270 is coupled across the base-emitter junction of an NPN bipolar junction transistor Q444, such that the transistor Q444 is rendered conductive when the lamp current ILAMP has a negative magnitude. Accordingly, when the transistor Q422 is rendered conductive (i.e., during the positive half-cycles of the lamp voltage VLAMP) and the transistor Q444 is conductive, another NPN bipolar junction transistor Q446 is rendered conductive and thus conducts the current from the secondary winding 270B.
The lamp current measurement circuit 420 is operable to integrate the current through the secondary windings 270A, 270B of the current transformer 270 using a capacitor C448 (e.g., having a capacitance of 0.1 μF). The lamp current measurement circuit 420 further comprises two resistors R450, R452 (e.g., having resistances of 6.34 kΩ and 681Ω, respectively) coupled in series between the DC supply voltage VCC and circuit common, such that the capacitor C448 is coupled between the junction of the two resistors R450, R452 and circuit common. The collectors of the transistors Q440, Q446, which are coupled together, are coupled to the junction of the capacitor C448 and the two resistors R450, R452. Accordingly, the transistors Q440, Q446 are operable to steer the current through either of the secondary windings 270A, 270B of the current transformer 270 into the capacitor C448 during the positive half-cycles of the lamp voltage VLAMP when the transistor Q422 is conductive. Thus, during the positive half-cycles of the lamp voltage VLAMP, the magnitude of the current IC448 conducted through the capacitor C448 is representative of the lamp current ILAMP, i.e.,

IC448=I270A+I270B=β·ILAMP,  (Equation 2)

where I270A and I270B are the magnitudes of the currents through the secondary windings 270A, 270B of the current transformer 270, respectively, and β is a constant that is dependent upon the number of turns of the current transformer 270. During the negative half-cycles of the lamp voltage VLAMP, the magnitude of the current IC448 is zero amps.

Since the integral of the reactive component IREACTIVE during the positive half-cycles of the lamp voltage VLAMP is equal to approximately zero amps, the lamp voltage control signal VLAMP—CUR is produced across the capacitor C448 and has a magnitude that is representative of the magnitude of the real component IREAL of the lamp current ILAMP, i.e.,




  
    
      
        
          
            
              
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where the integration is taken over the positive half-cycles of the lamp voltage VLAMP.

The transistors Q422, Q432, Q438, Q440, Q446 of the lamp current measurement circuit 420 operate such that the transistors do not operate in the saturation region, which minimizes the switching times of the transistors (i.e., the time between when one of the transistors is fully conductive and fully non-conductive). The lamp current measurement circuit 420 comprises a PNP bipolar junction transistor Q454 having an emitter coupled to the collector of the transistor Q438. The transistor Q454 has a base coupled to the junction of two resistors R456, R458, which are coupled in series between the DC supply voltage VCC and circuit common. For example, the resistors R456, R458 have resistances of 1 kΩ, and 10 kΩ, respectively, such that the transistor Q454 is non-conductive when the transistor Q440 is conductive. However, when the transistor Q440 is non-conductive, the transistor Q454 conducts current through the transistor Q438 to prevent the transistor Q438 from entering the saturation region during the times when the current through the first secondary winding 270A has a positive magnitude. If the transistor Q438 were to enter the saturation region when the transistor Q440 become conductive, the transistor Q438 would conduct a large unwanted pulse of current through the capacitor C448.
FIG. 9 is a simplified block diagram of the control circuit 160. The control circuit 160 includes a digital control circuit 510, which may comprise a microcontroller 610 (FIG. 10A). The digital control circuit 510 performs two functions, which are represented by a target voltage control block 512 and a ballast override control block 514 in FIG. 9. The target voltage control block 512 receives the zero-crossing control signal VZC from the zero-crossing detector 162, and generates a target voltage VTARGET, which has a DC magnitude between circuit common and the DC supply voltage VCC and is representative of the target lamp current ITARGET that results in the desired intensity of the lamp 102. The ballast override control block 514 controls the operation of the ballast 100 during preheating and striking of the lamp 102 and may be used to override the normal operation of the ballast in the occurrence of a fault condition, e.g., an overvoltage condition across the output of the ballast. The ballast override control block 514 is responsive to the lamp voltage VLAMP and the lamp current ILAMP, and generates an override control signal VOVERRIDE and a preheat control signal VPRE.
The control circuit 160 further comprises a proportional-integral (PI) controller 516, which attempts to minimize the error between target voltage VTARGET and the lamp current control signal VLAMP—CUR (i.e., the difference between the target lamp current ITARGET and the present magnitude of the lamp current ILAMP). Step variations of the magnitude of the bus voltage VBUS while the bus capacitor CBUS is recharging may result in step variations in the magnitude of the lamp current ILAMP. The control circuit 160 compensates for variations in the bus voltage VBUS by summing the output of the PI controller 516 with a voltage generated by a feed forward circuit 518, which is representative of the instantaneous magnitude of the bus voltage VBUS and has a faster response time than the PI controller. The summing operation generates the threshold voltage VTH to which the integral control signal VINT is compared, thus causing the inverter circuit 140 to switch at the appropriate operating frequency fOP to generate the desired lamp current ILAMP through the lamp 102.
The ballast override control block 514 is operable to override the operation to the PI controller 516 to control the operating frequency fOP to the appropriate frequencies during preheating and striking of the lamp by controlling the override control signal VOVERRIDE to an appropriate DC magnitude (between circuit common and the DC supply voltage VCC). During normal operation of the ballast 100, the override control signal VOVERRIDE has a magnitude of zero volts, such that that ballast override control block 514 does not affect the operation of the PI controller 516. If the ballast override control block 514 detects an overvoltage condition at the output of the resonant tank circuit 150, the override control block is operable to control the operating frequency fOP of the lamp 102 to a level such that the lamp current ILAMP is controlled to a minimal current, e.g., approximately zero amps.
The control circuit 160 receives the sense voltage VSENSE generated across the sense resistor RSENSE, and is responsive to inverter current IINV, which is conducted through the sense resistor. A scaling circuit 520 generates a scaled control signal that is representative of the magnitude of the inverter current IINV. The scaled control signal is integrated by an integrator 522 to produce the integral control signal VINT, which is compared to the threshold voltage VTH by a comparator circuit 524. A drive stage 526 is responsive to the output of the comparator circuit 524 and generates the FET enable control signal VDRV—ENBL. When the integral control signal VINT drops below the threshold voltage VTH, the output of the comparator circuit 524 goes high. In response, the drive stage 528 drives the FET enable control signal VDRV—ENBL low, which resets the integrator 522. The drive stage 528 maintains the FET enable control signal VDRV—ENBL low for the dead time period TD after which the drive stage drives the FET enable control signal high once again. A logic inverter inverts the FET enable control signal VDRV—ENBL to generate the first and second FET drive signals VDRV—FET1, VDRV—FET2.
FIGS. 10A and 10B are simplified schematic diagrams of the control circuit 160. As previously mentioned, the digital control circuit 510 comprises the microcontroller 610, which may be implemented as any suitable processing device, such as a programmable logic device (PLD), a microprocessor, or an application specific integrated circuit (ASIC). The microcontroller 610 executes a normal operation procedure 800 and a startup procedure 900, which are described in greater detail with reference to FIGS. 11 and 12, respectively. The microcontroller 610 receives the zero-crossing control signal VZC and generates a first pulse-width modulated (PWM) signal VPWM1, which has a duty cycle dependent upon the target lamp current. The first PWM signal VPWM1 is filtered by a resistor-capacitor (RC) circuit to generate the DC target voltage VTARGET. The RC circuit comprises a resistor R612 (e.g., having a resistance of 11 kΩ) and a capacitor C614 (e.g., having a capacitance of 1 μF).
The PI controller 516 comprises an operational amplifier (op amp) U616. The target voltage VTARGET is coupled to the inverting input of the op amp U616 through a resistor R618 (e.g., having a resistance of 22 kΩ). The lamp current control signal VLAMP—CUR is coupled to the non-inverting input of the op amp U616 through a resistor R620 (e.g., having a resistance of 33 kΩ). The PI controller 516 comprises two feedback resistors R622, R624, which both have resistances of 33 kΩ, for example. The feedback resistors R622, R624 are coupled between the output of the op amp U616 and the inverting and non-inverting inputs, respectively. A capacitor C626 (e.g., having a capacitance of 1000 pF) is coupled between the non-inverting input of the op amp U616 and circuit common. The series combination of a resistor R628 and a capacitor C630 is coupled in parallel with the capacitor C626. For example, the resistor R628 has a resistance of 10 kΩ, while the capacitor C630 has a capacitance of 0.22 μF. The output of the op amp U616 is coupled in series with a resistor R632 (e.g., having a resistance of 2.2 kΩ).
The PI controller 516 operates to minimize the error ei between the average of the first PWM signal VPWM1 and the lamp current control signal VLAMP—CUR, i.e.,

ei=VLAMP—CUR−avg[VPWM]  (Equation 4)

For the PI controller 516 as shown in FIG. 10A, the threshold voltage VTH is generated in dependence upon the following equation:

VTH=AP·ei+AI∫eidt,  (Equation 5)

where the values of the constants AP, AI are determined from the values of the components of the PI controller 516. Accordingly, the magnitude of the threshold voltage VTH is dependent upon the present value of the error ei and the integral of the error. The output of the PI controller 516, i.e., the threshold voltage VTH, is a DC voltage to which the integral control signal VINT is compared. If the lamp current control signal VLAMP—CUR is greater than the average of the first PWM signal VPWM1, the PI controller 516 increases the threshold voltage VTH, such that the inverter current IINV decreases in magnitude. On the other hand, if the lamp current control signal VLAMP—CUR is less than the average of the first PWM signal VPWM1, the PI controller 516 decreases the threshold voltage VTH, such that the inverter current IINV increases in magnitude.

The output of the PI controller 516 is modified by the bus voltage VBUS through the feed forward circuit 518. The feed forward circuit 518 includes two resistors R634, R636, which are coupled in series between the bus voltage VBUS and circuit common. A capacitor C638 and a resistor R640 are coupled in series between the junction of the resistors R634, R636 and the output of the PI controller 516. For example, the capacitor C638 has a capacitance of 0.33 pF, while the resistors R634, R636, R640 have resistances of 200 kΩ, 4.7 kΩ, and 1 kΩ, respectively. When the magnitude of the bus voltage VBUS increases, the magnitude of the threshold voltage VTH also increases, thus causing the peak value of the inverter current IINV (and the magnitude of the lamp current ILAMP) to decrease. When the magnitude of the bus voltage VBUS decreases, the magnitude of the threshold voltage VTH also decreases, thus causing the peak value of the inverter current IINV (and the magnitude of the lamp current ILAMP) to increase. Accordingly, the feed forward circuit 518 helps the control circuit 160 to compensate for ripple in the bus voltage VBUS, while maintaining the lamp current ILAMP and the intensity of the lamp 102 substantially constant.
The digital control circuit 510 is operable to override the operation of the PI controller 516 during startup of the ballast 100 and during fault conditions. The digital control circuit 510 is coupled to the non-inverting input of the op amp U616 of the PI controller 516 and is responsive to both the lamp voltage control signal VLAMP—VLT and the lamp current control signal VLAMP—CUR. The microcontroller 610 generates a second PWM signal VPWM2, which has a duty cycle dependent upon the operating mode of the ballast 110 (i.e., either normal operation, preheat mode, strike mode, or fault condition). To achieve the appropriate operating frequency fOP during startup and fault conditions, the microcontroller 610 controls the threshold voltage VTH to the appropriate levels by controlling the duty cycles of both of the first and second PWM signals VPWM1, VPWM2. The microcontroller 610 generates the preheat control signal VPRE for controlling the integrator 522 during preheating of the lamp 102, and the inverter startup control signal VDRV—STRT for starting up the operation of the inverter circuit 140 (as previously described with reference to FIG. 5).
The second PWM signal VPWM2 is filtered by an RC circuit comprising a resistor R642 (e.g., having a resistance of 10 kΩ) and a capacitor C644 (e.g., having a capacitance of 0.022 μF) to generate the override voltage VOVERRIDE. The PI controller 516 comprises a mirror circuit having two NPN bipolar junction transistors Q646, Q648 and a resistor R650 (e.g., having a resistance of 47 kΩ). The mirror circuit is coupled to the non-inverting input of the op amp U616 and receives the override voltage VOVERRIDE from the digital control circuit 510. The mirror circuit ensures that the override voltage VOVERRIDE only appears at the non-inverting input of the op amp U616 of the PI controller 516 if the override voltage exceeds the voltage generated at the non-inverting input of the op amp in response to the lamp current control signal VLAMP—CUR.
Referring to FIG. 10B, the scaling circuit 520 is responsive to the magnitude of the sense voltage VSENSE (i.e., responsive to the magnitude of the inverter current IINV of the inverter circuit 140). As shown in FIG. 10B, the scaling circuit 520 comprises, for example, a mirror circuit comprising two NPN bipolar junction transistors Q710, Q712 having bases that are coupled together. A resistor R714 is coupled to the emitter of the transistor Q712, such that a scaled current ISCALED is generated through the resistor R714 when one of the FETs Q220, Q230 is conducting the inverter current IINV (i.e., in the direction of one of the currents IINV1, IINV2 shown in FIG. 5). The scaled current ISCALED has a magnitude that is representative of the magnitude of the inverter current IINV, for example, proportional to the inverter current. Specifically, the resistor R714 has a resistance of approximately 1 kΩ, such that the magnitude of the scaled current ISCALED is equal to approximately 1/1000 of the magnitude of the inverter current IINV. The transistors Q710, Q712 may be provided as part of a dual package part (e.g., part number MBT3904DW1, manufactured by ON Semiconductor), such that the operational characteristics of the two transistors are matched as best as possible.
Since the emitter resistances seen by the transistors Q710, Q712 are quite different, the base-emitter voltages of the transistors Q710, Q712 will not be the same. As a result, there is a small bias current conducted through the base of the transistor Q712 even when the magnitude of the sense voltage VSENSE is approximately zero volts. To eliminate this bias current, the scaling circuit 520 comprises a compensation circuit including two PNP bipolar junction transistors Q716, Q718 (which may both be part of a dual package part number MMDT3906, manufactured by ON Semiconductor). The collector of the transistor Q710 is coupled to the collector of the transistor Q716 via a resistor R720 (e.g., having a resistance of 4.7 kΩ), while the collectors of the transistors Q712, Q718 are coupled directly together. The emitter of the transistor Q716 is coupled to the DC supply voltage VCC through a resistor R722 (e.g., having a resistance of 1 kΩ). The transistor Q718 provides a bias current having a magnitude approximately equal to the magnitude of the bias current conducted in the base of the transistor Q712, thus effectively canceling out the bias current.
The integrator 522 is responsive to the scaled current ISCALED and generates the integral control signal VINT, which is representative of the integral of the scaled current ISCALED and thus the integral of the inverter current IINV when the inverter current has a positive magnitude. A integration capacitor C724 is the primary integrating element of the integrator 522 and may have a capacitance of approximately 130 pF. The integrator 522 is reset in response to the FET enable control signal VDRV—ENBL. Specifically, the voltage across the capacitor C724 is set to approximately zero volts at the same time the FETs Q220, Q230 of the inverter circuit 140 are rendered non-conductive by the control circuit 160. A PNP bipolar junction transistor Q726 is coupled across the capacitor C724. The base of the transistor Q726 is coupled to the FET enable control signal VDRV—ENBL through a diode D728 and a resistor R730 (e.g., having a resistance of 10 kΩ). When the FET enable control signal VDRV—ENBL is pulled low (to turn the FETs Q220, Q230 off), the diode D728 and the resistor R730 conduct current through a resistor R732 (e.g., having a resistance of 4.7 kΩ). When the appropriate voltage is developed across the base-emitter junction of the transistor Q726, the transistor Q726 begins to conduct, thus discharging the capacitor C724 until the voltage across the capacitor C724 is approximately zero volts. A diode D734, which is coupled from the collector of the transistor Q726 and the junction of the diode D728 and the resistor R730, prevents the transistor Q726 from operating in the saturation region.
When the FET enable control signal VDRV—ENBL is once again driven high, the capacitor C724 has an initial voltage of approximately zero volts and the integral control signal VINT has a magnitude equal to approximately the DC supply voltage VCC as shown in FIG. 6. The capacitor C724 begins to charge through a resistor R735 (e.g., having a resistance of 47Ω). When the FETs Q220, Q230 begin to conduct the inverter current IINV (i.e., in the direction of currents IINV1, IINV2 in FIG. 5), the capacitor C724 begins to charge in response to the scaled current ISCALED, which increases in magnitude with respect to time. Accordingly, the integral control signal VINT decreases in magnitude as a function of the integral of the scaled current ISCALED as shown in FIG. 6. The resistor R735 provides a minimum charging current to cause oscillation even when the magnitude of the inverter current IINV is approximately zero amps.
The comparator circuit 524 compares the magnitude of the integral control signal VINT and the magnitude of the threshold voltage VTH, and signals to the drive stage 526 when the magnitude of the integral control signal VINT decreases below the magnitude of the threshold voltage VTH. The comparator circuit 524 comprises two PNP bipolar junction transistors Q736, Q738 and a resistor R740. The resistor R740 is coupled between the emitters of the transistors Q736, Q738 and the second DC supply voltage VCC2 (i.e., 15 V), and may have a resistance of approximately 10 kΩ. When the magnitude of the integral control signal VINT is greater than the magnitude of the threshold voltage VTH, the first transistor Q736 is conductive, while the second transistor Q738 is non-conductive. Accordingly, the output of the comparator circuit 524 is pulled down towards circuit common through a resistor R742 (e.g., having a resistance of 4.7 kΩ). When the magnitude of the integral control signal VINT decreases to less than the magnitude of the threshold voltage VTH, the second transistor Q738 is rendered conductive, thus pulling the output of the comparator circuit 524 up towards the DC supply voltage VCC (e.g., to approximately 0.7 V).
The drive stage 526 comprises an NPN bipolar junction transistor Q744 and a resistor R746, which is coupled between the collector of the transistor Q744 and the DC supply voltage VCC, and has, for example, a resistance of 10 kΩ. When the output of the comparator circuit 524 is pulled up away from circuit common, the transistor Q744 is rendered conductive, thus pulling the input of a first logic inverter Q748 down towards circuit common. Accordingly, the output of the logic inverter Q748 is driven up towards the DC supply voltage VCC and a capacitor C750 quickly charges through a diode D752 to approximately the DC supply voltage VCC. The capacitor C750 has, for example, a capacitance of 47 pF. A second logic inverter U754 is coupled to the capacitor C750, such that the FET enable control signal VFET—ENBL is generated at the output of the inverter U754. Accordingly, the FET enable control signal VFET—ENBL is pulled down towards circuit common when the capacitor charges to the DC supply voltage VCC.
The logic inverter circuit 528 simply comprises two logic inverters U758, U760, having inputs coupled to the FET enable control signal VFET—ENBL. The output of the first logic inverter U758 generates the first FET drive signal VDRV—FET1, while the output of the second logic inverter U760 generates the second FET drive signal VDRV—FET2.
When the magnitude of the integral control signal VINT drops below the magnitude of the threshold voltage VTH, the output of the comparator circuit 524 is pulled up towards the DC supply voltage VCC to render the transistor Q744 conductive. The drive stage 526 then pulls the FET enable control signal VFET—ENBL down towards circuit common, such that the first and second FET drive signals VDRV—FET1, VDRV—FET2 are driven high, thus rendering the FETs Q220, Q230 of the inverter circuit 140 non-conductive. The drive stage maintains the FET enable control signal VFET—ENBL at the logic high level for the dead time period TD after which the FETs Q220, Q230 are no longer rendered non-conductive.
Since the integrator 522 is reset (i.e., the magnitude of the integral control signal VINT returns to approximately the DC supply voltage VCC) in response to the FET enable control signal VFET—ENBL, the output of the comparator circuit 524 is once again pulled low towards circuit common as soon as the FETs Q220, Q230 are rendered non-conductive. The base of a PNP bipolar junction transistor Q770 is coupled to the FET enable control signal VFET—ENBL through a resistor R756 (e.g., having a resistance of 1 kΩ). When the FETs Q220, Q230 are rendered non-conductive, the transistor Q770 is rendered conductive pulling the input of the first logic inverter U748 up towards the DC supply voltage VCC through a resistor R772. The resistor R772 has a smaller resistance than the resistor R746, for example, 220Ω, such that the output of the logic inverter U748 is quickly driven towards circuit common. The capacitor C750 then discharges through a resistor R774. When the capacitor C750 discharges to the appropriate level, the logic inverter U754 drives the output high, such that the FETs Q220, Q230 are no longer rendered non-conductive after the dead time period TD. For example, the resistor R774 has a resistance of 4.7 kΩ, such that the dead time period TD is approximately 0.5 μsec.
During preheating of the lamp 102, the microcontroller 610 is operable to control the operation of the integrator 522 using the preheat control signal VPRE. As shown in FIG. 10B, the preheat control signal VPRE is pulled up to the DC supply voltage VCC through a resistor R776 (e.g., having a resistance of 10 kΩ), and is coupled to the base of an NPN bipolar junction transistor Q778 through a resistor R780. For example, the resistors R776, R780 both have resistances of 10 kΩDuring preheating of the filaments of the lamp 102, the microcontroller 610 drives the preheat control signal VPRE high, such that transistor Q778 is rendered conductive. Accordingly, the capacitor C724 is operable to additionally charge in response to a current drawn through the transistor Q778 and a resistor R782 (e.g., having a resistance of 47 kΩ). The additional current allows the capacitor C724 to charge faster, and causes the integral control signal VINT to drop below the threshold voltage VTH more quickly. Thus, the control circuit 160 is operable to control the inverter circuit 140 to achieve the appropriate high-frequency switching of the FETs Q220, Q230 at the preheat frequency fPRE during preheating of the lamp 102.
The values of the components of the integrator may be chosen to optimize the operating frequency fOP when the ballast 100 is operating at low-end, i.e., at the maximum operating frequency during normal operation. As the control circuit 160 controls the intensity of the lamp 102 from low-end to high-end, the operating frequency fOP changes from the maximum operating frequency to a minimum operating frequency. Since the magnitude of the threshold voltage VTH is lowest when the ballast 100 is at high-end, the capacitor C724 charges for a longer period of time until the magnitude of the integral control signal VINT drops below the magnitude of the threshold voltage.
In order to ensure that the control circuit 160 controls the inverter circuit 140 to achieve the appropriate operating frequency fOP at high-end, the integrator 522 slows down the charging of the capacitor C724 near high-end. Specifically, the integrator 522 comprises two resistors R784, R786, which are coupled in series between the DC supply voltage VCC and circuit common, and a diode D788, coupled from the junction of the two resistors R784, R786 to the integral control signal VINT. For example, the resistors R784, R786 have resistances of 3.3 kΩ and 8.2 kΩ, respectively, such that the current conducted through the diode D788 causes the capacitor C724 to charge slower if the magnitude of the integral control signal VINT drops below approximately 2.8 V.
FIG. 11 is a simplified flowchart of the target lamp current procedure 800 executed periodically by the microcontroller 610, e.g., once every half-cycle of the AC power source 102. The primary function of the target lamp current procedure 800 is to measure the conduction period TCON of the phase-controlled voltage VPC generated by the dimmer switch 104 and to determine the corresponding target lamp current ITARGET that will result in the desired intensity of the lamp 102. The microcontroller 610 uses a timer, which is continuously running, to measure the times of the rising and falling edges of the zero-crossing control signal VZC, and to calculate the difference between the times of the falling and rising edges to determine the conduction period TCON of the phase-control voltage VPC.
The procedure 800 begins at step 810 in response to a falling-edge of the zero-crossing control signal VZC, which signals that the phase-control voltage VPC has risen above the zero-crossing threshold VTH-ZC of the zero-crossing detect circuit 162. The present value of the timer is immediately stored in register A at step 812. The microcontroller 610 waits for a rising edge of the zero-crossing signal VZC at step 814 or for a timeout to expire at step 815. For example, the timeout may be the length of a half-cycle, i.e., approximately 8.33 msec if the AC power source operates at 60 Hz. If the timeout expires at step 815 before the microcontroller 610 detects a rising edge of the zero-crossing signal VZC at step 814, the procedure 800 simply exits. When a rising edge of the zero-crossing control signal VZC is detected at step 814 before the timeout expires at step 815, the microcontroller 610 stores the present value of the timer in register B at step 816. At step 818, the microcontroller 610 determines the length of the conduction interval TCON by subtracting the timer value stored in register A from the timer value stored in register B.
Next, the microcontroller 610 ensures that the measured conduction interval TCON is within predetermined limits. Specifically, if the conduction interval TCON is greater than a maximum conduction interval TMAX at step 820, the microcontroller 610 sets the conduction interval TCON equal to the maximum conduction interval TMAX at step 822. If the conduction interval TCON is less than a minimum conduction interval TMIN at step 824, the microcontroller 610 sets the conduction interval TCON equal to the minimum conduction interval TMIN at step 826.
At step 828, the microcontroller 610 calculates a continuous average TAVG in response to the measured conduction interval TCON. For example, the microcontroller 610 may calculate a N:1 continuous average TAVG using the following equation:

TAVG=(N·TAVG+TCON)/(N+1).  (Equation 6)

For example, N may equal 31, such that N+1 equals 32, which allows for easy processing of the division calculation by the microprocessor 610. At step 830, the microcontroller 610 determines the target lamp current ITARGET in response to the continuous average TAVG calculated at step 828, for example, by using a lookup table. The microcontroller 610 then stores the continuous average TAVG and the target lamp current ITARGET in separate registers at step 832. If the ballast 100 is in the normal operating mode at step 834 (i.e., the lamp 102 has been struck), the microcontroller 610 adjusts at step 836 the duty cycle of the first PWM signal VPWM1 appropriately, such that the average magnitude of the first PWM signal is representative of the target lamp current ITARGET and the procedure 800 exits. If the ballast 100 is not in the normal operating mode at step 834 (i.e., the lamp 102 has not been struck or a fault condition exists), the procedure 800 simply exits.

FIG. 12 is a simplified flowchart of a startup procedure 900, which is executed by the microcontroller 610 when the microcontroller is first powered up at step 910. First, the microcontroller 610 initializes the timer to zero seconds and starts the timer at step 912. Next, the microcontroller 610 preheats the filaments of the lamp 102 during a preheat time period TPRE. Specifically, the microcontroller 610 begins to preheat the filaments by driving the preheat control signal VPRE (which is provided to the integrator 822) high at step 914 and by adjusting the duty cycle of the second PWM signal VPWM2 to a preheat value at step 916. At step 918, the microcontroller 610 drives the inverter startup control signal VDRV—STRT low, after the threshold voltage VTH has reached a steady state value in response to the second PWM signal VPWM2 from step 916. As a result, the operating frequency fOP of the inverter circuit 140 is controlled to the preheat frequency fPRE, such that the filaments windings 242 provide the proper filament voltages to the filaments of the lamp 102. The microcontroller 610 continues to preheat the filaments until the end of the preheat time period TPRE at step 920.
After the preheat time period TPRE, the microcontroller 610 drives the preheat control signal VPRE low at step 922 and linearly decreases the duty cycle of the second PWM signal VPWM2 at step 924, such that the resulting operating frequency fOP of the inverter circuit 140 decreases from the preheat frequency fPRE until the lamp 102 strikes. At step 926, the microcontroller 610 samples the lamp current control signal VLAMP—CUR to determine if the lamp current ILAMP is flowing through the lamp 102 and the lamp has been struck. If the lamp has been struck at step 928, the microcontroller 610 drives the inverter startup control signal VDRV—STRT high at step 930 and adjusts the duty cycle of the second PWM signal VPWM2 to zero percent at step 932, such that the resulting override voltage VOVERRIDE has a magnitude of approximately zero volts and does not affect the operation of the PI controller 516.
While the startup procedure 900 is executing, the target lamp current procedure 800 is also being executed each half-cycle of the AC power source 104, such that the target lamp current ITARGET has been determined and stored in a register. At step 934 of the startup procedure 900, the microcontroller 610 sets the duty cycle of the first PWM signal VPWM1 to the appropriate level, before the startup procedure 900 exits and the ballast begins normal operation.
If the lamp has not been struck at step 928 and the duty cycle has not been decreased to a minimum duty cycle at step 936, the microcontroller 610 continues to linearly decrease the duty cycle of the second PWM signal VPWM2 at step 924. If the lamp has not been struck at step 928, but the duty cycle has reached a minimum duty cycle at step 936, the procedure 900 loops around, such that the microcontroller 610 starts over and attempts to preheat and strike the lamp 102 once again.
As previously mentioned, the dimmer switch 106 of FIG. 1 typically includes a bidirectional semiconductor switch, such as a triac, for generating the phase-controlled voltage VPC. When a typical triac is conductive, the current conducted by the triac must remain above a holding current rating of the triac for the triac to remain conductive. Therefore, when a dimmer switch 106 is coupled in series with a two-wire ballast (as shown in FIG. 1), the two-wire ballast must draw enough current to maintain the triac conductive and to ensure proper operation of the dimmer switch.
FIG. 13 is a simplified block diagram of an electronic dimming ballast 1000 according to a second embodiment of the present invention. The electronic dimming ballast 1000 comprises a charge pump circuit 1010, which is coupled in parallel electrical connection the diode D126 between the rectifier 124 and the inverter circuit 140. When the magnitude of the rectified voltage VRECT is less than the magnitude of the bus voltage VBUS, the charge pump circuit 1010 operates to draw a charge current ICP from the AC power source 104. Specifically, the charge pump circuit 1010 is coupled to the output of the inverter circuit 140, such that the charge pump circuit 1010 is operable to draw the charge current ICP every other half-cycle of the square-wave voltage VSQ. The charge current ICP drawn during the times that the magnitude of the rectified voltage VRECT is less than the magnitude of the bus voltage VBUS helps to prevent the current through the triac of the dimmer switch 106 from dropping below the holding current rating.
FIG. 14 is a simplified schematic diagram showing the charge pump 1010 in greater detail. The charge pump 1010 comprises two diodes D1012, D1014 connected in series across the diode D126. The charge pump 1010 further comprises a capacitor C1016 and an inductor L1018, which are coupled in series between the junction of the diodes D1012, D1014 and the output of the inverter circuit 140 at the junction of the main transformer 210 and the first FET Q220 (i.e., node A as shown in FIG. 14). For example, the capacitor C1016 may have a capacitance of 0.01 μF, while the inductor L1018 may have an inductance of 600 μH.
When the magnitude of the rectified voltage VRECT is greater than the magnitude of the bus voltage VBUS, the diode D126 is conductive as the bus capacitor CBUS charges. However, when the magnitude of the rectified voltage VRECT is less than the magnitude of the bus voltage VBUS and the first FET Q220 is conductive, the capacitor C1016 is operable to charge through the diode D1012, thus drawing the charge current ICP through the dimmer switch 106. The capacitor C1016 charges to approximately the instantaneous magnitude of the line voltage.
When the first FET Q220 is non-conductive and the voltage across the primary winding of the main transformer 210 has a magnitude of approximately twice the bus voltage (i.e., 2·VBUS), the capacitor C1016 charges to approximately the magnitude of the bus voltage VBUS and conducts an additional bus charging current IBUS through the diode D1014 and into the bus capacitor CBUS. Accordingly, while the magnitude of the rectified voltage VRECT is less than the magnitude of the bus voltage VBUS, the charge pump 1010 operates to periodically draw the charge current ICP through dimmer switch 106 and to conduct the additional bus charging current IBUS into the bus capacitor CBUS to allow the bus capacitor CBUS to charge during a time when the bus capacitor CBUS would normally be decreasing in charge. The inductor L1018 controls the rate at which the voltage across the capacitor C1016 changes in response to the changing voltage across the output of the inverter circuit 140.
FIG. 15 is a simplified schematic diagram of a lamp current measurement circuit 420′ of the measurement circuit 170 according to a third embodiment of the present invention. A current transformer 270′ has two primary winding coupled between the resonant tank circuit 150 and to the lamp 102 as shown in FIG. 4. However, the current transformer 270′ only has a single secondary winding coupled to the lamp current measurement circuit 420′. Specifically, the secondary winding of the current transformer 270′ is coupled across the base-emitter junction of a PNP bipolar junction transistor Q1510. The junction of the base of the transistor Q1510 and the secondary winding of the current transformer 270′ is coupled to the DC supply voltage VCC. When the lamp current ILAMP (and thus the current through the secondary winding of the current transformer 270′) has a positive magnitude, the transistor Q1510 is rendered conductive, thus conducting current through a capacitor C1512 and a resistor R1514. The lamp current control signal VLAMP—CUR generated across the parallel combination of the capacitor C1512 and the resistor R1514 is representative of the magnitude of the lamp current ILAMP. When the lamp current ILAMP has a negative magnitude, the transistor Q1510 is non-conductive, and the current through the secondary winding of the current transformer 270′ flows through a diode D1516.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

## Claims

1. A multi-switch power converter comprising:
a main transformer having a primary winding for producing an oscillating output voltage;
first and second semiconductor switches electrically coupled to the primary winding of the main transformer for conducting current through the primary winding on an alternate basis; and
first and second drive circuits for controlling the first and second semiconductor switches, respectively, on a cycle-by-cycle basis so as to generate the oscillating output voltage across the primary winding of the main transformer, the first and second drive circuits operable to turn on the respective semiconductor switches in response to first control signals derived from the main transformer and to turn off the respective semiconductor switches in response to second control signals received from a control circuit;
wherein the oscillating output voltage has an operating frequency dependent upon when the first and second semiconductor switches are turned on and off.

2. The power converter of claim 1, wherein the second and fourth control signals from the control circuit are substantially the same, such that the first and second semiconductor switches are controlled off at the same time.

3. The power converter of claim 2, wherein the first and second drive circuits turn on the first and second semiconductor switches in response to the first and third control signals from the main transformer, respectively, after a predetermined amount of time after the drive circuits turned off both of the first and second semiconductor switches.

4. The power converter of claim 1, further comprising:
a bus capacitor for producing a substantially DC bus voltage, the bus capacitor coupled to the main transformer, such that the DC bus voltage is provided to a center tap of the primary winding of the main transformer;
wherein the first and second semiconductor switches are coupled between the terminal ends of the primary winding of the main transformer and a circuit common, such that the DC bus voltage is provided across one half of the primary winding of the main transformer when one of the first and second semiconductor switches is conductive.

5. The power converter of claim 1, wherein the first and second semiconductor switches comprise field-effect transistors.

6. The power converter of claim 1, further comprising:
first and second windings magnetically coupled to the primary winding of the main transformer, the first and second windings electrically coupled to the first and second drive circuits, respectively, for providing the first control signals from the main transformer, respectively.

7. The power converter of claim 1, wherein the first and second drive circuits turn off the respective semiconductor switch in response to the magnitudes of the currents through each of the respective semiconductor switch.

8. The power converter of claim 1, wherein the first and second drive circuits turn off the respective semiconductor switch in response to a peak magnitude of an integral of the current through the respective semiconductor switch.

9. The power converter of claim 1, further comprising:
a bus capacitor coupled to the main transformer for conducting a converter current when one of the first and second semiconductor switches is conductive;
wherein the control circuit is operable to scale the converter current to produce a scaled current, integrate the scaled current to generate an integral control signal representative of the scaled current, compare the integral control signal to a threshold voltage, and render both semiconductor switches non-conductive in response to the integral control signal reaching the threshold voltage.

10. The power converter of claim 9, wherein the control circuit comprises:
a scaling circuit operable to produce the scaled current such that the magnitude of the scaled current is proportional to the converter current;
an integrator circuit operable to integrate the scaled current to generate the integral control signal; and
a comparator circuit operable to compare the integral control signal to the threshold voltage, and having an output representative of the integral control signal reaching the threshold voltage.

11. The power converter of claim 10, wherein the integrator circuit comprises a capacitor coupled to conduct the scaled current, such that the magnitude of the integral control signal is dependent upon a voltage generated across the capacitor.

12. The power converter of claim 11, wherein the integrator circuit further comprises a bias resistor coupled to the capacitor to conduct a bias current through the capacitor in addition to the scaled current.

13. The power converter of claim 1, wherein the integrator circuit further comprises a semiconductor switch coupled across the capacitor for resetting the voltage generated across the capacitor to approximately zero voltage when the first and second semiconductor switches are rendered non-conductive.

14. The power converter of claim 10, wherein the control circuit changes the threshold voltage in response to a desired output current of the power converter.

15. The power converter of claim 10, wherein the scaling circuit comprises a current mirror circuit.

16. The power converter of claim 10, further comprising:
a drive circuit coupled to control inputs of the first and second semiconductor switches, and responsive to the output of the comparator circuit to render the semiconductor switches non-conductive at the same time.

17. A method of controlling a switching power converter comprising a main transformer having a primary winding coupled across an output of the switching power converter, first and second semiconductor switches electrically coupled to the primary winding of the main transformer, first and second drive circuits coupled to the first and second semiconductor switches, respectively, and a control circuit coupled to the first and second drive circuits, the method comprising the steps of:
producing a high-frequency AC voltage across the primary winding of the main transformer;
deriving first control signals from the main transformer;
receiving second control signals from the control circuit; and
controlling the first and second semiconductor switches on a cycle-by-cycle basis to conduct current through the primary winding on an alternate basis in response to the first and second control signals:
wherein the step of controlling the first and second semiconductor switches further comprises turning on the semiconductor switches in response to the first control signals from the main transformer, and turning off the semiconductor switches in response to the second control signals from the control circuit, such that the high-frequency AC voltage has an operating frequency dependent upon when the first and second semiconductor switches are turned on and off.

18. The method of claim 17, wherein the power converter has an energy storage capacitor coupled to the main transformer and operable to conduct a converter current when one of the semiconductor switches is conductive, the method further comprising the steps of:
scaling the converter current to produce a scaled current;
integrating the scaled current to generate an integral control signal representative of the scaled current; and
comparing the integral control signal to a threshold voltage;
wherein the step of turning off the semiconductors switches comprises rendering the semiconductor switches non-conductive in response to the integral control signal reaching the threshold voltage.

19. The method of claim 18, wherein the step of integrating comprises conducting the scaled current through an integration capacitor, such that the magnitude of the integral control signal is dependent upon a voltage generated across the integration capacitor.

20. The method of claim 19, further comprising:
conducting a bias current through the integration capacitor in addition to the scaled current.

21. The method of claim 19, further comprising:
resetting the voltage generated across the integration capacitor to approximately zero voltage when the first and second semiconductor switches are rendered non-conductive.

22. The method of claim 18, further comprising the step of:
changing the threshold voltage in response to a desired output current of the power converter.