# Patent

## Title
Duty cycle characterization and adjustment

## Abstract

Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.

## Background
RELATED PATENT APPLICATIONS
This application is a continuation-in-part of U.S. patent application Ser. No. 10/255,502, filed Sep. 26, 2002, now U.S. Pat. No. 7,062,692, issued Jun. 13, 2006 the contents of which are incorporated herein by reference.


One or more aspects of the present invention generally relate to U.S. Pat. No. 5,877,632 filed by Goetting et al. on Apr. 11, 1997, entitled “FPGA with a Plurality of I/O Voltage Levels”, the contents of which are incorporated herein by reference.
FIELD OF THE INVENTION
Aspects of the present invention generally relate to duty cycle, and more particularly to characterization and adjustment of duty cycle.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory such as EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the configuration memory cells in the FPGA into which the bitstream is loaded then determine the function of the FPGA.
An important step in the manufacture of integrated circuits, such as CPLDs, FPGAs and the like, is testing these devices prior to shipment to a customer. However, chip handlers and testers are expensive, so chip designers have included test circuits on the devices (on the microchips) to reduce tester test time. Alternatively, test designers configure CPLDs and FPGAs to implement test designs to perform functions internally that can not be performed by a tester. This type of circuitry or configuration is known as “Built-In Self-Test” or “BIST”. U.S. Pat. Nos. 5,790,479, 6,005,829, 6,069,849, 6,144,262, 6,219,305, 6,232,845, 6,233,205, 6,356,514, and 6,452,489 describe how such structures are programmed and tested, and are incorporated herein by reference.
However, some tests still need to be done with a tester, especially analog characterization. One such area is input/output (I/O) duty cycle. Device operation is dependent upon proper I/O transistor operation. However, accurate performance measurement of I/O transistor operation is problematic. This is partly due to insufficient tester speed to measure I/O switching speed under operative conditions (“dynamic behavior”).
However, even with testers rated at the operational speed of microchips, accurate characterization of I/O transistor operation is elusive. Timing delays of leads and traces connecting the tester to the microchip are larger than some of the delays and periods being measured on the chip. Conventionally, parameters of I/O transistors are measured in a laboratory on a few sample chips to determine theoretical performance, which is then correlated with test data obtained from a tester on production chips. But it can take many hours of engineer and technician time to characterize and correlate less than ten microchips for just a few I/O transistors on each chip.
Though I/O transistors for each I/O are conventionally all made with the same semiconductor n-type and p-type processes for the chip on which they reside, differences among I/O transistors on a chip may exist. If duty cycle of an I/O is not within acceptable parameters, this can lead to catastrophic failure.
Accordingly, it is desirable and useful to be able to accurately characterize dynamic behavior of I/O transistors in a way that is less costly than previous approaches. Moreover, it is desirable to use dynamic behavior information for I/O transistor operation to shift operation away from failure, and, for more rigorous applications, to limit duty cycle.
SUMMARY OF THE INVENTION
An aspect of the present invention is a method for on-chip testing of duty cycle at an input/output node. A test signal having a non-zero frequency is generated. A duty cycle for the test signal is also generated. At least a portion of the test signal and the duty cycle is obtained at the input/output node. The duty cycle is checked to determine the proportion at the input/output node.
An aspect of the present invention is an apparatus for on-chip testing of an n-type to p-type transistor threshold voltage ratio for a bi-directional input/output block (IOB). An oscillator is configured to generate a waveform, and a divide-by circuit is coupled to receive the waveform to provide a duty cycle for the waveform. The IOB includes an input buffer and an output buffer, where the IOB is coupled to receive the waveform having the duty cycle of interest at the input buffer and to sample the waveform with the output buffer. A phase comparator circuit is coupled to the output buffer to receive the waveform sample and configured to generate a phase-shifted waveform sample and to provide an indication of whether the n-type to p-type transistor threshold voltage ratio of the IOB is balanced.
Alternatively, the divide-by circuit provides a duty cycle for the test signal. The IOB includes complementary-metal-oxide-semiconductor (CMOS) input and output buffers coupled to receive the test signal and programmed to provide the test signal as an output and to sample the output. Counters are coupled to receive the output to count ones and zeros of the output, and a sample clock signal is provided to the counters. The sample clock signal is synchronized to the test signal and has a frequency in excess of that of the test signal. Compare logic is configured to receive outputs from the counters to determine the n-type to p-type transistor threshold voltage ratio.
Another aspect of the present invention is a method for adjusting the duty cycle. A duty cycle indicator signal is provided to indicate duty cycle of an output signal. At least one transistor of a plurality of n-channel and p-channel transistors is turned on in response to the duty cycle indicator signal to adjust the duty cycle of the output signal.
Another aspect of the present invention is a duty cycle adjust system. Drive adjust circuitry is coupled to receive a duty cycle adjust enable signal and configured to provide a drive adjust address signal in response to the duty cycle adjust enable signal. A reference voltage generator is coupled to receive the drive adjust address signal and configured to provide a plurality of reference voltages in response to the drive adjust address signal. An output buffer is coupled to receive the plurality of reference voltages and configured to select at least one p-channel drive transistor and at least one n-channel drive transistor in response to the plurality of reference voltages. The output buffer is configured to sample an output signal to provide an output signal sample. Duty cycle check circuitry is coupled to receive the output signal sample and configured to provide a duty cycle indicator signal in response to the output signal sample. The output signal sample has a duty cycle responsive to the plurality of reference voltages. The drive adjust circuitry is coupled to receive the duty cycle indicator signal and configured to provide another drive adjust address signal in response to the duty cycle indicator signal.
Another aspect of the present invention is a method for adjusting transistor drive. A duty cycle for a signal is determined, where the duty cycle is at least partially responsive to at least one n-channel transistor and at least one p-channel transistor used for propagating the signal. Drive voltage on at least one of the at least one n-channel transistor and the at least one p-channel transistor is adjusted in response to the duty cycle determined.
Another aspect of the present invention is a method of testing duty cycle at an input/output node. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using the phase, as indicated, of the sampling signal at the first level change and the phase, as indicated, of the sampling signal at the second level change.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an exemplary embodiment of an FPGA in accordance with one or more aspects of the present invention coupled to program memory.
FIG. 2 is a block diagram of an exemplary embodiment of a wafer probe having a wafer in accordance with one or more aspects of the present invention.
FIGS. 3A and 3B are block diagrams of respective portions of an FPGA configured for a duty cycle check test mode in accordance with one or more aspects of the present invention.
FIGS. 4 and 5 are block diagrams of respective exemplary embodiments of duty-cycle check circuits in accordance with one or more aspects of the present invention.
FIG. 6 is a circuit diagram of an output driver circuit.
FIG. 7 is a circuit diagram illustrating the general manner in which p-channel transistors of an output driver circuit are matched with an external resistance.
FIG. 8 is a circuit diagram illustrating the general manner in which n-channel transistors of an output driver circuit are matched with an external resistance.
FIG. 9A is a circuit diagram illustrating a digitally controlled impedance (DCI) output driver circuit.
FIG. 9B is a circuit diagram illustrating an output driver circuit in which a DCI circuit has been bypassed.
FIG. 10A is a circuit diagram illustrating external termination resistors, which are coupled between the ends of a line and a VCC supply voltage terminal.
FIGS. 10B-10C are circuit diagrams illustrating termination resistors that are implemented using the digitally controlled impedances of output driver circuits, thereby eliminating the need for external termination resistors.
FIG. 11A is a circuit diagram illustrating external termination resistors, which are coupled between the ends of a line and a VCC/2 supply voltage terminal.
FIGS. 11B-11C are circuit diagrams of termination resistors that are implemented using the digitally controlled impedances of output driver circuits, thereby eliminating the need for external termination resistors and a VCC/2 supply.
FIG. 12 is a block diagram of an integrated circuit chip.
FIG. 13 is a circuit diagram illustrating selected portions of an IOB bank, including a bank impedance control circuit and selected IOBs.
FIG. 14 is a circuit diagram of a reference voltage supply.
FIG. 15 is a block diagram illustrating a bank DCI circuit and a local DCI circuit.
FIG. 16A is a block diagram of an exemplary duty cycle adjust system.
FIG. 16B is a block diagram of an exemplary programmable duty cycle adjust system.
FIG. 17 is a block diagram of an exemplary duty-cycle check circuit.
FIG. 18 is a block diagram of exemplary control logic of the duty-cycle check circuit of FIG. 17.
FIG. 19 is a flow diagram of an exemplary process for determining duty cycle of a test signal.
FIG. 20 is a flow diagram of another exemplary process for determining duty cycle of a test signal.



DETAILED DESCRIPTION OF THE DRAWINGS
In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.
FIG. 1 is a block diagram of an exemplary FPGA 100 in accordance of one or more aspects of the present invention coupled to program memory 112. Program memory 112 is programmed for putting FPGA 100 into a test mode, and is described below in more detail. Alternatively, programming instruction to put FPGA 100 into a test mode may be provided via a wafer probe 121, as shown in FIG. 2. FPGA 100 comprises CLBs 107, I/O routing ring 106A, memory, such as random access memory 111, delay lock loops (DLLs) 109, multiply/divide/de-skew clock circuits 110, and programmable IOBs 106B. DLLs 109 and clock circuits 110 collectively provide digital clock modules (DCMs). As described below in more detail, one or more IOBs 106B may be programmed to sample an output provided from FPGA 100.
FIG. 2 is a block diagram of an exemplary embodiment of a wafer probe 121 including wafer 122 in accordance with one or more aspects of the present invention. Wafer 122 may comprise a plurality of FPGAs 100 at a stage of manufacture, such as prior to packaging. Prior to packaging FPGA 100, there may be one or more pads accessible for probing FPGA 100. These pads may or may not be accessible via I/O pins after packaging FPGA 100. Wafer probe 121 is used to put an FPGA 100 of wafer 122 into a test mode for a BIST of such a device.
FIG. 3A is a block diagram of a portion of FPGA 100 configured for a duty cycle check test mode in accordance with one or more aspects of the present invention. Oscillator 130, which may be a ring oscillator as indicated by the odd number of inverters 131 in a loop configuration, provides a waveform signal 132 having a non-zero frequency to a divide-by circuit 133. Though a three stage ring oscillator is shown, more stages may be used. Furthermore, oscillator 130 may be any external (“off-chip”) clock signal source, such as a crystal oscillator, to FPGA 100, or any internal (“on-chip”) clock signal source. Divide-by circuit 133 may be implemented with a flip-flop or a DCM. Divide-by circuit 133 provides waveform signal 132 output with a duty cycle, namely test signal 132-0.
FIG. 3B is a block diagram of another portion of FPGA 100. Test signal 132-0 is provided to IOB 134. IOB 134 is a bi-directional I/O device. In IOB 134, buffers 135 and 136 are coupled in series. Input buffer 135 receives test signal 132-0 and provides test signal 132-1. Test signal 132-1 is provided as input to output buffer 136, which in turn outputs test signal 132-2.
Referring to FIGS. 3A and 3B, if divide-by circuit 133 is a divide-by-two circuit then an approximately fifty-fifty duty cycle is created for test signal 132-0. Accuracy of this fifty-fifty duty cycle depends on divide-by circuit 133. In a DCM embodiment it is currently possible to obtain a fifty-fifty duty cycle within approximately plus or minus twenty-five to fifty picoseconds. Notably, a flip-flop may be used to create a fifty-fifty duty cycle within approximately plus or minus fifty picoseconds as well. However, for simplicity, it will be assumed that a DCM embodiment for divide-by-circuit 133 is used, having a correction granularity of one tap equivalent to approximately fifty picoseconds.
Input buffer 135 is used to output test signal 132-1 to pad 137. Pad 137 may be accessible by a pin 139 after packaging of FPGA 100, or it may be a pad which is not accessible by an I/O pin after packaging FPGA 100.
Test signal 132-1 may have a duty cycle which is no longer fifty-fifty within approximately 50 picoseconds. This is because threshold voltages for n-type and/or p-type transistors used to form CMOS input buffer 135 may not have equal drive. Ratio of n-type to p-type threshold voltage is conventionally specified to provide a fifty-fifty duty cycle for an output driver 135 of an IOB 134. Access to signal 132-1 may be via pad 137, as indicated by path 199, or via output 132-2 of output buffer 136. Conventionally output buffer 136 is made using the same CMOS process as input buffer 135. Thus, any change in duty cycle from test signal 132-0 to test signals 132-1 and 132-2 caused by IOB 134 are provided by duty cycle check circuit 138. Whether test signal 132-1 is monitored from pad 137 or test signal 132-2 is monitored from output buffer 136, in either embodiment such signal is going to be provided to duty cycle check circuit 138.
FIGS. 4 and 5 are block diagrams of respective exemplary embodiments of duty-cycle check circuit 138. Input signal 132-1 or 132-2 is provided to counter 310. An inverter 312 is used to complement such input signals provided to counter 311. A sample clock 313 is provided to counters 310 and 311 for sampling test signal 132-1 or 132-2, and its respective complement. Sample clock signal 313 is higher in frequency than frequency of test signal 132-1 and 132-2. For purposes of example, it shall be assumed that frequency of a test signal is approximately 100 megahertz and frequency of a sample clock is approximately 500 megahertz.
Sample clock signal 313 is synchronized to an oscillator, namely oscillator 130 of FIG. 3A for sampling counters 310 and 311. In this manner, counter 310 will count a one if a logic high signal is sampled for signal 132-1 or 132-2, and counter 311 will count a one if a logic low signal is sampled for signal 132-1 or 132-2. Logic high-count output 314 and logic low count output 315 are provided to ratio-of-counts circuit 316. Ratio-of-counts circuit 316 provides ratio output 317. The ratio-of-counts output 317, indicates duty cycle of a sampled test input signal. Thus, if duty cycle is not between a predetermined minimum and maximum, duty cycle ratio signal 317 will provide an indication.
In order for counting highs and lows to be effective, sampling must be sufficiently long, since a statistically sufficient count is to be obtained. It may take some time to obtain a statistically sufficient number of samples, so a faster embodiment may instead be employed.
FIG. 5 is a block diagram of an alternative embodiment of duty cycle check circuit 138. Test input signal 132-1 or 132-2 is provided to a DCM 318 of FPGA 100. DCM 318 is configured to provide a phase adjusted output signal 320 for test input signal 132-1 or 132-2, respectively. This phase adjusted output signal is set to be at approximately 180° from test input signal 132-1 or 132-2.
A variable phase shift signal 319 is provided to DCM 318 to adjust the phase of signal 320 such that there is approximately a 180° phase separation between input and output. Phase adjusted signal 320 and test signal 132-1 or 132-2 are provided to phase compare logic 322. Phase compare logic 322 compares the phases of these two input signals to provide phase relationship output signal 323.
In the event that duty cycle is no longer fifty-fifty, phase relationship signal 323 will indicate this, since phase adjusted signal 320 will not be 180° out of phase with an input test signal 132-1 or 132-2. Thus, phase relationship signal 323 may be used to adjust variable phase shift signal 319, namely to adjust phase such that edges line up such as by selecting fewer or more taps on a DLL, as described below in more detail.
The number of taps of adjustment needed such that signal 320 is 180° out of phase with signal 132-1 or 132-2, indicates the amount that duty cycle was out of adjustment from signal 132-0. For example, if there were 256 taps, zero to 255, then a signal may be divided into such increments. Thus, for a particular range of acceptable duty cycles, a tap of a corresponding selection of taps (and therefore tap delays) may be selected to produce a phase adjust signal 320 that is 180° out of phase with test signal 132-1 or 132-2. If signal 319 cycled through taps such that no tap 126 through 130, produced an acceptable result, then it could be determined that duty cycle had been shifted to a degree causing failure of a part, or needing adjustment. Signals 314, 315 of FIG. 4 or signals 320, 132-1 or 132-2 of FIG. 5, may be provided to a wafer probe to produce signals 317 or 323, respectively. However, since a PLD may be programmed to provide the functions of blocks 316 or 322, fewer instructions need to be provided to such a wafer probe. This is important, since wafer probes conventionally have less bandwidth than PLDs. Moreover, if signal 317 or 323 is coupled to an I/O pin 139 then a tester 325 may be used to check duty cycle. Thus, signals 317 and 323 may be used to indicate whether a device passes or fails the test for duty cycle.
IOB with DCI
FIG. 6 is a circuit diagram of an output driver 200. Output driver 200 includes digitally controlled impedance (DCI) circuit 201, p-channel pull-up transistors P1-P7 and P11-P15, n-channel pull-down transistors N1-N7 and N11-N15, and I/O pad 202. P-channel pull-up transistors P1-P7 and P11-P15 are collectively referred to as p-channel transistors 211, and n-channel pull-down transistors N1-N7 and N11-N15 are collectively referred to as n-channel transistors 212. In other embodiments, other combinations of transistors can be used.
As described in more detail below, p-channel transistors P1-P7 are used as “fine-adjustment” transistors, each having an on-conductance of “YP” siemens. Similarly, n-channel transistors N1-N7 are used as “fine-adjustment” transistors, each having an on-conductance of “YN” siemens. P-channel transistors P11-P15 are used as “coarse-adjustment” transistors, having on-conductances of 1XN, 2XN, 4XN, 8XN, and 16XP, siemens, respectively. N-channel transistors N11-N15 are also used as “coarse-adjustment” transistors, having on-conductances of 1XN, 2XN, 4XN, 8XN and 16XN siemens, respectively. In the described embodiment, YP is approximately equal to XP, and YN is approximately equal to XN/2. In other embodiments, other conductance values can be used.
Each of fine p-channel transistors P1-P7 and coarse p-channel transistors P11-P15 has a source coupled to a VCC voltage supply terminal. Each of fine n-channel transistors N1-N7 and coarse n-channel transistors N11-N15 has a source coupled to a ground voltage supply terminal. The drains of transistors P1-P7, P11-P15, N1-N7 and N11-N15 are coupled to I/O pad 202.
The gates of fine p-channel transistors P1-P7 are coupled to receive control signals FP1-FP7 respectively, from DCI circuit 201. Similarly, the gates of coarse p-channel transistors P11-P15 are coupled to receive control signals CP11-CP15, respectively, from DCI circuit 201.
The gates of fine n-channel transistors N1-N7 are coupled to receive control signals FN1-FN7, respectively, from DCI circuit 201. Similarly, the gates of coarse n-channel transistors N11-N15 are coupled to receive control signals CN11-CN15, respectively, from DCI circuit 201.
DCI circuit 201 is configured to receive a data input signal DIN and a tri-state signal 3ST, each having a logic high or logic low value. In general, if signal 3ST has a logic low value (i.e., driver 200 is not tri-stated) and the DIN signal has a logic low value, DCI circuit 201 asserts one or more of the control signals FP1-FP7, CP11-CP15 to a logic low value, thereby turning on one or more of p-channel transistors P1-P7, P11-P15. DCI circuit 201 also provides logic low control signals FN1-FN7, CN11-CN15, thereby turning off all of n-channel transistors N1-N7 and N11-N15. As a result, pad 202 is coupled to the VCC voltage supply terminal through the turned-on p-channel transistors. DCI circuit 201 selects the turned-on p-channel transistors to provide a particular resistance between the VCC voltage supply terminal and pad 202.
If signal 3ST has a logic high value, then output driver circuit 200 is tri-stated and will generally not drive pad 202. However, if output driver circuit 200 is used to provide a transmission line termination (as described in more detail below), then output driver circuit 200 will be configured to turn on a combination of n-channel and/or p-channel transistors to provide the appropriate transmission line termination resistance. In this case, signal 3ST has no effect on the line termination.
In the examples described below, coarse p-channel transistors P11-P15 are enabled in a binary count order to provide a coarse resistance adjustment. Fine p-channel transistors P1-P7 are then enabled or disabled to provide a fine resistance adjustment. For example, fine p-channel transistors P1-P3 and coarse p-channel transistor P13 may be turned on when the DIN signal has a low value. In this example, the equivalent conductance of the p-channel portion of output driver circuit 200 would be equal to XP+XP+XP+4XP, or 7XP, siemens.
If signal 3ST has a logic low value and the DIN signal has a logic high value, then DCI circuit 201 asserts one or more of the control signals FN1-FN7, CN11-CN15 to a logic high value, thereby turning on one or more of n-channel transistors N1-N7, N11-N15. DCI circuit 201 also provides logic high control signals FP1-FP7, CP11-CP15, thereby turning off all of p-channel transistors P1-P7 and P11-P15. As a result, pad 202 is coupled to the ground terminal through the turned-on n-channel transistors. DCI circuit 201 selects the turned-on n-channel transistors to provide a particular resistance between the ground terminal and pad 202.
In the examples described below, the coarse n-channel transistors N11-N15 are turned on in a binary count order to provide a coarse resistance adjustment. Fine n-channel transistors N1-N7 are then enabled or disabled to provide a fine resistance adjustment. For example, fine n-channel transistors N1-N2 and coarse n-channel transistors N11 and N14 may be turned on when the DIN signal has a high value. In this example, the equivalent conductance of the n-channel portion of output driver circuit 200 would be equal to XN/2+XN/2+XN+8XN, or 10XN siemens.
A chip will include a plurality of output driver circuits identical to output driver circuit 200. In general, one output driver circuit is selected to be a p-channel reference circuit, which is used to determine which p-channel transistors must be turned on to provide a desired resistance for a logic high output value or a desired transmission line termination. Similarly, one output driver circuit is selected to be an n-channel reference circuit, which is used to determine which n-channel transistors must be turned on to provide a desired resistance for a logic low output value or a desired transmission line termination. The determinations made by the p-channel and n-channel reference circuits are then transmitted to, and used by, other active output driver circuits.
FIG. 7 is a circuit diagram illustrating the general manner in which p-channel transistors P1-P7 and P11-P15 of output driver circuit 200 are controlled with respect to an external resistance 305. That is, FIG. 7 illustrates output driver circuit 200 being used as a p-channel reference circuit. As shown in FIG. 7, external resistor 305, having a resistance of RPREF, is coupled between pad 202 and ground. Internally, pad 202 is also coupled to a positive input terminal of comparator 303. The negative input terminal of comparator 303 is coupled to receive a p-channel reference voltage VPREF from a reference voltage generator 311. In the described example, reference voltage generator 311 includes a pair of resistors 301-302 connected in series between the VCC voltage supply and the ground supply. Resistors 301-302 are connected at a common node, which provides the VPREF voltage. In the described example, resistors 301-302 each have a resistance of R ohms. As a result, the reference voltage VPREF has a value of approximately VCC/2. The voltage on pad 202 will exhibit a voltage of approximately VCC/2 when the equivalent on-resistance of the enabled p-channel transistors 211 is approximately equal to the resistance RPREF of reference resistor 305. In other examples, other resistance values and ratios can be used for resistors 301 and 302.
DCI circuit 201 operates as follows. Initially, all of the p-channel transistors P1-P7 and P11-P15 are turned off. As a result, the voltage on pad 202 is pulled down to a voltage less than the reference voltage VPREF. As a result, comparator 303 provides a logic low HI_LO_P output signal.
DCI circuit 201 then asserts logic low control signals FP1-FP31 thereby turning on fine p-channel transistors P1-P3 (3XP siemens). If the equivalent resistance of fine p-channel transistors P1-P3 is greater than the resistance RPREF, then the voltage on pad 202 will be less than the reference voltage VPREF. As a result, comparator 303 will provide a logic low HI_LO_P output signal.
In response, DCI circuit 201 asserts a logic low control signal CP11, thereby turning on coarse p-channel transistor P11 (XP siemens) (along with fine p-channel transistors P1-P3).
Note that fine p-channel transistors P1-P7 are set near the midpoint of their range by initially turning on three of these transistors P1-P3 while the coarse p-channel transistors are selected. This enables the fine p-channel transistors P1-P7 to maintain an appropriate operating range when the resistance needs to be increased or decreased.
If the equivalent resistance of fine p-channel transistors P1-P3 and coarse p-channel transistor P11 is still greater than the resistance RPREF, then the voltage on pad 202 will still be less than the reference voltage VPREF. As a result, comparator 303 will again provide a logic low HI_LO_P output signal. In response, DCI circuit 201 de-asserts coarse control signal CP11 (high), and asserts coarse control signal CP12 (low), thereby turning on coarse p-channel transistor P12 (2XP siemens) (along with fine p-channel transistors P1-P3).
If the equivalent resistance of fine p-channel transistors P1-P3 and coarse p-channel transistor P12 is still greater than the resistance RPREF, then the voltage on pad 202 will still be less than the reference voltage VPREF. As a result, comparator 303 will again provide a logic low HI_LO_P output signal. In response, DCI circuit 201 asserts both coarse control signals CP11 and CP12 (low), thereby turning on coarse p-channel transistors P11-P12 (3XP siemens) (along with fine p-channel transistors P1-P3).
This sequence continues, with coarse p-channel transistors P11-P15 being turned on in a binary count order (e.g., in combinations achieving conductances of 1XP, 2XP, 3XP, 4XP, 5XP, 6XP . . . ) until the equivalent resistance of fine p-channel transistors P1-P3 and the enabled coarse p-channel transistors is less than the reference resistance RPREF. At this time, the voltage on pad 202 will be greater than reference voltage VPREF, thereby providing a logic high HI_LO_P signal. In response, DCI circuit 201 returns the coarse p-channel transistors to the binary count prior to the binary count that caused the HI_LO_P signal to go high.
For example, if the equivalent resistance of fine p-channel transistors P1-P3 and coarse p-channel transistors P12 and P13 (6XP) is less than reference resistance RPREF, then a logic high HI_LO_P signal will be generated. In response, DCI circuit 201 de-asserts control signal CP12 (high), thereby turning off coarse p-channel transistor P12. DCI circuit 201 also asserts logic low control signals CP1 and CP13, thereby turning on coarse p-channel transistors P11 and P13 (5XP). Coarse p-channel transistors P11 and P13 are thereby selected to be the only turned-on coarse p-channel transistors for the duration of the present operating scheme. All further adjustments in the on-resistance of p-channel transistors 211 are made by enabling and disabling fine p-channel transistors P1-P7.
After the coarse adjustment described above, if coarse p-channel transistors P11 and P13 and fine p-channel transistors P1-P3 present an equivalent resistance that is greater than reference resistance RPREF, comparator 303 again provides a logic low HI_LO_P signal to DCI circuit 201. Because the coarse transistors P11 and P13 have been set, DCI circuit 201 will only adjust the fine p-channel transistors at this time. Thus, DCI circuit 201 asserts the FP4 control signal (in addition to the FP1-FP3, CP11 and CP13 signals), thereby turning on fine p-channel transistor P4 (in addition to fine p-channel transistors P1-P3 and coarse p-channel transistors P11 and P13). If the equivalent resistance of p-channel transistors P1-P4, P11 and P13 is less than reference resistance RPREF, then comparator 303 will provide a high HI_LO_P signal. In response, DCI circuit 201 will subsequently turn off fine p-channel transistor P4.
If the equivalent resistance of fine p-channel transistors P1-P4 and coarse p-channel transistors P11 and P13 is greater than reference resistance RPREF, then comparator 303 will again provide a low HI_LO_P output signal. In response, DCI circuit 201 will assert the FP5 signal (in addition to the FP1-FP4, CP11 and CP13 signals), thereby turning on fine p-channel transistor P5 (in addition to fine p-channel transistors P1-P4 and coarse p-channel transistors P11 and P13). If the equivalent resistance of p-channel transistors P1-P5, P11 and P13 is less than (or greater than) reference resistance RPREF, then comparator 303 will provide a high (or low) HI_LO_P output signal. Operation continues in this manner, with the fine p-channel transistors being adjusted as required. As a result, the equivalent resistance of the turned on p-channel transistors will have a predetermined relationship with the reference resistance RPREF. Advantageously, the number of turned on p-channel transistors will be further modified in response to the operating conditions of the system (e.g., changes in temperature and/or voltage) to maintain the equivalent resistance.
As described in more detail below, information identifying the enabled transistors in the p-channel reference circuit (FIG. 7) is transmitted to other output driver circuits, such that these other output driver circuits are operated by enabling the same transistors as the p-channel reference circuit.
FIG. 8 is a circuit diagram illustrating the general manner in which n-channel transistors N1-N7 and N11-N15 of output driver circuit 200 are matched with an external resistance 405. That is, FIG. 8 illustrates output driver circuit 200 being used as an n-channel reference circuit. As shown in FIG. 8, external resistor 405, having a resistance of RNREF, is coupled between pad 202 and the VCC supply terminal. Internally, pad 202 is also coupled to the positive input terminal of comparator 403. The negative input terminal of comparator 403 is coupled to receive a reference voltage VNREF from a reference voltage generator 411. In the described example, reference voltage generator 411 includes a pair of resistors 401-402 connected in series between the VCC supply terminal and the ground terminal. Resistors 401-402 are connected at a common node, which provides the VNREF voltage. In the described example, resistors 401-402 each have a resistance of R ohms. As a result, the reference voltage VNREF has a value of approximately VCC/2. The voltage on pad 202 will exhibit a voltage of approximately VCC/2 when the resistance provided by the turned on n-channel transistors is approximately equal to the resistance RNREF of reference resistor 405.
DCI circuit 201 selects the n-channel transistors to be enabled in the same manner that the p-channel transistors are selected, as described above in connection with FIG. 7. Thus, all of the n-channel transistors N1-N7 and N11-N15 are initially turned off by DCI circuit 201. Fine n-channel transistors N1-N3 are then turned on by DCI circuit 201. If necessary, coarse n-channel transistors N11-N15 are turned on in a binary count order until comparator 403 provides a logic low HI_LO_N output signal. Upon detecting the logic low HI_LO_N output signal, DCI circuit 201 enables the coarse n-channel transistors corresponding with the previous binary count, and makes all further adjustments using the fine n-channel transistors N1-N7.
As described in more detail below, information identifying the enabled transistors in the n-channel reference circuit (FIG. 8) is transmitted to other output driver circuits, such that these other output driver circuits are operated by enabling the same transistors as the n-channel reference circuit. As a result, the output driver circuits will be referenced to external reference resistances. This advantageously optimizes the operation of the output driver circuits.
In another embodiment, instead of the linear search algorithm described above, a binary search algorithm can be used to determine the P or N channel transistors to be turned on.
In accordance with one embodiment, adjustments made by DCI circuit 201 can be dynamically enabled or disabled. For example, after DCI circuit 201 has determined which coarse and fine p-channel transistors should be turned on, and which coarse and fine n-channel transistors should be turned on, DCI circuit 201 can be prevented from making further changes to the enabled and disabled transistors. Thus, if DCI circuit 201 initially determines that p-channel transistors P1-P3, P13 and P15 should be turned on, then further adjustments by DCI circuit 201 can be disabled, thereby causing this p-channel determination to be used, without change, until the DCI circuit 201 is re-enabled.
In the embodiment described above, both of the reference voltages VPREF and VNREF have a value of approximately VCC/2, thereby causing the p-channel transistors to be referenced to reference resistance 305 (RPREF) and the n-channel transistors to be referenced to reference resistance 405 (RNREF). In another embodiment, the reference voltages VPREF and VNREF can be modified to have values of approximately 2VCC/3 and VCC/3, respectively. This effectively references the p-channel transistors to 1⁄2 of the reference resistance 305 (RPREF), and references the n-channel transistors to 1⁄2 of the reference resistance 405 (RNREF). In other embodiments, the reference voltages VPREF and VNREF can be modified to have other values, such that the turned on transistors will have different relationships to the reference resistors 305 and 405. This advantageously allows reference resistors having different values to be used.
In another embodiment, external reference resistor 405 can be eliminated. In this embodiment, the reference resistance for the n-channel reference circuit is provided by turning on the p-channel transistors 211 determined by the p-channel reference circuit in response to reference resistor 305. Thus, if the p-channel reference circuit determines that coarse p-channel transistors P13 and P15 and fine p-channel transistors P1-P4 must be turned on to provide the desired correspondence with reference resistor 305, then transistors equivalent to P1-P4, P13 and P15 are turned on in the n-channel reference circuit. The n-channel reference circuit then determines which n-channel transistors 212 should be turned on to correspond with the turned on p-channel transistors in the output driver circuit. In this manner, the n-channel transistors 212 turned on by the n-channel reference circuit are indirectly referenced to the external reference resistance RPREF 305.
In a similar manner, external reference resistor 305 can be eliminated. In this embodiment, the n-channel reference circuit determines which n-channel transistors should be turned on in response to the external reference resistance 405 (RNREF). This information is then transmitted to the p-channel reference circuit, such that the same n-channel transistors are turned on in the p-channel reference circuit. The p-channel reference circuit then determines which p-channel transistors should be turned on to correspond with the turned on n-channel transistors. In this manner, the p-channel transistors turned on by the p-channel reference circuit are indirectly referenced to the external reference resistance 405.
As described above, adjusting the p-channel and n-channel transistors to be enabled in an output driver circuit in response to reference resistances advantageously enables the output driver circuit to exhibit a particular resistance with respect to reference resistors. An output driver circuit that is adjusted in this manner will be referred to as a digitally controlled impedance (DCI) output driver circuit. FIG. 9A is a circuit diagram illustrating a DCI output driver circuit 501 that has a digitally controlled impedance Z. Impedance Z is selected to correspond with the impedance Z0 of a line 502 located between the DCI driver circuit 501 and a receiver circuit 503.
In another embodiment, DCI circuit 201 is bypassed, such that some or all of the p-channel transistors 211 are turned on to provide a logic high output signal, and some or all of the n-channel transistors 212 are turned on to provide a logic low output signal. FIG. 9B is a circuit diagram illustrating an output driver circuit 504 in which DCI circuit 201 has been bypassed. Although output driver circuit 504 will exhibit an impedance, this impedance is not controlled to have a particular correspondence with the impedance Z0 of line 502.
DCI circuit 201 can also be controlled to turn on user-selected p-channel transistors to provide a logic high output signal, and to turn on user-selected n-channel transistors to provide a logic low output signal. For example, DCI circuit 201 can be controlled to turn on only the coarse p-channel transistors P11-P15 to provide a logic high output signal, and to turn on only the coarse n-channel transistors N11-N15 to provide a logic low output signal, regardless of the external impedance Z0. This alternative is described in more detail in commonly owned U.S. Pat. No. 5,877,632, which is hereby incorporated by reference.
In addition to controlling the turned on transistors of output driver circuit 200 to correspond with an external impedance Z0, DCI circuit 201 can be controlled to provide a transmission line termination resistance. As illustrated in FIG. 10A, it is common to provide external termination resistors 601-602, which are coupled between the ends of line 502 and a VCC supply voltage terminal. In FIG. 10A, output driver circuit 501 is coupled to an input buffer 513 at one end of line 502, thereby providing an input/output I/O configuration. Similarly, input buffer 503 is coupled to output driver circuit 511 at the other end of line 502.
As illustrated in FIGS. 10B and 10C, termination resistors 611 and 612 can be implemented using the digitally controlled impedance of output driver circuits 501 and 511, respectively, thereby eliminating the need for external termination resistors 601 and 602. To determine the p-channel transistors to be turned on to implement termination resistors 611 and 612, the DCI circuits in output driver circuits 501 and 511 are referenced to a known resistance in response to reference voltages VPREF and VNREF having values of approximately VCC/2 and VCC/2, respectively. Advantageously, the termination resistance is controlled with respect to external reference resistors and can be adjusted for changes in temperature, voltage and/or process.
Within output driver circuits 501 and 511, a user-selected set of p-channel transistors is used to drive a logic high output signal. For example, the coarse p-channel transistors P11-P15 may be selected to drive a logic high output signal in response to a corresponding input data signal. In this example, a subset of the fine p-channel transistors P1-P7 is selected to provide the termination resistance. While the coarse p-channel transistors are only turned on to drive a logic high output signal, the selected subset of fine p-channel transistors P1-P7 are turned on at all times to provide the desired termination resistance. In other embodiments, other combinations of coarse and fine transistors can be used to serve as the user-selected transistors and the termination transistors.
FIG. 10B illustrates a signal D1 being driven from output driver 511 to input buffer 513. At this time, output driver 511 is configured in a manner described above. That is, output driver 511 provides logic high and low output signals by turning on user-selected transistors (e.g., all coarse p-channel transistors or all coarse n-channel transistors). In addition, a second set of p-channel transistors in driver circuit 511 are turned on to implement termination resistor 612. A tri-state signal applied to output driver circuit 501 is asserted, such that this output driver circuit 501 is not responsive to signals applied to its input terminal. However, the set of p-channel transistors in output driver circuit 501 that have been selected to implement termination resistor 611 remain turned on. As a result, the desired termination resistances 611 and 612 are provided between line 502 and the VCC supply terminal.
FIG. 10C illustrates a signal D2 being driven from output driver 501 to input buffer 503. At this time, output driver 501 is configured in the same manner as output driver circuit 511 of FIG. 10B, such that this output driver 501 provides logic high and low output signals by turning on user-selected transistors, and provides the termination resistor 611 by turning on the set of p-channel transistors that have been selected to implement this termination resistor. A tri-state signal applied to output driver circuit 511 is asserted, such that this output driver circuit 511 is not responsive to signals applied to its input terminal. However, the set of p-channel transistors in output driver circuit 511 that have been selected to implement termination resistor 612 remain turned on. As a result, the desired termination resistances 611 and 612 are provided between line 502 and the VCC supply terminal. In this manner, output driver circuits 501 and 511 provide termination resistances 611 and 612, respectively, for bi-directional signal transfer on line 502. The terminations illustrated in FIGS. 10B-10C are referred to as single terminations, because a single set of transistors is used to provide each termination.
As illustrated in FIG. 11A, it is also common to provide external termination resistors 701 and 702, which are coupled between the ends of line 502 and a VCC/2 supply voltage terminal.
As illustrated in FIGS. 11B and 11C, termination resistors 711-712 and 713-714 can be implemented using the DCI circuits of driver circuits 501 and 511, respectively, thereby eliminating the need for external termination resistors 701 and 702 and the VCC/2 power supply. Each of resistors 711-714 is determined to have a resistance that is equal to twice the resistance of resistor 701 (or 702). As a result, resistors 711-712 and 713-714 are the Thevenin equivalents of resistors 701 and 702, respectively.
To determine the p-channel and n-channel transistors to be turned on to implement termination resistors 711-714, the DCI circuits in output driver circuits 501 and 511 are referenced to known resistances in response to reference voltages VPREF and VNREF having values of approximately 2VCC/5 and 3VCC/5, respectively. Advantageously, impedance is controlled with respect to external reference resistors and can be adjusted for changes in temperature, voltage and/or process.
FIG. 11B illustrates a signal D1 being driven from output driver 511 to input buffer 513. At this time, output driver 511 is configured in the same manner as output driver circuit 511 of FIG. 10B, such that this output driver 511 provides logic high and low output signals by turning on user-selected transistors, and provides termination resistances 713 and 714 by turning on the p-channel and n-channel transistors that have been determined to provide these desired termination resistances 713 and 714. A tri-state signal applied to output driver circuit 501 is asserted, such that this output driver circuit 501 is not responsive to signals applied to its input terminal. However, the p-channel transistors and the n-channel transistors that have been determined to provide the desired termination resistances 711 and 712 remain turned on in output driver 501. As a result, output driver circuit 501 provides the equivalent of termination resistance 701 coupled between line 502 and a VCC/2 supply terminal. Similarly, output driver circuit 511 provides the equivalent of termination resistance 702 between line 502 and a VCC/2 supply terminal.
FIG. 11C illustrates a signal D2 being driven from output driver 501 to input buffer 503. At this time, output driver 501 is configured in the same manner as output driver circuit 511 of FIG. 11B, and output driver 511 is configured in the same manner as output driver circuit 501 of FIG. 11B. In this manner, output driver circuits 501 and 511 provide termination resistances 711-712 and 713-714, respectively, for bi-directional signal transfer on line 502.
The terminations illustrated in FIGS. 11B-11C are referred to as split terminations, because two sets of transistors are required to provide each termination.
The variations illustrated in FIGS. 9A-9B, 10A-10C and 11A-11C, as well as the manner of transmitting information from the p-channel and n-channel reference circuits to other output driver circuits, will now be described in more detail. Other information about such circuits is provided in U.S. Pat. No. 6,445,245, the content of which is incorporated herein by reference.
FIG. 12 is a block diagram of an integrated circuit chip 800. IC chip 800 includes eight input/output block (IOB) banks 801-808 and core logic 810. IOB banks 801-808 are substantially identical. In one embodiment, core logic 810 includes an array of configurable logic blocks and programmable interconnect circuitry. However, other core logic is contemplated. In general, IOB banks 801-808 provide an interface between core logic 810 and circuitry external to chip 800.
In the described embodiment, two IOB banks are located along each edge of IC chip 800, with each IOB bank having 20 to 150 IOBs. An exploded view illustrates that IOB bank 801 includes a plurality of IOBs 901-905 and a bank impedance control (BIC) circuit 910. A further exploded view illustrates that IOB 901 includes output driver circuit 911, comparator 921, input buffer circuit 931, I/O pad 941 and local digitally controlled impedance (DCI) circuit 961. Yet another exploded view illustrates that bank impedance control circuit 910 includes a bank digitally controlled impedance (DCI) circuit 960 and bank reference voltage generator 970. As described in more detail below, local DCI circuit 961 and bank DCI circuit 960 combine to perform the functions of DCI circuit 201 (FIGS. 6-8). As also described in more detail below, bank reference voltage generator 970 provides the reference voltages that are used by IOBs 901-905. Thus, bank reference voltage generator 970 performs the functions of reference voltage circuits 311 and 411 (FIGS. 7 and 8).
In another embodiment, only one bank impedance control circuit 910 is provided for the entire chip 800. In this embodiment, bank impedance control circuit 910 provides the necessary control for all of the local DCI circuits on chip 800. In another embodiment, there are multiple bank impedance control circuits, which are capable of controlling one or more IOB banks.
FIG. 13 is a circuit diagram illustrating selected portions of IOB bank 801, including bank impedance control circuit 910 and IOBs 901-904. Note that the input buffer circuits (e.g., input buffer circuit 931) are not shown in FIG. 13 for purposes of clarity. IOBs 901-904 include respective local DCI circuits 961-964, respective output driver circuits 911-914, respective comparators 921-924 and respective I/O pads 941-944. Each of output driver circuits 911-914 includes a set of p-channel transistors 211 and a set of n-channel transistors 212, as described above in connection with FIGS. 6-8.
In a low voltage differential signaling (LVDS) embodiment, reference voltage generator 970 provides the n-channel reference voltage, VNREF, and the p-channel reference voltage VPREF, on lines that extend through IOB bank 801. The comparator in every odd numbered IOB (e.g., 901, 903, 905) in IOB bank 801 is coupled to receive the VPREF, voltage. The comparator in every even numbered IOB (e.g., 902, 904) in IOB bank 801 is coupled to receive the VNREF voltage.
The output terminals of the comparators in odd numbered IOBs are coupled to programmable connections (e.g., 951, 953), which if programmed, will connect a corresponding comparator to a common HI_LO_P line. Similarly, the output terminals of the comparators in even numbered IOBs are coupled to programmable connections (e.g., 952, 954), which if programmed, will connect a corresponding comparator to a common HI_LO_N line. The HI_LO_P line and the HI_LO_N line are routed to bank DCI circuit 960.
Bank DCI circuit 960 also provides control signals to local DCI circuits 961-964. These control signals will be described in more detail below. In general, IOB bank 801 operates as follows. One of the odd-numbered IOBs is selected to be a p-channel reference circuit, and one of the even-numbered IOBs is selected to be an n-channel reference circuit. This selection is made by setting a configuration memory bit in the local DCI circuit of each of these IOBs, and programming the connection to couple the output terminals of the comparators of these IOBs to the HI_LO_N and HI_LO_P lines. Although any one of the odd-numbered IOBs can be selected to be the p-channel reference circuit, IOB 901 is selected in the described embodiment. Thus, a configuration memory bit in local DCI circuit 961 is set, and programmable connection 951 is enabled. Similarly, although any one of the even-numbered IOBs can be selected to be the n-channel reference circuit, IOB 902 is selected in the described embodiment. Thus, a configuration memory bit in local DCI circuit 962 is set, and programmable connection 952 is enabled.
Because IOB 901 is to serve as the p-channel reference circuit, a predetermined reference resistance RPREF is connected between pad 941 and the ground terminal in the manner illustrated in FIG. 7. As a result, IOB 901 is configured in substantially the same manner illustrated in FIG. 7, except that the DCI circuit 201 of FIG. 7 has been divided into bank DCI circuit 960 and local DCI circuit 961.
Because IOB 902 is to serve as the n-channel reference circuit, a predetermined reference resistance RNREF is connected between pad 942 and an external VCC supply terminal in the manner illustrated in FIG. 8. As a result, IOB 902 is configured in substantially the same manner illustrated in FIG. 8, except that the DCI circuit 201 of FIG. 8 has been divided into bank DCI circuit 960 and local DCI circuit 962.
In general, IOB bank 801 operates as follows. P-channel reference circuit 901 and n-channel reference circuit 902 are initially set to have predetermined turned-on p-channel and n-channel transistors. During a first time period, bank DCI circuit 960 processes the HI_LO_P signal provided by p-channel reference circuit 901. In response, bank DCI circuit 960 instructs local DCI circuit 961 to enable/disable the p-channel transistors in driver circuit 911 in the manner described above in connection with FIG. 7. At the same time, bank DCI circuit 960 also instructs other local DCI circuits to enable/disable the same p-channel transistors as local DCI circuit 961. Thus, when logic low data signals D3-D4 are applied to local DCI circuits 963-964, these local DCI circuits will enable the same p-channel transistors determined by the p-channel reference circuit 901. For example, if bank DCI circuit 960 instructs local DCI circuit 961 in the p-channel reference circuit 901 to enable fine p-channel transistors P1-P4 and coarse p-channel transistor P14, then bank DCI circuit 960 will similarly instruct local DCI circuit 963 to enable fine p-channel transistors P1-P4 and coarse p-channel transistor P14 when data signal D3 has a logic low value.
During a second time period, bank DCI circuit 960 processes the HI_LO_N signal provided by n-channel reference circuit 902. In response, bank DCI circuit 960 instructs local DCI circuit 962 to enable/disable the n-channel transistors in driver circuit 912 in the manner described above in connection with FIG. 8. Bank DCI circuit 960 also instructs other local DCI circuits to enable/disable the same n-channel transistors as local DCI circuit 962. Thus, if bank DCI circuit 960 instructs local DCI circuit 962 in the n-channel reference circuit 902 to enable fine n-channel transistors N1-N2 and coarse n-channel transistor N13, then bank DCI circuit 960 will similarly instruct local DCI circuit 963 to enable fine n-channel transistors N1-N2 and coarse n-channel transistor N13 when data signal D3 has a logic high value.
In accordance with another embodiment, the IOB 904 can be configured in a manner different from IOB 903. For example, output driver circuit 913 of IOB 903 can be configured in response to different reference voltages (VNREF and VPREF) than output driver circuit 914 of IOB 904. As a result, output driver circuit 913 will exhibit different resistances than output driver circuit 914. This is accomplished by providing different sets of reference voltages with reference voltage supply 970.
Reference voltage supply 970 can be controlled to provide different reference voltages VPREF and VNREF at different times. For example, reference voltage supply 970 can be controlled to provide a first set of reference voltages that are used by p-channel and n-channel reference circuits 901 and 902 to determine the appropriate p-channel and n-channel transistors to be enabled within IOB 903. Reference voltage supply 970 can also be controlled to provide a second set of reference voltages that are used by p-channel and n-channel reference circuits 901 and 902 to determine the appropriate p-channel and n-channel transistors to be enabled within IOB 904. In the described embodiment, reference voltage supply 970 can be controlled to provide up to four sets of reference voltages. By providing different reference voltages, the on-resistances of different output driver circuits can be controlled to have different values, even though the resistances of the external reference resistors 305 and 405 remain constant. Bank DCI circuit 960 is able to address the local DCI circuits 961-964, such that the appropriate information is provided to the appropriate IOBs.
FIG. 14 is a circuit diagram of reference voltage supply 970. Reference voltage supply 970 includes p-channel reference voltage generator 1010, n-channel reference voltage generator 1020 and decoder circuit 1030. P-channel reference voltage generator 1010 includes transmission gates 1001-1004, resistors 1011-1014 and n-channel transistor 1021. Resistors 1011, 1012, 1013 and 1014 have relative resistances of 8R, 4R, 12R and 8R, respectively. N-channel reference voltage generator 1020 includes transmission gates 1005-1008, resistors 1015-1018, n-channel transistors 1022-1023 and p-channel transistor 1024. Resistors 1015, 1016, 1017 and 1018 have relative resistances of 8R, 8R, 4R and 12R, respectively. Decoder circuit receives address signals a[2:0] from bank DCI circuit 960, and in response, provides control signals to transmission gates, 1001-1008 and transistors 1021-1023. Table 1 summarizes the status of transmission gates 1001-1004, transistor 1021 and the p-channel reference voltage VPREF for the various address signals a[2:0].













TABLE 1





a [2:0]
1001
1002
1003
1004
1021
VPREF







000
OFF
OFF
OFF
OFF
ON
0


101


110


111


001
ON
OFF
OFF
ON
OFF
VCC/2


010
OFF
ON
OFF
ON
OFF
2 VCC/3


011
ON
OFF
OFF
ON
OFF
VCC/2


100
OFF
OFF
ON
ON
OFF
2 VCC/5









Table 2 summarizes the status of transmission gates 1005-1008, transistor 1022-1024 and the n-channel reference voltage VNREF for the various address signals a[2:0].













TABLE 2






1005



1023



a [2:0]
1022
1006
1007
1008
1024
VNREF







000
OFF
OFF
OFF
OFF
ON
0


101


110


111


001
ON
ON
OFF
OFF
OFF
VCC/2


010
ON
OFF
ON
OFF
OFF
VCC/3


011
ON
ON
OFF
OFF
OFF
VCC/2


100
ON
OFF
OFF
ON
OFF
3 VCC/5









Addresses of “001” or “010” are used to provide DCI output driver circuits with different impedances (FIG. 9A). An address of “011” is used to provide a single termination pull-up to VCC (FIG. 10B). An address of “100” is used to provide a split termination to VCC and ground (FIG. 11B).
FIG. 15 is a block diagram illustrating bank DCI circuit 960 and local DCI circuit 963 in more detail. Local DCI circuits 961-962 and 964 are identical to local DCI circuit 963.
Local DCI circuit 963 includes shift register 1101, data decoder 1102, p-channel register 1103, n-channel register 1104, configuration memory cells 1110, address decoder 1111 and logical AND gates 1121-1122. Bank DCI circuit 960 and local DCI circuit 963 operate as follows.
Configuration memory cells 1110 store four configuration bits. One of these configuration bits indicates whether IOB 903 will serve as a reference IOB. If this configuration bit is set, then address decoder 1111 will assert an ENABLE signal regardless of the state of the applied address signal a[2:0]. The remaining three configuration bits identify a “type” of the output driver circuit 913 (assuming that IOB 903 is not a reference IOB). There are five “types” of output driver circuits in accordance with the described embodiment. Table 3 defines the reference voltages used for each of the five types. Note that the contents of configuration memory cells 1110 will correspond with one of the address signals a[2:0].











TABLE 3







Type Configuration





Memory Cells 1110
VPREF
VNREF









000, 101, 110, 111
0
0



001
VCC/2
VCC/2



010
VCC/3
2VCC/3



011
VCC/2
VCC/2



100
3VCC/5
2VCC/5










If the address signal a[2:0] from bank DCI circuit 960 matches the contents of configuration memory cells 1110, then address decoder 1111 will assert an ENABLE signal, thereby enabling shift register 1101. In response to this ENABLE signal (and a SCLK clock signal provided by bank DCI circuit 960), shift register 1101 will sequentially shift in the DATA signal provided by bank DCI circuit 960. The DATA signal identifies the p-channel transistors 211 or the n-channel transistors 212 to be turned on during the present iteration. Shift register 1101 provides the loaded DATA values to data decoder 1102.
Bank DCI circuit 960 provides a N_OR_P control signal to data decoder 1102, thereby indicating whether the contents of shift register 1101 are intended to control the p-channel transistors 211 (N_OR_P=0), or the n-channel transistors 212 (N_OR_P=1) of output driver circuit 913. Bank DCI circuit 960 initially provides a N_OR_P signal having a logic “0” value. In response, data decoder 1102 will decode the contents of shift register 1101, and transmit the results to p-channel register 1103.
Bank DCI circuit 960 then asserts a logic high UPDATE signal, which causes AND gate 1121 to assert a logic high UPDATE_P signal. In response, p-channel register 1103 loads the results provided by data decoder 1102. The contents of p-channel register 1103 are then used to control p-channel transistors P1-P7 and P11-P15 in the manner described above.
Data decoder 1102 operates as follows. Data decoder receives the 8-bit signal D[7:0] received from shift register 1101. The D[7:0] signal includes five bits D[7:3] to control coarse transistors (i.e., coarse p-channel transistors P11-P15 or coarse n-channel transistors N11-N15). These five bits D[7:3] are routed directly through decoder 1102 to either register 1103 or 1104 in response to the N_OR_P signal. The D[7:0] signal also includes three bits D[2:0] to control fine transistors (i.e., fine p-channel transistors P1-P7 or fine n-channel transistors N1-N7). Decoder 1102 provides signals that will turn on 0 to 7 of the fine transistors in response to the D[2:0] bits.
The operation of IOB bank 801 will now be summarized. First, one of IOBs 901-905 is configured as a p-channel reference circuit, and another one of IOBs 901-905 is configured as an n-channel reference circuit. The remaining IOBs are configured to have a particular ‘type’ (e.g., a first type, a second type, etc.) by appropriately programming the configuration memory cells 1110 within the IOBs.
Bank DCI circuit 960 then asserts a first address signal a1[2:0] (e.g., “001”) and a first data signal D1[7:0]. The first address signal a1[2:0] causes reference voltage circuit 970 to generate a first pair of reference voltages VPREF1 and VNREF1 (e.g., VCC/2 and VCC/2). The first data signal D1[7:0], which identifies p-channel transistors to be enabled, is latched into the p-channel reference IOB. The first address signal a1[2:0] also causes the first data signal D1[7:0] to be latched into all of the IOBs of the first type.
The bank DCI circuit 960 then provides a logic low N_OR_P signal and a logic high UPDATE signal, thereby causing the first data signal D1[7:0] to be decoded and used to control the p-channel transistors in both the p-channel reference circuit and the IOBs of the first type. In response, the p-channel reference circuit provides a HI_LO_P signal having a logic high or low value to bank DCI circuit 960. This process is repeated until the p-channel reference circuit has provided the desired p-channel settings to all of the IOBs of the first type.
The address signal a[2:0] is then incremented to the second type (“010”), such that the reference voltage circuit 970 generates a second pair of reference voltages. In response, the p-channel reference circuit is used to provide the desired p-channel settings to all of the IOBs of the second type.
This process is repeated such that the desired p-channel settings are provided for all of the different types of IOBs. The n-channel reference circuit is then used to provide the desired n-channel settings for the different types of IOBs.
To provide the desired settings for the n-channel transistors, bank DCI circuit 960 asserts the first address signal a1[2:0] and then provides a data signal D2[7:0]. This data signal D2[7:0], which identifies n-channel transistors to be enabled, is latched into the n-channel reference circuit. The first address signal a1[2:0] also enables the second data signal D2[7:0] to be latched into all of the IOBs of the first type.
The bank DCI circuit 960 then provides a logic high N_OR_P signal and a logic high UPDATE signal, thereby causing the data signal D2[7:0] to be decoded and used to control the n-channel transistors in both the n-channel reference circuit and the IOBs of the first type. In response, the n-channel reference IOB provides a HI_LO_N signal having a logic high or low value to bank DCI circuit 960. This process is repeated until the n-channel reference circuit has provided the desired n-channel settings to all of the IOBs of the first type.
The address signal a[2:0] is then incremented to the second type (“010”), such that the reference voltage circuit 970 generates a second pair of reference voltages. In response, the n-channel reference circuit is used to provide the desired n-channel settings to all of the IOBs of the second type.
This process is repeated such that the desired n-channel settings are provided for all of the different types of IOBs. The process then repeats, with the p-channel transistor settings being updated for the various types, and then the n-channel transistor settings being updated for the various types. In this manner, the p-channel and n-channel determinations are continuously being updated for each type during operation of the chip.
Note that IOBs can be excluded from this process by programming the configuration memory cells 1110 to store a 3-bit value of “000”, “101”, “110” or “111”. In this case, the p-channel and n-channel transistors to be enabled are determined by the user programming configuration memory cells.
Though connection with the control of output driver circuits has been described, it is understood that the DCI may be applied to circuits which do not drive output signals. For example, selection of which parallel-connected transistors should be turned on between any node and a voltage supply terminal may be done. In addition the DCI block 201 can be implemented as a state machine. In addition, although p-channel transistors have been used as pull-up elements, and n-channel transistors have been used as pull-down elements, n-channel transistors can be used as pull-up elements and p-channel transistors can be used as pull-down elements in other embodiments.
Duty Cycle Adjust System
Referring to FIG. 16A, there is shown a block diagram of an exemplary embodiment of a Duty Cycle Adjust System 360 in accordance with one or more aspects of the present invention. Duty Cycle Adjust System 360 comprises a drive adjust 350, reference voltage 970, one or more IOBs 901, 902, 903, 904, and one or more duty cycle check circuits 138. A duty cycle adjust enable signal 351 is provided to drive adjust 350. Duty cycle adjust enable signal 351 is to inform drive adjust 350 of a selected duty cycle to be used, such as a 50-50 duty cycle, a 60/40 duty cycle, a 40/60 duty cycle, or some other desired duty cycle with respect to n-channel and p-channel drive transistors. As mentioned above, I/O drive transistors may be selected in order to provide a desired impedance. Moreover, such I/O n-channel and p-channel type transistors may be selected to provide a desired duty cycle, as is explained. Drive adjust circuit 350 provides drive adjust address 352 in response to a desired duty cycle as indicated by duty cycle adjust enable signal 351.
Drive adjust address signal 352 is provided to reference voltage generator 970. Reference voltage generator 970 provides n-channel and p-channel reference voltages, namely, VNREF and VPREF voltages. These reference voltages are provided to an IOB, such as IOB 901, 902, 903 and 904. Conventionally n-channel and p-channel transistors formed from a same process on a same semiconductor integrated circuit and in near proximity to one another will behave substantially similarly, that is all n-channel transistors will act substantially similar to one another and all p-channel transistors will act substantially similar to one another, so it is possible to provide only two respective n-channel and p-channel reference voltages to a plurality of IOBs.
However, if one so desires, it is possible to have different duty cycles on different I/O's. Thus, a plurality of duty cycle adjust enable signals 351 may be provided to a plurality of drive adjust circuits 350 to produce respective drive adjust address signals 352 to reference voltage generators 970 for generating a plurality of respective reference voltages for respective IOBs, such as IOBs 901, 902, 903, and 904. Each of these IOBs can provide a signal sample 911, 912, 913, 914 as an input to a respective duty cycle check circuit 138 to provide respective duty cycle indicator signals 317, 323. However, for simplicity, it will be assumed that only a single duty cycle indicator signal 317 or 323 is used for a plurality of IOBs, and thus use of only one output signal sample, such as output signal sample 911, is described. Accordingly, drive adjust circuit 350 receives a duty cycle indicator signal 317 or 323, and compares it to a desired duty cycle as indicated by duty cycle adjust enable signal 351. Drive adjust circuit 350 in response to this comparison can provide a new drive adjust address signal 352 to reference voltage generator 970. In the event that a duty cycle indicator signal 317 or 323 is not within an acceptable limit of a desired duty cycle as indicated by duty cycle adjust enable signal 351, reference voltage generator 970, can compensate by altering one or more reference voltages output to one or more IOBs. Of course, however, if duty cycle indicator signal 317 or 323 is within an acceptable limit, then drive adjust address signal 352 does not need to be adjusted from a prior iteration.
Alternatively, reference voltage generator 970 may be coupled to body or well bias voltages for IOBs 901, 902, 903 and 904. Thus, VNREF and VPREF voltages would be coupled to NMOS and PMOS wells, respectively, to adjust such body biases. Notably, changes in body bias to n-wells and p-wells affect threshold voltage ratio for n-channel and p-channel transistors, respectively. Notably, double isolated well structures, among other well configurations, may be used, and thus using VPREF voltages to bias an n-well to affect threshold voltage for a p-channel device, as well as using VNREF voltage to bias a p-well to affect threshold voltage for an n-channel device, may be done. By changing one or more body biases, drive strengths of PMOS and NMOS transistors may be brought into balance, or otherwise tuned, depending on application.
Referring to FIG. 16B, there is shown a block diagram of a programmable duty cycle adjust system 370. Programmable duty cycle adjust system 370 has similar elements and signals to duty cycle adjust system 360 of FIG. 16A, and for clarity similar aspects are not repeated. Programmable duty cycle adjust system 370 has drive adjust configuration memory cells 1110 instead of drive adjust circuitry 350. Drive adjust configuration memory cells 1110 may be programmed in response to a duty cycle adjust enable signal 351. Prior to programming, drive adjust configuration memory cells 1110 may have a standard duty cycle default, such as the 50/50 duty cycle. However, if some duty cycle other than the default duty cycle is desired or if duty cycle must be selected, duty cycle adjust enable signal 351 may be provided in order to cause drive adjust configuration memory cells 1110 to be programmed to provide a different drive adjust address 352 to decoder 1111 of one or more IOBs. Decoder 1111 of IOBs 901, 902, 903, 904 receives drive adjust address signal 352 in order to select one or more additional p-channel or n-channel drive transistors in order to tailor duty cycle to that programmed into drive adjust configuration memory cells 1110. Using direct addressing of an IOB to provide selection of drive transistors to adjust duty cycle avoids use of reference voltage generator 970 of FIG. 16A for this purpose. Accordingly, after direct addressing of an IOB to select drive transistors is done, output from such an IOB may be sampled as described above, and provided to one or more duty cycle check circuits 138 to provide one or more duty cycle indicator signals 317 or 323 to drive adjust configuration memory cells 1110. Duty cycle indicator signals 317 and 323 provide feed-back control to drive adjust configuration memory cells 1110 for purposes of determining whether or not output of an IOB is within acceptable limits of a desired programmed duty cycle.
Accordingly, it should be appreciated that by inferring threshold voltage ratio for n-channel and p-channel transistors, Vtn/Vtp, from duty cycle, circuits can be configured to meet performance criteria, not only off a production line, but also over time as stability of threshold voltages of transistors degrades. Moreover, threshold voltage ratio for n-channel and p-channel transistors may be changed during operation. Additionally, devices which would not yield due to threshold voltage ratio for n-channel and p-channel transistors may be adjusted to be acceptable parts. Furthermore, it should be appreciated that as devices are scaled down, threshold voltage conventionally tends be become less stable, so this ability to adjust enhances ability to scale down transistors. Note that Vtn/Vtp ratio may be adjusted as described independent of transistor size.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. For example, drive transistors were described; however, transistors for oscillators and flip-flops—especially toggle flip-flops, among other known devices dependent on Vtn/Vtp ratio may be adjusted in accordance with one or more aspects of the present invention.
FIG. 17 depicts a block diagram showing another exemplary embodiment of duty-cycle check circuit 138 in accordance with one or more aspects of the present invention. As described above, a portion of FPGA 100 is configured for duty cycle check test mode. A clock signal 1715 is coupled to a DCM 1702, which provides waveform signals 1718 and 1720 having a particular duty cycle. Though other phase relationships and duty cycles may be used, in this example it will be assumed that waveform signals 1718 and 1720 have approximately a fifty-fifty duty cycle and are approximately 180° out of phase with each other. Clock signal 1715 may or may not have the same duty cycle as waveform signals 1718 and 1720.
Waveform signals 1718 and 1720 are coupled to an output buffer 1704. Output buffer 1704 includes a portion of an exemplary implementation of IOB 134 shown in FIG. 3B. Output buffer 1704 receives waveform signals 1718 and 1720 and outputs a test signal 1705. Test signal 1705 is output via a pad 1706. Pad 1706 may be electrically accessible via a pin 1709 after packaging of FPGA 100, or it may be an unused pad, namely, a pad that is not accessible by an I/O pin after packaging FPGA 100. Output buffer 1704 outputs data on a particular edge of each of waveform signals 1718 and 1720 (e.g., a rising edge of waveform signals 1718 and 1720). If waveform signals 1718 and 1720 are 180° out of phase with each other, then output buffer 1704 operates as a double-data-rate (DDR) output buffer (i.e., output buffer 1704 operates on two clock edges per period of waveform signals 1718 and 1720).
Test signal 1705 may have a duty cycle different from that of waveforms 1718 and 1720. For example, as described above, the threshold voltages of n-type and/or p-type transistors within output buffer 1704 may be outside minimum and maximum design limits. Change in duty cycle from waveforms 1718 and 1720 with respect to test signal 1705 is detected by duty cycle check circuit 138, as describe below in additional detail.
Duty cycle check circuit 138 comprises a DCM 1714, a register 1712, and duty cycle module 1710 (“control logic”). Inputs of DCM 1714 are respectively coupled to a clock signal 1716 and a variable phase shift signal 1717. Clock signal 1716 may or may not be the same as clock signal 1715. DCM 1714 provides a sampling waveform 1722 as output. Register 1712 may be implemented as a clocked D-flip-flop or other type of clocked flip-flop known in the art. A clock input of register 1712 is coupled to sampling waveform 1722, and a data input of register 1712 is coupled to test signal 1705. Register 1712 provides an output signal 1711. Inputs of control logic 1710 are respectively coupled to clock signal 1716 and output signal 1711. One output of control logic 1710 is provided to an output pad 1708, and another output of control logic 1710 provides variable phase shift signal 1717.
In one embodiment, duty cycle check circuit 138 is formed in part using configured logic blocks of FPGA 100, where DCM 1714 is hardwired. Alternatively, duty cycle check circuit 138 may comprise dedicated logic embedded within FPGA 100. In yet another embodiment, a portion of duty cycle check circuit 138 may be external to FPGA 100, such as control logic 1710.
In operation, control logic 1710 provides variable phase-shift signal 1717 to DCM 1714 for adjusting the phase relationship of sampling waveform 1722 with respect to test signal 1705. DCM 1714 includes a plurality of taps for selectively incrementing or decrementing the phase of sampling waveform 1722. In one embodiment, DCM 1714 includes 256 taps providing 256 phase shift increments. However, fewer or more taps may be provided. Sampling waveform 1722 clocks data from test signal 1705 into register 1712. Control logic 1710 shifts the phase of sampling waveform 1722 using variable phase-shift signal 1717 in response to output signal 1711. In an embodiment, control logic 1710 provides duty cycle information that may be used to compute duty cycle of test signal 1705 in response to output signal 1711 and the amount of phase shift provided to sampling signal 1722. Alternatively, control logic 1710 may directly compute the duty cycle. Control logic 1710 provides duty cycle information to pad 1708.
FIG. 18 shows an exemplary embodiment of control logic 1710 in accordance with one or more aspects of the present invention. Control logic 1710 includes a central processing unit (CPU) 1802, a memory 1808, a variety of support circuits 1804, and an input/output (I/O) interface 1806. CPU 1802 may be any of a variety of microprocessors or micro-controllers known in the art. Support circuits 1804 for CPU 1802 include conventional cache, power supplies, clock circuits, data registers, I/O interfaces, and the like. I/O interface 1806 may be directly coupled to memory 1808 or coupled through CPU 1802, and may be coupled to a conventional keyboard, mouse, printer, and interface circuitry adapted to receive and transmit data, such as data files and the like. Memory 1808 includes read/write random access memory (RAM), read only memory (ROM), hard disk storage, floppy disk storage, or optical disk storage, or any combination of these devices.
Memory 1808 may store all or portions of one or more programs and/or data for duty cycle test algorithm 1900 of FIG. 19. Although control logic 1710 has been disclosed as being implemented as a computer executing a software program, those skilled in the art will appreciate that control logic 1710 may be implemented in hardware, software, or a combination of hardware and software. Such implementations may include a number of processors independently executing various programs and dedicated hardware, such as application specific integrated circuits (ASICs).
FIG. 19 depicts a flow diagram showing an exemplary embodiment of a duty cycle test signal process 1900 in accordance with one or more aspects of the present invention. Process 1900 is described with simultaneous reference to FIG. 17. Process 1900 begins at step 1902, where test signal 1705 is generated. Test signal 1705 is produced by output buffer 1704 in response to waveforms 1718 and 1720. As described above, output buffer 1704 outputs data on a particular edge of each of waveform signals 1718 and 1720 (e.g., a rising edge of waveform signals 1718 and 1720). If waveform signals 1718 and 1720 are 180° out of phase with each other, then output buffer 1704 operates as a double-data-rate (DDR) output buffer (i.e., output buffer 1704 operates on two clock edges per period of waveform signals 1718 and 1720).
At step 1904, test signal 1705 is sampled using sampling waveform 1722 while the phase of sampling waveform 1722 is shifted in one direction. The phase of sampling waveform 1722 is shifted until a level change is detected in test signal 1705. This level change is used to indicate a starting location (“start point”).
At step 1906, test signal 1705 is sampled using sampling waveform 1722 while phase of sampling waveform 1722 is shifted in an opposite direction from that of step 1904. The phase of sampling waveform 1722 is shifted in such opposite direction until another level change is detected in test signal 1705. This level change is used to indicate a start of a positive pulse (“pulse start”) of test signal 1705.
At step 1908, test signal 1705 is sampled using sampling waveform 1722 while the phase of sampling waveform 1722 continues to be shifted in the above-mentioned opposite direction from that of step 1904. The phase of sampling waveform 1722 is shifted until yet another level change is detected in test signal 1705. This level change is used to indicate an end of the above-mentioned positive pulse (“pulse end”) of test signal 1705.
At step 1910, a difference between phase of sampling waveform 1722 at, or at least proximal to, pulse start and phase of sampling waveform 1722 at, or at least proximal to, pulse end is computed. This phase difference indicates a total time test signal 1705 remained at a particular logic level within a period of test signal 1705.
At step 1912, duty cycle of test signal 1705 is computed using pulse phase difference from step 1910. At optional step 1914, pulse width of test signal 1705 may be computed from using duty cycle from step 1912.
Those skilled in the art will appreciate that process 1900 may be executed a plurality of times to compute an average duty cycle, and optionally an average pulse width, of test signal 1705 by storing information in memory 1808 of FIG. 18 from iterations of process 1900.
For example, output buffer 1704 may generate test signal 1705 by producing a logic high output on each rising edge of waveform 1718, and a logic low output on each rising edge of waveform 1720. Phase of sampling waveform 1722 is first decremented one tap interval at a time until a high-to-low transition is detected in output signal 1711. As described above, a one tap interval may be 1/256 of the period of clock signal 1716, or some other fraction depending on a number of taps in DCM 1714, as output from DCM 1714. This high-to-low transition indicates the above-described start point, namely, at least a proximal location to where direction of phase adjust may be switched for detection of at least a proximal location for a pulse starting point.
Then, phase of sampling waveform 1722 may be incremented one tap interval at a time until a low-to-high transition is detected in output signal 1711, indicating approximately where start of a positive pulse of test signal 1705 occurs. The phase of sampling waveform 1722 is then continually incremented one tap interval at a time until another high-to-low transition is detected in output signal 1711. This high-to-low transition indicates approximately where the positive pulse of test signal 1705 ends.
The number of taps, which may be accumulated with a counter of control logic 1710, between pulse start and pulse end is then determined. The number of accumulated taps (“#taps”) may be used to compute duty cycle of test signal 1705 in accordance with the following formula:

Duty cycle=#taps/Total number of taps(e.g., 256).

Positive pulse width of test signal 1705 may be computed in accordance with the following formula:

Pulse width=Duty cycle/Frequency,

where frequency is the frequency of test signal 1705. For example, if input frequency is 310 MHz and #taps determine (e.g., counted) is 123, where each tap interval is 1/256 of an input clock period for such input frequency, then duty cycle of test signal 1705 is 48.05% and positive pulse width is 1.55 ns. Of course, other values of input frequency and phase granularity may be used.

Rather than decrementing phase of sampling signal 1722 to a start point and incrementing to find pulse start and pulse for positive pulse width, another direction of measurement may be employed. For example, phase of sampling signal 1722 may be first incremented to find a start point. Then phase of sampling signal 1722 may be decremented to find pulse start and pulse end locations for a positive pulse of test signal 1705. In addition, rather than measuring duration of the positive pulse (i.e., the time test signal 1705 is logically high), duration of a negative pulse may be measured (i.e., the time test signal 1705 is logically low). Moreover, output buffer 1704 may generate an alternative test signal 1705 by producing a logic low output on each rising edge of waveform 1718, and a logic high output on each rising edge of waveform 1720. This results in test signal 1705 having a 180° phase shift from that described in the above example. By shifting the phase of test signal by 180°, an average duty cycle may be computed, whereby effects of skew between waveforms 1718 and 1720 are reduced or eliminated.
FIG. 20 depicts a flow diagram showing another exemplary embodiment of a process 2000 for determining duty cycle of a test signal in accordance with one or more aspects of the present invention. Process 2000 is described with simultaneous reference to FIG. 17. Process 2000 begins at step 2002, where output buffer 1704 produces test signal 1705 having a first phase. At step 2004, duty cycle of test signal 1705 having the first phase is determined, for example, using process 1900. At step 2006, output buffer 1704 produces test signal 1705 having a second phase, where the second phase is approximately 180° out phase with the first phase. At step 2008, duty cycle of test signal 1705 having the second phase is determined, for example, using process 1900. At step 2010, an average duty cycle for test signal 1705 is computed. By averaging duty cycle measurements, skew between waveforms 1718 and 1720 is reduced or eliminated. At optional step 2012, an average pulse width and/or skew between waveforms 1718 and 1720 may be computed.
For example, assume input frequency is 310 MHz, the number of taps accumulated in a first duty cycle measurement is 123, and the number of taps accumulated in a second duty cycle measurement is 133. Then, the duty cycle of test signal 1705 having the first phase is 48.05% and the duty cycle of test signal 1705 having the second phase is 51.95%. The average duty cycle without clock skew is thus 50%. Pulse width of test signal 1705 having the first phase is 1.550 ns, and pulse width of test signal 1705 having the second phase is 1.676 ns. The skew between waveforms 1718 and 1720 that are used to generate test signal 1705 may be computed by averaging the pulse widths. In the present example, the skew is 63 ps. Of course, other frequencies may be used, and other measurement values may be obtained.
Method and apparatus for testing duty cycle at an input/output node has been described. The present invention may be used to internally test duty cycle of output drivers of an integrated circuit, such as an FPGA. Such an internal duty cycle test avoids the problems associated with an external measurement of duty cycle using, for example, an oscilloscope. In particular, external measurements of duty cycle are potentially influenced by the overall RC characteristics of the integrated circuit package, the socket in which the integrated circuit is supported, the header pin, and the printed circuit board to which the integrated circuit is attached. In addition, an external measurement of duty cycle cannot differentiate between duty cycle of the output driver and duty cycle of other components before the output driver within the integrated circuit. That is, an external measurement of duty cycle is but a composite result of interfering factors both inside and outside the device under test.
Duty cycle measurement in accordance with the present invention may be used to test integrated circuits, such as FPGAs, to determine operational parameters of the device. For example, duty cycle measurements may be used to “speed-rate” devices, whereby particular devices are rated for a higher operational speed than other devices. Devices with a higher speed rating may then be sold for a higher price than devices with a lower speed rating. In addition, duty cycle measurement may be used to control the fabrication process. For example, the threshold voltages of n-type and/or p-type transistors within output buffers may be modified if a particular batch of devices fails a duty cycle measurement test.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the present invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. For example, drive transistors were described; however, transistors for oscillators and flip-flops—especially toggle flip-flops, among other known devices dependent on Vtn/Vtp ratio may be adjusted in accordance with one or more aspects of the present invention. Claims listing steps do not imply an order of the steps.

## Claims

1. A system for testing duty cycle at an input/output node of an integrated circuit, comprising:
a first digital clock module having a first clock signal and a second clock signal as respective outputs, the second clock signal having a phase shifted approximately 180° from a phase of the first clock signal;
an output buffer having a timing signal as an output, the timing signal responsive to the first clock signal and the second clock signal;
a second digital clock module having a sampling signal as an output and a phase adjust signal as an input;
a register having a data input to receive the timing signal, a clock input to receive the sampling signal, and a sampled test signal as an output;
a control logic having the sampled test signal as an input and a phase adjust signal as an output, the phase adjust signal configured to shift the phase of the sampling signal, the control logic configured to provide duty cycle information, the duty cycle information being associated with the sampled test signal and a phase shift which the sampling signal undergoes responsive to the phase adjust signal;
the sampling signal being phase shifted in opposite directions responsive to the phase adjust signal to determine respective level changes in the sampled test signal, the respective level changes being associated with respective phase indicators, the phase indicators being the duty cycle information;
wherein the duty cycle of the test signal is determinable responsive to the duty cycle information;
a drive adjust circuit having a duty cycle adjust enable signal and the duty cycle information as inputs, and a drive adjust signal as an output;
the drive adjust circuit configured to provide the drive adjust signal responsive to the duty cycle adjust enable signal and the duty cycle information, wherein the drive adjust signal provides information associated with at least one set of drive transistors selected from a group consisting of n-type drive transistors and p-type drive transistors for obtaining a duty cycle indicated by the duty cycle adjust enable signal;
a reference voltage circuit having the drive adjust signal as an input;
the reference voltage circuit configured to provide a first reference voltage as an output using one or more of either the n-type drive transistors or the p-type drive transistors responsive to the drive adjust signal; and
the first reference voltage being provided to either an n-type well or a p-type well of an output buffer to provide a first body bias voltage of the output buffer.

2. The system of claim 1, wherein the digital clock module, the register, and the control logic are formed using configured logic blocks within the integrated circuit.

3. The system of claim 1, wherein the control logic comprises a processor and a memory.

4. The system of claim 1, wherein the reference voltage circuit further provides a second reference voltage,
wherein the second reference voltage is coupled to provide a second body bias voltage of the output buffer.

5. The system of claim 4, wherein the first reference voltage adjusts a p-channel transistor threshold voltage; and
wherein the second reference voltage adjusts an n-channel transistor threshold voltage.

6. A system for determining duty cycle, comprising:
a first digital clock module configured to provide a timing signal at least partially responsive to a first clock signal;
a phase-adjustment loop including control logic, a second digital clock module and a register;
the register of the phase-adjustment loop being coupled to receive the timing signal;
the phase-adjustment loop being configured to respond to input of the timing signal and a second clock signal, the second clock signal being provided to the control logic and the second digital clock module;
the second digital clock module configured to produce a phase adjustable sampling signal responsive to the second clock signal and a phase adjust signal, the register coupled to be clocked responsive to the phase adjustable sampling signal;
the control logic of the phase-adjustment loop configured to provide a duty cycle output and the phase adjust signal, the control logic configured to determine whether phase is to be adjusted to determine duty cycle of the timing signal, the duty cycle output indicating the duty cycle of the test signal;
a drive adjust module configured to provide a drive adjust address signal responsive to a duty cycle adjust enable signal and the duty cycle output;
the drive adjust address signal having address information associated with n-type drive transistors and p-type drive transistors for targeting the duty cycle of the timing signal;
a reference voltage module configured to provide reference voltage signals respectively using some of each of the n-type drive transistors and the p-type drive transistors responsive to the drive adjust address signal;
the reference voltage signals being respectively coupled to an n-well and a p-well of the output module to provide body bias voltages to the output module;
the duty cycle output being generated by:
the register being configured to store a test signal sample and to provide a sampled test signal responsive to the test signal and the phase adjustable sampling signal;
the control logic being coupled to receive the test signal sample from the register and configured to phase-shift the test signal sample incrementally to detect a phase difference responsive to the second clock signal and the test signal sample;
the control logic being configured to incrementally phase shift in one direction until a first change of state is detected and then to incrementally phase shift in an opposite direction until a second change of state is detected to provide a starting point; and
the control logic being configured to incrementally phase shift in the opposite direction and to count each increment until a third change of state is detected to provide an ending point, the starting point and the ending point being the duty cycle output.

7. The system of claim 6, wherein the control logic is configured to incrementally phase shift in the opposite direction and to count each increment until a third change of state is detected to provide an ending point, wherein total increments counted from the starting point to the ending point indicate the duty cycle.

8. The system of claim 7, wherein the total increments counted represents a number of taps in the second digital clock module incrementally applied.

9. The system of claim 8, wherein the duty cycle is determined by multiplying the total increments counted by a fraction indicating granularity of each tap of the second digital clock module.

10. The system of claim 6, wherein the reference voltage signals comprises a first reference voltage for adjusting a p-channel transistor threshold voltage of the output module and a second reference voltage for adjusting an n-channel transistor threshold voltage of the output module.