# Patent

## Title
Method for two-cycle sensing in a two-terminal memory array having leakage current

## Abstract

A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

## Background
This is a division of U.S patent application Ser. No. 11/583,676, filed Oct. 19, 2006, now U.S. Pat. No. 7,372,753.


FIELD OF THE INVENTION
The present invention relates generally to sensing a signal in a two-terminal memory array. More specifically, the present invention relates to sensing a signal in a two-terminal memory array during a read operation or in preparation for a write operation.
BACKGROUND OF THE INVENTION
Data storage in high-density memory devices can be accomplished using a variety of techniques. Often, the technique used depends on whether or not the stored data is volatile or non-volatile. In volatile memory devices, such as SRAM and DRAM, for example, stored data is not retained when power is removed from the memory device. On the other hand, for non-volatile memory devices, such as MRAM and Flash devices, stored data is retained when power is removed from the memory device.
Resistive state memory devices are a promising new type of non-volatile memory in which data is stored in a memory element as a plurality of resistive states. A first resistive state can represent a logic “1” and a second resistive state can represent a logic “0”. The first and second resistive states can be set by applying a write voltage of a predetermined magnitude, polarity, and duration across the memory element during a write operation. For example, voltage pulses can be used to write a logic “1” and a logic “0”, respectively.
In either case, after data has been written to the memory element, reading the value of the stored data in the memory element is typically accomplished by applying a read voltage across the memory element and sensing a read current that flows through the memory element. For example, if a logic “0” represents a high resistance and a logic “1” represents a low resistance, then for a constant read voltage, a magnitude of the read current can be indicative of the resistive state of the memory element. Therefore, based on Ohm's law, the read current will be low if the data stored is a logic “0” (e.g., high resistance) or the read current will be high if the data stored is a logic “1” (e.g., low resistance). Consequently, the value of the stored data can be determined by sensing the magnitude of the read current.
In high density memory devices, it is desirable to pack as many memory cells as possible in the smallest area possible in order to increase memory density and data storage capacity. One factor that can have a significant impact on memory density is the number of terminals that are required to access a memory element for reading or writing. As the number of terminals required to access the memory element increases, device area increases with a concomitant decrease in areal density. Most memory technologies, such as DRAM, SRAM, and some MRAM devices, require at least three terminals to access the core memory element that stores the data. However, in some memory technologies, such as certain resistance based memories, two terminals can be used to both read and write the memory element.
An array of two terminal memory elements can include a plurality of row conductors and a plurality of column conductors and each memory element can have a terminal connected with one of row conductors and the other terminal connected with one of the column conductors. The typical arrangement is a two terminal cross-point memory array where each memory element is positioned approximately at an intersection of one of the row conductors with one of the column conductors. The terminals of the memory element connect with the row and column conductors above and below it. A single memory element can be written by applying the write voltage across the row and column conductors the memory element is connected with. Similarly, the memory element can be read by applying the read voltage across the row and column conductors the memory element is connected with. The read current can be sensed (e.g., measured) flowing through the row conductor or the column conductor.
One challenge that arises from a two-terminal configuration is that memory elements that share a row or column conductor with the memory element being read will also have a potential difference across their respective row and column conductors. The adjacent memory elements can be referred to as half-selected memory elements. The potential difference across the terminals of half-selected memory elements can cause half-select currents to flow through those memory elements. The half-select currents are additive and can be considered as a leakage current that occurs during a read operation. In a high density memory device, the number of memory elements in an array can be several thousand or more. During a read operation to a selected memory element in the array, the half-select currents from half-selected memory elements in the same row or same column as the selected memory element can vastly exceed the magnitude of the read current flowing through the selected memory element. The read current can be considered to be a signal and a magnitude of that signal is indicative of a data value of the data stored in the selected memory element. On the other hand, the leakage current can be considered to be noise that masks the read current signal. Therefore, in a large array, a signal-to-noise ratio (S/N) of the read current to the leakage current is low. A low S/N ratio can make it difficult to distinguish between the read current and the leakage current. Consequently, the low S/N ratio makes it difficult to detect an accurate value for the stored data.
There are continuing efforts to improve accuracy in reading data and in increasing S/N ratios in memory arrays having leakage current.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram depicting one embodiment of an apparatus for sensing current in a two-terminal memory array.
FIG. 2A is a schematic depicting one embodiment of a two-terminal memory array.
FIG. 2B is a perspective view depicting the two-terminal memory array of FIG. 2A.
FIG. 2C is a block diagram depicting an exemplary apparatus for sensing current in a two-terminal memory array that includes bit-block arrays laid out next to one another and positioned above a substrate including circuitry.
FIG. 2D is a cross-sectional view depicting another exemplary apparatus for sensing current in a two-terminal memory array that includes stacked bit-block arrays positioned above a substrate including circuitry.
FIG. 3 is a perspective view depicting a selected memory element and a half-selected memory element during a read operation.
FIG. 4 is a perspective view depicting a selected memory element and a half-selected memory element during a write operation.
FIG. 5 is a schematic view depicting one embodiment of sensing current in a two-terminal memory array during a read operation.
FIGS. 6A and 6B are schematic views depicting examples of select voltages applied across selected first and second conductive traces during a read operation.
FIG. 7 is a schematic view depicting an alternative embodiment of sensing current in a two-terminal memory array during a read operation.
FIGS. 8A and 8B are schematic views depicting examples of select voltages applied across selected first and second conductive traces during a write operation.
FIG. 9A is a schematic view depicting one embodiment of a memory plug.
FIG. 9B is a cross-sectional view of the memory plug depicted in FIG. 9A.
FIG. 9C is a cross-sectional view depicting an exemplary memory plug.
FIG. 9D is as cross-sectional view depicting an alternative embodiment of a memory plug.
FIG. 10 is a graph depicting an exemplary IV characteristic of a memory plug.
FIG. 11 is a block diagram depicting another embodiment of an apparatus for sensing current in a two-terminal memory array.
FIG. 12A is a schematic view depicting one embodiment a data unit.
FIG. 12B is a schematic view depicting another embodiment of a data unit.
FIG. 12C is a schematic view depicting yet another embodiment of a data unit.
FIGS. 13A, 13B, and 14 are schematic views depicting exemplary current-to-voltage converters.
FIG. 15 is a schematic view depicting one embodiment of a storage unit.
FIG. 16 is a block diagram depicting yet another embodiment of an apparatus for writing data in a two-terminal memory array.
FIG. 17A is a schematic view depicting one embodiment of an analog circuit for generating a result signal.
FIG. 17B is a schematic view depicting one embodiment of a logic circuit for generating a result signal.
FIG. 17C depicts one example of a truth table for generating a result signal.
FIG. 18 is a schematic view depicting one embodiment of an equalization circuit.
FIG. 20 is a timing diagram depicting one example of a pre-read operation.
FIG. 21A is a timing diagram depicting one example of a consummated write operation.
FIG. 21B is a timing diagram depicting one example of an aborted write operation.
FIG. 22 is a block diagram depicting another embodiment of an apparatus for sensing current in a two-terminal memory array.
FIG. 23A is a block diagram depicting a row voltage switch and a column voltage switch.
FIG. 23B depicts an example of a truth table for the row and column voltage switches.
FIG. 24A is a block diagram depicting one embodiment of a row decoder and an example of a truth table for the row decoder.
FIG. 24B is a block diagram depicting one embodiment of a column decoder and an example of a truth table for the column decoder.
FIG. 25A is a schematic view depicting one embodiment of applying select voltages and sensing total and leakage currents.
FIG. 25B is a schematic view depicting an alternative embodiment of applying select voltages and sensing total and leakage currents.
FIG. 26A depicts an example of a truth table for alternating read voltage polarity.
FIG. 26B is a timing diagram depicting one example of toggling a direction signal.
FIG. 27 is a timing diagram depicting another example of toggling a direction signal.
FIG. 28A is a schematic view depicting current flow in a first cycle of a two-cycle pre-read operation.
FIG. 28B is a schematic view depicting current flow in a second cycle of the two-cycle pre-read operation.
FIG. 28C is a block diagram depicting one embodiment of a sense unit.
FIG. 28D is a schematic view depicting an exemplary circuit for leakage error correction for a two-cycle pre-read operation.
FIG. 28E is a timing diagram depicting a two-cycle pre-read operation.
FIG. 28F depicts an exemplary memory bank for a two-cycle pre-read operation.
FIG. 29A is a block diagram depicting one embodiment of a sense unit.
FIG. 30A is a schematic view depicting one embodiment of a reference generator.
FIG. 30B is a schematic view depicting one embodiment of row and column voltage switches.
FIG. 31 is a block diagram depicting another embodiment of a reference generator.
FIG. 32 is a schematic view depicting one example of a reference resistance.
FIG. 33 is a flow diagram depicting a method of sensing current in a two-terminal memory array.
FIG. 33A is a flow diagram depicting a combining step and a storing step.
FIGS. 33B and 33C are flow diagrams depicting steps for generating a data signal.
FIG. 34 is a flow diagram depicting a method of sensing current in a two-terminal memory array.
FIG. 34A is a flow diagram depicting storing steps and a combining step.
FIGS. 34B and 34C are flow diagrams depicting alternative embodiments of steps for generating one or more data signals.



Although the previous Drawings depict various examples of the invention, the invention is not limited by the depicted examples. Furthermore, the depictions are not necessarily to scale.
DETAILED DESCRIPTION
In the following detailed description and in the several figures of the drawings, like elements are identified with like reference numerals. As shown in the drawings for purpose of illustration, the present invention is embodied in an apparatus for sensing current in a two-terminal memory array and in a method of sensing a signal in a two-terminal memory array.
In one embodiment, the present invention discloses an apparatus for two-cycle sensing in a two-terminal memory array having leakage current. The apparatus includes an array having a plurality of first conductive traces and a plurality of second conductive traces. An address unit receives an address, selects one of the plurality of second conductive traces during a first cycle, applies a first select voltage to the selected second conductive trace and applies a non-select voltage potential to un-selected traces. During a second cycle, the address unit selects one of the plurality of first conductive traces and applies a second select voltage to the selected first conductive trace. A sense unit senses a leakage current flowing through the selected second conductive trace during the first cycle and senses a total current flowing through the selected second conductive trace during the second cycle.
In another embodiment, the present invention discloses a method for two-cycle sensing in a two-terminal memory array having leakage current. The method includes providing an array having a plurality of first conductive traces and a plurality of second conductive traces. Receiving an address associated with a selected first conductive trace from the plurality of first conductive traces and one or more selected second conductive traces from the plurality of second conductive traces. A first select voltage is applied to one or more selected second conductive traces during a first cycle and during a second cycle. A non-select voltage potential is applied to the plurality of first conductive traces and unselected second conductive traces during the first cycle. During the first cycle, one or more leakage currents that flow through the one or more selected second conductive traces are sensed. During the second cycle, a second select voltage is applied to the selected first conductive trace while applying the non-select voltage potential to unselected first and second conductive traces and one or more total currents that flow through the one or more selected second conductive traces are sensed.
In the following detailed description, numerous specific details are set forth to provide a through understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known elements and process steps have not been described in depth in order to avoid unnecessarily obscuring the present invention.
In FIG. 1, an apparatus 150 for sensing a signal in a two-terminal memory array 100 includes a plurality of first conductive traces 1, a plurality of second conductive traces 2, an address unit 101, and a sense unit 103. The address unit 101 receives an address ADDR and selects at least one of the plurality of first conductive traces (denoted as 1′) and one of the plurality of second conductive traces (denoted as 2′). The address unit 101 applies a select voltage across the selected first and second conductive traces 1′ and 2′. The address unit 101 also applies a non-select voltage potential (non-select voltage hereinafter) to unselected traces 1 and 2. The sense unit 103 senses a total current IT flowing through the selected first conductive trace 1′ and senses a leakage current IL flowing through unselected second conductive traces 2. One skilled in the art will appreciate that the apparatus 150 and its sub-components (e.g. 101 and 103) can be coupled with and controlled by an external device (e.g., a microprocessor or a memory controller). Optionally, the apparatus 150 can include at least one control unit 105 operative to coordinate and control operation of the address and sense units 101 and 103. One or more signal lines 115 and 117 can couple the control unit 105 with the address and sense units 101 and 103. The control unit 105 can be electrically coupled with an external system (e.g., the microprocessor or the memory controller) through one or more signal lines 113.
Two-Terminal Memory Array
Turning to FIG. 2A, the two-terminal array 100 (array 100 hereinafter) includes the plurality of first conductive traces 1 and the plurality of second conductive traces 2. For purposes of explanation, an orientation of the first and second conductive traces 1 and 2 is depicted relative to an x-y coordinate system 202. Accordingly, the first conductive traces 1 are arranged in rows aligned with an x-axis (as depicted by dashed arrow 225 for row) and the second conductive traces 2 are arranged in columns aligned with a y-axis (as depicted by dashed arrow 227 for col). The arrangement of the first and second conductive traces 1 and 2 can be reversed such that the first conductive traces 1 are arranged in columns and the second conductive traces 2 are arranged in rows.
The array 100 includes a plurality of memory elements 10 for storing data. The memory elements 10 store data as a plurality of conductivity profiles with discrete resistances at certain voltages. Therefore, each memory element 10 is schematically depicted as a resistor. A magnitude of a resistance at a certain voltage of a specific memory element 10 is indicative of a value of stored data in the specific memory element 10. As an example, each memory element 10 can store a single bit of data as one of two distinct conductivity profiles with a first resistive state R0 at a read voltage VR indicative of a logic “0” and a second resistive state R1 at VR indicative of a logic “1”, where R0≠R1. Preferably, a change in conductivity, measured at VR, between R0 and R1, differs by at least a factor of approximately 10 (e.g., R0≈1MΩ and R1≈100 kΩ). The memory elements 10 are not necessarily linear resistors and the resistance of the memory elements 10 may not be a linear function of the voltage applied across the memory elements 10. Therefore, a resistance R of the memory elements 10 can approximately be a function of the read voltage VR such that R≈f(VR).
The actual convention for determining which resistive state represents a logic “0” and a logic “1” will be application dependent and one skilled in the art will understand that the first resistive state R0 can be indicative of a logic “0” and the second resistive state R1 can be indicative of a logic “1”. Initially, memory elements 10 in the array 100 may be in a predetermined initial resistive state in which the conductivity profile of all of the memory elements 10 is indicative of the first resistive state R0 or the second resistive state R1. Subsequently, write operations to selected memory element 10′ can effectuate a change from the initial resistive state to the first resistive state R0 or the second resistive state R1. In some conventions, the first resistive state R0 (e.g., high resistance at VR) is referred to as a programmed state and the second resistive state R1 (e.g., low resistance at VR) is referred to as an erased state. Accordingly, a write operation in which a logic “1” is to be written to a programmed memory element 10 will result in the conductivity profile changing from the programmed state of R0 to the erased state of R1. One skilled in the art will appreciate that an opposite convention in which the erased state is R0 and the programmed state is R1 can also be used. Hereinafter, for the sake of clarity, the first resistive state R0 denotes a high resistance and a logic “0” and the second resistive state R1 denotes a low resistance and a logic “1”.
As another example, each memory element 10 can store multiple bits of data. Therefore, if two-bits of data are stored in each memory element 10, then there will be four distinct conductivity profiles with corresponding resistive states of R00, R01, R10, and R11, where R00>R01>R10>R11. For multi-bit data storage, it may be desirable for the highest and lowest resistive states R00 and R11 to differ by at least a factor of 100 at VR (e.g., R00≈1MΩ and R11≈10 kΩ). Preferably, intermediate resistive states R01 and R10 have a resistance that falls between the highest and lowest resistance. For example, the intermediate resistive states R01 and R10 can have a resistance that is approximately evenly divided between the highest and lowest resistance or they may fall between the highest and lowest resistance based on a logarithmic scale. The difference between the highest and the lowest resistive states is necessary in order to distinguish between a magnitude of a read current that flows through a selected memory element 10 during a read operation. If the resistive states are spaced too closely together, then it may be difficult to sense differences between the read current for R01 and the read current for R10, for example. The ability to distinguish between the read currents for each resistive state becomes more critical in the presence of leakage currents that flow in the array 100 at the same time as the read current. The combined magnitude of the leakage currents can mask the read current, making it difficult to accurately determine the resistive state of the selected memory element 10 during the read operation.
Referring again to FIG. 2A, each memory element 10 includes a first terminal 11 in communication with only one of the first conductive traces 1 and a second terminal 12 in communication with only one of the second conductive traces 2. Moreover, each memory element 10 is electrically in series with its first and second terminals 11 and 12. Consequently, each memory element 10 in the array 100 can be uniquely selected for a read operation or for a write operation by applying an appropriate select voltage across the first conductive trace 1 in communication with the first terminal 11 of the selected memory element 10 and the second conductive trace 2 in communication with the second terminal 12 of the selected memory element 10. As used herein, a memory element that is selected for a read operation or a write operation will be denoted as 10′ and the selected conductive traces that are electrically in series with the selected memory element 10′ will be denoted as 1′ and 2′ for the selected first and second conductive traces respectively. Furthermore, as used herein, memory elements 10 can include a plurality of layers, some of which directly contribute to switching and some of which are included for other considerations such as process related considerations and/or electrical considerations, for example.
Cross-Point Array
In FIG. 2B, the first conductive traces 1 are spaced apart from one another and do not come into direct contact with each other or with any of the second conductive traces 2. Similarly, the second conductive traces 2 are also spaced apart from one another other and do not come into direct contact with each other or with any of the first conductive traces 1. Preferably, the first and second conductive traces 1 and 2 cross one another in a substantially orthogonal orientation (i.e., approximately 90 degrees) and each memory element 10 is positioned approximately at an intersection of one of the first conductive traces 1 with one of the second conductive traces 2 so that the array 100 comprises a cross-point array structure. Access (e.g., for a read or write operation) to a selected memory element 10′ is accomplished by applying a select voltage across the first and second conductive traces 1′ and 2′ that cross the selected memory element 10′. In a manner similar to the order of the rows and columns in the array 100, the second conductive traces 2 may be positioned above the first conductive traces 1 or vice-versa, with the memory elements 10 positioned between the first and second conductive traces 1 and 2.
Read Operations
A read operation to the selected memory element 10′ is effectuated by applying a select voltage VS having an appropriate read voltage magnitude across the selected first and second conductive traces 1′ and 2′. The select voltage VS is applied to the selected first and second conductive traces 1′ and 2′ based on the address ADDR received by the address unit 101. For example, the address ADDR can be from an address bus 125. The address unit 101 decodes the address ADDR and applies the select voltages across the appropriate pair of selected conductive traces 1′ and 2′. Furthermore, the address unit 101 applies the non-select voltage to the remaining conductive traces 1 and 2 (i.e., unselected traces 1 and 2).
Turning now to FIG. 3, a portion of the array 100 is depicted during a read operation to a selected memory element 10′. Different magnitudes of the select voltage VS can be used to read data from and to write data to the selected memory element 10′. Typically, a magnitude of the select voltage VS for a read operation is lower than a magnitude of the select voltage VS for a write operation. By using a lower magnitude for the select voltage during read operations, read disturbs that can overwrite or corrupt the stored data in the selected memory element 10′ are substantially reduced or eliminated. Hereinafter, the select voltage VS used for a read operation will be denoted as a read voltage VR and the select voltage VS used for a write operation will be denoted as a write voltage VW. Accordingly, for a read operation, the read voltage VR is applied across the selected first and second conductive traces 1′ and 2′
The read voltage VR can be supplied by a single voltage source coupled with the selected first and second conductive traces 1′ and 2′ as depicted in FIG. 3 or the read voltage VR can be supplied by multiple voltage sources with one voltage source electrically coupled with the selected first conductive trace 1′ and a second voltage source electrically coupled with the selected second conductive trace 2′. On the other hand, the read voltage VR can be applied to only one of the selected conductive traces and the other selected conductive trace can be at approximately a ground potential. For example, the read voltage VR can be applied to the selected second conductive trace 2′ and the selected first conductive trace 1′ can be at approximately a ground potential, or vice-versa.
FIG. 3 also depicts a memory plug 300 that includes the memory element 10′ and any other materials that may be necessary to form an operable memory device. For example, the memory plug 300 includes a portion of the first and second conductive traces 1′ and 2′ that cross the memory element 10′. Although a selected memory element 10′ is depicted, the concept of the memory plug 300 also applies to unselected and half-selected memory elements 10 as well. For example, memory plug 300 is adjacent to the selected memory element 10′ and its memory element 10 is a half-selected memory element because the read voltage VR is electrically coupled only to the selected second conductive trace 2′ and the first conductive trace 1 is electrically coupled with a non-select voltage VN.
Read Current
The selected memory element 10′ is electrically in series with the selected traces 1′ and 2′. Consequently, the read voltage VR causes a read current IR to flow through the selected memory element 10′. The magnitude of the read current IR will depend on the magnitude of the read voltage VR and a resistive state RS of the selected memory element 10′, such that IR≈VR÷RS. For a given read voltage VR, the read current IR will be lower when RS=R0 (e.g., high resistance) and IR will be higher when RS=R1 (e.g., low resistance). The direction of flow for the read current IR will depend on a polarity of the read voltage VR. The read voltage VR need not be a constant voltage and VR may be applied as a pulse. Preferably, VR is applied as a voltage pulse (e.g., a positive and/or negative pulse) One advantage to using a voltage pulse is that voltage pulses can have varying waveform shapes. Examples of waveform shapes include but are not limited to square waves, triangle waves, sine waves, and complex waveforms. A potential difference for the read voltage VR can be provided by separate voltage sources coupled with the selected conductive traces 1′ and 2′ such that VR=(VR1′−VR2′), where VR1′ is a first read voltage applied to the selected first conductive trace 1′ and VR2′ is a second read voltage applied to the selected second conductive trace 2′.
Half-Select Current
During a read or write operation, it is preferable that unselected traces 1 and 2 not be allowed to float. Floating traces can result in voltages that disturb the resistive state in unselected memory elements 10. Accordingly, in FIG. 3, an unselected memory element 10 has the non-select voltage VN applied to its unselected first conductive trace 1. As mentioned above, the unselected memory element 10 is referred to as a half-selected memory element because it has one of its conductive traces 2′ connected with the read voltage VR and one of its conductive traces 1 connected with the non-select voltage VN resulting in a potential difference across the half-selected memory element 10. Consequently, during the read operation, a half-select current IH flows through the half-selected memory element 10 due to the potential difference across conductive traces 1 and 2′. As a first example, if the non-select voltage VN is applied to the un-selected first conductive trace 1 and the read voltage VR2′ is applied to the selected second conductive trace 2′, then the potential difference is (VR2′−VN) and a magnitude of the half-select current is IH≈(VR2′−VN)÷RS. As a second example, if the non-select voltage VN is applied to the un-selected second conductive trace 2 and read voltage VR1′ is applied to the selected first conductive trace 1′, then the potential difference is (VR1′−VN) and a magnitude of the half-select current is IH≈(VR1′−VN)÷RS. As was described above, the resistive state RS may not be a linear function of the voltage applied across the memory elements 10 such that RS≈f (VR2′−VN) for the first example and RS≈f (VR1′−VN) for the second example. In either case, a direction of current flow for the half-select current IH will depend on a polarity of the read voltage VR and a polarity of the non-select voltage VN. The magnitude and polarity of the non-select voltage VN will be application dependent and can depend on several factors including but not limited to the magnitude and polarities of the read and write voltages applied across the selected traces (1′, 2′).
Write Operations
A write operation to the selected memory element 10′ in the array 100 is effectuated by applying a select voltage VS having an appropriate write voltage magnitude and polarity across the selected first and second conductive traces 1′ and 2′. In FIG. 4, a portion of the array 100 is depicted during a write operation to the selected memory element 10′. The write voltage is denoted as VW and is applied across the selected traces 1′ and 2′ during the write operation. The write voltage VW can be applied as a voltage pulse. Preferably, the write voltage VW is applied as a bipolar voltage pulse. One example of a bipolar voltage pulse includes applying a positive voltage pulse to one of the selected conductive traces and applying a negative voltage pulse to the other of the selected conductive traces. The voltage pulses (positive and/or negative) can have varying waveform shapes. Examples of waveform shapes include but are not limited to square waves, triangle waves, sine waves, and complex waveforms.
The resistive state RS of the selected memory element 10′ can be changed by applying the appropriate write voltage VW to the selected traces 1′ and 2′. As one example, if the memory elements 10 are initially in the first resistive state R0 (e.g., high resistance) indicative of a logic “0”, then to overwrite the logic “0” with a logic “1”, a negative write voltage is applied to the selected second conductive trace 2′ and a positive write voltage is applied to the selected first conductive trace 1′. As a result, the selected memory element 10′ is overwritten and the first resistive state R0 is replaced by the second resistive state R1 (e.g., low resistance). As another example, to overwrite the state R1, a positive write voltage is applied to the selected second conductive trace 2′ and a negative write voltage is applied to the selected first conductive trace 1′. Consequently, the memory element 10′ is overwritten and the state R1 is replaced by the state R0.
A write current IW flows through the selected memory element 10′ during the write operation. A magnitude of the write current IW will depend on the resistive state RS (e.g., R0 or R1) of the selected memory element 10′ and a magnitude of the write voltage VW, such that IW≈VW÷RS. A direction of current flow for the write current IW will depend on a polarity of the write voltage VW. During the write operation, a half-select current flows through half-selected memory elements 10 as is depicted by a half-select current IH flowing through adjacent memory element 10 in FIG. 4. The memory element 10 is half-selected because the write voltage VW is applied to the selected second conductive trace 2′ and the non-select voltage VN is applied to the un-selected first conductive trace 1. Typically, the magnitude of the write voltage VW is higher than the magnitude of the read voltage VR. Consequently, the magnitude of the half-select current IH can be higher during write operations. A direction of current flow for the half-select current IH will depend on a polarity of the write voltage VW and a polarity of the non-select voltage VN. A potential difference for the write voltage VW can be supplied by separate voltage sources coupled with each of the selected conductive traces 1′ and 2′ such that VW=(VW1′−VW2′), where VW1′ is a first write voltage applied to the selected first conductive trace and VW2′ is a second write voltage applied to the selected second conductive trace. Therefore, if the non-select voltage VN is applied to the un-selected first conductive trace 1 and the write voltage VW2′ is applied to the selected second conductive trace 2′, then the potential difference across half-selected memory elements 10 is (VW2′−VN). Conversely, if the non-select voltage VN is applied to the un-selected second conductive trace 2 and the write voltage VW1′ is applied to the selected first conductive trace 1′, then the potential difference across half-selected memory elements 10 is (Vw1′−VN). A magnitude of the half-select current IH will depend on the resistive state RS of the half-selected memory element 10 and a magnitude of the potential difference (VW−VN) across traces (1, 2′), such that IH≈(VW−VN)÷RS.
One-Cycle Pre-Read Operation
During a read operation, the read current IR flows through the selected memory element 10′ and the half-select current IH flows through the half-selected memory elements 10. In a memory device suitable for high-density data storage, the selected memory element 10′ will be greatly outnumbered by the half-selected memory elements 10 because in a large array 100 there can be several thousand or more half-selected memory element 10 in the same row and column as the selected memory element 10′. On an individual basis, each half-select current IH will typically be lower in magnitude than the read current IR. However, a combined magnitude of the half-select currents IH for all of the half-selected memory elements 10 can exceed that of the read current IR. Therefore, in order to accurately read the value of stored data in the selected memory element 10′, it is necessary to separate a signal representing the read current IR from a signal representing the total half-select currents IH.
Referring back to FIG. 2A, the first conductive traces 1 are arranged in rows labeled r0, r1, r2, and r3 and the second conductive traces 2 are arranged in columns labeled c0, c1, c2, and c3. In the array 100, there are sixteen memory elements 10 labeled m0 through m15. The 0th memory element 10 is positioned in an upper left-hand corner of the array 100 (i.e., m0 is at r0, c0) and the 15th memory element 10 is positioned in a lower right-hand corner of the array 100 (i.e., m15 is at r3, c3). One skilled in the art will appreciate that the array 100 may be smaller or larger than the four-by-four array 100 depicted in FIG. 2A. Moreover, the array 100 may be symmetrical with an equal number of rows and columns or the array 100 may be non-symmetrical with an unequal number of rows and columns.
Furthermore, it should be appreciated that this technique will typically generate data from only one memory cell. Accordingly, multiple bit block arrays are typically used in a multi-bit memory. Bit blocks arrays are typically electrically isolated from each other and are only capable of selecting a single memory cell at a time. The term bit block array describes both memories that store a single bit of data and multiple bits of data in a single memory cell (e.g., a memory cell that can store two bits of data as 00, 01, 10, and 11). The bit block arrays may be laid out next to each other in a single-layer cross-point array fabricated over a substrate in which the circuitry portions of the apparatus 150 (e.g., address unit 101, sense unit 103, and control unit 105) are fabricated, or may be stacked one upon another over a substrate in which the circuitry portions of the apparatus 150 are fabricated in a stacked cross-point memory, or some combination of both techniques. Reference is now made to FIGS. 2C and 2D where a substrate 200 includes the apparatus 150 fabricated in the substrate 200 and a plurality of bit block arrays 100. In FIG. 2C, the bit block arrays 100 are fabricated over the substrate 200 and are laid out next to one another and each array 100 is electrically coupled with the apparatus 150 by an interconnect structure (not shown). In FIG. 2D, the bit block arrays 100 are fabricated above the substrate 200, are stacked upon one another, and are electrically coupled with the apparatus 150 by an interconnect structure (not shown). In either case, the apparatus 150 and any other circuitry are fabricated in the substrate 200.
Turning now to FIG. 5, based on the address ADDR received by the address unit 101, the 10th memory element 10′ (i.e., m10 at r2, c2) is selected for a read operation. Accordingly, a select voltage VSR is applied to the first conductive trace 1′ in row r2 and a select voltage VSC is applied to the second conductive trace 2′ in column c2. For purposes of explanation, VSR denotes a select voltage applied to a selected first conductive trace 1′ in a row and VSC denotes a select voltage applied to a selected second conductive trace 2′ in a column. Additionally, a non-select voltage VNR is applied to the remaining first conductive traces 1 in rows r0, r1, and r3. Similarly, a non-select voltage VNC is applied to the remaining second conductive traces 2 in columns c0, c1, and c3. Therefore, VNR denotes a non-select voltage applied to unselected first conductive traces 1 in the rows and VNC denotes a non-select voltage applied to unselected second conductive traces 2 in the columns.
As was described above, the application of the select voltages VSR and VSC across the first and second conductive traces 1′ and 2′ causes the read current IR to flow through the selected memory element 10′ (denoted by a heavy dashed arrow for IR). In FIG. 5, the select voltage VSR is more positive than the select voltage VSC so that the read current IR flows in a direction depicted by the heavy dashed arrow through the selected memory element 10′ (denoted as SC). Accordingly, the read current IR flows from the selected first conductive trace 1′ to the selected second conductive trace 2′. In the same row r2 as the selected memory element 10′, there are also three half-selected memory elements 10 (denoted as hC). The aforementioned half-select current IH flows through each of the half-selected memory elements 10 as denoted by dashed arrows IH0, IH1, and IH3. The half-select current IH flows from the selected first conductive trace 1′ to the unselected second conductive traces 2 because the unselected second conductive traces 2 are at a lower voltage potential than the selected first conductive trace 1′.
Therefore, a total current IT flowing through the selected first conductive trace 1′ in row r2 is approximately: IT≈IH0+IH1+IH3+IR, where the half-select currents IH0, IH1, and IH3 represent leakage currents. A total leakage current IL flowing from the selected first conductive trace 1′ to the unselected second conductive traces 2 in columns (c0, c1, c3) is approximately: IL≈IH0+IH1+IH3. The half-select currents IH0, IH1, and IH3 can be sensed through the unselected second conductive traces 2 in columns (c0, c1, c3) because the memory elements 10 above and below the half-selected hC memory elements 10 in columns (c0, c1, c3) have the non-select voltages VNR and VNC applied across their respective terminals 11 and 12 so that the potential difference across those terminals is approximately 0 volts, assuming VNR and VNC are approximately equal to each other (i.e., VNR≈VNC). Therefore, little or no current flows through those memory elements 10 and the current entering the unselected second conductive traces 2 is approximately the half-select currents IH0, IH1, and IH3.
Both the total current IT and the leakage current IL represent signals that can be processed to derive another signal that is indicative of a value of stored data in the selected memory cell 10′. Accordingly, the sense unit 103 senses the total current IT flowing in the selected first conductive trace 1′ and senses the leakage current IL flowing in the unselected second conductive traces 2 and output those currents as signals (see FIG. 1) that are processed along with other signals (to be described below) to derive the value of stored data in the selected memory cell 10′.
Since the row and column orientation is arbitrary, one skilled in the art will appreciate that the total current IT can be sensed flowing through the selected second conductive trace 2′ and the leakage current IL can be sensed flowing through unselected first conductive traces 1. Accordingly, FIG. 7 depicts an alternative embodiment for sensing the total current IT and the leakage current IL, where the address unit 101 selects the same memory element 10′ (i.e., m10 at r2, c2) for a read operation, the appropriate select voltages VSR and VSC are applied to the selected first and second conductive traces 1′ and 2′, and the appropriate non-select voltages VNR and VNC are applied to unselected conductive traces 1 and 2. However, the sense unit 103 senses the total current IT flowing through the selected second conductive trace 2′ and senses the leakage current IL flowing through the unselected first conductive traces 1. Therefore, the total current IT flowing through the selected second conductive trace 2′ in column c2 is approximately: IT≈IH0+IH1+IH3+IR. The total leakage current IL flowing from the unselected first conductive traces 1 in rows r0, r1, and r3 and into the selected second conductive trace 2′ is approximately: IL≈IH0+IH1+IH3. The embodiment depicted in FIG. 7 assumes that the select voltage VSR is more positive than the select voltage VSC so that the read current IR and the half-select currents IH0, IH1, and IH3 flow in the direction indicated by their respective dashed arrows.
Therefore, pre-reading can be an apparatus and/or a method for sensing a signal indicative of stored data in a selected memory element 10′ by distinguishing the signal represented by the read current IR from a noise signal represented by the leakage current IL. In the context of a read operation where the signal to noise ratio between the read current IR and the leakage current IL is low (i.e., IL>>IR), it is desirable for the pre-read operation to be an integral part of a read operation to the array 100 so that an accurate sensing of the read current IR can be used to accurately determine the value of the stored data.
In the context of a write operation, it is not necessary to separate the read current IR from the leakage current IL in order to accurately determine the value of the stored data. However, the optional use of the pre-read operation during a write operation may be desirable and can have several advantages, particularly when the stored data and the data to be written are approximately identical to each other (e.g., overwriting redundant data). The advantages in a redundant data scenario include but are not limited to preventing the overwriting of redundant data, reducing write operation latency by aborting the write operation when the data is redundant, and reducing memory element 10 wear out and stress by preventing unnecessary write operations to selected memory elements 10′.
Read Operation Select Voltages
The select voltages VSR and VSC can be generated in a variety of ways. As one example, VSR can be a positive or negative voltage and VSC can be approximately at a ground potential. On the other hand, VSC can be a positive or negative voltage and VSR can be approximately at a ground potential. As another example, both VSR and VSC can be either positive or negative voltages with one of the voltages more positive or more negative than the other. Preferably, the select voltage for a read operation comprises the first read voltage VR1′ applied to the selected first conductive trace 1′ and the second read voltage VR2′ applied to the selected second conductive trace 2′. It is preferable, but not necessary, that the first read voltage VR1′ is approximately equal in magnitude and opposite in polarity to second read voltage VR2′. In FIG. 6A, the first and second read voltages VR1′ and VR2′ are applied to the selected first and second conductive traces 1′ and 2′ respectively, so that the read current IR will flow in a direction determined by the relative magnitudes and polarities of the first and second read voltages VR1′ and VR2′. In FIG. 6B, the first read voltage VR1′ can have a positive polarity and the second read voltage VR2′ can have a negative polarity, or vice-versa. The positive and negative polarities can be referenced to ground, for example. Moreover, the first and second read voltages VR1′ and VR2′ can be applied as voltage pulses as was describe above.
Non-Select Voltages
Preferably, the non-select voltages VNR and VNC are equal to each other so that no current flows through memory elements 10 that have the non-select voltages VNR and VNC applied across their respective first and second conductive traces 1 and 2. The non-select voltages VNR and VNC can be generated by the same voltage source or by different voltage sources. As an example, for a very large array 100, the non-select voltages VNR and VNC can be generated by separate voltage sources. If separate voltage sources are used, then it is desirable for the voltages supplied be equal voltages (e.g., VNR=VNC) to eliminate half-select current flow through unselected memory elements 10. The non-select voltages VNR and VNC can be the same for read and write operations. Preferably, the voltage potentials for the non-select voltages VNR and VNC are approximately half-way between the select voltages VSR and VSC for read and write operations, such that VNR=VNC=1⁄2(|VSR|−|VSC|). Alternatively, VNR=VNC=1⁄2(|VSC|−|VSR|). The non-select voltages VNR and VNC can be positive or negative voltage potentials. As one example, for a read operation, the non-select voltages are VNR=VNC=1⁄2(|VR1′|−|VR2′|). As a second example, for a write operation, the non-select voltages are VNR=VNC=1⁄2(|VW1′|−|VW2′|). TABLE 1 and TABLE 2 below list examples of the non-select voltages VNR and VNC for read and write operations respectively, where VNR=VNC=1⁄2(|VSR|−|VSC|). The read and write voltages can be uni-polar or bi-polar. Furthermore, the read and write voltages can be applied as voltage pulses.












TABLE 1







VR1′
VR2′
VNR
VNC









+2 V
−2 V
0 V
0 V



−2 V
+2 V
0 V
0 V



+4 V
 0 V
2 V
2 V



 0 V
−4 V
−2 V 
−2 V 



+1 V
−3 V
−1 V 
−1 V 



+2 V
−1 V
+0.5 V  
+0.5 V  






















TABLE 2







VW1′
VW2′
VNR
VNC









+3 V
−3 V
0 V
0 V



−3 V
+3 V
0 V
0 V



+6 V
 0 V
3 V
3 V



 0 V
−6 V
−3 V 
−3 V 



+4 V
−3 V
+0.5 V  
+0.5 V  



+2 V
−4 V
−1.0 V  
−1.0 V  










One skilled in the art will appreciate that the non-select voltages VNR and VNC may not be exactly equal to each other due to process variations, voltage drops due to variations in the as-routed length of interconnect structures, just to name a few. As a result, when VNR and VNC are not exactly equal to each other, (e.g., VNR≈VNC) there will be some current flow through unselected memory elements 10.
Write Operation Select Voltages
As was described above, the appropriate select voltages can be applied to the selected first and second conductive traces 1′ and 2′ during a read or a write operation. The select voltages VSR and VSC used for write operations can be generated in a variety of ways. As one example, VSR can be a positive or negative voltage and VSC can be approximately at a ground potential, or VSC can be a positive or negative voltage and VSR can be approximately at a ground potential. As another example, both VSR and VSC can be either positive or negative voltages with one of the voltages more positive or more negative than the other. Preferably, the select voltage for the write operation comprises the first write voltage VW1′ applied to the selected first conductive trace 1′ and the second write voltage VW2′ applied to the selected second conductive trace 2′. It is preferable, but not necessary, that the first write and second write voltages VW1′ and VW2′ be approximately equal in magnitude but opposite in polarity to each other. In FIG. 8A, the first and second write voltages VW1′, and VW2′ are applied to the selected first and second conductive traces 1′ and 2′ respectively, and a direction of write current IW flow will depend on the relative magnitudes and polarities of the first and second write voltages VW1′, and VW2′. In FIG. 8B, the first write voltage VW1′ can have a positive polarity and the second write voltage VW2′ can have a negative polarity, or vice-versa. Moreover, the first and second write voltages VW1′, and VW2′ can be applied as voltage pulses. The positive and negative polarities can be referenced to ground, for example. As was described above, select voltages for write operations are typically greater in magnitude than the select voltages for a read operation. Typically, this means |VW|>|VR| such that the relationship between the voltages is: |VW1′|>|VR1′|; |VW1′|>|VR2′|; |VW2′|>|VR2′|; and |VW2′|>|VR1′|.
Memory Elements and Memory Plugs
In FIG. 9A, the memory element 10 includes a thin layer of an electronic insulator material 914 in series with a conductive metal oxide material 916, a first terminal 11 in communication with the first conductive trace 1, and a second terminal 12 in communication with the second conductive trace 2. Although the thickness of the electronic insulator material 914 will be application dependent, typically the thickness is approximately 50 Å or less. Preferably, the thickness of the electronic insulator material 914 is approximately 25 Å or less. A material for the conductive metal oxide 916 includes but is not limited to a manganite, such as a perovskite, for example. Examples of perovskites include but are not limited to praseodymium-calcium-manganese-oxygen (PCMO) and lanthanum-nickel-oxygen (LNO). Suitable materials for the electronic insulator material 914 include but are not limited to yttria stabilized zirconia (YSZ) and hafnium oxide (HfOX), for example.
The memory element 10 is electrically in series with the first and second terminals 11 and 12. The configuration depicted in FIG. 9A also applies to selected memory elements 10′. Accordingly in FIG. 9B, each memory element 10 is electrically in series with the first and second terminals (11, 12) and is electrically in series with the first and second conductive traces (1, 2). As depicted in FIG. 9B, the terminals 11 and 12 can be electrodes made from an electrically conductive material including but not limited to platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), and aluminum (Al), for example.
FIGS. 9A and 9B also depict the memory plug 300. The memory plug 300 includes the memory element 10 and any other materials that may be necessary to form an operable memory device. For example, the memory plug 300 includes the first and second terminals 11 and 12 that electrically couple the memory element 10 in series with the first and second conductive traces 1 and 2 and a portion of the first and second conductive traces 1 and 2 that cross the memory element 10. In FIG. 9B, the first and second terminals 11 and 12 comprise electrodes as was described above. One skilled in the art will appreciate that other layers of materials may be included in the memory plug 300. For example, those layers can include but are not limited to adhesion layers, glue layers, diffusion barriers, and seed layers.
One method of creating memory elements 10 that store data as a plurality of distinct resistive states is described in “Memory Using Mixed Valence Conductive Oxides,” U.S. application Ser. No. 11/095,026, filed Mar. 30, 2005, which is incorporated herein by reference in its entirety and for all purposes. The application describes a two terminal memory element that changes conductivity when exposed to an appropriate voltage drop across the two terminals. The memory element includes an electrolytic tunnel barrier and a mixed valence conductive oxide. A voltage drop across the electrolytic tunnel barrier causes an electrical field within the mixed valence conductive oxide that is strong enough to move oxygen ions out of the mixed valence conductive oxide and into the electrolytic tunnel barrier. When certain mixed valence conductive oxides (e.g., praseodymium-calcium-manganese-oxygen perovskites—PCMO and lanthanum-nickel-oxygen perovskites—LNO) change valence, their conductivity changes. Additionally, oxygen accumulation in certain electrolytic tunnel barriers (e.g., yttrium stabilized zirconia—YSZ) can also change conductivity. If a portion of the mixed valence conductive oxide near the electrolytic tunnel barrier becomes less conductive, the tunnel barrier width effectively increases. If the electrolytic tunnel barrier becomes less conductive, the tunnel barrier height effectively increases. Both mechanisms are reversible if the excess oxygen from the electrolytic tunnel barrier flows back into the mixed valence conductive oxide. A memory can be designed to exploit tunnel barrier height modification, tunnel barrier width modification, or both. One skilled in the art will recognize that some aspects of the present invention are not limited to a particular choice of memory elements.
In FIG. 9C, an exemplary memory plug 300 would preferably include a non-ohmic device 900 coupled with the memory element 10, as is described in “High Density NVRAM”, U.S. Pat. No. 6,917,539, which is incorporated herein by reference in its entirety and for all purposes. The memory plug 300 includes a plurality of separate thin film layers that are sandwiched between the first and second conductive traces 1 and 2. Those layers are the second terminal 12, the electronic insulator material 914, the conductive metal oxide material 916, the first terminal 11, a plurality of layers that make up a metal-insulator-metal (MIM) structure 923, 921, and 925 (providing the non-ohmic device 900), and an optional electrode 927. In the MIM structure, one of the plurality of layers is an insulator layer 921 (e.g., a dielectric material). The layers 11, 12, and 927 are only necessary to the extent fabrication methods require them. Therefore, the layers 11, 12, and 927 would ideally be as thin as possible while still preventing metal inter-diffusion and if necessary, being useful as a seed layer.
In FIG. 9D, in an alternative embodiment of the memory plug 300 the memory element 10 includes the conductive metal oxide material 916 electrically in series with the first and second terminals (11, 12) and electrically in series with the first and second conductive traces (1, 2). Unlike the memory element 10 depicted in FIG. 9B, the memory element 10 in FIG. 9D does not include the thin layer of the electronic insulator material 914.
In the embodiments depicted in FIGS. 9A through 9D, the first terminal 11, the second terminal 12, or both, can be a portion of the first and second conductive traces 1 and 2 if at least one of the electrodes is not needed to electrically couple the memory element 10 with the first and second conductive traces 1 and 2 in the array 100. Advantages to eliminating one or both of the terminals (11, 12) and coupling the memory element 10 with the first and second conductive traces (1, 2) include reducing microelectronic processing steps required to fabricate the array 100. Reducing the processing steps can result in an increase in device yield and lower manufacturing costs.
Furthermore, the embodiments depicted in FIGS. 9A through 9D do not need to operate in a silicon substrate, and, therefore, can be fabricated above circuitry fabricated on the silicon substrate and being used for other purposes (e.g., address, decode, and selection circuitry). Optionally, the apparatus 150 can include a stacked cross-point array as described in “Re-writable Memory With Multiple Memory Layers”, U.S. Pat. No. 7,095,643, which is incorporated herein by reference in its entirety and for all purposes. The stacked cross-point array consists of multiple cross point arrays 100 stacked upon one another, sometimes sharing first and second conductive traces (1, 2) between layers, and sometimes having electrically isolated and second conductive traces (1, 2) that are not shared between layers. Both single-layer cross-point arrays and stacked cross-point arrays may be arranged as third dimension memories. The apparatus 150 (i.e., sans the single-layer cross-point array or the stacked cross-point arrays) can be fabricated in a silicon substrate and the arrays can be fabricated above the substrate and electrically coupled with the apparatus 150 using an interconnect structure. One skilled in the art will appreciate that the substrate can include other circuitry that interacts with the apparatus 150 or that acts independently of the apparatus 150 (e.g., a μP, a DSP, a memory controller, programmable logic, or application specific logic).
FIG. 10 depicts an exemplary I-V curve 1000 for the non-ohmic device 900. The non-ohmic device 900 imparts a high resistance to the memory plug 300 at low voltages and a low resistance to the memory plug 300 at high voltages. Therefore, leakage current is limited at low voltages and current is able to flow at high voltages. Specifically, a low voltage might be considered to be approximately one-half of a first write voltage +1⁄2 VW1′ and approximately one-half a second write voltage −1⁄2 VW2′. A high voltage might be the first write voltage +VW1′ and the second write voltage −VW2′. For purposes of reading stored data from a selected memory element 10′ without disturbing or overwriting the stored data, a suitable voltage might be a first read voltage +VR1′ and a second read voltage −VR2′. Applying approximately one-half of the voltage to the memory plug 300 via the selected first conductive trace 1′ and applying approximately one-half of the voltage via the selected second conductive trace 2′ can be used to apply a full write voltage to a particular memory element 10′ while unselected memory elements 10 are not subject to excessive current. The non-ohmic device 900 exhibits a very high resistance regime for a certain range voltages (VNO− to VNO+) and a very low resistance regime for voltages above and below that range.
Generating a Data Signal
In FIG. 11, the total current IT and leakage current IL signals from the sense unit 103 may require additional processing in order to accurately derive a signal that is indicative of the stored data in the selected memory element 10′. Therefore, the apparatus 150 includes a data unit 1130 in communication with the sense unit 103. Signals in addition to the total current IT and the leakage current IL are electrically coupled with the data unit 1130 in order to derive the signal that is indicative of the stored data. During the read operation, the address unit 101 receives the address ADDR and selects the selected memory element 10′ by applying the appropriate read voltage VR across the selected conductive traces 1′ and 2′. In some embodiments using certain memory elements 10, the magnitude of the read voltage VR is non-destructive to the stored data in the selected memory element 10′. That is, the magnitude of the read voltage VR is not sufficient to overwrite or corrupt the stored data.
The application of the read voltage VR causes the total and leakage currents (IT, IL) to flow. The data unit 1130 combines the total current IT, the leakage current IL, and a reference signal RSIG to generate a data signal RDATA that is indicative of the value of stored data in the selected memory element 10′. For example, if the selected memory element 10′ is in the first resistive state R0 (i.e., high resistance), such that the read current IR is low, then RDATA will have a value indicative of the stored data being approximately a logic “0”. Conversely, if the selected memory element 10′ is in the second resistive state R1 (i.e., low resistance), such that the read current IR is high, then RDATA will have a value indicative of the stored data being approximately logic a “1”. Communication and control between the control unit 105 and the data unit 1130 can be effectuated by at least one signal 1109. One skilled in the art will appreciate that other units in the apparatus 150 may also communicate with and/or control operation of the data unit 1130. The reference signal RSIG can be generated by a reference generator 1140. The reference signal RSIG can be a voltage or a current. The reference generator 1140 can be in communication with and/or controlled by the address unit 101 and/or the control unit 105 as indicated by the dashed lines 1117, and 1111 respectively, or the reference generator 1140 can be part of the array 100 as described in “Two terminal memory array having reference cells”, U.S. application Ser. No. 10/895,218, filed on Jul. 20, 2004, now issued U.S. Pat. No. 7,075,817, which is incorporated herein by reference in its entirety and for all purposes, or can exist as memory elements positioned outside of the array 100.
Turning to FIG. 12A, in one embodiment of the data unit 1130, an add unit 1211 adds the leakage current IL with the reference signal RSIG and generates a sum signal SUM as an output (e.g., SUM≈IL+RSIG). Additionally, the data unit 1130 can include a comparator 1213 that compares the sum signal SUM with the total current IT and generates the data signal RDATA. In FIG. 12B, in an alternative embodiment of the data unit 1130, a subtract unit 1215 subtracts the leakage current IL from the total current IT and generates a difference signal DIFF as an output (e.g., DIFF≈IT−IL). Additionally, the data unit 1130 can include a comparator 1217 that compares the difference signal DIFF with the reference signal RSIG and generates the data signal RDATA.
In FIG. 12C, in yet another embodiment of the data unit 1130, the difference signal DIFF is generated by a subtract unit 1219 and the output of the subtract unit 1219 is coupled with a current-to-voltage converter (I/V converter) 1221. The I/V converter 1221 converts the difference signal DIFF from a current domain signal to a voltage domain signal. An output 1223 of the I/V converter 1221 is coupled with an input to a circuit 1225 that generates the data signal RDATA. The circuit 1225 can be a logic gate, such as a buffer or an inverter, for example. The circuit 1225 generates the data signal RDATA based on a value (e.g., a magnitude of the voltage) of the difference signal DIFF. For example, if the circuit 1225 is a logic gate that generates a logic “0” if the difference signal DIFF is below a first threshold voltage VT1 and generates a logic “1” if the difference signal DIFF is above a second threshold voltage VT2, then the value of the data signal RDATA will be determined by a property of the circuit 1225 and not by a comparison between signals (i.e., a comparison between RSIG and DIFF or a comparison between IT and SUM). Accordingly, the embodiment depicted in FIG. 12C provides one example in which the reference signal RSIG can be eliminated and the value of the data signal RDATA is indicative of a property (e.g., a threshold voltage) of the circuitry that generates the data signal RDATA. Optionally, an enable signal EN can be used to enable the circuit 1225 (e.g., switch the output between a logic state and a high-impedance state).
It may be desirable to perform the adding, subtracting, and comparing functions on voltages rather than currents. Accordingly, the leakage current IL, the total current IT, and optionally the reference signal RSIG may be processed as voltages by using an I/V converter to convert signals in the current domain to signals in the voltage domain or by sensing the voltages directly. Therefore, in FIG. 13A, an I/V converter 1301 converts leakage current IL to an equivalent voltage signal VL. Consequently, the add unit 1211 or subtract unit 1215 can receive the voltage signal VL instead of the leakage current IL. Similarly, in FIG. 13B, an I/V converter 1303 converts total current IT to an equivalent voltage signal VT and the comparator 1213 or subtract unit 1215 can receive the voltage signal VT as an input instead of the total current IT. In FIG. 14, an IV converter 1401 converts the reference signal RSIG to an equivalent voltage signal VSIG. Consequently, the add unit 1211 or the comparator 1217 can receive the voltage signal VSIG as an input in place of the reference signal RSIG.
Storing the Data Signal
Optionally, the value of RDATA can be stored for later use by the apparatus 150 or by another system in communication with the apparatus 150. In FIG. 11, the apparatus 150 includes a storage unit 1150 for storing the data signal RDATA. The storage unit 1150 can be a device including but not limited to a flip-flop, a latch, a buffer, and a register, for example. Moreover, the storage unit 1150 can output the stored data signal RDATA as a data out signal DOUT. The data out signal DOUT can be coupled with a data bus 1180, with the apparatus 150, or with another system in communication with the apparatus 150, for example. One skilled in the art will appreciate that the storage unit 1150 can include a tri-state buffer or the like so that the output of the storage unit 1150 can be placed in a high impedance state when the storage unit 1150 is not driving the data out signal DOUT onto the data bus 1180, for example. One skilled in the art will understand that the stored data in the memory elements 10 of the array 100 can be non-volatile and retain data in the absence of power; however, the storage unit 1150 may be fabricated from circuitry (e.g., CMOS circuitry) that does not retain the data signal RDATA in the absence of power.
In FIGS. 12A through 12C, the data signal RDATA is input into the storage unit 1150 and a signal Store can be pulsed (i.e., high or low) to store the data signal RDATA in the storage unit 1150. In FIG. 15, one example of an implementation of the storage unit 1150 is depicted. The data signal RDATA is connected to an input terminal 1521 of a FET 1510 and the other terminal 1523 of the FET 1510 is connected with an input 1515 of a latch comprising back-to-back inverters 1511 and 1513. The signal Store is connected with a gate 1512 of the FET 1510 and is driven high to allow the data signal RDATA to pass from the source node 1521 to the drain node 1523. The latch (1511, 1513), latches RDATA and the data out signal DOUT is driven onto an output 1517 of the latch. Optionally, the data out signal DOUT can be connected with an input 1526 of a tri-state buffer 1527. An output 1529 of the tri-state buffer 1527 can be connected to the data bus 1180. The tri-state buffer 1527 provides buffering and a high impedance output connection to the data bus 1180. A signal applied to the enable input 1528 can drive DOUT onto the data bus 1180 or place the output 1529 in a high-impedance state. Although only one-bit of data is depicted for RDATA and DOUT, one skilled in the art will appreciate that apparatus 150 can include multiple arrays 100 that can be simultaneously accessed during read or write operations such that several bits of data (e.g., bytes or words) are read or written during a memory access cycle. Therefore, the read data can be stored in a multi-bit register or latch and data bus 1180 can be a multi-bit wide data bus.
Pre-Read Timing
Referring to FIG. 20, a timing diagram depicts an example of timing for a pre-read operation that is triggered by a read operation to the array 100 as was described above. For example, a read enable signal RE can be used to initiate the pre-read operation. Accordingly, a low-to-high transition on RE indicates a read operation has been initiated. After the transition on RE and when the address ADDR is stable, a pre-read signal PR transitions high and causes the select voltages (VSR, VSC) to increase in magnitude from a zero voltage or the non-select voltage level, for example, to the aforementioned voltage levels for the read voltages VR1′ and VR2′. A maximum positive range and a maximum negative range for the select voltages are denoted by the dashed lines “+” and “−” for VSR and VSC respectively. Although the write voltages can be applied at or near their positive and negative maximums, the read voltages VR1′ and VR2′ are applied below the ±maximums to prevent overwriting the stored data during the pre-read operation. Consequently, the pre-read operation is non-destructive to stored data in the selected memory element 10′. Following the high transition on PR, the read voltages +VR1′ and −VR2′ are applied across the selected conductive traces 1′ and 2′. After a sufficient time has passed for the data unit 1130 to combine the total current IT, the leakage current IL, and optionally the reference signal RSIG, the data signal RDATA is generated. The Store signal can be pulsed to store the data signal RDATA in the storage unit 1150.
Pre-Reading Data During a Write Operation
Turning to FIG. 16, during a write operation to the array 100, the address unit 101 receives the address ADDR and selects the selected memory element 10′ to which write data DIN is to be written to. For example, write data DIN can be at least one bit of data from the data bus 1180. Prior to writing the write data DIN to the selected memory element 10′, the aforementioned pre-reading operation can optionally be performed and the stored data in the selected memory element 10′ can be compared with the write data DIN. If the value of the stored data and the value of the write data DIN are approximately equal to each other (i.e., the write data DIN is redundant to the stored data), then the write operation can be aborted to prevent the overwriting of identical data (i.e., RDATA≈DIN). For example, if DIN is a logic “0” and RDATA is indicative of a logic “0”, then there is no need to re-write the selected memory element 10′ to the R0 state. Similarly, if DIN is a logic “1” and RDATA is indicative of a logic “1”, then there is no need to re-write the selected memory element 10′ to the R1 state.
However, if RDATA≠DIN, then the write operation can be consummated, that is, DIN overwrites the current value of the stored data. Consequently, the value of DIN is written to the selected memory element 10′ by applying the appropriate write voltage VW across the selected first and second conductive traces 1′ and 2′. As was described above, the write voltage VW can be the combination of the first and second write voltages VW1′ and VW2′. For example, the address unit 101 can receive the write data DIN as an input and the value of the write data DIN can be used by the address unit 101 to determine the polarity and/or magnitude of the write voltage VW to be applied across the selected first and second conductive traces 1′ and 2′. For example, the write voltages can be +VW1′ and −VW2′ to write a logic “0” and −VW1′ and +VW2′ to write a logic “1”. One skilled in the art will appreciate that the write data DIN need not be coupled with the address unit 101 and that a signal from another unit in the apparatus 150 (e.g., the control unit 105) can be used to communicate the value of the write data DIN to the address unit 101.
During a write operation, before write data DIN is written to the selected memory element 10′, the pre-reading operation may be initiated to pre-read the stored data in the selected memory element 10′. Therefore, the select voltage applied across the selected first and second conductive traces 1′ and 2′ is initially the read voltage VR as was described above (e.g., VR1′ and VR2′). The data unit 1130 combines the write data DIN, the total current IT, the leakage current IL, and optionally the reference signal RSIG to generate the data signal RDATA as was described above in reference to FIGS. 11 through 15. After RDATA is generated, the write data DIN is compared with RDATA to determine whether or not to abort (RDATA≈DIN) or consummate (RDATA≠DIN) the write operation.
A signal Result can be generated based on the comparison between DIN and RDATA. A variety of means can be used to generate the signal Result, including but not limited to analog circuitry, digital circuitry, or a combination of analog and digital circuitry. Depending on the value of the signal Result, the write operation is either consummated or aborted. In FIG. 17A, an analog comparator 1701 compares RDATA with DIN and generates the signal Result. If necessary, additional circuitry can be used to convert Result into a logic level signal. On the other hand, in FIG. 17B, Result is a logic level output of a XOR gate 1703 that receives the signals RDATA and DIN as logic level signals. Alternatively, an adaptive programming scheme, such as described in “An Adaptive Programming Technique for a Re-Writable Conductive Memory Device”, U.S. Pat. No. 6,940,744, which is incorporated herein by reference in its entirety and for all purposes, can be used to generate the signal Result.
In FIG. 17C, a truth table depicts one example of logic for aborting or consummating the write operation using Result. The truth table depicts a XOR relationship between RDATA, DIN, and Result; however, one skilled in the art will appreciate that XOR logic depicted can be replaced by other logic that determines whether or not to abort or consummate the write operation. In row 1 of the truth table, RDATA and DIN are both approximately a logic “0” and in row 4, RDATA and DIN are both approximately a logic “1”. Therefore, in rows 1 and 4 where RDATA≈DIN, Result=0 and the write operation is aborted because the data to be written is redundant to the stored data in the selected memory element 10′. Consequently, there is no change in the stored data as denoted by the asterisk “*” in the “Stored Data” column of the truth table. The aborting of the write operation can be triggered by Result alone or by another signal that is generated in response to Result. In that Result=0, the voltages applied across the selected conductive traces (1′, 2′) do not reach write voltage magnitudes and the stored data in the selected memory element 10′ is not affected.
On the other hand, in row 2, RDATA=0 and DIN=1, and in row 3, RDATA=1 and DIN=0. Therefore, in rows 2 and 3 where RDATA≠DIN, Result=1 and the write operation is consummated because the stored data and the data to be written are different from each other (i.e., they are not redundant). Consequently, the stored data is overwritten with the value of DIN by applying the appropriate write voltages (VW1′, VW2′) across the selected conductive traces (1′, 2′).
Consummating the Write Operation
In FIG. 21A, a timing diagram depicts one example of a write operation to a selected memory element 10′ in which a pre-read operation is performed with a resulting consummation of the write operation. In this example, the Result from the pre-reading is a logic “1”; therefore, RDATA≠DIN and the stored data will be overwritten with the write data DIN. Initiation of the write operation is triggered by a high transition on a write enable signal WE, a stable write address on ADDR, and stable write data DIN on data bus 1180. A high transition on a pre-read signal PR triggers a transition of the select voltages applied across the selected first and second conductive traces 1′ and 2′. Therefore, the select voltage VSR for a row is applied to the selected first conductive trace 1′ and the select voltage VSC for a column is applied to the selected second conductive trace 2′.
Initially, the select voltages VSR and VSC are read voltages so that the stored data in the selected memory element 10′ can be read to determine whether or not to abort or consummate the writer operation. A maximum positive range and a maximum negative range for the select voltages are denoted by the dashed lines “+” and “−” for VSR and VSC respectively. The write voltages can be applied at or near their positive and negative maximums; however, the read voltages are applied below the positive and negative maximums to prevent overwriting the stored data during the pre-reading. Accordingly, at this stage of the write operation, stored data in the selected memory element 10′ is being pre-read to determine if RDATA≠DIN. A low-to-high transition on Result can be used to indicate that RDATA≠DIN. The low-to-high transition on Result causes the select voltages VSR and VSC to change (i.e., increase in magnitude) from the lower magnitude read voltages to the higher magnitude write voltages so that the stored data is overwritten by the write data DIN. The polarities of the write voltages will depend on the value of the write data DIN. For example, if the write data DIN is a logic “0” and RDATA is a logic “1”, then the polarities of the select voltages can be +VSR and −VSC to overwrite the logic “1” with the logic “0”. Conversely, if the write data DIN is a logic “1” and RDATA is a logic “0”, then the polarities of the select voltages can be −VSR and +VSC to overwrite the logic “0” with the logic “1”. In FIG. 21A, RDATA≈1 and DIN≈0; therefore, from the truth table in FIG. 18, Result=1 and the write operation is consummated to overwrite the stored data with the write data DIN. Following the low-to-high transition on Result, the Store signal can be used to by the system 150 to test the value of Result. If Result=1, then a transition on Store can be used to trigger (e.g., on a falling edge) the change in select voltage levels (VSR, VSC) from the lower level read voltages (VR1′, VR2′) to the higher level write voltages (VW1′, VW2′).
Aborting the Write Operation
In FIG. 21B, a timing diagram depicts one example of a write operation to a selected memory element 10′ in which a pre-read operation is performed with a resulting abort of the write operation. In this example, the Result from the pre-reading is a logic “0”. Therefore, RDATA≈DIN, and the stored data will not be overwritten by the write data DIN. The initiation of the write operation is the same as described above in reference to FIG. 21A. However, even though the Result signal is a logic “0”, the read voltages may be changing (i.e., increasing) to the write voltage levels in anticipation of the possibility that Result=1 and the write operation would be consummated. In this example, Result does not make the low-to-high transition and stays at a logic “0”. The Store signal can be used to by the system 150 to test the value of Result. If Result=0, then a transition on Store can be used to trigger (e.g., on a falling edge) a change in select voltage levels (VSR, VSC) that halts an increase in the select voltages VSR and VSC before they reach write voltages levels at or near the ±maximums. Consequently, the select voltages decrease to the lower level read voltages (VR1′, VR2′) thereby preventing the overwriting of the stored data with redundant write data DIN.
Write operations to the array 100 can be accomplished by applying the select voltages VSR and VSC at a write voltage magnitude to the selected first and second conductive traces 1′ and 2′ selected by the ADDR received by the address unit 101 such that the write voltage is applied across the terminals 11 and 12 of the selected memory element 10′. Therefore, the aforementioned pre-read operation is not necessary for write operations to the array 100 and may optionally be used, particularly when some of the aforementioned advantages to pre-reading are necessary for a specific application.
Equalizing Charge on Inputs
In the comparators depicted in FIGS. 12A, 12B, and 17A, residual charge can accumulate on the inputs to the comparators prior to a read or write operation or can be left-over voltage from a previous read or write operation. Accumulated charge can result in output signals (e.g., Result or RDATA) that are not accurate because the built up charge is added to the signals to be compared, such as RDATA and DIN, IT and SUM, or RSIG and DIFF, for example. Moreover, the charge build up on the inputs may not be equal for both inputs, resulting in an input bias to the comparator. Errors caused by input bias and/or by unequal charge build up can be substantially reduced or eliminated by using an equalization circuit to equalize the charge on the inputs to the comparator. One skilled in the art will appreciate that there are a variety of ways for implementing such equalization techniques, which are typically used with differential sensing circuits. In particular, a FET may be replaced by a CMOS pass gate with NMOS and PMOS transistors to pass all appropriate levels.
In FIG. 18, one example of an equalization circuit 1811 includes a FET 1820 with a gate node 1822 in communication with an EQ signal, a source node 1824 connected with an input 1825 of a comparator 1821, and a drain node 1826 connected with an input 1827 of the comparator 1821. Driving the EQ signal to a logic “1” turns the FET 1820 on, resulting in a low resistance path between the source 1824 and drain 1826 that equalizes built up charge on the inputs 1825 and 1827 of the comparator 1821. The equalization circuit 1811 can be used with the comparators 1213, 1217, and 1701 in FIGS. 12A, 12B, and 17A. The timing diagrams in FIGS. 20, 21A and 21B depict an optional use of the EQ signal to equalize charge build up. For example, in FIG. 20, during a pre-read operation, EQ can be pulsed after the select voltages (VSR, VSC) have stabilized. The pulse on EQ stays active long enough to equalize any charge build up on the inputs to a comparator (e.g., comparator 1213 or 1217). Prior to the signals at the inputs being compared to each other, EQ goes inactive, turning the FET 1720 off and placing a high impedance across the inputs to the comparator. Subsequently, the signals at the inputs can be compared and the comparator can generate an accurate value for RDATA.
As another example, in FIGS. 21A and 21B, for a write operation in which a pre-read is performed to determine whether or not the stored data RDATA is approximately equal to the write data DIN. The signal EQ can be pulsed prior to the comparison of RDATA and DIN in the comparator 1701 of FIG. 17A. The pulse on EQ stays active long enough to equalize any charge build up on the inputs to the comparator 1701 and then EQ goes inactive so that the signals RDATA and DIN can be compared and the comparator can generate an accurate value for Result.
Applying Select Voltages
In FIG. 22, the address unit 101 can include a row decoder 2251, a column decoder 2253, a row voltage switch 2255, and a column voltage switch 2257. The address ADDR from the address bus 125 can be divided into a row address 2203 and a column address 2205 that are coupled with their respective row and column decoders (2251, 2253). Read enable RE, write enable WE, direction DIR, and data in DIN signals can be coupled with both voltage switches 2255 and 2257. The row voltage switch 2255 can include the following voltages as inputs: read voltages +VR1 and −VR1, write voltages +VW1 and −VW1, and non-select voltage VNR. The column voltage switch 2257 can include the following voltages as inputs: read voltages +VR2 and −VR2, write voltages +VW2 and −VW2, and non-select voltage VNC.
For a read operation to a selected memory element 10′, the row voltage switch 2255 selects one of the read voltages (+VR1 or −VR1) and outputs the selected voltage as the row select voltage VSR. The row select voltage VSR is an input to the row decoder 2251. Based on the row address 2203, the row decoder 2251 applies the row select voltage VSR to the selected first conductive trace 1′ in the appropriate row in the array 100. Similarly, the column voltage switch 2257 selects one of the read voltages (+VR2 or −VR2) and outputs the selected voltage as the column select voltage VSC. The column select voltage VSC is an input to the column decoder 2253. Based on the column address 2205, the column decoder 2253 applies the column select voltage VSC to the selected second conductive trace 2′ in the appropriate column in the array 100. As a result, the memory element 10 positioned at the intersection of the selected first and second conductive traces (1′, 2′) becomes the selected memory element 10′ for the read operation.
Similarly, for a write operation to a selected memory element 10′, the row voltage switch 2255 selects one of the write voltages (+VW1 or −VW1) and outputs the selected write voltage to the row decoder 2251 as the row select voltage VSR. Based on the row address 2203, the row decoder 2251 applies the row select voltage VSR to the selected first conductive trace 1′. Furthermore, the column voltage switch 2257 selects one of the write voltages (+VW2 or −VW2) and outputs the selected write voltage to the column decoder 2253 as the column select voltage VSC. Based on the column address 2205, the column decoder 2253 applies the column select voltage VSC to the selected second conductive trace 2′.
The non-select voltages VNR and VNC for the rows and columns can be connected with their respective switches 2255 and 2257. The switches 2255 and 2257 pass those voltages through to their respective decoders 2251 and 2253 as depicted in FIG. 22. On the other hand, because the non-select voltages VNR and VNC for the rows and columns will be applied to all of the unselected conductive traces 1 and 2, the non-select voltages VNR and VNC can be connected directly to their respective decoders 2251 and 2253 and the connection to the switches 2255 and 2257 can be eliminated in certain applications. As will be described in greater detail below, the sense unit 103 can include a row current mirror 2261 and a column current mirror 2263 that output mirrored equivalents of the total current IT and the leakage current IL to the data unit 1130.
Turning now to FIG. 23A, the application of the select voltages VSR and VSC to the selected first and second conductive traces (1′, 2′) depends on the type of operation being performed. For a valid read operation, the row and column voltage switches 2255 and 2257 need to apply the appropriate read voltages. Similarly, for a valid write operation the appropriate write voltages must be applied. Therefore, if both RE and WE are active high signals, then for a valid read operation RE=1 and WE=0 and for a valid write operation is RE=0 and WE=1. When there is a conflict between RE and WE that results in either operation being invalid (i.e., RE=WE=1 or RE=WE=0), then row and column decoders 2251 and 2253 can apply the non-select voltages to all of the conductive traces (1, 2) in the array 100.
In FIG. 23B, a truth table depicts one example of logic for determining which select voltages to apply to the selected first and second conductive traces (1′, 2′) for read and write operations and which non-select voltages to apply during an invalid operation. For a valid read operation (i.e., RE=1 and WE=0) the row voltage switch 2255 selects −VR1 for the row select voltage VSR and the column voltage switch 2257 selects +VR2 for the column select voltage VSC. In this example, the same read voltage polarity (−VR1, +VR2) is selected for each read operation. For a valid write operation (i.e., RE=0 and WE=1) the polarities of the write voltages can depend on the value of the write data DIN. Therefore, when DIN=0, row voltage switch 2255 selects +VW1 and column voltage switch 2257 selects −Vw2. Conversely, when DIN=1, row voltage switch 2255 selects −VW1 and column voltage switch 2257 selects +Vw2. One skilled in the art will appreciate that the polarities of the select voltages for write operations may be reversed so that when WE=1 and DIN=0, the row select voltage VSR=−VW1 and column select voltage VSC=+VW2 and when WE=1 and DIN=1, the row select voltage VSR=+VW1 and column select voltage VSC=−VW2.
Optionally, a signal DIR can be used to select a polarity for the read voltages during a valid read operation. For example, when DIR=0, the row voltage switch 2255 selects −VR1 for the row select voltage VSR and the column voltage switch 2257 selects +VR2 for the column select voltage VSC. On the other hand, when DIR=1, the row voltage switch 2255 selects +VR1 for the row select voltage VSR and the column voltage switch 2257 selects −VR2 for the column select voltage VSC. The advantages of alternating read voltage polarity will be discussed in greater detail below.
Address Decoding
The address unit 101 receives and decodes the address ADDR from the address bus 125 and applies the appropriate select voltages and non-select voltages to the conductive traces 1 and 2 in the array 100. Referring again to FIG. 22, the address ADDR on the address bus 125 can be separated into the row address 2203 and the column address 2205, with the row decoder 2251 receiving the row address 2203 as an input and the column decoder 2253 receiving the column address 2205 as an input. To uniquely address one of the four first conductive traces 1 and one of the four second conductive traces 2 in the array 100, a two-bit wide row address 2203 and a two-bit wide column address are required. Therefore, to select a single memory element 10′, only one of the first conductive traces 1 can be the selected conductive trace 1′ and only one of the second conductive traces 2 can be the selected conductive trace 2′. Therefore, the two-bits of the row address 2203 are decoded to select which of the four first conductive traces 1 will be the selected first conductive trace 1′ for a read or write operation. Similarly, the two-bits of the column address 2205 are decoded to select which of the four second conductive traces 2 will be the selected second conductive trace 2′. The row and column decoders 2251 and 2253 apply the select voltages VSR and VSC to the selected first and second conductive traces 1′ and 2′ and apply the non-select voltages VNR and VNC to the remaining first and second conductive traces 1 and 2.
Row Decoder
Turning to FIG. 24A, an exemplary row decoder 2251 includes a logic unit 2451 and a switch unit 2453. The logic unit 2451 receives the two-bits (b[0], b[1]) from the row address 2203 as inputs. The logic unit 2451 outputs four row signals (ra, rb, rc, rd) that are coupled with the switch unit 2453. Based on the values of the row signals (ra, rb, rc, rd), the switch unit 2453 routes the select voltage VSR to the selected first conductive trace 1′ and routes the non-select voltage VNR to the unselected first conductive traces 1. The most significant bit of the row address 2203 is b[1] and the least significant bit is b[0]. For a given row address 2203, only one of the four row signals (ra, rb, rc, rd) will be a logic “1” and the remaining row signals will be a logic “0”. Accordingly, as one example of how the two-bits (b[0], b[1]) can be decoded, when b[1]=1 and b[0]=0, then the row signal rc is a logic “1” and the remaining three row signals (ra, rb, rd) are a logic “0”. Accordingly, the select voltage VSR is applied to the selected first conductive trace 1′ which corresponds to the first conductive trace 1 in row r2 of the array 100 and is depicted by a heavy dashed arrow connected with trace 1′. On the other hand, the non-select voltage VNR is applied to the remaining first conductive traces 1 in rows r0, r1, and r3 as depicted by the dashed arrows connected with first conductive traces 1.
A truth table in FIG. 24A depicts logic for the above example with the four possible values for the two-bits b[1:0] in the first column and the resulting values for the four row signals (ra, rb, rc, rd) in the adjacent columns. Therefore, for b[1:0]=10, rc=1 and ra, rb, rd=0. The columns denoted as R0, R1, R2, and R3 represent the outputs of four multiplexers in the switching unit 2453 that receive the row signals ra, rb, rc, and rd as inputs. Referring now to FIG. 25A, each multiplexer (R0, R1, R2, and R3) selects the select voltage VSR or the non-select voltage VNR based on the value of its input and applies the selected voltage to the first conductive trace 1 connected with the multiplexers output. Multiplexers R0, R1, R2, and R3 have their respective outputs connected with the first conductive traces 1 in rows r0, r1, r2, and r3 of the array 100. As will be appreciated by those skilled in the art, multiplexers R0, R1, R2, and R3 may actually choose from a variety of power supplies, such as +VR1, −VR1, +VW1, and −VW1. Accordingly, additional control signals can control which of these inputs is delivered to the selected first conductive trace 1′.
Therefore, in the truth table in FIG. 24A for b[1:0]=10, the row signal rc=1 and multiplexer R2 selects the select voltage VSR and applies it to the selected conductive trace 1′. The other multiplexers (R0, R1, and R3) select the non-select voltage VNR and apply it to the remaining first conductive traces 1 because their respective inputs ra, rb, and rd are a logic “0”. The truth table also depicts the outcome for the other values of b[1:0]. To uniquely select the selected memory cell 10′, the column decoder 2253 must also select the selected second conductive trace 2′ based on the bits b[3:2] of the column address 2205.
Column Decoder
In FIG. 24B, an exemplary column decoder 2253 includes a logic unit 2455 and a switch unit 2457. The logic unit 2455 receives two-bits (b[2], b[3]) from the column address 2205 as inputs. The logic unit 2455 outputs four column signals (ca, cb, cc, cd) that are coupled with the switch unit 2457. Based on the values of the column signals (ca, cb, cc, cd), the switch unit 2457 routes the select voltage VSC to the selected second conductive trace 2′ and routes the non-select voltage VNC to the unselected second conductive traces 2. The most significant bit of the column address 2205 is b[3] and the least significant bit is b[2]. For a given column address 2205, only one of the four column signals (ca, cb, cc, cd) will be a logic “1” and the remaining column signals will be a logic “0”. Accordingly, as another example of how the two-bits (b[2], b[3]) can be decoded, when b[3]=1 and b[2]=0, then the column signal cc is a logic “1” and the remaining three column signals (ca, cb, cd) are a logic “0”. Accordingly, the select voltage VSC is applied to the selected second conductive trace 2′ which corresponds to the second conductive trace 2 in column c2 of the array 100 and is depicted by a heavy dashed arrow connected with trace 2′. Conversely, the non-select voltage VNC is applied to the remaining second conductive traces 2 in columns c0, c1, and c3 as depicted by the dashed arrows connected with the second conductive traces 2.
A truth table in FIG. 24B depicts logic for the above example with the four possible values for the two-bits b[3:2] in the first column and the resulting values for the four column signals (ca, cb, cc, cd) in the adjacent columns. Therefore, for b[3:2]=10, cc=1 and ca, cb, cd=0. The columns denoted as C0, C1, C2, and C3 represent the outputs of four multiplexers in the switching unit 2457 that receive the column signals ca, cb, cc, cd as inputs. Referring now to FIG. 25B, each multiplexer (C0, C1, C2, and C3) selects the select voltage VSC or the non-select voltage VNC based on the value of its input and applies the selected voltage to the second conductive trace 2 connected with the multiplexers output. Multiplexers C0, C1, C2, and C3 have their respective outputs connected with the second conductive traces 2 in columns c0, c1, c2, and c3 of the array 100. As will be appreciated by those skilled in the art, multiplexers C0, C1, C2, and C3 may actually choose from a variety of power supplies, such as +VR2, −VR2, +VW2, and −VW2. Accordingly, additional control signals can control which of these inputs is delivered to the selected second conductive trace 2′.
Therefore, in the truth table in FIG. 24B, for b[3:2]=10, the column signal cc=1 and multiplexer C2 selects the select voltage VSC and applies it to the selected conductive trace 2′. The other multiplexers (C0, C1, and C3) select the non-select voltage VNC and apply it to the remaining second conductive traces 2 because their respective inputs ca, cb, and cd are a logic “0”. The truth table also depicts the outcome for the other values of b[3:2].
Accordingly, with the select voltages VSR and VSC applied to the selected first and second conductive traces 1′ and 2′ and the non-select voltages VNR and VNC applied to unselected traces 1 and 2, the memory element 10′ in row r2 and column c2 is uniquely selected for a read or a write operation. In a similar manner, the other memory elements 10 in the array 100 can be selected for a read or a write operation by providing appropriate row and column addresses 2203 and 2205.
Sensing Total and Leakage Currents
After the select voltages VSR and VSC have been applied across the selected conductive traces 1′ and 2′, the total current IT and the leakage current IL are sensed by the sense unit 103. Referring again to FIG. 25A, a power source 2504 supplies the row select voltage VSR and a power source 2506 supplies the column select voltage VSC. Similarly, a power source 2505 supplies the row non-select voltage VNR and a power source 2507 supplies the column non-select voltage VNC. Depending on the polarities of the select and non-select voltages, the power sources 2504, 2506, 2505, and 2507 will either sink or source current through the conductive traces they are connected with. The power sources 2504 and 2506 that supply the select voltages VSR and VSC will typically be supplying the read and write voltages +VR, −VR, +VW, and −VW. Accordingly, four separate power sources (or inputs if obtained externally) can be used. Although the power sources 2504 and 2506 are shown as separate components, a single power source for a particular magnitude (e.g., −VW) might be shared by multiple rows or columns across bit-blocks, shared by rows and columns in one or more bit-blocks, or might supply a single row or column.
One means for sensing the total current IT and/or the leakage current IL is to monitor the current flowing through the power source that supplies the select voltages VSR and VSC and non-select voltages VNR and VNC. The following examples describe how monitoring current flow can be used to sense IT and/or IL. As a first example, in FIG. 25A, power source 2504 sources the total current IT flowing through the selected first conductive trace 1′ and power source 2507 sinks the leakage current IL flowing through the unselected second conductive traces 2.
In that the row and column orientation is arbitrary, the total current IT flowing through the selected second conductive trace 2′ can be sensed by monitoring current flow through a power source and the leakage current IL flowing through the unselected first conductive traces 1 can be sensed by monitoring current flow through another power source.
Therefore, as a second example, in FIG. 25B, a power source 2506 sinks the total current IT flowing through the selected second conductive trace 2′ and a power source 2505 sources the leakage current IL flowing through the unselected first conductive traces 1. Therefore, the total current IT can be sensed by monitoring the current flow through power source 2504 or 2506 and the leakage current can be sensed by monitoring the current flow through power source 2507 or 2505.
Alternating Read Voltage Polarities
As was described above in reference to FIG. 23A, RE can be active high during a read operation and WE can be active high during a write operation. During read operations to the array 100, it may be desirable to toggle the DIR signal between “0” and “1”. Accordingly, a truth table in FIG. 26A depicts one example of logic for toggling DIR during a read operation. In the first row of the truth table, where RE=1 and DIR=0, the row select voltage VSR and the column select voltage VSC are set to −VR1 and +VR2 respectively. Conversely, in the second row, where RE=1 and DIR=1, the row select voltage VSR and the column select voltage VSC are set to +VR1 and −VR2 respectively. The control unit 105 can generate and control the toggling of DIR between logic “0” and logic “1” for successive read operations, for example. Reference is now made to FIG. 26B, where the toggling of DIR is depicted over a period of time in which four successive read operations are performed as indicated by a series of four pulses of the RE signal denoted as 1st, 2nd, 3rd, and 4th During the period depicted, DIR toggles from 0-to 1 for the 1st RE pulse, DIR is a 0 for the 2nd RE pulse, DIR toggles from 0-to-1 for the 3rd RE pulse, and DIR is a 0 for the 4th RE pulse.
One advantage to toggling DIR is that the polarity of the read voltages applied to selected memory cells 10′ is not always of the same polarity. Alternating read voltage polarity during a pre-read can reduce or eliminate data corruption caused by read disturbs in certain types of memory elements 10. A read disturb is caused by multiple read operations to a memory element 10 using a read voltage of unchanging polarity (e.g., +VR1 and −VR2). After several thousand or more read operations to the same memory element 10, the resistive state of the memory element 10 can be slowly degraded such that an accurate reading of the resistive state is not possible.
For example, if the memory element 10 is in the first resistive state of R0≈1 MΩ, then after one-million read operations to that memory element 10 using the same read voltage (e.g., +VR1 and −VR2), the read disturb may result in a gradual degradation in R0 from 1 MΩ to 0.8 MΩ. Consequently, during subsequent read operations to the same memory element 10, it may not be possible to accurately determine whether or not the stored data in the memory element 10 is a logic “0” or a logic “1”. By alternating read voltage polarity, the average read disturb over time is approximately zero because approximately fifty-percent of the read operations apply read voltages of +VR1 and −VR2 and approximately fifty-percent of the read operations apply read voltages of −VR1 and +VR2.
Although the above example illustrates the toggling of DIR in conjunction with a read operation, one skilled in the art will appreciate that alternating read voltages can be accomplished using signals other than DIR or using other signals in conjunction with DIR. For example, in that pre-reading can occur for a read operation or a write operation (i.e., to prevent the writing of redundant data), the pre-read signal PR can be used to effectuate the toggling of DIR. Moreover, for write operation where WE=1 and RE=0, the PR signal can be used to initiate a pre-read of the selected memory element 10′ to determine whether or not to abort or consummate the write operation. The pre-read signal PR can also initiate the toggling of DIR so that pre-reads during a write operation use alternating read voltages for the reasons set forth above.
Reference is now made to FIG. 27 where an example of a pre-read during either a read operation or a write operation depicts a first rising edge 2703 on PR resulting in DIR rising to a logic “1”, a second rising edge 2705 on PR resulting in DIR falling to a logic “0”, and a third rising edge 2707 on PR resulting in DIR rising to a logic “1”. Therefore, over a course of three assertions of PR, the signal DIR toggles from 1-to-0 and then from 0-to-1. Consequently, during the pre-read, the average read disturb over time is approximately zero because approximately fifty-percent of the read operations apply read voltages of +VR1 and −VR2 and approximately fifty-percent of the read operations apply read voltages of −VR1 and +VR2. As was mentioned above, the DIR signal can be eliminated and PR or some other signal can be used to effectuate alternating the read voltage polarities.
Two-Cycle Pre-Read Operation
The signals that represent the leakage current IL and the total current IT can be sensed in two-cycles. During both cycles, the currents IL and IT are sensed flowing through the same selected conductive trace (i.e., 1′ or 2′). Each of the currents IL and IT can be stored after being sensed so that the leakage current IL and the total current IT can be compared to each other. Preferably, the currents IL and IT are converted to voltages and then stored. Subsequently, a comparator can be used to compare a voltage equivalent of IL with a voltage equivalent of IT. For example, the comparator can subtract the voltage equivalent of IL from voltage equivalent of IT to generate a signal indicative of the read current IR and that signal can be compared with RSIG to generate the data signal RDATA. As another example, as was described above, a property of a device (e.g., logic threshold voltage or a trip point of a logic gate) combined with a signal can be used to generate the data signal RDATA.
First Cycle Current Sensing
Turning to FIG. 28A, a first cycle of an exemplary two-cycle pre-read operation includes the address unit 101 receiving the address ADDR during a read operation. As was described above, the address ADDR can include the row address 2203 received by the row decoder 2251 and the column address 2205 received by the column decoder 2253. In that the currents IL and IT are sensed flowing through the same selected conductive trace in both the first and second cycles, during the first cycle, either the row decoder 2251 selects one of the first conductive traces 1′ in the rows of the array 100 and both currents IL and IT are sensed flowing through the selected first conductive trace 1′ or the column decoder 2253 selects one of the second conductive traces 2′ in the columns of the array 100 and both currents IL and IT are sensed flowing through the selected second conductive trace 2′.
In the embodiment depicted in FIG. 28A, the currents IL and IT are sensed flowing through the selected second conductive trace 2′. Accordingly, the address ADDR selects the 10th memory element 10′ (i.e., m10 at r2, c2) and the column decoder 2253 selects second conductive trace 2′ based on the bits for the column address 2205 being set to b[3:2]=10. Consequently, the power source 2506 applies the column select voltage VSC to the selected second conductive trace 2′ at a read voltage magnitude (e.g., +VR2′ or −VR2′). In a truth table in FIG. 28A, during the first cycle with b[3:2]=10, the non-select voltage VNR is applied to all of the first conductive traces 1 and the non-select voltage VNC is applied to the remaining second conductive traces 2. As a result, memory elements m2, m6, m10, and m14 have one of their terminals (i.e., 11) connected with the non-select voltage VNR and the other of their terminals (i.e., 12) connected with the select voltage VSC, such that those memory elements are half-selected memory elements hc through which half-select currents IH0, IH1, IH2, and IH3 flow. The leakage current IL approximately is the sum of the half-select currents (i.e., IL≈IH0+IH1+IH2+IH3). It should be noted that during the first cycle of the two-cycle pre-read operation, the 10th memory element 10′ (i.e., m10) is also a half-selected memory element hc (i.e., it is not fully selected during the first cycle).
Second Cycle Current Sensing
Turning now to FIG. 28B, in a second cycle, bits b[1:0]=10 of the row address 2203 result in the row select voltage VSR being applied to a selected first conductive trace 1′ such that the 10th (i.e., m10) memory element 10′ is a fully selected memory element Sc and has appropriate read voltages applied across both of its terminals 11 and 12 (e.g., +VR1′ and −VR2′). Therefore, during the second cycle, the read current IR flows through the selected memory element 10′ and the total current IT flowing through the selected second conductive trace 2′ approximately is the sum of the read current IR and the remaining half-select currents IH0, IH1, and IH3 such that IT≈IH0+IH1+IR+IH3. The read current IR can be determined by taking the difference between the total current IT and the leakage current IL, that is, the read current IR approximately is IR≈IT−IL.
Sensing Leakage Current and Total Current
In FIG. 28C, an exemplary circuit for sensing the total current IT and the leakage current IL includes a current mirror circuit connected in series with the power source that supplies the read voltage to the selected conductive trace (i.e., 1′ or 2′). The current mirror circuit is used for sensing the magnitudes of both the total current IT and the leakage current IL. Therefore, in FIG. 28C, a column current mirror 2263 is electrically in series with the column switch 2257 and column decoder 2253. A current I2 represents current that flows through the selected second conductive trace 2′ during the first and second cycles of the two-cycle pre-read operation. A mirrored current IM2 represents a mirrored current that is output by the column current mirror 2263 at a node 2851. Therefore, during the first cycle, the mirrored current IM2 is approximately equal to the leakage current IL (i.e., IM2≈IL) and during the second cycle the mirrored current IM2 is approximately equal to the total current IT (i.e., IM2≈IT).
Storing and Comparing Signals
Reference is now made to FIG. 28D where an exemplary circuit 2800 for comparing the leakage current IL and the total current IT includes an I/V converter 2801 that receives the mirrored current IM2 and converts the mirrored current IM2 into an output voltage V2. The voltage V2 is connected with the input terminals of FET 2811 and FET 2813. Signals PR1 and PR2 are connected with the gate terminals of FET 2811 and FET 2813, respectively. During the first cycle, the signal PR1 turns FET 2811 on and the signal PR2 turns FET 2813 off. Therefore, when the FET 2811 is on, the voltage V2 charges a capacitor 2815 that is connected with an output terminal of the FET 2811. The signal PR1 is held active (e.g., is a logic 1) long enough for capacitor 2815 to charge to a level of the voltage V2. Accordingly, a voltage equivalent to the leakage current IL is applied to a first terminal 2802 of an operation block 2805.
Similarly, during the second cycle, the signal PR2 goes active (e.g., is a logic 1) turning on FET 2813 and the signal PR1 goes inactive (e.g., is a logic 0) turning off FET 2811 thereby preserving charge in the capacitor 2815 and the voltage applied to the first terminal 2802. Therefore, when the FET 2813 is on, the voltage V2 charges a capacitor 2817 that is connected with an output terminal of the FET 2813. The signal PR2 is held active long enough for capacitor 2817 to charge to a level of the voltage V2. Accordingly, a voltage equivalent to the total current IT is applied to a second terminal 2804 of the operation block 2805.
The operation block 2805 operates on voltage equivalents of the total current IT and leakage current IL, and optionally, other signals (e.g., RSIG), to generate the data signal RDATA on an output node 2806. Generation of the data signal RDATA by the operation block 2805 will be application specific and will depend on which signals in addition to those on the terminals 2802 and 2804 are coupled with the operation block 2805. As one example, the operation block 2805 can subtract the voltages at first and second the terminals 2802 and 2804 from each other to generate the data signal RDATA. The output signal 706 can be connected with an input terminal of the storage unit 1150 as was described above.
Preferably, before the first cycle begins, a signal DIS is asserted to discharge the capacitors 2815 and 2817 to an approximately equal potential so that voltages on the first and second terminals 2802 and 2804 are equalized (e.g., are approximately 0 Volts or approximately equal voltages). The DIS signal is connected to the gate terminals of FET 2819 and FET 2821. The input terminals of FET 2819 and FET 2821 are connected to a ground potential and the output terminals of FET 2819 and FET 2821 are connected with the first and second terminals 2802 and 2804 of the operation block 2805, respectively. Therefore, when the signal DIS goes active (e.g., is a logic 1), the capacitors 2815 and 2817 discharge prior to the start of the first cycle. Additionally, the nodes 2802 and 2804 can also be equalized by an FET while the DIS signal is active, to ensure that these two nodes are at the same value before the beginning of the two read cycles.
Optionally, the operation block 2805 can receive the reference signal RSIG and the voltages at the first and second terminals 2802 and 2804 can be used in conjunction with the reference signal RSIG to derive the data signal RDATA. As one example, the voltages at the first and second terminals 2802 and 2804 can be subtracted from each other to generate a difference signal that is compared with the reference signal RSIG to generate the data signal RDATA. As another example, the voltage at the first terminal 2802 and the reference signal RSIG can be added to each other and the sum compared with the voltage at the second terminal to generate the data signal RDATA. Preferably, the signals received by the operation block 2805 are in the voltage domain.
FIG. 28E depicts an exemplary timing diagram for a two-cycle pre-read operation. The two-cycle pre-read operation is initiated by a high transition on the read enable signal RE and a stable read address on ADDR. The transition on RE causes the discharge signal DIS to go active thereby discharging the capacitors 2815 and 2817. A falling edge on the signal DIS initiates the first cycle and the signal PR1 goes active resulting in the read voltage −VR2′ being applied to the selected second conductive trace 2′. The resulting leakage current IL flowing through the selected second conductive trace 2′ is converted to the voltage V2 and charges the capacitor 2815 via the FET 2811. A falling edge on PR1 initiates the second cycle and the signal PR2 goes active resulting in the read voltage +VR1′ being applied to the selected first conductive trace 1′. The resulting total current IT flowing through the selected second conductive trace 2′ is converted to the voltage V2 and charges the capacitor 2817 via the FET 2813. The capacitor 2815 applies a voltage that is equivalent to the leakage current IL to the first terminal 2802 and the capacitor 2817 applies a voltage that is equivalent to the total current IT to the second terminal 2804. Subsequent to PR1 and PR2 going inactive, FET 2811 and FET 2813 are turned off to prevent charge from draining out of the capacitors 2815 and 2817 so that the voltages at terminals 2802 and 2804 are stable. Consequently, the operand block 2805 generates the data signal. The Store signal can be pulsed to store the value of RDATA in the storage unit 1150.
Those skilled in the art can appreciate that the apparatus 150 may include arrays 100 that are configured into one or more memory banks. A memory bank can provide read/write access to one bit of data or multiple bits of data. If one bit of data is accessed, the memory bank can be referred to as a bit block. Turning now to FIG. 28F, the apparatus 150 includes two memory banks 2850 and 2860. Some of the circuitry previously depicted in apparatus 150 and the arrays 100 have been omitted in order to explain two-cycle pre-read operation for multi-bit memory banks. The memory banks 2850 and 2860 are multi-bit banks with each bank partitioned into two portions as denoted by a dashed line that defines partitions 2851 and 2853 in bank 2850 and partitions 2861 and 2863 in bank 2860. The banks 2850 and 2860 with their associated partitions (2851, 2853 and 2861, 2863) provide two-cycle pre-read access to data in four memory cells. For example, if a word is 4-bits wide, and each memory cell holds a single bit, one word can be read from or written to the banks 2850 and 2860.
Current Sensing
An exemplary means for sensing the currents IT and IL is to use a current mirror circuit. Referring back to FIG. 22, an exemplary sense unit 103 includes a row current mirror 2261 and a column current mirror 2253. The row current mirror 2261 is electrically in series with the row switch 2255 and the row decoder 151. The column current mirror 2263 is electrically in series with the column switch 2257 and the column decoder 2253. The mirrored currents IMT1 and IML2 depict one embodiment where IMT1 is the mirrored total current and is substantially equal to the total current IT flowing through the selected first conductive trace 1′; whereas, IML2 is the mirrored leakage current flowing through unselected second conductive traces 2 and is substantially equal to the leakage current IL. Accordingly, the mirrored currents IMT1 and IML2 are output as the total current IT and the leakage current IL by the sense unit 103 and those currents serve as inputs to the data unit 1130.
Turning now to FIG. 29A, where exemplary row and column current mirrors 2261 and 2263 are depicted in greater detail. The row voltage switch 2255 selects read voltage +VR1 (i.e., for a read operation) and the row decoder 2251 applies the read voltage +VR1 to the selected first conductive trace 1′. The row decoder 2251 also applies the non-select voltage VNR to the unselected first conductive traces 1. The row current mirror 2261 is electrically in series with the row voltage switch 2255 and the row decoder 2251 so that the current flowing from the power source 2504 (see FIG. 25A) that supplies the select voltage VSR (e.g., +VR1) can be mirrored. Therefore, the total current IT from the power source 2504 that supplies the select voltage VSR, flows through the row voltage switch 2255, the row current mirror 2261, the row decoder 2251, and through the selected first conductive trace 1′. The total current IT is mirrored by the row current mirror 2261 and is output as a mirrored total current IMT1 on a node 2903. In FIG. 22, the node 2903 connects with the data unit 1130 and is denoted by the heavy solid line for IMT1.
Column voltage switch 2257 selects the read voltage −VR2 and the column decoder 2253 applies the read voltage −VR2 to the selected second conductive trace 2′. The column decoder 2253 also applies the non-select voltage VNC to the unselected second conductive traces 2. The column current mirror 2263 is electrically in series with the column voltage switch 2257 and the column decoder 2253 so that the current flowing from the power source 2507 (see FIG. 25A) that supplies the non-select voltage VNC can be mirrored. Therefore, the leakage current IL from the power source 2507 that supplies non-select voltage VNC, flows through the column voltage switch 2257, the column current mirror 2263, the column decoder 2253, and through the unselected second conductive traces 2. The leakage current IL is mirrored by the column current mirror 2263 and is output as a mirrored total leakage current IML2 on a node 2905. In FIG. 22, the node 2905 connects with the data unit 1130 and is denoted by the heavy solid line for IML2.
Reference Signal Generation
The reference signal RSIG can be generated by a reference generator 1140 that outputs the reference signal RSIG as a current or a voltage. One means of generating the reference signal RSIG is to use a constant current source or a constant voltage source. If RSIG is a current, then an I/V converter (e.g., 1401 in FIG. 14) can be used to convert RSIG to a voltage (e.g., VSIG). RSIG can be generated by an off-chip reference source and supplied to the apparatus 150 via an input pad, for example. Preferably, the reference signal RSIG is internally generated as opposed to being externally generated (i.e., off-chip via an input pad).
Alternatively, in FIG. 30A, the reference generator 1140 comprises a reference memory element 10r with a reference resistance RR. The reference resistance RR can be fixed at a predetermined value or the reference resistance RR can be programmed to a desired valued. The desired value for the reference resistance RR can be intermediate between the high and low resistance states R0 and R1, for example. The reference memory element 10r includes a first terminal 11r connected with a first conductive trace 1r and a second terminal 12r connected with a second conductive trace 2r. The reference memory element 10r is electrically in series with the first terminal 11r and the second terminal 12r and is also electrically in series with the first conductive trace 1r and the second conductive trace 2r. The reference memory element 10r, the terminals 11r and 12r, and the conductive traces 1r and 2r can be integrated with the array 100. The first conductive trace 1r can be associated with the x-axis direction of the first conductive traces 1 in the rows and the second conductive trace 2r can be associated with the y-axis direction of the second conductive traces 2 in the columns. During a pre-read operation, a reference voltage is applied across the first and second conductive traces 1r and 2r so that a reference current ISIG flows through the reference memory element 10r. For example, the reference voltage can include an x-direction voltage VX applied to the first conductive trace 1r and a y-direction voltage VY applied to the second conductive trace 2r. The voltages (VX, VY) can have opposite polarities and can have magnitudes that are approximately equal. For example, the magnitudes and polarities of VX and VY can be the same as those for the read voltage VR as described above.
In FIG. 30B, a voltage switch 3055 selects between a x-direction reference voltage VRX, a x-direction non-select voltage VNX, and a x-direction programming voltage VPX based on a value of a pre-read signal PR and a program signal PGM. A truth table depicts one example of logic for the switch 3055. Accordingly, with PGM=0, the x-direction voltage VX=VNX when PR=0 and the x-direction voltage VX=VRX when PR=1. Similarly, a voltage switch 3057 selects between a y-direction reference voltage VRY, a y-direction non-select voltage VNY, and a y-direction programming voltage VPY based on the value of the pre-read signal PR and the program signal PGM. A truth table depicts one example of logic for the switch 3057. Accordingly, with PGM=0, the y-direction voltage VY=VNY when PR=0 and the y-direction voltage VY=VRY when PR=1. Therefore, when PR=1 the reference current ISIG flows through the reference memory element 10r because of a potential difference of |VRX−VRY| across the first and second conductive traces 1r and 2r. For the same reasons described above for the first and second conductive traces 1 and 2, it may also be desirable to prevent the first and second conductive traces 1r and 2r from floating during a read operation to the array 100. During a write operation to the array 100, the first and second conductive traces 1r and 2r may be allowed to float. Therefore, when PR=0, the non-select voltages VNX and VNY are applied to the first and second conductive traces 1r and 2r. The non-select voltages VNX and VNY can be identical to the non-select voltages VNR and VNC, and the reference voltages VRX and VRY can be identical to the select voltages VSR and VSC.
Programming the desired value for the reference resistance RR can be accomplished by applying an appropriate programming voltage across the first and second conductive traces 1r and 2r of the reference memory element 10r. A magnitude and polarity of the programming voltage can be selected to set the desired value for the reference resistance RR. For example, the programming voltage can be two separate voltages VPX and VPY. Programming voltages VPX and VPY can be internally generated in the apparatus 150 or they can be supplied by an external voltage source connected with the apparatus 150 by input pads, for example. Moreover, the programming of the reference resistance RR can occur during a manufacturing process for the apparatus 150 or a system that includes the apparatus 150. As one example, automatic test equipment (ATE) can be used to apply test vectors to the apparatus 150 and voltage sources coupled with the ATE can be used to supply the programming voltages VPX and VPY to pads on the apparatus 150 to program the desired value for the reference resistance RR. For example, when the apparatus 150 is in a test mode or a programming mode, the program signal PGM can be active high (i.e., PGM=1) and based on the truth table in FIG. 30B the voltage switches 3055 and 3057 select programming voltages VPX and VPY respectively and those voltages are applied to the first and second conductive traces 1r and 2r. The program signal PGM can be internally generated by the apparatus 150 based on a value of some other signal or the program signal PGM can be externally generated and supplied to the apparatus 150 via an input pad, for example. A software program can control the magnitude and the polarity of the programming voltages VPX and VPY generated by the voltages sources within the ATE. The ATE can also be used to sense current flowing through the reference memory element 10r during programming or after programming to determine whether or not the desired value for the reference resistance RR has been obtained.
Reference Signal Sensing
A current mirror can also be used to sense the reference current ISIG and to generate the reference signal RSIG. For example, in FIG. 31, the reference generator 1140 includes an x-direction current mirror 3151 coupled with the voltage switch 3055 and the row decoder 2251. During the pre-read operation, with PR=1, the reference current ISIG that flows from the x-direction reference voltage VRX is mirrored by the x-direction current mirror 3151 and is output as the reference signal RSIG. The reference signal RSIG can be converted to a voltage using an I/V converter as was described above. In this example, the total current IT flowing through the selected first conductive trace 1′ is mirrored by the current mirror 2261 and is sensed by the sense unit 103. The pads used for programming the reference resistance RR may be used for some other function when the apparatus 150 is not in the test mode or program mode.
Reference Resistance
A value for the reference resistance RR for the reference memory element 10r can be selected to fall between the values for the first resistive state R0 and the second resistance state R1. As a first example, if R0≈1MΩ and R1≈100 kΩ, then the reference resistance RR can be selected to be about half-way in between the values for R0 and R1 (e.g., RR≈550 kΩ). As a second example, the reference resistance RR can be selected to be approximately half-way on a logarithmic scale such that RR≈300 kΩ). As a third example, another method for selecting the value for the reference resistance RR can be based on selecting desired magnitudes for the read current IR and the half-select currents IH. For example, in FIG. 30A, if IR=10 μA for the second resistance state R1 and IR=1.0 μA for the first resistive state R0, then the value for the reference resistance RR can be selected so that ISIG=5 μA when a potential difference of |VX−VY| is applied across the conductive traces 1r and 2r Those skilled in the art will appreciate that some memory elements 10 can be directly programmed to the desired reference resistance RR.
Alternatively, FIG. 32 depicts one embodiment where a plurality of the reference memory elements 10r can be arranged in both serial and parallel to form a resistive circuit 3200 that produce the desired reference resistance RR. The conductive traces 1r and 2r can be connected with nodes 11r and 12r of the resistive circuit 3200. Some of the reference memory element 10r are programmed to the first resistive state R0 and some of the reference memory element 10r are programmed to the second resistive state R1. The resulting reference resistance RR is determined by the series and parallel resistances of the resistive circuit 3200. The reference memory elements 10r need not be programmed to the first and second resistive states (R0 and R1) and can be programmed to values that are between the first and second resistive states (R0 and R1) or on a logarithmic scale, for example. One skilled in the art will understand that the resistive circuit 3200 need not be configured as depicted in FIG. 32 and that other circuit configurations using different combinations of a plurality of the reference memory elements 10r can be used to obtain a desired value for the reference resistance RR. Moreover, the apparatus 150 may include a plurality of reference resistances RR that are programmed to predetermined resistance values that can be different from each other.
Method of Sensing Current
The sensing of the total current IT and the leakage current IL can be accomplished using hardware, software, or a combination of hardware and software. Software for sensing the currents can be implemented in a computer readable media including but not limited to RAM, ROM, optical disc, magnetic disc, magnetic tape, firmware, communicated over a network electrically, optically, or wirelessly (e.g., a LAN), volatile memory, and non-volatile memory, just to name a few. The software can be code running on a computer such as a PC or a microprocessor, for example.
Referring now to FIG. 33, a flow chart depicts a method 3300 for sensing current in a two-terminal memory array. At a stage 3301, the array 100 including a plurality of first and second conductive traces 1 and 2 is provided. Alternatively, at the stage 3301, a plurality of bit-block arrays 100 may be provided (see FIGS. 2C and 2D), with each bit-block array 100 including a plurality of first and second conductive traces 1 and 2. As was described above, the array 100 can be a two-terminal cross-point array. At a stage 3303, an address ADDR is received and is operative to select at least one of the plurality of first conductive traces 1′ and at least one of the plurality of second conductive traces 2′. At a stage 3305 a select voltage VSR and VSC is applied across the selected first and second conductive traces 1′ and 2′. At a stage 3307, a non-select voltage VNR and VNC is applied to unselected conductive traces 1 and 2. At a stage 3309, a total current IT flowing through the selected first conductive trace 1′ is sensed. At a stage 3311, a leakage current IL flowing through unselected second conductive traces 2 is sensed. One skilled in the art will understand that at the stage 3309, the total current IT can be sensed flowing through the selected second conductive trace 2′ and at the stage 3311, the leakage current IL can be sensed flowing through unselected first conductive traces 1.
In FIG. 33A, the method may optionally include, at a stage 3321, combining the total current IT, the leakage current IL, and a reference signal RSIG to generate a data signal RDATA. At a stage 3331, a decision to store the data signal RDATA can be implemented. If the YES branch is selected, then at a stage 3333, the data signal RDATA is stored. If the NO branch is selected, then the method terminates. The combining step at the stage 3321 can include additional steps such as adding, subtracting, and comparing steps, for example. The combining step at the stage 3321 can occur after the stage 3311, for example.
The method 3300 may optionally include an adding step as depicted in FIG. 33B, where at a stage 3323, the reference signal RSIG is added to the leakage current IL to generate a sum signal SUM. At a stage 3325, the sum signal SUM is compared with the total current IT to generate the data signal RDATA. The adding at the stage 3323 and the comparing at the stage 3325 can be accomplished using the add unit 1211 and the comparator 1213 as described above in reference to FIG. 12A. For example, the stages 3323 and 3325 can occur during or after the stage 3321 and the stage 3331 can occur after the stage 3325.
The method 3300 may optionally include a subtracting step as depicted in FIG. 33C, where at a stage 3327, the leakage current IL is subtracted from the total current IT to generate a difference signal DIFF. At a stage 3329, the difference signal DIFF is compared with the reference signal RSIG to generate the data signal RDATA. The stages 3327 and 3329 can be implemented using the subtract unit 1215 and the comparator 1217 as described above in reference to FIG. 12B. For example, the stages 3327 and 3329 can occur during or after the stage 3321 and the stage 3331 can occur after the stage 3329.
Turning now to FIG. 34, a flow chart depicts a method 3400 for sensing current in a two-terminal memory array. At a stage 3401, the array 100 including a plurality of first and second conductive traces 1 and 2 is provided. Alternatively, at the stage 3401, a plurality of bit-block arrays 100 may be provided (see FIGS. 2C and 2D), with each bit-block array 100 including a plurality of first and second conductive traces 1 and 2. Optionally, the arrays 100 may be configured into memory banks (see 2850 and 2860 in FIG. 28F). As was described above, the arrays 100 can be two-terminal cross-point arrays. At a stage 3403, an address ADDR is received and the address ADDR is associated with one of the selected first conductive traces 1′ and one or more of the selected second conductive traces 2′. At a stage 3405, a first select voltage VSC is applied to the one or more selected second conductive traces 2′ during a first cycle and during a second cycle. At a stage 3407, a non-select voltage is applied to the plurality of first conductive traces 1 (e.g., VNR) and to un-selected second conductive traces 2 (e.g., VNC) during the first cycle. Therefore, during the first cycle, the non-select voltage VNR is applied to all of the plurality of first conductive traces 1; whereas, the non-select voltage VNC is applied to only a subset of the plurality of second conductive traces 2 (see FIG. 28A). At a stage 3409, one or more leakage currents IL are sensed flowing through the one or more selected second conductive traces 2′ during the first cycle.
At a stage 3411, a second select voltage VSR is applied to the selected first conductive trace 1′ during the second cycle. Furthermore, during the second cycle, the non-select voltage (e.g., VNR and VNC) are applied to the un-selected first and second conductive traces 1 and 2. Therefore, during the second cycle, the second select voltage VSR is applied only to one of the plurality of first conductive traces (i.e., selected conductive trace 1′). A remaining portion of the plurality of first conductive traces 1 are un-selected traces, and the non-select voltage VNR is applied to those un-selected traces. Also during the second cycle, the first select voltage VSC is applied only to the one or more selected second conductive traces 2′. A remaining portion of the plurality of second conductive traces 2 are un-selected traces and the non-select voltage VNC is applied to those un-selected second conductive traces 2 (see FIG. 28B). At a stage 3413, one or more total currents IT are sensed flowing through the one or more selected second conductive traces 2′ during the second cycle.
In FIG. 34A, the method 3400 may optionally include at a stage 3410, storing one or more first values that are indicative of each of the one or more leakage currents IL in a first circuit. For example, the stage 3410 can occur after the stage 3409. The method 3400 may optionally include at a stage 3414, storing one or more second values that are indicative of the one or more total currents IT in a second circuit. The stage 3414 can occur after the stage 3413, for example. Furthermore, the method 3400 may optionally include at a stage 3419, combining the one or more first values, the one or more second values, and at least one reference signal RSIG to generate one or more data signals RDATA. The stage 3419 can occur after the stage 3414, for example.
Referring now to FIG. 34B, the method 3400 may optionally include at a stage 3421, adding the at least one reference signal RSIG to each of the one or more first values to obtain one or more sum signals SUM. At a stage 3423, the one or more sum signals SUM are compared with each of the one or more second values to generate the one or more data signals RDATA. The stage 3421 can occur after the stage 3419, for example.
Reference is now made to FIG. 34C, where the method 3400 may optionally include at a stage 3427, subtracting the one or more first values from each of the one or more second values to generate one or more difference signals DIFF. At a stage 3429, the one or more difference signals DIFF are compared with the at least one reference signal RSIG to generate the one or more data signals RDATA. The stage 3427 can occur after the stage 3419, for example.
Although several embodiments of an apparatus and a method of the present invention have been disclosed and illustrated herein, the invention is not limited to the specific forms or arrangements of parts so described and illustrated. The invention is only limited by the claims.

## Claims

1. A method for sensing current in a two-terminal memory, comprising:
providing an array including a plurality of first conductive traces and a plurality of second conductive traces;
receiving an address associated with a selected first conductive trace from the plurality of first conductive traces and one or more selected second conductive traces from the plurality of second conductive traces;
applying a first select voltage to one or more selected second conductive traces during a first cycle and during a second cycle;
applying a non-select voltage potential to the plurality of first conductive traces and unselected second conductive traces during the first cycle;
sensing one or more leakage currents flowing through the one or more selected second conductive traces during the first cycle;
applying a second select voltage to the selected first conductive trace during the second cycle while applying the non-select voltage potential to unselected first and second conductive traces; and
sensing one or more total currents flowing through the one or more selected second conductive traces during the second cycle.

2. The method as set forth in claim 1, wherein the array comprises a two-terminal cross-point array.

3. The method as set forth in claim 1, wherein the non-select voltage potential is approximately half-way between the first select voltage and the second select voltage.

4. The method as set forth in claim 1, wherein sensing a selected one or both of the one or more total currents or the one or more leakage currents is accomplished by sensing a voltage.

5. The method as set forth in claim 1, wherein applying the first select voltage comprises applying a first voltage pulse to the one or more selected second conductive traces and wherein applying the second select voltage comprises applying a second voltage pulse to the selected first conductive trace.

6. The method as set forth in claim 1 and further comprising:
storing one or more first values indicative of each of the one or more leakage currents in a first circuit during the first cycle; and
storing one or more second values indicative of each of the one or more total currents in a second circuit during the second cycle.

7. The method as set forth in claim 6 and further comprising:
combining the one or more first values, the one or more second values, and at least one reference signal to generate one or more data signals indicative of stored data.

8. The method as set forth in claim 7, wherein the combining occurs in a voltage domain.

9. The method as set forth in claim 7, wherein the address is a read address and receiving the address occurs during a read operation to the array, the first and second select voltages comprise a read voltage applied across the one or more selected second conductive traces and the selected first conductive trace during the second cycle, the read voltage generates one or more read currents that are a component of the one or more total currents, and wherein a magnitude of each of the one or more read currents is indicative of the stored data.

10. The method as set forth in claim 9, wherein the combining further comprises:
adding the at least one reference signal to each of the one or more first values to obtain one or more sum signals; and
comparing the one or more sum signals with each of the one or more second values to generate the one or more data signals.

11. The method as set forth in claim 9, wherein the combining further comprises:
subtracting each of the one or more first values from each of the one or more second values to generate one or more difference signals; and
comparing the one or more difference signals with the at least one reference signal to generate the one or more data signals.

12. The method as set forth in claim 7, wherein the address is a write address and receiving the address occurs during a read-before-write operation to the array.

13. The method as set forth in claim 7 and further comprising:
combining at least one reference signal, the one or more first values, the one or more second values, and write data to generate one or more result signals, wherein the address is a write address and receiving the address occurs during a write operation, the first and second select voltages initially comprise a read voltage applied across the selected first conductive trace and the one or more selected second conductive traces during the second cycle, and based on each of the one or more result signals, either aborting or consummating the write operation for each of the one or more selected second conductive traces.

14. The method as set forth in claim 13, wherein the one or more result signals are indicative of write data that is not approximately equal to the stored data at the address and the consummating further comprises changing the read voltage to a write voltage applied across the selected first conductive trace and only those selected second conductive traces for which the result signal is indicative of write data that is not approximately equal to the stored data, the write voltage operative to overwrite the stored data with the write data.

15. The method as set forth in claim 13, wherein the one or more result signals are indicative of stored data that is approximately equal to the write data to be written to the address, the aborting further comprises terminating the write operation by reducing a magnitude of the first and second select voltages.

16. The method as set forth in claim 13, wherein the combining comprises adding the one or more reference signals to the one or more first values to obtain one or more sum signals, comparing the one or more sum signals with the one or more second values to generate one or more data signals, and comparing the write data to the one or more data signals to generate the one or more result signals.

17. The method as set forth in claim 13, wherein the combining comprises subtracting the one or more first values from the one or more second values to obtain one or more difference signals, comparing the one or more difference signals with the one or more reference signals to generate one or more data signals, and comparing the write data with the one or more data signals to generate the one or more result signals.

18. The method as set forth in claim 7 and further comprising:
providing one or more reference memory elements, each reference memory element electrically in series with a first terminal and a second terminal;
applying a reference voltage across the first and second terminals of the one or more reference memory elements so that one or more reference currents flow through the one or more reference memory elements; and
sensing the one or more reference currents to generate the one or more reference signals, wherein the one or more reference signals are indicative of stored reference data in the one or more reference memory elements.

19. The method as set forth in claim 18 and further comprising: programming the one or more reference memory elements so that the stored reference data is indicative of a reference resistive state that is intermediate to a plurality of conductivity profiles.

20. The method as set forth in claim 19, wherein the programming further comprises applying a programming voltage across the first terminal and the second terminal of the one or more reference memory elements.

21. The method as set forth in claim 20, wherein a magnitude and a polarity of the programming voltage determines the reference resistive state.

22. A method for sensing current in a two-terminal memory, comprising:
providing a plurality of bit block arrays, each bit block array including a plurality of first conductive traces and a plurality of second conductive traces;
receiving an address associated with a selected first conductive trace from the plurality of first conductive traces and one or more selected second conductive traces from the plurality of second conductive traces;
applying a first select voltage to one or more selected second conductive traces during a first cycle and during a second cycle;
applying a non-select voltage to the plurality of first conductive traces and unselected second conductive traces during the first cycle;
sensing one or more leakage currents flowing through the one or more selected second conductive traces during the first cycle;
applying a second select voltage to the selected first conductive trace during the second cycle while applying the non-select voltage to unselected first and second conductive traces; and
sensing one or more total currents flowing through the one or more selected second conductive traces during the second cycle.

23. The method as set forth in claim 22, wherein each bit block array comprises a two-terminal cross-point array.

24. A method for sensing current in a two-terminal memory, comprising:
providing an array including a plurality of first conductive traces and a plurality of second conductive traces;
receiving an address associated with a selected first conductive trace from the plurality of first conductive traces and one or more selected second conductive traces from the plurality of second conductive traces;
alternating a polarity of a first select voltage from a current polarity to a polarity that is opposite the current polarity;
applying the first select voltage to one or more selected second conductive traces during a first cycle and during a second cycle;
applying a non-select voltage potential to the plurality of first conductive traces and unselected second conductive traces during the first cycle;
sensing one or more leakage currents flowing through the one or more selected second conductive traces during the first cycle;
alternating a polarity of a second select voltage from a current polarity to a polarity that is opposite the current polarity;
applying the second select voltage to the selected first conductive trace during the second cycle while applying the non-select voltage potential to unselected first and second conductive traces; and
sensing one or more total currents flowing through the one or more selected second conductive traces during the second cycle.

25. The method as set forth in claim 24, wherein the first select voltage comprises a first read voltage potential and the second select voltage comprises a second read voltage potential.