# Patent

## Title
Partial response receiver with clock data recovery

## Abstract

In a receive circuit within an integrated circuit device, a binary input signal is sampled in response to transitions of a sampling clock signal to generate a set of data samples. The binary input signal is additionally compared with first and second threshold levels to generate respective first and second edge samples. The phase of the sampling clock signal is adjusted based, at least in part, on the first edge sample if the set of data samples matches a first data pattern and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part of U.S. patent application Ser. No. 10/662,872, filed Sep. 16, 2003, which claims priority from U.S. Provisional Application No. 60/461,729, filed Apr. 9, 2003. U.S. patent application Ser. No. 10/662,872 and U.S. Provisional Application No. 60/461,729 are hereby incorporated by reference.


FIELD OF THE INVENTION
The present invention relates generally to the field of communications, and more particularly to high speed electronic signaling within and between integrated circuit devices.
BACKGROUND
Electrical pulses transmitted on a band-limited signaling path disperse in time as they travel from source to destination. In systems in which data is transmitted as a sequence of level-encoded electrical pulses, such time-domain dispersion results in a blending of neighboring pulses; an effect known as dispersion-type inter-symbol interference (ISI). Dispersion-type ISI becomes more pronounced at faster signaling rates, ultimately degrading the signal quality to the point at which distinctions between originally transmitted signal levels may be lost.
FIG. 1 illustrates a prior-art signaling system having an equalizing transmitter 109 and an equalizing receiver 103 to mitigate dispersion-type ISI resulting from signal transmission on a signaling path 102. The receiver 103 includes a sampling circuit 105 to generate digitized samples 106 of the incoming signal, a shift register 107 to store some number (N) of the most recently received samples, and an equalizer 112 to generate an equalization signal 114 based on samples stored in the shift register 107. Ideally, the equalization signal 114 represents the residual signal level on path 102 of the N prior received samples in the incoming signal so that, by subtracting the equalization signal 114 from the incoming signal in difference circuit 115, the dispersion-type ISI resulting from the prior transmissions is canceled. Because the prior decisions of the sampling circuit 105 are fed back to the sampling circuit input in the form of the equalization signal 114, the receiver 103 is commonly referred to as a decision feedback equalizer (DFE).
One major limitation of the DFE 103 is that the time delay in the overall feedback path from sampling circuit 105 to difference circuit 115 makes it difficult to generate the equalization feedback signal 114 in time to equalize the signal level of the immediately following data value if the least latent sample (i.e., the most recently captured sample 106) is included in the equalization feedback signal 114. Including the least latent sample in the equalization signal is particularly challenging in modern high-speed signaling systems in which incoming symbols are present on the signal path 102 for extremely brief intervals (e.g., less than a nanosecond for signal rates above one Gigabit per second). One solution to the least-latent sample problem is to omit one or more of the least-latent samples from contributing to generation of the decision-feedback equalization signal. Unfortunately, the least latent sample, being nearest in time to the incoming symbol, tends to be the largest contributor to dispersion-type ISI and therefore a primary objective of cancellation by the DFE. Consequently, in signaling systems in which the least-latent sample is omitted from contribution to decision-feedback equalization, transmit-side pre-emphasis is often used to decrease the dispersion-type ISI caused by the least-latent symbol. That is, when a given symbol is transmitted by the equalizing transmitter 109, one or more previously transmitted symbols stored in shift register 113 (i.e., the least latent symbols relative to the outgoing symbol driven by primary output driver 101) are supplied to equalizing output drivers 111 which operate to pre-shape the outgoing waveform to reduce the dispersion-type ISI observed at the receiver. Unfortunately, as can be seen in the raw and equalized pulse responses depicted in FIG. 2, forcing the least-latent sample, DN−1, to zero (or near zero) results in significant attenuation of the overall signal level, thereby reducing signaling margins and ultimately limiting the data rate of the signaling system.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
FIG. 1 illustrates a prior-art signaling system;
FIG. 2 illustrates raw and equalized pulse responses observed in the prior art signaling system of FIG. 1;
FIG. 3 illustrates a signaling system that includes a partial response receiver according to an embodiment of the invention;
FIG. 4 illustrates a relationship between clock and data signals in one embodiment of the signaling system of FIG. 3;
FIG. 5 illustrates the bimodal distribution of a binary signal observed at a signal receiver when the primary source of dispersion-type ISI is the signal transmitted in the immediately preceding symbol time;
FIG. 6 illustrates the four partial response signal levels depicted in FIG. 5 relative to a common mode level, LCM;
FIG. 7 illustrates a partial response receive circuit according to an embodiment of the invention;
FIG. 8 illustrates a double data rate signaling protocol in which two symbols are transmitted in succession during each cycle of a sampling clock signal;
FIG. 9 illustrates a partial response receive circuit for use in a double data rate signaling system;
FIG. 10 illustrates even and odd pipelines of sample values generated within the partial response receive circuit of FIG. 9;
FIG. 11 illustrates the use of embedded scoping to generate a time-based trace of an incoming data signal;
FIG. 12 illustrates a signaling system according to an embodiment of the invention;
FIG. 13 illustrates a waveform trace of a pulse response captured by an embedded scope within the signaling system of FIG. 12;
FIG. 14 illustrates a partial response receiver according to an embodiment of the invention that adaptively generates partial response threshold levels;
FIG. 15 illustrates a embodiment of the adaptive module of FIG. 14;
FIG. 16 illustrates an alternative circuit arrangement that may be used in place of the averaging circuits of FIG. 15;
FIG. 17 illustrates a comparator that may be used within the receiver circuits and level sampling circuits of FIGS. 7, 9 and 14;
FIG. 18 illustrates an embodiment of the current DAC of FIG. 17;
FIG. 19 illustrates an alternative comparator embodiment that may be used within the receiver circuits and level sampling circuits of FIGS. 7, 9 and 14;
FIG. 20 illustrates a partial response receiver according to another alternative embodiment of the invention;
FIG. 21 illustrates the operation of the adaptive module of FIG. 20 according an embodiment of the invention;
FIG. 22 illustrates an embodiment of a dual mode receiver that may be operated in either a multi-level signaling mode or a partial response mode;
FIG. 23 illustrates a multi-level signaling protocol used within dual mode receiver of FIG. 22;
FIG. 24 illustrates a partial response receiver having a clock data recovery function according to an embodiment of the invention;
FIG. 25 illustrates a number of possible data signal transitions when the incoming data signal has the bimodal distribution shown in FIG. 4;
FIG. 26 illustrates an embodiment of a clock recovery circuit that adjusts the phase of edge clock signal and sampling clock signal based on selected transitions detected in the incoming data signal;
FIG. 27 illustrates a potential source of non-convergence in a system that adaptively generates partial response threshold levels;
FIG. 28 illustrates an embodiment of a dual-mode, partial response receiver with clock data recovery;
FIG. 29 illustrates signal transitions between successive 4-PAM (Pulse Amplitude Modulation) symbols;
FIG. 30 illustrates data signal transitions that may be used for clock recovery when the dual mode receiver of FIG. 28 is operated in a partial response mode;
FIG. 31 illustrates a transition detect circuit and sample select circuit that may be used within the clock recovery circuit of FIG. 28;
FIG. 32 illustrates additional data signal transitions that may be used for clock recovery when the dual mode receiver of FIG. 28 is operated in a partial response mode;
FIG. 33 illustrates a threshold select circuit according to an embodiment of the invention;
FIG. 34 illustrates an embodiment of a dual-mode partial response receiver that operates in generally the same manner as the partial response receiver of FIG. 28, but with reduced clock recovery circuitry;
FIG. 35 illustrates a more detailed embodiment of the clock data recovery circuit shown in FIG. 34;
FIG. 36 illustrates embodiments of the transition detect circuit and sample select circuit of FIG. 35 in greater detail;
FIG. 37 illustrates an embodiment of a second-order clock data recovery circuit that includes dual compensation paths to correct both phase and frequency errors;
FIG. 38 illustrates the increased lock range achieved through addition of the frequency-error compensation circuitry within the second-order clock data recovery circuit of FIG. 37;
FIG. 39 illustrates a distribution of signal levels in a system in which the two most recently received symbols are the primary source of residual channel response;
FIG. 40 illustrates a partial response receiver according to an embodiment of the invention that operates in accordance with the partial response states shown in FIG. 39;
FIG. 41 illustrates a partial response receiver according to another embodiment of the invention;
FIG. 42 illustrates a constellation of possible signal levels in a 4-PAM signaling system;
FIG. 43 illustrates a 4-PAM partial response receiver according to an embodiment of the invention;
FIG. 44 illustrates an input circuit that includes multiple partial response receivers according to an embodiment of the invention;
FIG. 45 illustrates an input circuit according to an alternative embodiment of the invention;
FIG. 46 illustrates a partial-response signaling system according to an embodiment of the invention;
FIG. 47 illustrates a raw pulse response and a pulse response equalized by the signaling system of FIG. 46 to enable partial-response data reception; and
FIG. 48 illustrates residual inter-symbol interference that may be equalized by transmit preemphasis within the signaling system of FIG. 46.



DETAILED DESCRIPTION
In the following description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘ <signal name>’) is also used to indicate an active low signal. The term “exemplary” is used herein to mean an example, not a preference or requirement.
A novel signal receiving circuit for use in electrical signaling systems is disclosed in various embodiments. In one embodiment, the signal receiving circuit includes a pair of comparators for comparing an incoming electrical signal against respective threshold levels, with each threshold level being set according to the level of a dispersed component of a previously received signal. More specifically, one of the threshold levels corresponds to the dispersion-type ISI introduced by a previously transmitted signal representative of a first digital state, and the other of the threshold levels corresponds to the dispersion-type ISI introduced when the previously transmitted signal is representative of a second digital state. In the case of a binary signaling system, the previously transmitted signal is resolved into one of two states by the receiving circuit, then used to select which of the comparators is to source the sample to be used for selection of the subsequent pair of samples. By this arrangement, each of the comparators compares the incoming signal against a threshold that is offset from a nominal value according to a respective, anticipated level of ISI, with the comparator having its threshold level offset in the direction that corresponds to the state of the previously received signal ultimately being selected as the sample source. Because samples are captured on the assumption of dispersion-type ISI resulting from both possible states of the previously captured sample (i.e., the least-latent sample), both samples are available for later selection when the state of the previously captured sample is resolved. Thus, by establishing separate threshold levels according to the different possible levels of dispersion-type ISI and comparing the incoming signal against each threshold level, the timing problems associated with generating an equalization signal that includes the least latent sample are avoided. Because the threshold level supplied to each of the comparators includes an offset according to the residual, partial response of the signaling path to the previously transmitted signal, a receive circuit having such offset-threshold comparators is referred to herein as a partial response receiver.
In another embodiment of the invention, a multi-level signal receiver (i.e., receiver capable of receiving a symbol representative of more than a single binary bit), may be switched to a binary signaling, partial response mode. In one implementation, a multi-PAM receiver (Pulse Amplitude Modulation receiver—a type of multi-level signal receiver) includes multiple comparators for distinguishing different possible levels (e.g., 4 levels in a 4-PAM receiver, 8 levels in an 8-PAM receiver, etc.) such that no additional comparators are necessary to support partial response operation. Instead, when the partial response mode is enabled, the threshold levels supplied to the comparators are adjusted to match the partial response levels for the least-latent symbol (or set of N least-latent symbols) and the post processing of the comparator outputs is switched from a symbol decoding operation to a sample selection operation.
In other embodiments of the invention, methods and circuits for generating partial response threshold levels are disclosed. Also, methods and circuits for transmitting a partial-response data signal that includes a partial response from selected prior-transmitted bits are disclosed. Further, methods and circuits for recovering a clock signal from a partial response data signal are also disclosed.
Signaling System Overview
FIG. 3 illustrates a signaling system 117 in which embodiments of the present invention may be used. The system 117 includes an equalizing transmitter 118 and equalizing receiver 116 coupled to one another via a high-speed signal path 122, and a controller 141 coupled to the transmitter 118 and the receiver 116 via relatively low-speed signal paths 142A 142B, respectively. In one embodiment, the signal path 122 is formed by component signal paths 122A, 122B and 122C (e.g., transmission lines that introduce respective, nonzero propagation delays and exhibit respective impedance characteristics), each disposed on respective circuit boards that are coupled to one another via circuit board interfaces 125 and 127 (e.g., connectors). In a specific implementation, signal path 122B is formed on a backplane and signal paths 122A and 122C are formed on respective daughterboards (e.g., line cards) that are removably coupled to the backplane via circuit board interfaces 125 and 127. The transmitter 118 and receiver 116 are implemented in respective integrated circuit (IC) devices that are mounted on the daughterboards. The controller, which may be a general or special purpose processor, state machine or other logic circuit, is implemented within a third integrated circuit device mounted to a yet another circuit board. In the embodiment of FIG. 3, signal paths 142A and 142B are used to convey configuration information from the controller 141 to the transmitter 118 and receiver 116, respectively, and may be disposed on the same circuit board (or circuit boards) as signal path 122 or implemented by an alternative structure such as a cable. The controller may alternatively be coupled to the transmitter 118 and receiver 116 by a shared signal path such as a multi-drop bus. The operation of the controller 141 is discussed in greater detail below. In alternative embodiments, the IC devices containing the transmitter 118, receiver 116 and controller 141 may be mounted to a common structure with the signaling paths 122, 142A and 142B coupled directly to the IC devices (e.g., all three ICs mounted to a circuit board and coupled to one another via circuit board traces, or all three ICs packaged within a single multi-chip module with signal paths 122 and 142 formed between the ICs by bond wires or other conducting structures). Also, the transmitter 118, receiver 116 and controller 141, or any subset thereof, may be included within the same IC device (e.g., system on chip) and the signaling paths 122 and/or 142 implemented by a metal layer or other conducting structure within the IC device.
The equalizing transmitter 118 transmits data on the signaling path 122 during successive time intervals, referred to herein as symbol times. In one embodiment, illustrated by the timing diagram of FIG. 4, each symbol time, TS, corresponds to a half cycle of a transmit clock signal, TCLK, such that two data values (e.g., values A and B) are transmitted on signaling path 122 per transmit clock cycle. The transmitted data signal arrives at the input of the equalizing receiver 116 after propagation time, TP, and is sampled by the receiver 116 in response to edges of a receive clock signal, RCLK. The receive clock signal may be received within the receive circuit via an external clock line, or may be a recovered version of a reference clock signal (e.g., recovered by a delay-locked loop or phase locked loop circuit). In other embodiments, discussed below, the receive clock signal may be recovered from the transmitted data signal. Still referring to FIG. 4, the receive clock signal has a quadrature phase relation to data valid windows (i.e., data eyes) in the incoming data signal such that each sample is captured at the midpoint of a data eye. In alternative embodiments, the sampling instant may be skewed relative to data eye midpoints as necessary to satisfy signal setup and hold time requirements in the receiver 116. Also, more or fewer symbols may be transmitted per cycle of the transmit clock signal.
The equalizing transmitter 118 includes a transmit shift register 124, output driver 121 and transmit equalizer 129; the transmit equalizer 129 itself including a shift register 120 and a bank of output drivers 131. At the start of each symbol time, the data value at the head (i.e., output) of the transmit shift register 124, referred to herein as the primary data value, is driven onto the signal path 122 by the output driver 121, and the transmit equalizer 129 simultaneously drives an equalizing signal onto the signal path 122. This type of equalization is referred to herein as transmit preemphasis. In one embodiment, the signal driven onto the signal path 122 by the output driver 121 (referred to herein as the primary signal) is a multi-level signal having one of four possible states (e.g., defined by four distinct signal ranges) and therefore constitutes a symbol representative of two binary bits of information. In alternative embodiments, the primary signal may have more or fewer possible states and therefore represent more or fewer than two binary bits. Also, the primary signal may be single-ended or differential (an additional signal line is provided to carry the complement signal in the differential case), and may be a voltage or current mode signal.
Each of the output drivers 131 within the transmit equalizer 129 form either a pre-tap driver or post-tap driver according to whether the source data value has already been transmitted (post-tap data) or is yet to be transmitted (pre-tap data). In the specific embodiment of FIG. 3, the equalizer includes N post-tap drivers sourced by data values within the shift register 120 and one pre-tap driver sourced by a data value within the transmit shift register 124. Accordingly, the resultant equalizing signal driven onto the data path 122 will have a signal level according to data values having symbol latencies of −1, 1, 2, . . . , N, where the symbol latency of a given data value refers to the number of symbol times by which transmission of the data value precedes the transmission of the primary value. Different numbers of post-tap and pre-tap drivers may be provided in alternative embodiments, thereby allowing for equalization based on values having different symbol latencies.
Still referring to FIG. 3, the equalizing receiver 116 includes a partial-response receive circuit 123, buffer 132 (e.g., shift register), tap select circuit 128 and tap select logic 139. Data signals are sampled by the partial response receive circuit 123 to generate digitized samples that are stored in the buffer 132 for eventual use by application logic (not shown). Because the buffered data is stored for at least a predetermined time and represents historical data up to a predetermined number of symbol latencies, the buffered data forms a source of post-tap data values that may be selected by the tap select circuit 128 to source equalizer taps in a receive-side equalizer circuit. Because a subset of buffered data values may be selected according to the precise symbol latencies of reflections and other high-latency distortions, a relatively small number of buffered data values may be selected to form receive-side equalization taps having latencies that match the latencies of the distortions. By this arrangement, high latency distortions may be reduced by receive-side equalization without dramatically increasing the parasitic capacitance of the receiver (i.e., as would result from a large number of receive-side equalization taps). In one embodiment, the tap select logic 139 is a configuration circuit that outputs a tap select signal 134 according to a configuration value. The configuration value may be automatically generated by system 117 (e.g., at system startup) or may be empirically determined and stored within the configuration circuit or elsewhere within system 117.
In the embodiment of FIG. 3, buffer 132 is formed by a shift register having a dead range component 133 having M storage elements and a selectable-range component 135 having R storage elements, the tap select circuit 128 being coupled to the selectable-range component 135 to select the subset of tap data sources therefrom. In alternative embodiments, the dead range component of the buffer 132 may include fewer than M storage elements or even zero storage elements, depending on the time required to receive data and transfer data into the buffer 132. Also, the tap select circuit 128 may be coupled to one or more storage elements within the dead range component 133 to enable the size of the dead range to be programmed according to the configuration of the transmit circuit 118. Finally, as discussed below, the buffer 132 may include one or more parallel registers in addition to (or instead of) the shift register formed by components 133 and 135.
Still referring to FIG. 3, numerous alternative types of equalization circuits may be used within the receiver 116. For example, in one embodiment, the receiver 116 includes an output driver 140 (illustrated in dashed outline in FIG. 3 to indicate its optional nature) to drive an equalizing signal onto the signal path 122 (and therefore to the input of the partial response receive circuit 123) coincidentally with the symbol time of an incoming signal. In another embodiment, the partial response receive circuit 123 includes a preamplifier having an equalizing subcircuit.
Multi-Modal Signal Distribution—Partial Response
FIG. 5 illustrates the bimodal distribution of a binary signal observed at a signal receiver when the primary source of dispersion-type ISI is the signal transmitted in the immediately preceding symbol time. That is, the symbol sampled at time TN−1 is the primary source of dispersion-type ISI in the symbol sampled at time TN; the symbol sampled at time TN is the primary source of dispersion-type ISI in the symbol sampled at time TN+1; and so forth. Referring to the signal levels at time TN, it can be seen that if the if the preceding symbol was a logic ‘1’, the partial response to the preceding symbol will raise the signal level at time TN to one of the circled levels ‘11’ or ‘01’ (the second bit of the ‘11’ and ‘01’ bit sequences corresponding to the state of the signal at time TN−1). If the preceding symbol was a logic ‘0’, the partial response to the preceding symbol will lower the signal level at time TN to one of the square-designated levels ‘10’ or ‘00’. In a single-ended signaling system, the incoming signal is sampled and compared with a reference voltage level at the midpoint between the steady state extremes (i.e., midway between the ‘11 . . . 1’ and ‘00 . . . 0’ signal levels). Accordingly, the worst case voltage margins (i.e., smallest voltage differences between the signal and reference voltage) occur when the signal transitions from a ‘1’ to a ‘0’ or vice-versa; the ‘10’ and ‘0’ signaling levels becoming indistinguishable when the partial response level (i.e., residual signal level from the preceding symbol transmission) is large. In a differential signaling system, the incoming signal and its complement are sampled, for example, by a differential amplifier which amplifies the difference between the complementary signal levels. As in the single-ended case, the worst case voltage margins occur when the differential signal transitions from a ‘1’ to a ‘0’ or vice-versa; the ‘10’ and ‘01’ signaling levels becoming indistinguishable when the partial response pushes the ‘10’ and ‘01’ levels to the common mode (i.e., the average of a differential signal pair).
FIG. 6 illustrates the four partial response signal levels depicted in FIG. 5 relative to a common mode level, LCM. In the case of a differential signaling system, the partial response to the preceding symbol may be viewed as increasing or decreasing the differential amplitude (i.e., the amplitude difference between the signals that form the differential signal pair) relative to a nominal differential amplitude. Normalizing the positive and negative signal levels for the nominal differential amplitude to 1 and −1, respectively, the common mode level, LCM, becomes zero, and the four possible signal levels become 1+α, 1α, −1+α and −1−α, where a represents the magnitude of the partial response to the preceding symbol. Thus, when the preceding symbol, DN−1, is a ‘0’, the incoming symbol, DN, is represented by a signal level at either 1−α or −1−α, depending on whether DN is a ‘1’ or ‘0’. Similarly, when DN−1=1, the incoming symbol is represented by a signal level at either 1+α or −1+α according to the state of the current symbol. In the former case (i.e., when DN−1=0), the two complementary signal levels, −1−α and 1−α, have a common mode of −α, as shown in box 151. In the latter case (i.e., when DN−1=1), the two complementary signal levels, 1+α and −1+α, have a common mode of +α, as shown in box 153.
Partial Response Receiver
FIG. 7 illustrates a partial response receive circuit 200 according to an embodiment of the invention that exploits the bi-modal characteristic of the signal levels depicted in FIGS. 5 and 6. The partial response circuitry includes a compare circuit 202 to sample the input data signal, DN, and a decision circuit 204 to generate an output data value (i.e., received data value) based on data samples generated by the compare circuit 202. Rather than a single comparator that distinguishes between binary signaling levels based on whether the sampled signal is above or below a common mode threshold, the compare circuit 202 includes two comparators 201 and 203 having threshold levels that are offset from the common mode threshold by the two possible partial responses to the preceding symbol. That is, the threshold level of the comparator 201 is set the +α level, and the threshold level of the comparator 203 is set to the −α level. By this arrangement, if the preceding symbol was a ‘1’ (i.e., DN−1=1), the comparator 201 will resolve the incoming signal as being a ‘1’ or ‘0’ by determining whether the signal level is above or below the partial response level, +α. Conversely, if DN−1=0, the comparator 203 will resolve the incoming signal as being a ‘1’ or ‘0’ by determining whether the signal is above or below the partial response level, −α. Because both comparisons are performed for each incoming symbol, the selection of which comparator output represents the state of the symbol may be delayed until the state of the preceding symbol is resolved. In the partial response receive circuit 200, for example, the sample values output by the comparators 201 and 203 are output to the decision circuit 204 where they are optionally stored in storage elements 208 and 209 (e.g., D flip-flops or other types of storage circuits) and provided to respective input ports of a select circuit 205 (e.g., a multiplexer). The sample value selected by the select circuit 205 is stored in a storage circuit 207 in response to a sampling clock signal 210 (or other timing control signal) at which point the sample value becomes the DN−1 sample value. The DN−1 sample value stored within storage circuit 207 is fed back to the select input of the select circuit 205 to select one of the two sample values generated by the comparators 201 and 203. That is, the DN−1 sample value is used to select, via select circuit 205, which of the comparators 201 and 203 will source the DN sample. In an embodiment that includes the storage elements 208 and 209, the output of storage circuit 207 becomes the DN−2 sample value and is used to select one of the DN−1 sample values output from the storage elements 208 and 209.
Reflecting on the operation of the partial response receive circuit 200 of FIG. 7 in reference to the signal distribution shown in FIG. 6, it can be seen that the signaling margin (i.e., difference between signal levels representative of ‘1’ and ‘0’ states) within either of the comparators 201, 203 exceeds the signaling margin between the worst-case partial response states. That is, the signaling margin between the worst-case partial response states (10-to-01) is (1−α)−(−1+α)=2−2α, while the signaling margin in either pair of the separated signal constellation is (1−α)=(−1−α)=2. Thus, as alpha grows, the signaling margin in a single-comparator receiver decreases, going to zero as a approaches 1. By contrast, the signaling margin in the partial response receive circuit 200 of FIG. 7 remains substantially constant at 2, even as a grows. In effect, by offsetting the threshold of the comparators 201 and 203 by the partial response levels +α and −α, respectively, the partial response to the preceding symbol is canceled, making the full response of the incoming symbol available to resolve the symbol state.
Still referring to FIG. 7, a threshold generator 211 is used to generate the +a thresholds supplied to the comparators 201 and 203. In the case of a single-ended signaling system, the threshold values ±α may be voltage levels applied to reference inputs of the comparators 201 and 203, respectively, to enable pseudo-differential signal detection (i.e., comparison of the incoming signal level with the threshold voltage level to resolve the digital state of the sample value). In the case of a differential signaling system, the threshold values ±α may be voltages or currents applied to offset the common modes of the comparators to the ±α voltage levels depicted in FIG. 6. The threshold values ±α may also be digital values for controlling digital-to-analog converters (DACs) within the comparators 201 and 203. In one embodiment, the threshold generator 211 includes circuitry for a one-time or periodic determination of the ±α threshold levels, for example in one or more calibration operations. In other embodiments, the ±α threshold levels are adaptively generated based on incoming signal levels produced by selected data patterns. Embodiments of the threshold generator 211 are discussed in further detail below.
Multi-Data-Rate Signaling
In the partial response receive circuit 200 of FIG. 7, a single symbol is captured during each cycle of the sampling clock signal 210. That is, a rising (or falling) edge of the sample clock is used to capture samples of the incoming data signal. In a multi-data rate system, multiple symbols are captured per cycle of the sampling clock signal 210. In such systems, clock generation circuitry is provided to generate multiple instances of the sampling clock signal 210 that are phase-distributed through a period (1/frequency) of the sampling clock signal. FIG. 8, for example, depicts a double data rate signaling protocol in which two symbols are transmitted in succession during each period (i.e., cycle time) of a sampling clock signal. Accordingly, two instances of the sampling clock signal are provided: an even-phase sampling clock signal, SCLKE, to sample even-numbered symbols DN, DN+2, DN+4 . . . ; and an odd-phase sampling clock signal, SCLKO, to sample odd-numbered symbols DN−1, DN+1, DN+3. . . . This technique may be extended to achieve virtually any data rate, including quad data rate (4 symbols per sampling clock cycle), octal data rate (8 symbols per sampling clock cycle), decade data rate (10 symbols per sampling clock cycle), and so forth.
FIG. 9 illustrates a partial response receive circuit 215 for use in a double data rate signaling system. The partial response receive circuit 215 includes an odd-phase receive circuit 216 clocked by an odd-phase sampling clock signal 210O (SCLKO), and an even-phase receive circuit 217 clocked by an even-phase sampling clock signal 210E (SCLKE). The odd- and even-phase receive circuits 216, 217 are similar to the partial response receive circuit 200 of FIG. 7, except that, due to the interleaved nature of the samples they generate, the select circuit 225 of the odd-phase receive circuit 216 is controlled by a latched instance of a sample selected by the select circuit 239 in the even-phase receive circuit 217 and, conversely, the select circuit 239 of the even-phase receive circuit 217 is controlled by a latched instance of a sample selected by the select circuit 225 in the odd-phase receive circuit 216. Samples DN+/DN− are generated by comparators 232 and 233, stored in storage circuits 235 and 237, and then selected by select circuit 239 to form the even-phase pipeline (EVEN PIPE) illustrated in FIG. 10 (the output of the select circuit 239 optionally being buffered in storage circuit 243 in response to the even-phase sampling clock signal 210E). Similarly, samples DN+1+/DN+1− are generated by comparators 218 and 219, stored in storage circuits 221 and 223, then selected by the select circuit 225 form the odd-phase pipeline (ODD PIPE) illustrated in FIG. 10 (the output of the select circuit 225 optionally being buffered in storage circuit 227 in response to the odd-phase sampling clock signal 210O). Thus, when an odd phase sample DN−1 is selected by select circuit 225, the DN−1 sample is latched within latch element 241 of the even-phase receive circuit (thereby making DN−1 available for a full cycle of the even-phase clock signal 210E) and thereafter used to select the subsequent even-phase sample DN. The selected even phase sample DN is then latched within latch element 228 of the odd-phase receiver and thereafter used to select the subsequent odd-phase sample, DN+1. For higher data rates, the number of partial-cycle receive circuits (circuits 216 and 217 each being a half-cycle receive circuit) may be increased according to the data rate. For example, in a quad data rate system, a partial-response receiver includes four quarter-cycle receive circuits interconnected such that sample N within a first quarter-phase receive circuit is used to select sample N+1 within a second quarter-phase receive circuit; sample N+1 within the second quarter-phase receive circuit is used to select sample N+2 in a third quarter-phase receive circuit; sample N+2 is used to select sample N+3 in a fourth quarter-phase receive circuit; sample N+3 is used to select sample N+4 in the first quarter phase receiver; and so forth. In the remainder of this description, various partial response receive circuit embodiments are described in the context of a single data rate (SDR) signaling system. Each of the embodiments disclosed may be modified as described in reference to FIGS. 8-10 to support multi-data rate signaling.
Threshold Level Generation
In one embodiment of the invention, a technique referred to herein as embedded scoping is used to determine the ±α threshold levels applied within the comparators of the partial response receive circuit. Embedded scoping involves iteratively receiving a sequence of symbols in a receiver and comparing the received symbol sequence with a local generation of the sequence to confirm error-free reception. With each receive-and-confirm iteration, a threshold voltage used to distinguish between symbol values in the incoming signal is offset from a calibrated level by a progressively larger amount until a symbol in the sequence no longer matches the expected value. The threshold voltage offset at which the failure occurs is referred to herein as a pass/fail offset and represents a measure of the signal level at the sampling instant at which the failure occurred. Thus, by sweeping the threshold voltage through a range of threshold voltages until the pass/fail offsets for each symbol in the symbol sequence have been detected, a sample plot for the incoming signal may be developed. Further, by sweeping the receive clock signal through an incremental sequence of phase offsets, and determining the pass/fail offset at each phase offset, a complete trace of the incoming signal may be generated. Also, the granularity and start stop points of the phase offsets and/or threshold voltage steps may be controlled (e.g., by configuring a programmable circuit or register) to enable the waveform trace to be constrained to selected points of interest in the incoming signal (e.g., ±N° from an intended sampling instant, N representing a sweep angle).
FIG. 11 illustrates the use of embedded scoping to generate a time-based trace 290 of an incoming data signal 286. The range of threshold voltage offsets over which the incoming signal 286 is sampled is indicated by VT, and the range of phase offsets at which the signal is sampled is indicated by φ. Each sample point within the sweep is indicated by a respective dot within a grid of sample points 280. Note that the sweep may be obtained by stepping the voltage threshold through the range of VT values for each value of φ, or, alternatively, by stepping the clock phase through the range of φ values for each value of VT.
Still referring to FIG. 11, reference numeral 288 indicates a pair of samples for which a pass/fail condition is detected. A corresponding pass/fail offset (PFO) is determined according to the difference between the calibrated VT level (VT(CAL)) and the average of the VT offsets between the pass and fail samples, and recorded as a measure of the incoming signal. That is, the pass/fail offset may be used to establish a data point within the trace 290 as shown. After sweeping through all the sample points within the grid 280 (which sweep may be repeated numerous times to obtain an average and to discard statistical outliers), a measure of the incoming signal is obtained as illustrated graphically by the trace 290.
Embedded scoping has a number of benefits over traditional signal measurement techniques. First, because the technique is non-invasive (i.e., no probe contact), the electrical characteristics of the system under test are unaltered, thereby yielding potentially more accurate results. Also, the trace is generated from the perspective of the receive circuit itself, meaning that any non-ideal characteristics of the receive circuit are accounted for in the resulting signal trace information. Finally, because all components needed for embedded scoping may be included within a finished signaling system, embedded scoping may be used to perform numerous run-time analyses in addition to partial response measurement including, without limitation, determining the latency and amplitude of reflections and other distortions within the signaling system.
FIG. 12 illustrates a signaling system 300 according to an embodiment of the invention. The signaling system 300 includes a transmit device 301 and receive device 309 that employ embedded scoping to determine partial response amplitudes. The transmit device 301 includes a pattern generator 303, data selector 305, equalizing transmitter 307 and application logic 302. The application logic 302 performs the core function of the transmitting device (e.g., signal processing, instruction processing, routing control, or any other function) and provides transmit data (TX DATA) to a first input of the data selector 305. During normal operation, the application logic 302 outputs a logic low scope signal 306 (SCOPE) to the data selector 305 to select the transmit data to be passed to the equalizing transmitter 307 for transmission to the receive device 309 via signal path 122 (which may include or be connected to numerous sources of discontinuity such as connectors, vias, stubs, etc.). During a scoping mode of operation, the application logic 302 drives the scope signal 306 high to enable a scoping mode of operation within the transmit device 301. In the scoping mode, the data selector 305 selects a repeating single-symbol pulse sequence (e.g., a test signal such as: 00100 . . . 00100 . . . 00100 . . . ) generated by the pattern generator 303 to be transmitted to the receive device 309. The receive device 309 includes a partial response receiver 310 to receive the incoming data signal, a pattern register 311 to store a local version of the single-symbol pulse sequence, a multiplexer 312 to enable the pattern register 311 to be switched between load and barrel-shifting modes, a XOR gate 313 to compare the received data sequence with the locally generated sequence, and application logic 315 (or other logic) to generate a threshold voltage adjust signal (THRESH ADJ) to step the threshold voltage used within the partial response receive circuit through their scoping ranges. In on embodiment, the thresholds applied to the multiple comparators of the partial response receive circuit are set to the same nominal starting value and stepped together for purposes of embedded scoping. In an alternative embodiment, only one comparator of the partial response receive circuit is used when scoping mode is enabled. The application logic may additionally generate a clock adjust signal (not shown) to step the sampling clock through a sequence of phase offsets within a cycle of the sampling clock signal. The application logic 315 additionally builds a trace record (i.e., data indicative of the incoming data sequence) based on the output of XOR gate 313.
When the receive device 309 is in a scoping mode of operation, the multiplexer 312 is initially set to load the pattern register 311 with the output of the partial response receiver 310. After a desired sequence of data (e.g., the single-symbol pulse sequence) is shifted into the pattern register 311, the multiplexer 312 is set to enable the barrel-shifting mode of the pattern register 311. That is, the multiplexer 312 selects the output of the pattern register 311 to be fed back to the input of the pattern register 311 so that the contents of the pattern register 311 are continuously rotated through the pattern register 311 (i.e., a barrel shifting operation). By this arrangement, the data sequence loaded into the pattern register 311 is repeatedly output, bit by bit, to a first input of the XOR gate 313. The data sequence received by the partial response receiver 310 is input to a second input of the XOR gate 313 so that the received data sequence is compared, bit by bit, with the data sequence stored within the pattern register 311. By selecting the length of the repeatedly transmitted data sequence to match the storage size of the pattern register 311, the pattern register contents are repeatedly compared with a newly received version of the same data sequence (i.e., putatively the same data sequence). Any reception error will result in a mismatch between the received value and the corresponding value within the pattern register and therefore, when compared by XOR gate 313, will result in an error signal being output from the XOR gate 313 to the application logic 315. The application logic 315 may then record the adjusted threshold voltage (and optionally the clock phase offset) at which the error occurred as a signal level within the waveform trace.
FIG. 13 illustrates a sample waveform trace 320 of a pulse response captured by an embedded scope within the signaling system of FIG. 12. As shown, the waveform starts and ends at a steady-state low level which corresponds to the −1−α level discussed in reference to FIGS. 5 and 6. A pulse (i.e., D=1) is received at time T3, and the partial response of the pulse is received at time T4. Due to the preceding zero-valued symbol, the signal level sampled at time T3 corresponds to the 1−α level. Similarly, due to the preceding one-valued symbol, the signal level sampled at time T4 corresponds to the −1+α level. The difference between the −1+α level and the −1−αlevel may be determined by the application logic 315 of FIG. 12 (or other circuitry) and used to determine ±α. That is, α=((−1+α)−(−1−α))/2. The normalized signal level, 1, may be used in certain clock recovery operations (discussed below) and may be determined from the pulse level and the steady-state low level (i.e., 1=((1−α)−(−1−α))/2). Once determined, the a level may be applied to the comparators of the partial response receive circuit to enable partial response operation.
FIG. 14 illustrates a partial response receiver 325 that includes circuitry for adaptively generating the partial response threshold levels ±α. The partial response receiver 325 includes a partial response receive circuit 200, a level sampler 327, and an adaptive module 329. The partial response receive circuit 200 operates generally as described above in reference to FIG. 7 to generate a pair of sample values based on comparisons (in comparators 201 and 203) of the incoming signal DN with offset thresholds ±α. The samples are stored in storage elements 208 and 209 as samples DN−1+ and DN−1− (the ‘+’ and ‘−’ designating the samples as corresponding to relatively positive and negative partial responses). A select circuit 205 selects one of the DN−1+ and DN−1 samples to be the selected DN−1 sample based on the state of the DN−2 sample stored in storage circuit 207. As discussed above, in a multi-data rate system, the DN−2 sample may be supplied by a counterpart partial response receive circuit clocked by a phase shifted version of the sampling clock signal 210. In either case, single- or multi-data rate, two or more time-adjacent sample values are supplied to (or buffered within) the adaptive module 329. In the embodiment of FIG. 14, sample values DN−2 and DN−1 are supplied to the adaptive module 329, though higher or lower latency samples may be provided in alternative embodiments.
The level sampler 327 includes four comparators 3311-3314 for comparing the signal level of the incoming symbol, DN, with each of the four signal levels that correspond to the bimodal signal distribution of FIG. 5. That is, comparator 3314 compares the incoming signal with a threshold level at 1+α and generates a corresponding error sample E11 according to whether the incoming signal is above or below the 1+α level. Similarly, comparators 3313, 3312 and 3311 compare the DN signal level with threshold levels at 1−α, −1+α and −1−α, respectively, and generate corresponding error samples E10, E01 and E00. Each of the error samples is buffered in a respective storage circuit 3351-3354 before being provided to the adaptive module 329. By this arrangement, the error samples arrive at the adaptive module 329 with the same latency as the DN−1 sample generated by the partial response receive circuit 200.
The adaptive module 329 responds to the data samples from the partial response receive circuit 200 and the error samples from the level sampler 327 by selectively updating the threshold values supplied to the comparators 201 and 203 within the partial response receive circuit 200 and comparators 3311-3314 within the level sampler 327. For example, when the data samples indicate a 11 state (i.e., D[N−1:N−2]=11), the adaptive module 329 increases or decreases the 1+α threshold level according to whether the incoming signal level is indicated by error sample E11 to be above or below the 1+α threshold level. The adaptive module similarly updates the 1−α, −1+α, and −1−α thresholds based on error samples E10, E01 and E00 when the data samples indicate the 10, 01 and 00 states, respectively. As discussed below, the ±α levels may be derived from the 1+α, 1−α, −1+α and −1−α threshold levels, or a subset thereof.
FIG. 15 illustrates an embodiment of the adaptive module 329 of FIG. 14. The adaptive module includes a 2:4 decoder 353, up/down counters 3571-3574, averaging circuits 361 365, digital-to-analog converters (DACs) 3591-3596, and, optionally, a filter circuit 351. The 2:4 decoder 353 activates one of four enable signal lines 3541-3544 (i.e., asserts an enable signal on the signal line) according to the state of the input data samples DN−1 and DN−2 (also expressed herein as D[N−1:N−2]). Each of the counters 357 has an up/down input (U/D) coupled to receive a respective one of the four error samples (i.e., E00, E01, E10 and E11), a count enable input (CEN) coupled to a respective one of the enable signal lines 354, and a strobe input coupled to receive the sample clock signal 210. By this arrangement, during each cycle of the sample clock signal 210, the counter 357 coupled to the activated enable signal line 354 is incremented or decremented according to the state of the corresponding error sample. Thus, when D[N−2:N−1]=11, counter 3574 is incremented if error sample E11 indicates that the incoming signal level is above the 1+α threshold level, and decremented if E11 indicates that the incoming signal level is below the 1+α threshold level. The count values maintained within counters 3573, 3572 and 3571 are similarly incremented and decremented according to error samples E10, E01 and E00, respectively, when enabled by their respective enable signal lines 354. In one embodiment, the filter circuit 351 is used to filter the incoming error samples, for example, by requiring a predetermined number of same-state error samples to be received within a given time before the corresponding count value is adjusted. Other types of error sample filtering may be applied in alternative embodiments. Also, the filter 351 may be omitted altogether.
The count values maintained within the counters 3571-3574 are output as control values to respective DACs 3591-3594 to generate the 1+α, 1−α, −1+α and −1−α levels. Thus, the adaptive module 329 operates to selectively update the 1+α, 1−α, −1+α and −1−α threshold levels according to the state of the received data values D[N−1:N−2].
The averaging circuits 361 and 365 generate the ±α threshold levels by averaging the control values output from counters 3571-3574. Averaging circuit 365, for example, includes a summing circuit 366 to sum the C1+α and C1+α control values from counters 3574 and 3572, respectively, and a divide-by-2 element 367 (which may be achieved without active circuitry by dropping the least significant bit of the sum) to generate a control value Cα that corresponds to the desired a threshold level (i.e., (C1+α+C−+α)/2=Cα). Averaging circuit 361 similarly includes a summing circuit 362 to sum the count values C−α and C−1−α from counters 3573 and 3571, and a divide-by-2 element 363 to generate control value C−α. In one embodiment, each of the control values generated by the counters 357 and the averaging circuits 361, 365 are input to respective DACs 3591-3596 to generate the threshold levels used within the comparators of the partial response receive circuit 200 and level sampler 327 of FIG. 14. In an alternative embodiment, each of the comparators within the partial response receive circuit 200 and level sampler 327 include internal DACs and receive respective threshold values in the form of the control values themselves (i.e., Cα, C−α, C1+α, C1−α, C−1+α, C−1−α). Also, in a differential embodiment (and in certain single-ended embodiments), the C+α and C−1+α values may be complements of one another so that one of the averaging circuits 361 or 365 may be replaced by a multi-bit inverter. Further, the C1+α and C−1−α values may be complements, and the C1−α and C−1+α values may be complements such that two of the comparators within the level sampler 327 of FIG. 14 and two of the counters 357 within the adaptive module 329 (and two of the DACs 359, if used) may be omitted.
FIG. 16 illustrates an alternative circuit arrangement 375 that may be used in place of the averaging circuits 361 and 365 of FIG. 15. Instead of averaging the C+α and C−1+α count values to generate the C+α value, C+α is generated by halving the difference between the C1+α and the C−α control values (i.e., Cα=((C+α)−(C1−α))/2). Similarly, the C−α value is generated by halving the difference between the C−1−α and the C−1+α control values. Thus, the circuit of FIG. 16 includes a difference circuit 376 to generate 2α by subtracting the C1−α control value from the C1+α control value, and a divide-by-2 element 377 (which may be a implemented by dropping the least significant bit of the difference) to generate Cα by halving the 2α value. Difference circuit 379 and divide-by-2 element 380 are used in a similar manner to generate C−α from count values C−1+α and C−1−α in a corresponding manner.
Differential Comparator
FIG. 17 illustrates a comparator 400 that may be used within the receiver circuits and level sampling circuits of FIGS. 7, 9 and 14. The comparator 400 includes a preamplifier 401 and a sampling circuit 425. The preamplifier 401 includes a pair of differential amplifiers 402 and 403 each biased by a respective current DAC (IDAC) 411 and 413, and each having first and second output nodes 418 and 419 coupled to a supply voltage via a respective resistive element, R. The resistive elements may be implemented, for example, using diode-configured transistors, biased transistors, resistors, or any other active or passive circuitry for establishing a resistance. Transistors 405 and 404 within differential amplifier 402 have widths W1 and W2, respectively, with W1 being greater than W2. Transistors 408 and 407 within differential amplifier 403 also have respective widths W1 and W2. A differential input signal composed of signal components D and /D is coupled to each of the differential amplifiers 402, 403 such that D is coupled to transistors 404 and 408 and /D is coupled to transistors 405 and 407. By this arrangement, when Cα and /Cα are substantially equal (e.g., in an 8-bit control word, Cα=128 and /Cα=127), the differential amplifiers 402 and 403 are substantially balanced, operating in effect as a single differential amplifier having component transistors of width W1+W2. Thus, if D is greater than /D, transistors 404 and 408 will collectively sink more current than transistors 405 and 407, thereby causing the voltage on output node 418 to be pulled down (i.e., via the resistive element, R, coupled to the output node 418) more than the voltage on output node 419.
When the preamplifier 401 is balanced (i.e., Cα substantially equal to /Cα), the voltages on the preamplifier output nodes 418 and 419 are substantially equal when D and /D are at the common mode potential (i.e., as when D and /D cross one another in transition). Thus, the effective threshold of the preamplifier 401, and therefore the comparator 400 as a whole, occurs at the common mode of D and /D. By contrast, when the preamplifier is imbalanced by increasing Cα relative to /Cα, equal values of D and /D result in output node 419 being pulled lower than output node 418, due to the fact that transistor 405 is wider than transistor 404 (and therefore has a greater gain), and that the compensating (balancing) effect of differential amplifier 403 is diminished by the reduced control value /Cα. Thus, increasing Cα relative to /Cα increases the effective threshold of the preamplifier above the common mode. By increasing Cα to the point at which the threshold between ‘0’ and ‘1’ signal levels is set to α, a differential comparator having a threshold level at α is achieved. By reversing the connections of the Cα and /Cα values to the current DACs of a counterpart comparator (not shown), a differential comparator having a threshold level at −α is achieved.
The sampling circuit 425 includes a differential amplifier 426 formed by transistors 423 and 424, a sense amplifier 427 formed by back-to-back coupled inverters 428 and 429, and a storage circuit 436 formed by a set-reset flip-flop. The differential amplifier 426 includes control inputs coupled to the output nodes 418 and 419, respectively, of the preamplifier 401, and output nodes 431 and 433 coupled to source terminals of the inverters 428 and 429, respectively. A biasing transistor 430, switchably controlled by the sampling clock signal 210 (or other sample control signal), is coupled between the differential amplifier 426 and a ground reference (or other low voltage reference). The sampling clock signal 210 is additionally coupled to control inputs of positively-doped MOS (PMOS) transistors 434 and 435 which are coupled between a supply voltage (e.g., VDD) and output nodes of the inverters 428 and 429. By this arrangement, when the sample clock signal 210 is low, transistor 430 is switched off, and transistors 434 and 435 are switched on to pre-charge the output nodes of the inverters 428 and 429 to the supply voltage. The output nodes of the inverters 428 and 429 are coupled to active-low set and reset inputs, respectively, of the storage circuit 436, so that the content of the storage circuit 436 is maintained through the low half-cycle of the sample clock signal 210. When the sample clock signal 210 goes high, biasing transistor 430 is switched on and draws current through the two transistors 424 and 423 of the differential amplifier 426 in proportion to the voltages developed on the output nodes 418 and 419 of the preamplifier 401. Thus, if the voltage developed on node 419 is higher than the voltage on node 418, the current drawn by biasing transistor 430 will flow primarily through transistor 423. Conversely, if the voltage developed on node 418 is higher than the voltage on 419, the current drawn by biasing transistor will flow primarily through transistor 423. Transistors 434 and 435 are switched off in response to the high-going sample clock signal 210, so that the pre-charged outputs of the inverters 428 and 429 are discharged by currents flowing through transistors 423 and 424. By this operation, if the incoming signal (D) exceeds the common mode voltage, ((D+/D) divided by 2), by more than the +α threshold level (i.e., the incoming signal exceeds the +α threshold level), the current drawn by biasing transistor 430 will flow primarily through transistor 423. Consequently, the output node of inverter 429 will be discharged more rapidly than the output node of inverter 428, driving the output of inverter 429 low and driving the output of inverter 428 high (i.e., the PMOS transistor within inverter 428 is switched on and the NMOS transistor within inverter 428 is switched off). The low output of inverter 429 is applied to the active-low set input of the storage circuit 436, causing the storage circuit 436 to store a logic ‘1’ sampled data value. By contrast, if the incoming signal level does not exceed the +α threshold level, the current drawn by biasing transistor 430 will flow primarily through transistor 424, thereby driving inverter 428 low (and driving inverter 429 high) to store a logic ‘0’ sampled data value within storage circuit 436.
FIG. 18 illustrates an embodiment of the current DAC 411 of FIG. 17. The current DAC 411 includes control transistors 4370-437N−1 and biasing transistors 4390-439N−1 Each of the control transistors 4370-437N−1 is coupled in series (e.g., source to drain) with a corresponding one of the biasing transistors 4390-439N−1 to form a transistor pair that is coupled between a reference voltage (ground in this example) and an output node 438 (i.e., the node to be connected to the source terminals of the transistors which form the differential amplifier 402). Gate terminals of the control transistors 4370-437N−1 are coupled to receive respective component signals, Cα[0]−Cα[N−1], of a multi-bit control value, Cα (or, control value/Cα). Each of the control transistors 4370-437N−1 has a binary weighted gain such that a current of IREFx2i (where i represents the ith transistor in the positions 0, 1, 2, . . . , N−1) flows through control transistor 437i when the corresponding control signal component is high. Thus, if all the constituent bits of the control value Cα [N−1:0] are high, then IREF flows through control transistor 4370, IREFx2 flows through transistor 4371, IREFx4 flows through control transistor 4372, and so forth to control transistor 437N−1 which conducts IREFx2N−1. Accordingly, control transistors 4370-437N−1 are designated x1, x2. . . , x2N−1 transistors, respectively. By this arrangement, the control value Cα [N−1:0] may be set to any of 2N values to select bias currents that range from 0 to IREFx2N−1 in increments of IREF. The biasing transistors 4390-439N−1 have gate terminals coupled to receive a bias voltage, VBIAS, that is adjusted as necessary (e.g., by a biasing circuit) to establish or maintain a desired IREF.
In one embodiment, the relative gains (i.e., transconductance values) of the various transistors used to implement the current DAC 411 (and therefore drive strengths of the sub-drivers) are established by adjusting the width-length ratio (i.e., W/L) of individual control transistors 437 and/or biasing transistors 439. For example, the width-length ratio of the x2 control transistor 4371 is twice the width-length ratio of the x1 control transistor 4370, the width-length ratio of the x4 control transistor 4372 is twice the width-length ratio of the x2 control transistor 4371, and so forth. The biasing transistors 439 may have similar gain ratios relative to one another (e.g., x1, x2, x4, x2N−1 as shown in FIG. 18). Other techniques for adjusting the relative gains of the control transistors 437 and biasing transistors 439 may be used in alternative embodiments. Also, weightings other than binary weightings may be used. For example, in one embodiment, each of the control transistors 437 has an equal gain to each of the other control transistors 437 such that the current drawn by the current DAC 411 is proportional to the number of logic ‘1’ bits in the control value, Cα.
FIG. 19 illustrates an alternative embodiment of a differential comparator 450 that may be used to implement the comparators depicted in FIGS. 7, 9 and 14. The comparator 450 includes a sampling circuit 452 and an offset control circuit 440. The sampling circuit 452 is implemented in generally the same manner as the sampling circuit 425 of FIG. 17 (and includes differential amplifier 426, sense amplifier 427, biasing transistor 430, and storage circuit 436), except that the input signal lines carrying D and /D are coupled directly to the control terminals of transistors 423 and 424, respectively. The offset control circuit 440 includes a differential amplifier 446 having output nodes coupled to nodes 431 and 433 of the sampling circuit 452. Control terminals of the transistors 447 and 449 of the differential amplifier 446 are biased by respective voltage DACs (e.g., implemented by current DACs 443 and 445 coupled to respective resistive pull-up elements 451 and 453) controlled by Cα and /Cα, respectively. By this arrangement, when the sample clock signal goes high the current through output node 433 of the sampling circuit 452 is a sum of the currents drawn by transistor 423 of the sampling circuit 452 and transistor 447 of the offset control circuit 440. Similarly, the current through node 431 of the sampling circuit 452 is a sum of the currents drawn by transistor 424 of the sampling circuit 452 and transistor 449 of the offset control circuit 440. As discussed above in reference to FIG. 17, when the current through node 431 exceeds the current through node 433, a logic ‘1’ is stored within storage circuit 436 and, conversely, when the current through node 433 exceeds the current through node 431, a logic ‘0’ is stored within storage circuit 436.
When the DAC control values Cα and /Cα are substantially the same, the comparator 450 is balanced and the effective threshold occurs at the common mode of the D and /D signal levels. That is, if D exceeds the common mode voltage, VCM=((D+/D) divided by 2), the current through node 433 exceeds the current through node 431, causing a logic ‘1’ to be captured as the sampled data value. As Cα is increased and /Cα decreased, the effective threshold of the differential amplifier is increased such that D must be higher than /D by an amount necessary to overcome the additional current drawn by transistor 449 of the offset control circuit. Thus, by increasing Cα and decreasing /Cα, the effective threshold of the sampling circuit may be set to the partial response level, α. That is, a logic ‘1’ is output as the sampled data value if the difference between the D exceeds the common mode voltage, VCM by more than α, and a logic ‘0’ is output otherwise. A counterpart comparator having a −α threshold may be provided by switching the Cα and /Cα inputs to the DACs 443 and 445.
Threshold Level Generator with Single Level-Adapting Comparator
FIG. 20 illustrates a partial response receiver 500 according to another alternative embodiment. The partial response receiver 500 includes a partial response receive circuit 200 that operates generally as described in reference to FIGS. 7 and 14, a level sampler 501, and an adaptive module 503. In contrast to the level sampler 327 of FIG. 14, the level sampler 501 includes a single comparator 507 that generates an error sample, EDLEV, according to whether the incoming signal exceeds or is below a data level threshold generated by the adaptive module 503. In the embodiment of FIG. 20, the data level threshold is established by a multi-bit control value, CDLEV, generated by the adaptive module. In alternative embodiments, the data level threshold may be established by an analog voltage or current generated by the adaptive module 503. The error sample may be buffered in one or more storage circuits 509 before being forwarded to the adaptive module 503, thereby aligning the latency of the error sample with data samples generated by the partial response receive circuit 200.
The adaptive module 503 receives the error sample from the level sampler 501 and data samples DN−1 and DN−2 from the partial response receive circuit 200 and, in response, generates control values, Cα and /Cα, to establish the ±α levels within the partial response receive circuit 200, and the control value, CDLEV, to establish the data level threshold within the level sampler 501. In one embodiment, the adaptive module 503 initially updates the CDLEV value upon detecting reception of the 1+α data pattern (i.e., D[N−1:N−2]=11) until the comparator 507 indicates that the data level threshold matches the 1+α data level. Thereafter, the adaptive module 503 updates the CDLEV value in response to the 1−α data pattern (10) until the DLEV threshold matches the 1−α data level. The control value, Cα, may be generated, for example, by halving the difference between the two CDLEV values (i.e., C1+α and C1−α), and the /Cα control value may be generated by complementing the Cα value.
FIG. 21 illustrates the operation of the adaptive module 503 of FIG. 20 according one embodiment. Initially, at block 521, the control values, Cα and CDLEV, and an internally maintained control value, C2α, are each set to a nominal zero value. In one embodiment, the nominal zero value corresponds to a DAC midpoint value. For example, in an 8-bit DAC, a midpoint value of 1000 0000b (the ‘b’ indicating binary notation) or 128 decimal may be used as the nominal zero value. The C−α value may be generated by subtracting the Cα value from the full-scale DAC value. Thus, in the eight-bit example, when C+α=128, C−α=(28−1)−128=127. It will be appreciated that this result may be obtained by complementing Cα (i.e., /Cα=C−α).
At decision block 523, a history of increment and decrement operations applied to CDLEV value is evaluated to determine whether the threshold level that corresponds to the 1+α signal level has been reached (i.e., UPPER DLEV FOUND). In one embodiment, if, over the last N updates to the CDLEV value, the difference between the number of increment operations and the number of decrement operations is less than a predetermined value, the data level threshold is deemed to be dithering about the 1+α signal level and the upper data level threshold is therefore considered found. If the upper data level threshold has not been found, then the sample values generated by the partial response receive circuit (D[N−1:N−2]) are evaluated in decision block 525 to determine whether a signal level at the 1+α level has been received. If so, the error sample generated by the level sampler, EDLEV, is evaluated in decision block 527 to determine whether the incoming signal level is greater than or less than the threshold level established by the present value of CDLEV. If the error sample is a ‘1’, the incoming signal level is greater than the threshold level, and the CDLEV value is incremented at 529 to increase the data level threshold. If the error sample is a ‘0’, the signal level is less than the data level threshold and the CDLEV value is decremented at 531 to decrease the data level threshold. As discussed above in reference to FIG. 15, some level of filtering may be applied before incrementing or decrementing the CDLEV value. After the CDLEV value has been incremented or decremented (i.e., in block 529 or 531), the CDLEV increment/decrement history is evaluated again at decision block 523 to determine whether the upper data level threshold has been found.
Returning to decision block 525, if D[N−1:N−2] is not equal to ‘11’, the error sample, EDLEV, is not evaluated and the operation at 525 is repeated for a subsequent set of data samples. Thus, in the level-adapting loop formed by blocks 523-531, the adaptive module selectively updates the CDLEV value, and therefore the data level threshold according to the state of the data samples generated by the partial response receive circuit (i.e., updates the CDLEV value in response to detection of the 1+α sample pattern).
If, at decision block 523, the upper data level is deemed to be found, the history of increment and decrement operations is cleared and a second level adapting loop is begun at decision block 535. At decision block 535, the history of increment and decrement operations is evaluated to determine whether a data level threshold corresponding to the 1−α data level has been found (i.e., LOWER DLEV FOUND). In one embodiment, if, over the last N updates to the CDLEV value, the difference between the number of increment operations and the number of decrement operations is less than a predetermined value, the data level threshold is deemed to be dithering about the 1−α signal level and the lower data level threshold is therefore considered found. If the lower data level threshold has not been found, then the sample values generated by the partial response receive circuit, D[N−1:N−2], are evaluated in decision block 537 to determine whether a signal level at the 1−α level has been received. If not, decision block 537 is repeatedly entered for subsequent sample value pairs until a signal level at the 1−α level has been received. When data samples that correspond to the 1−α level are detected, the error sample generated by the level sampling circuit, EDLEV, is evaluated at decision block 539 to determine whether the incoming signal level is above or below the data threshold level established by the present value of CDLEV. If the error sample is a ‘O’, as it will be initially, the signal level is below the data threshold level, and the CDLEV value is decremented at 543 to decrease the DLEV threshold level, and the C2α control value is incremented to track the difference between the upper and lower data level thresholds. If the error sample is determined to be a ‘1’ at decision block 537, then CDLEV is incremented and C2α decremented at block 541. By this arrangement, when the data level threshold reaches the 1−α data level, the control value, C2α, will be representative of twice the +α threshold level. Accordingly, at block 545, the Cα value is generated by dividing C2α by 2 (e.g., by right shifting or otherwise dropping the least significant bit of C2α). The C−α value may be generated by complementing the Cα value. Thereafter, the process is repeated starting at decision block 523. Alternatively, an updated C2α value may be generated by counting the return increments from the lower data level threshold to the upper data level threshold, and another updated value of C2α generated on a subsequent return to the lower data level threshold, and so forth. The Cα value may be updated after each regeneration of the C2ααvalue. Also, rather than finding the 1+α and 1−α data levels, the 1+α and −1+α data levels may be determined, and the corresponding data level control values averaged to generate the Cα value.
Dual Mode Receiver
FIG. 22 illustrates an embodiment of a dual mode receiver 550 that may be operated in either a multi-level signaling mode or a partial response mode. When a mode select signal 572 (MSEL) is in a first state (e.g., a logic low state), a two-bit per symbol, multi-level signaling mode is selected. In one embodiment, illustrated in FIG. 23, the signal level of each incoming symbol falls into one of four voltage ranges distinguished by three threshold levels. The four voltage ranges are designated 10, 11, 01 and 00 in FIG. 23 according to the pair of data bits represented at each level. Because each symbol constitutes a pulse having one of four possible amplitudes, the incoming multi-level signal is referred to herein as a 4-PAM (Pulse Amplitude Modulation) signal. Different PAM levels (e.g., 8-PAM, 10-PAM, etc.) may be used in alternative embodiments.
In the multi-level signaling mode, comparator 557 compares the incoming signal with a midlevel threshold (referred to herein as the zero threshold) to determine the state of the most significant bit (MSB) of the symbol. In the embodiment of FIGS. 22 and 23, the MSB is resolved to be a ‘1’ if the signal level exceeds the zero threshold, and a ‘O’ if the signal level does not exceed the zero threshold. Comparators 553 and 555 compare the incoming signal with threshold levels +α and −α, respectively. For example, in a 4-PAM signal mode, the +α threshold level is set to the steady-state low level plus 5⁄6 of the difference between the steady-state high and low levels, and the a threshold is set to the steady-state low level plus 1⁄6 of the difference between the steady-state high and low levels. Referring to FIG. 23, if the incoming signal level exceeds the +α threshold level, both comparators 553 and 555 generate a logic high sample value, and if the signal level is below the −α threshold level, both comparators 553 and 555 generate a logic low sample value. By contrast, if the incoming signal level is between the +a and −α threshold levels, the comparators 553 and 555 generate outputs having different states. Thus, by assigning the least significant bit (LSB) of the incoming symbol to be a logic ‘0’ in the case of a signal level above the +α threshold level or below the −α threshold level, and a logic ‘1’ in the case of a signal level between the +α and a thresholds, the LSB may be generated by exclusive ORing the sample values generated by the comparators 553 and 555. Accordingly, exclusive OR gate 561 is coupled to receive the sample values generated by the comparators 553 and 555 (i.e., after the sample values are buffered in storage circuits 554 and 556), and outputs the LSB to a first port of select circuit 565. When the mode select signal selects the 4-PAM mode of the dual-mode receiver, the LSB is selected to be passed to next stage storage circuits 567 and 578, and ultimately is selected by select circuit 579 to be provided to the adaptive module 581. Thus, in 4-PAM mode, the adaptive module 581 receives an LSB and MSB (the MSB bit being stored in succession in storage circuits 558, 571 and 573 for latency alignment with the LSB) for each set of sample values generated by the comparators 553, 555, and 557.
It should be noted that the threshold levels and data signal levels described in reference to FIG. 23 may be used in both differential and single-ended signaling systems. In the case of single-ended signaling systems, the voltage levels of the thresholds and data signals are expressed as an offset from a common, substantially fixed reference voltage, such as a ground reference. In differential signaling systems, the data signals and thresholds are each represented by differential signal pair, with the voltage level of the data signal or threshold being the voltage difference between the two differential signals (e.g., subtracting the voltage level of one signal from the other).
Still referring to the 4-PAM mode of the dual mode receiver 550, the comparator 551 generates an error sample EDLEV that is buffered within storage circuits 552 and 570, then provided to the adaptive module 581. In one embodiment, the adaptive module generates the 4-PAM mode threshold level control values C0, C+α and C−α (i.e., the control values supplied to comparators 557, 553, 555, respectively) by determining the data signal level at MSB/LSB=11, and then the signal level at MSB/LSB=00. For example, the C+α value is offset from the 00 signal level by two-thirds of the difference between the 11 and 00 signal levels, C0 is set to the midpoint between the 11 and 00 signal levels, and C−α is offset from the 00 signal level by one-third of the difference between the 11 and 00 signal levels. As with the adaptive module described in reference to FIG. 14, the error sample generated by the comparator 551 may be filtered to obtain the steady state 11 signal level and the steady state 00 signal level.
Still referring to FIG. 22, when the mode select signal 572 is high, the dual mode receiver 550 is switched to the partial response mode. In the partial response mode, the comparators 553 and 55 are used to compare the incoming data signal against the partial response threshold levels +α and −α, respectively. The samples values generated by the comparators 553 and 555 are buffered in storage circuits 554 and 556, respectively, then provided to select circuit 563 which selects one of the samples according to the state of the previously received sample. That is, one of the DN−1 samples stored in storage circuits 554 and 556 is selected to be stored in storage circuit 567 according to the DN−2 sample previously stored in the storage circuit 567. The DN−2 sample is stored in the storage circuit 578 to generate the DN−3 sample value. During a given symbol time, both the DN−2 and DN−3 samples are provided to the adaptive module 581 via select circuits 579 and 575, respectively. Thus, in 4-PAM mode, the adaptive module 581 receives the MSB/LSB pair for each incoming 4-PAM symbol, and in partial response mode, the adaptive module 581 receives the D[N−2:N−3] sample values that represent one of the four states of the bimodal signal illustrated in FIG. 4.
Still referring to FIG. 22, in partial response mode, the comparator 551 and adaptive module 581 operate to generate the +α and −α levels in the manner described in reference to FIGS. 20 and 21. Alternatively, because the MSB comparator 557 is not otherwise used in the partial response mode, the comparator 557 may be used to determine the level of the 1−α partial response state, thereby enabling both the 1+α and 1−α signal levels to be determined simultaneously. The ±α levels may then be generated based on the 1+α and the 1−α signal levels (i.e., Cα=((C1+α)−(C1−α))/2, and C−α=/Cα). In another alternative embodiment, the MSB comparator may be used to determine the −1+α signal level, thereby enabling ±α to be determined by averaging the 1+α and −1+α signal levels. The error signal generated by the MSB comparator, E10 (or E01) is illustrated by dashed line 574 to indicate its optional nature.
Reflecting on the dual mode receiver 550 of FIG. 22, it can be seen that much of the circuitry provided for 4-PAM operation (e.g., the four comparators (551, 553, 555 and 557), storage circuits (552, 554, 556, 558, 567, 570, 571, 578 and 573) and adaptive module 581) is re-used in the 2-PAM partial response mode, thereby providing partial response operation with relatively little additional hardware overhead. The mode select signal 572 may be provided from an external source or from a configuration control circuit within the integrated device that includes the dual mode receiver 550. In one embodiment the configuration control circuit is a configuration register that may be programmed by one or more other integrated circuits within a system (e.g., a host processor or similar control device) to establish the mode of the dual mode receiver 550. The configuration control circuit may also be a non-volatile control circuit such as a non-volatile memory, fusible circuit or similar circuit that may be programmed with a mode select value. In yet other embodiments, the configuration control circuit may dynamically change the state of the mode select signal in response to detecting selected system conditions (e.g., detection of threshold error rate when in one operating mode or the other).
Clock Recovery
FIG. 24 illustrates an embodiment of a partial response receiver 600 that performs a clock data recovery (CDR) function. That is, the partial response receiver 600 recovers both data and clocking information from the incoming data signal, DN. The partial response receiver 600 includes a data receive and level sampling circuit 601, adaptive module 603, clock recovery circuit 605, edge-sampling comparator 607, and one or more storage circuits 609. The data receive and level sampling circuit 601 operates as described above in reference to FIGS. 14 and 20 to generate one or more error samples, EDLEV, and data samples D[N−1:N−2]. The data receive and level sampling circuit 601 may also be operable in a multi-PAM mode as described in reference to FIG. 22. The adaptive module 603 generates one or more threshold control values that are supplied to the data receive and level sampling circuit 601, including one or more data level control values, CDLEV, and partial response control values, C+α and C−α. The control values are used to establish threshold values in the partial response compare circuits (i.e., the ±α comparators) and one or more level adapting comparators as discussed above.
The clock recovery circuit 605 generates a sampling clock signal 210 (SCLK) and edge clock signal 610 (ECLK) in response to a transition sample, TN−1, generated by the edge-sampling comparator 607 and the data and error samples generated by the data receive and level sampling circuit 601 (i.e., EDLEV and D[N−1:N−2]). The sampling clock signal 210 is used to time the operation of comparators and storage circuits within the data receive and level sampling circuit 601 and, at least in one embodiment, is phase aligned with midpoints in the incoming data eyes (i.e., midpoint of data valid intervals in the incoming data signal, DN). In an alternative embodiment, the sampling clock signal 210 may be offset from the midpoints in the incoming data eyes, for example, to accommodate asymmetric setup and hold time requirements in the comparators or other circuitry in the data receive and level sampling circuit 601. Note that while only a single sampling clock signal 210 is shown, multiple sampling clocks may be generated by the clock recovery circuit to enable receipt of multi-data rate signals. For example, in a double data rate system, the clock recovery circuit may generate SCLK and /SCLK to enable capture of data and signal level samples in both odd and even phases of the sampling clock signal 210.
The clock recovery circuit 605 adjusts the phase of the edge clock signal 610 to maintain phase alignment between the edge clock signal 610 and transition points between incoming data eyes (i.e., the edge clock signal 610 is edge aligned with data valid intervals in the incoming data signal). The edge clock signal 610 is supplied to the edge-sampling comparator 607 where it is used to time the sampling of transitions in the incoming data signal, and to one or more storage circuits 609 provided to latency-align the transition sample, TN−1, with the data sample, DN−1. In the case of a low-to-high data signal transition, a logic ‘1’ transition sample (i.e., TN−1=1) indicates that the edge clock transition occurred after the transition in the data signal and therefore that the edge clock signal 610 lags the data signal transition. Conversely, a logic ‘0’ transition sample indicates that the edge clock transition occurred prior to the low-to-high data signal transition and therefore that the edge clock signal 610 leads the data signal transition. The transition samples from edge-sampling comparator 607 and data samples from the data receive and level sampling circuit 601 are used within the clock recovery circuit 605 to adjust the phase of the edge clock signal 610 as necessary to maintain alignment between the edge clock signal 610 and transitions in the incoming data signal. In one embodiment, the sampling clock signal 210 is maintained at a substantially constant phase offset from the edge clock signal 610 such that phase alignment between the edge clock signal 610 and data signal transitions yields a desired phase alignment between the sampling clock signal 210 and midpoints in the incoming data eyes.
FIG. 25 illustrates a number of possible data signal transitions when the incoming data signal has the bimodal distribution shown in FIG. 5. That is, if the incoming data signal has one of the four bimodal signal levels corresponding to the partial response states 11, 10, 01, 00, then the signal may transition from either the 11 or 10 level to the 01 level (i.e., D[N−1:N−2]=11 or 10 and D[N:N−1]=01), and the signal may transition from either the 00 or 01 level to the 10 level. Note that signal transitions from the 10 level to the 11 level (illustrated by dashed line 631) and from the 01 level to the 00 level (illustrated by dashed line 632) are also possible.
Considering the transitions from 10-to-01 and from 01-to-10, it can be seen that each of these transitions crosses the midpoint threshold (i.e., zero threshold level) at a time, T1, midway between the centers of the data eyes 628 and 630. That is, if the edge clock signal 610 is phase aligned to the transitions in the incoming data signal, the 10-to-01 and 01-to-10 data signal transitions cross the midpoint threshold coincidentally (i.e., in phase alignment) with the edge clock transition. Accordingly, the 10-to-01 and 01-to-10 transitions may be compared with the zero threshold level (designated ‘0’ in FIG. 25) to generate transition samples for adjusting the phase of the edge clock signal. Note that, because the signal swings in the transitions from 11-to-01 and 00-to-10 are not symmetric with respect to the zero threshold level, the 11-to-01 and 00-to-10 transitions do not cross the zero threshold level at the same time as the 10-to-01 and 01-to-10 transitions, but rather cross the zero threshold level at some time later (indicated by circle 636). Consequently, use of the 11-to-01 and 00-to-10 transitions to determine zero-crossing times (i.e., times at which the zero threshold level is crossed) may introduce phase error and/or bi-modal jitter in the recovered edge and sampling clock signals 610 and 210. Accordingly, in one embodiment of the invention, transitions in the incoming data signal are selected according to their zero-crossing characteristics, with the selected transitions being used to adjust the phase of the edge and sampling clock signals 610 and 210.
FIG. 26 illustrates an embodiment of a clock recovery circuit 650 that adjusts the phase of edge clock signal 610 and sampling clock signal 210 based on selected transitions detected in the incoming data signal. The clock recovery circuit 650 includes a transition detect circuit 651, early/late detector 661, early/late counter 663, majority detector 665, interpolator 667 and reference loop 669. In the embodiment of FIG. 26, the transition detect circuit 651 asserts a transition detect signal 652 (TDET) upon detecting a 01-to-10 or a 10-to-01 transition in the incoming data signal. More specifically, incoming data samples DN−1 and DN−2 are compared in exclusive-OR gate 653 to determine whether a transition has occurred, and signals DN and DN−2 are compared in exclusive-NOR gate 657 to determine whether the DN state matches the DN−2 state. The outputs of the exclusive OR and exclusive-NOR gates 653, 657 are supplied to AND gate 659 which generates the transition detect signal 652. By this arrangement, the transition detect signal 652 goes high if D[N:N−2]=010 or 101 (i.e., in response to a 01-to-10 transition or a 10-to-01 transition). The transition detect signal 652 is applied to a count enable input (CEN) of the early/late counter 663 to enable an early/late count value to be incremented or decremented according to the output of the early/late detector 661. In one embodiment, the early late detector 661 is implemented by an exclusive OR gate, and therefore asserts an early signal 654 (e.g., a logic high signal) if the transition sample, TN, does not match data sample DN, and a late signal (e.g., logic low signal 654) if the TN matches DN. That is, if the transition sample is captured after the transition from DN−1 to DN, the transition sample will match the DN sample and thereby indicate that the edge clock signal transition is late relative to the data signal transition. Conversely, if the transition sample is captured before the transition from DN−1 to DN, the transition sample will not match the DN sample and thereby indicate that the edge clock signal transition is early relative to the data signal transition.
In one embodiment, the early/late counter 663 is initialized to a zero level, and is then incremented in response to an early signal (i.e., from the early/late detector 661) and decremented in response to a late signal. By this arrangement, the sign bit (e.g., the MSB) of the early/late count maintained within the early/late counter 663 indicates whether more early signals than late signals, or more late than early signals have been received from the early/late detector (i.e., the count value will underflow to a negative value if more late signals than early signals are detected). Accordingly, after a predetermined number of transition detect assertions (or after a predetermined time), the majority detector 665 evaluates the sign of the early/late count and asserts an up/down signal 668 to the interpolator accordingly. The early/late count value may then be reset to zero in order to count a subsequent set of early/late signal assertions.
In one embodiment, the interpolator 667 maintains a digital control word that is incremented in response to a logic high up/down signal 668 and decremented in response to a logic low up/down signal 668. The most significant bits of the digital control word are used to select a pair of phase vectors from the set of N phase vectors 672 generated by the reference loop 669, and the least significant bits of the digital control word are used to interpolate between the selected pair of phase vectors. As the control word is incremented, the interpolation is incrementally shifted from a leading one of the phase vectors to a lagging one of the phase vectors, thereby incrementally retarding the phase of the edge and sampling clock signals 610, 210. Conversely, as the control word is decremented, the interpolation is incrementally shifted toward the leading one of the selected phase vectors, thereby incrementally advancing the phase of the edge and sampling clock signals 610, 210.
In one embodiment, the reference loop 669 is formed by a delay locked loop (DLL) that receives a reference clock signal 670 and, in response, generates a plurality of phase vectors 672 that are phase distributed within a cycle time of the reference clock signal 670. Alternatively, the reference loop 669 may be a phase locked loop (PLL) that multiplies the reference clock frequency to generate a plurality of phase vectors 672 having a higher frequency than the reference clock frequency. In another alternative embodiment, the reference loop 669 may include an internal timing reference generator (e.g., a ring oscillator or other clock generating circuit) so that no reference clock signal 670 is required. Also, as discussed above, the interpolator 667 may generate any number of sampling clock and edge clock signals. For example, in a double data rate system, the interpolator generates an edge clock signal and complement edge clock signal, and a sampling clock signal and complement sampling clock signal, the sampling clock signal being offset from the edge clock signal by a quarter cycle (90 degrees) of the edge clock signal. The quarter cycle offset may be achieved, for example, by a second interpolator that maintains a control word having a 90 degree digital offset from the control word used to generate the edge clock signal. Other techniques may be used to generate the edge clock-to-sample clock offset in alternative embodiments. In a quad data rate system, the interpolator generates four edge clock signals and four sampling clock signals, the combined set of eight clock signals being distributed in phase through a cycle time of the edge clock signal (i.e., 45 degree increments between successive clock edges). This approach may be extended to support virtually any data rate.
It should be noted that numerous changes may be made to the clock recovery circuit of FIG. 26 without departing from the scope of the present invention. For example, in one alternative embodiment, the up/down signal is a two-bit signal in which the 00 state indicates a hold condition in which control word maintained within the interpolator is not adjusted. In such an embodiment, the majority detector may receive the entire early/late count from the early/late counter, and output the up/down signal in the 00 state if the count value indicates a balanced reception of early and late detections (e.g., the early/late count is zero). Alternatively, the majority detector may be omitted altogether and the sign of the early/late count value output directly to the interpolator to control the phase adjustment of the edge and sampling clock signals.
Returning to FIG. 25, it can be seen that the 11-to-01 transition occurs between the 1+α and −1+α signal levels, and therefore crosses the midpoint between the centers of data eyes 628 and 630 (i.e., time T1) at the +α threshold level. That is, the 11-to-01 transition crosses the +α threshold coincidentally with the desired transition time of the edge clock signal 610. Similarly, the 00-to-10 transition crosses the −α threshold coincidentally with the desired transition time of the edge clock signal 610. Moreover, the 11-to-01 and 00-to-10 transitions have a faster slew rate than the 10-to-01 and 01-to-10 transitions and therefore tend to yield more accurate timing edges. That is, the signal passes through the metastable region more quickly, thereby generating less timing jitter. Accordingly, in one embodiment, additional edge comparators are provided to generate transition samples at the +α and/or −α thresholds. Additional circuitry is also provided within the clock recovery circuit 650 of FIG. 26 to detect the 11-to-01 and/or 00-to-10 transitions and, in response, to update the early/late counter according to the corresponding transition samples. By this arrangement, the overall number of data signal transitions that are used for clock recovery is increased, thereby relaxing the transition density required in the incoming signal for clock recovery purposes.
In partial response receiver embodiments in which the ±α levels are adapted (i.e., as opposed to being initially calibrated or determined empirically and one-time programmed), the ±α levels may initially be incorrect (e.g., started at 0) so that edge comparison based on the ±α levels may be undesirable. In such a system, a zero-threshold edge comparator (e.g., edge-sampling comparator 607 of FIG. 24) may be used to recover the edge and sampling clock signals initially, with switchover to ±α edge comparators occurring after the ±α levels are determined. Transition samples generated by zero-threshold edge comparator may then be ignored, or the samples may continue to be used.
In a system that recovers edge and sampling clock signals based on ±α threshold crossings, and that adapts ±α levels based on a difference between the 1+α and 1−α signal levels, a non-convergence of the ±α threshold levels may occur in certain situations. Referring to bimodal distribution shown in FIG. 27, it can be seen that as the sampling clock phase moves left (i.e., in the increasingly lagging direction), the difference between signal levels 682 and 684 increases. Unfortunately, the increased difference between signal levels 682 and 684 yields larger magnitudes for the ±α threshold levels which, as can be seen in the diagram of FIG. 25, shifts the phase of the edge and sampling clock signals further in the lagging direction (i.e., further to the left), thereby further increasing the clock phase error. If the clock phase error becomes too large, accurate data and edge samples are no longer received by the partial response receiver so that the ±α threshold levels will not converge to the desired setpoints.
Still referring to FIG. 27, one solution to the non-convergence problem is to limit the data samples used to adapt the ±α threshold levels to those indicated by bolded lines 681 and 683. That is, in the case of a sample for which D[N:N−1]=11, the +α level is updated only if the preceding state was 10 (i.e., D[N−1:N−2]=10). Similarly, in the case of a sample for which D[N:N−1]=10, the −α threshold level is updated only if the preceding sate was 01 (i.e., D[N−1:N−2]=01). By this arrangement, as the edge and sampling clock signals begin to lag the desired phase offsets (i.e., TSAMPLE moving to the left in the diagram of FIG. 27), the difference between the +α and −α threshold levels will decrease, thereby producing a counter-effect to shift the edge and sampling clock signals in the leading direction. The level-adapting procedure described in reference to FIG. 21 may be modified to accommodate the above change by changing the evaluation in decision block 525 to D[N−1:N−3]=1 10 and changing the evaluation in decision block 537 to D[N−1:N−3]=101. Note that these sample patterns are illustrated in FIG. 27 as being patterns for bits D[N:N−2]. In general, the data samples relied upon for level adaptation may have any latency.
FIG. 28 illustrates an embodiment of a dual-mode, partial response receiver 700 with clock data recovery. The partial response receiver 700 includes a dual-mode data receive/level sampling circuit 701, adaptive module 703, edge comparators 707, 708, 709, and clock recovery circuit 705. The dual-mode data receive/level sampling circuit 701 and the adaptive module 703 operate in generally the same manner as the circuitry described in reference to FIG. 22. That is, when the mode select signal selects a 4-PAM mode of operation, the data receive and level sampling circuit samples incoming 4-PAM signals to generate an MSB and LSB per captured sample, and generates a data level error sample (EDLEV) that allows the adaptive module to determine the full scale difference between steady-state high and low signal levels. The +α, −α and zero threshold levels are then established by the adaptive module 703 at the Cα=2⁄3 full-scale, C−α=1⁄3 full-scale and C0=1⁄2 full-scale levels, respectively (other threshold levels may be used in alternative embodiments). When the mode select signal selects a 2-PAM mode of operation, the data receive and level sampling circuit 701 generates data samples by selecting between partial-response comparators (i.e., the comparators receiving the ±α threshold levels) and supplies the selected samples to the adaptive module 703 in pairs to enable determination of which of partial response state is reflected by the error sample, EDLEV, generated by data level comparator (or data level comparators). The adaptive module 703 then adjusts the ±α threshold levels and the zero threshold level according to the incoming data signal levels determined by the data level comparator.
The edge comparators 707, 708 and 709 capture transition samples TN−2(+α), TN−2(−α) and TN−2(0), respectively, of the incoming data signal in response to transitions of an edge clock signal, ECLK, and provide the transition samples to the clock data recovery circuit 705. The 4-PAM/partial response data samples captured by the data receive and level sampling circuit 701 (i.e., MSB/LSB in 4-PAM mode, D[N−2:N−3] in partial response mode) are also provided to the clock data recovery circuit 705. The clock data recovery circuit selectively adjusts the phases of the edge clock signal 610 and sampling clock signal 210 based on the transition samples and data samples.
FIG. 29 illustrates the possible signal transitions between successive 4-PAM symbols. As shown, from each of four possible signal levels, the incoming data signal may transition to any of three other signal levels. For example, a signal level above +a (corresponding to data state 10) may transition to a signal level between +α and 0 (data state 11); a signal level between 0 and −α (data state 01); and a signal level below −α (data state 00). Examining the different possible transitions, it can be seen that any transitions that cross all three threshold levels will cross the zero threshold level at the timing center, T1, between the desired data sampling instants. Similarly, transitions that cross a single threshold level will cross either the zero threshold level, the +α threshold level or the −α threshold level at T1. By contrast, any transitions that cross two threshold levels, but not three, do not cross the zero, +α or −α threshold levels at T1. Enumerating the different transitions that cross the zero, +α and −α threshold levels at T1 as transition types (1), (2) and (3), respectively, it can be seen that type (1) transitions are those in which the LSB remains unchanged at either ‘1’ or ‘0’, while the MSB changes state (i.e., (MSBN xor MSBN−1) & (LSBN xnor LSBN−1)); type (2) transitions are those in which the MSB remains high while the LSB changes state (i.e., MSBN & MSBN−1 & (LSBN xor LSBN−1)); and type (3) transitions are those in which the MSB remains low, while the LSB changes state (i.e., /MSBN & /MSBN−1 & (LSBN xor LSBN−1)). Thus, in one embodiment, when the mode select signal 712 selects a 4-PAM mode of operation within the partial response receiver 700 of FIG. 28, the clock recovery circuit adjusts the phase of the edge clock signal and sampling clock signal in response to the data samples generated by the data receive and level sampling circuit 701 and the transition samples generated by comparators 707, 708, 709 in accordance with the following table:













TABLE 1







Center








Time




Crossing



Early/Late


DN − 1(4P)
DN(4P)
At:
TN(+α)
TN(−α)
TN(0)
Count Adj.







00
01
−α
X
0/1*
X
+1/−1


00
11
—
X
X
X
—


00
10
0
X
X
0/1
+1/−1


01
00
−α
X
0/1
X
−1/+1


01
11
0
X
X
0/1
+1/−1


01
10
—
X
X
X
—


11
00
—
X
X
X
—


11
01
0
X
X
0/1
−1/+1


11
10
+α
0/1
X
X
+1/−1


10
00
0
X
X
0/1
−1/+1


10
01
—
X
X
X
—


10
11
+α
0/1
X
X
−1/+1





(*‘0/1’ means ‘0’ or ‘1’ and corresponds to the +1 or −1 adjustment to the early/late count)






Still referring to FIG. 28, when the partial response receiver 700 is operated in the partial response mode, the transitions of interest are as shown in FIG. 30. That is, a partial-response state transition from 10-to-01 or 10-to-01 crosses the zero threshold level at the desired edge clock transition time, T1; a state transition 11-to-01 crosses the +α threshold level at T1; and a state transition from 00-to-10 crosses the −α threshold level at T1. Enumerating the partial response mode transitions that cross the zero, +α and −α threshold levels at T1 as transition types (1), (2) and (3), respectively, it can be seen that type (1) transitions are those in which the current data sample, DN, does not match the immediately preceding data sample, DN−1, which, in turn, does not match the twice-removed data sample, DN−2 (i.e., (DN xor DN−1) & (DN xor DN−2)); type (2) transitions are those in which the current data sample, DN, is low, and the two immediately preceding data samples, DN−1 and DN−2, are high (i.e., /DN & DN−1 & DN−2); and type three (3) transitions are those in which the current data sample, DN, is high, and the two immediately preceding data samples, DN−1 and DN−2, are low (i.e., DN & /DN−1 & /DN−2). Thus, in one embodiment, when the mode select signal 712 selects a partial response mode of operation within the partial response receiver 700, the clock recovery circuit 705 adjusts the phase of the edge clock and sampling clock signals 610, 210 in response to the data and transition samples generated by circuit 701 and comparators 707, 708, 709 in accordance with the following table:













TABLE 2







Center



Early/




Time



Late


D[N − 1:
D
Crossing



Count


N − 2]
[N:N − 1]
At:
TN(+α)
TN(−α)
TN(0)
Adj.







00
10
−α
X
0/1
X
+1/−1


01
00
—
X
X
X
—


01
10
0
X
X
0/1
+1/−1


10
01
0
X
X
0/1
−1/+1


10
11
—
X
X
X
—


11
01
+α
0/1
X
X
−1/+1









Still referring to FIG. 30, if the +α and −α threshold levels are initially set to zero as indicated by reference numeral 741, it can be seen that the edge clock alignment will initially converge to a point that is phase delayed relative to the desired edge sampling point, T1. As the levels of ±α progress toward their ultimate setpoints at 742 and 743, however, the edge clock phase alignment will converge to the desired sampling point, T1.
FIG. 31 illustrates a transition detect circuit 725 and sample select circuit 740 that may be used within the clock recovery circuit 705 of FIG. 28. The transition detect circuit receives the data sample pair generated by the data receive and level sampling circuit 701 and generates a transition detect signal 732 (TDET) in accordance with the states of successive data sample pairs, the mode select signal 712 (MSEL) and a transition select signal 728 (TS[3:1]). The transition detect circuit additionally generates component transition detect signals 7331, 7332 and 7333 (i.e., TDET(0), TDET(+α) and TDET(−α), respectively) which are output to the transition select circuit 740. The transition select circuit includes AND gates 7411, 7412, and 7413 to gate the transition samples TN(0), TN(+α) and TN(−α), according to the state of the corresponding transition select signals 7331-7333. The outputs of the AND gates 741 are input to OR gate 743 to generate an early signal 734. The transition detect signal 732 is itself generated by a logic OR combination of the component transition detect signals 733 in OR gate 733. By this arrangement, if any of the component transition detect signals 733 is asserted (e.g., to a logic high state), the transition detect signal 732 is asserted, and the state of the corresponding transition sample TN is output as the early signal 734.
The transition detect circuit 725 includes a set of combinatorial logic circuits 7271, 7272 and 7273 that generate type (1), type (2) and type (3) transition detect signals 730 for both 4-PAM and partial response data states in accordance with the type (1), type (2) and type (3) transition types described in reference to FIGS. 29 and 30. In the embodiment of FIG. 31, combinatorial logic circuit 7271 generates a 4-PAM type (1) transition detect signal 7301A and a 2-PAM, partial response type (1) transition detect signal 7301B as follows:

    
    
        Signal 7301A=(MSBN xor MSBN−1) & (LSBN xnor LSBN−1); and
        Signal 7301B=(DN xor DN−1) & (DN−1 xor DN−2).

Similarly, combinatorial logic circuits 7272 and 7273 generate 4-PAM type (2) and type (3) transition detect signals 7302A and 7303A, and 2-PAM, partial response type (2) and type (3) transition detect signals, 7302B and 7303B, as follows:

        Signal 7302A=(MSBN & MSBN−1) & (LSBN xor LSBN−1);
        Signal 7303A=(/MSBN & /MSBN−1) & (LSBN xor LSBN−1);
        Signal 7302B=/DN & DN−1 & DN−2; and
        Signal 7303B=DN & /DN−1 & /DN−2.

It should be noted that, in both partial-response mode and 4-PAM mode, two successive pairs of data samples are used within the transition detect circuit 725 (e.g., MSB/LSBN and MSB/LSBN−1 in 4-PAM mode; DN/DN−1 and DN−1/DN−2 in partial response mode) to generate the transition detect signals 730. One or more of the data sample pairs may be buffered within a storage circuit within transition detect circuit 725 or elsewhere within the dual mode receiver and made available to the various combinatorial logic circuits 727. Also, the latency of the data samples referred to in FIG. 31, though depicted as N, N−1 and N−2, may be any latency necessary to match the latency of the data samples output from the data receive and level sampling circuit 701 of FIG. 28.

    
    


Select circuits 7291, 7292 and 7293 each have a first input port coupled to receive a respective one of the 4-PAM type (1), type (2) and type (3) transitions detect signals 7301A, 7302A and 7303A, respectively, and a second input port coupled to receive a respective one of the 2-PAM, partial response type (1), type (2) and type (3) transition detect signals 7301B, 7302B and 7303B, respectively. The mode select signal 712 is coupled to a select input of each of the select circuits 729 so that, when the mode select signal 712 is low to select a 4-PAM mode of operation, the 4-PAM transition detect signals 7301A, 7302A and 7303A are supplied to inputs of respective AND gates 7311, 7312 and 7313, respectively. By contrast, when the mode select signal 712 is high, the 2-PAM, partial response transition detect signals 7301B, 7302B and 7303B are supplied to respective inputs of the AND gates 731. In the embodiment of FIG. 31, the transition select signal 728 includes three component signals, TS[1], TS[2] and TS[3], that are input to AND gates 7311, 7312 and 7313, respectively, to gate the generation of the component transition detect signals 7331, 7332, and 7333. Thus, the transition select signal 728 may be used selectively enable the different types of data signal transitions to be used for clock recovery purposes. For example, if TS[3:1]=001, then detection of type (1) transitions (i.e., crossing the zero-threshold at the desired time) is enabled, but detection of type (2) and type (3) transitions (i.e., crossing the +α thresholds at the desired time) is disabled. When TS[3:1]=111, then detection of all three types of transitions depicted in FIGS. 29 and 30 is enabled. Other settings of the transition select signal may be used to enable detection of the different transition types in other combinations. In one embodiment, the transition select signal is generated according to a transition select value stored in a configuration circuit that may be run-time programmed (e.g., by a host processor or other system control component). The transition select value may alternatively be programmed into a non-volatile storage circuit (e.g., at production time) or similar hardware configurable circuit (e.g., fuse-blowing to establish desired configuration).
The transition detect signal 732 and early signal 734 generated by the transition detect circuit 725 and transition select circuit 740 may be used to control the phase of one or more sampling clock signals and one or more edge clock signals in the manner above in reference to FIG. 26. For example, in one embodiment the transition detect signal 732 is applied to the count enable input of an early/late counter, and the early signal 734 is applied to the up/down input. The transition detect signal 732 and early signal 734 may alternatively be supplied to other logic circuitry that determines whether detected transitions occur early or late relative to an edge clock signal.
Numerous changes may be made to the transition detect circuit 725 and transition select circuit 740 without departing from the spirit and scope of the present invention. For example, if the data signal transitions to be used for clock recovery is a subset of the three transition types shown in FIGS. 29 and 30, one or more component signals of the transition select signal (and corresponding components of the combinatorial logic 727, select circuitry 729 and gating circuitry 731, 741) may be omitted. Moreover, if the transition types are fixed for a given application (e.g., all three types of the transitions depicted in FIGS. 29 and 30, or any subset or single one thereof), the transition select signal may be omitted altogether along with the combinatorial logic and gating circuitry for any unused types of transitions.
FIG. 32 illustrates the full set of transitions that may be detected when the partial response receiver 700 of FIG. 28 is operated in the partial response mode. In particular, transitions 750 and 751 (i.e., transitions from 10-to-11 and from 01-to-00), designated type (4) and type (5) transitions, respectively, can be seen to cross the nominal 1 and −1 threshold levels (referred to herein as unity threshold levels), respectively, at the desired edge sampling point, T1. Note that, in these transitions, the input signal slews substantially faster than in the 01-to-10 and 10-to-01 transitions and therefore is a potentially more accurate (and/or more jitter-free) source of clock phase information. Accordingly, in one embodiment, additional edge comparators are provided in the circuit of FIG. 28 (not shown), and corresponding additional logic is added to the transition detect and select circuits (725, 740) of FIG. 31 to enable clock recovery based on type (4) and/or type (5) transitions. Alternatively, in one embodiment, the zero-threshold comparator 709 of FIG. 28 is re-allocated to a unity threshold comparator function after the ±α threshold levels are established (e.g., converge to the points 742 and 743 depicted in FIG. 30). FIG. 33 illustrates an embodiment of a threshold select circuit 760 that is used to select between control values C0 and C1 for the zero and unity threshold levels, respectively. Initially a threshold select signal 762 (LSEL) is supplied in a first state to multiplexer 761 (or other select circuit) to select the C0 control value to be provided to edge comparator 709, thereby enabling the 10-to-01 and 01-to-10 transitions to be used for clock recovery purposes as the ±α levels are adapted. After the ±α levels have reached convergence points (e.g., begin to dither), the threshold select signal 762 is switched to an alternate state to select the C1 control value to be used for generation of edge samples. The C1 control value may be generated by the adaptive module 703 of FIG. 28 using the techniques discussed above in reference to FIG. 22. The C0 and/or C1 control values may be buffered in registers 763 and 765 as shown in FIG. 33 (or other storage circuits), or provided directly to the multiplexer 761 from the adaptive module.
Referring again to the partial response receiver 700 of FIG. 28, it should be noted that the receiver may alternatively be a single-mode 4-PAM circuit having the clock recovery function described above in reference to FIGS. 28, 29 and 31 (i.e., omitting the combinatorial circuitry and mode select circuitry used to enable the partial response mode). That is, the 4-PAM circuit may include data receive circuitry for capturing a sequence of 2-bit data samples (or more bits per data sample in the case of M-PAM, M>4), and clock recovery circuitry that captures transition samples at one or more of the 0, +α and −α threshold levels, and that selectively uses the transition samples to recover a sampling clock signal and edge clock signal according to the state of successive data samples. Conversely, the circuitry necessary to enable the 4-PAM mode of operation may be omitted to provide a partial-response receiver with clock recovery circuitry that captures transition samples at one or more of the 0, +α and −α threshold levels, and that selectively uses the transition samples to recover a sampling clock signal and edge clock signal according to the state of successive data samples.
In another alternative embodiment, the partial response receiver 700 of FIG. 28 may include a third, non-partial-response operating mode in which binary signal reception and clock recovery are performed without regard to partial response. That is, the +α and −α comparators within the data sampling circuit and edge sampling circuit may be disabled, and the zero-threshold comparators within the data and edge sampling circuits being used to sample data and edges in the incoming signal. Alternatively, in the non-partial-response mode, the ±α threshold levels may be set to zero such that all the comparators within the data and edge sampling circuits perform a zero-threshold comparison. In yet other embodiments, the partial response receiver 700 of FIG. 28 may be operable in either a 4-PAM or binary mode, with partial response signal detection being separately enabled in either mode. That is, the partial response receiver 700 may be operated in either a binary non-partial response mode; a binary partial response mode; a 4-PAM non-partial response mode; or a 4-PAM partial response mode. Moreover, the number of least-latent data samples included in the partial response may be extended to any number. More generally, the receive circuit 700 may be operated in PAM modes ranging from M-PAM to (M−X)-PAM (where M is any integer and X is any integer less than M−1), and may be operated with or without regard to partial response in each PAM mode. Circuitry to support extended-bit partial response operation, and 4-PAM partial response operation is discussed below in greater detail.
Clock Recovery with Reduced Input Hardware
As discussed above, if a subset of the available data signal transitions are to be used for clock recovery within the partial response receiver 700 of FIG. 28, circuitry otherwise provided to recover phase error information from the unused transitions may be omitted, including one or more of edge comparators 707, 708 and 709 and corresponding logic circuitry within the clock data recovery circuit 705. As each of the edge comparators 707, 708 and 709 represents additional input capacitance and signal reception hardware, a deliberate determination to omit one or more of the edge comparators, and thus forego the phase error information provided by the comparator(s), effects a tradeoff between reduced signal path loading (and signal reception hardware) and transition detection rate. In a mesochronous system (i.e., clock or timing domains having same fundamental frequency but arbitrary phase relationship), a reduced transition detection rate may be tolerated if the resulting reduced phase error correction rate is sufficient to compensate for phase drift between the sampling clock signal and desired sampling instant. By contrast, in a plesiochronous system (clock or timing domains having a frequency difference up to a specified tolerance value expressed, for example, as a part-per-million (ppm) ratio to the frequency of one of the domains), reduced transition detection rate may be tolerated if the resulting reduced phase error correction rate is sufficient to compensate for a frequency difference up to the specified tolerance value.
Referring to the partial-response data-state transitions shown in FIG. 32, it can be seen that the zero-threshold comparator 709 of FIG. 28 has particularly high utility in terms of transitions detected per hardware footprint (or gate count) as the type (1) transitions detected by comparator 709 include both rising-edge and falling-edge transitions. By contrast, the α-threshold comparators 707 and 708 each detect transitions in only one direction and thus have lower utility. Accordingly, if one or more of the comparators 707, 708, 709 are to be omitted, one (or both) of the a-threshold comparators 707, 708 is a more likely candidate than the zero-threshold comparator 709. Further, because all low-going (i.e., 1-to-0) data-state transitions (i.e., changes in the state of the conveyed data value) will occur through either a type (1) transition (010) or a type (2) transition (110), all low-going transitions may be detected by a combination of the zero-threshold detector 709 and the +α comparator 707. Thus, because low-going transitions constitute half of all data-state transitions in a binary signaling system, even without the −α comparator 708, at least 50% of all data-state transitions will be detected and may be used for timing updates. Similarly, because all high-going transitions may be detected by a combination of the zero-threshold detector 709 and the −α comparator 708, at least 50% of all data-state transitions may be detected and used for timing updates even without the +a comparator 707. Note that more than 50% of the data-state transitions will be detected in a system lacking −α comparator 708 if at least some of the high-going transitions are type (1) transitions and, likewise, that more than 50% of the data-state transitions will be detected in a system lacking +α comparator 707 if at least some of the low-going transitions are type (1) transitions.
FIG. 34 illustrates an embodiment of a dual-mode partial response receiver 767 that operates in generally the same manner as the partial response receiver 700 of FIG. 28, except that the a comparator 708 is omitted, and the clock data recovery circuit 770 has been modified relative to counterpart 705 of FIG. 28 by omitting circuitry for processing the −α transitions. The partial response receiver 767 includes a dual-mode data receive/level sampling circuit 701 and adaptive module 703 that operate in generally the same manner as like-numbered circuits described in reference to FIG. 28. That is, when the mode select signal 712 (MSEL) selects a 4-PAM mode of operation, the data receive and level sampling circuit 701 samples incoming 4-PAM signals in response to a sampling clock signal 210 (SCLK) to generate an MSB and LSB per captured sample, and generates a data level error sample (EDLEV) that allows the adaptive module to determine the full scale difference between steady-state high and low signal levels. The +α, −α and zero threshold levels are then established by the adaptive module 703 at the Cα=2⁄3 full-scale, C−α=1⁄3 full-scale and C0=1⁄2 full-scale levels, respectively (other threshold levels may be used in alternative embodiments). When the mode select signal 712 selects a 2-PAM mode of operation, the data receive and level sampling circuit 701 generates data samples in response to the sampling clock signal 210 by selecting between partial-response comparators (i.e., the comparators receiving the ±α threshold levels) and supplies the selected samples to the adaptive module 703 in pairs to enable determination of which of partial response state is reflected by the error sample, EDLEV, generated by data level comparator (or data level comparators). The adaptive module 703 then adjusts the ±α threshold levels and the zero threshold level according to the incoming data signal levels determined by the data level comparator.
Turning to the clock recovery function, the edge comparators 707 and 709 capture transition samples TN−2(+α) and TN−2(0), respectively, from the incoming data signal, DN, in response to transitions of an edge clock signal 610 (ECLK) and provide the transition samples to the clock data recovery circuit 770. As in the embodiment of FIG. 28, the 4-PAM/partial response data samples captured by the data receive and level sampling circuit 701 (i.e., MSB/LSB in 4-PAM mode, D[N−2:N−3] in partial response mode) are also provided to the clock data recovery circuit 770. The clock data recovery circuit 770 selectively adjusts the phases of the edge clock signal 610 and sampling clock signal 210 based on the transition samples and data samples generally as described in reference to FIGS. 28, 29 and 30, except that type (3) transitions (i.e., transitions that cross the −α threshold at timing center T1 as shown in FIGS. 29 and 30) are not detected and thus not used to generate timing updates.
FIG. 35 illustrates an embodiment of the clock data recovery circuit 770 of FIG. 34 in greater detail. As shown, the clock data recovery circuit 770 includes a phase detector 771, accumulator 775 (ACCUM), interpolator 779 (INTERP) and reference loop 669 (REF LOOP) that operate generally as described in reference to FIGS. 26 and 28 to generate a sampling clock signal 210 and edge clock signal 610. More specifically, the phase detector 771 includes a transition detect circuit 772 (TD) to detect selected data-state transitions (i.e., type (1) transitions and type (2) transitions) and assert transition detect signal 732 in response, and a sample select circuit 773 (SS) to generate early signal 734 according to the states of transition samples that correspond to the detected data-state transitions. The early signal 734 is a phase error signal that indicates whether the edge clock signal transitioned early or late relative to a transition in the incoming data signal and therefore whether the sampling clock signal is early or late relative to a desired sampling time. The transition detect signal 732 and early signal 734 are supplied to count-enable and up/down inputs, respectively, of counter logic 774 which, in one embodiment, operates in generally the same manner as the early/late counter 663 and majority detector 665 of FIG. 26 to generate a phase error count (i.e., count of early/late indications) and, from the phase error count, a signed two-bit update signal 776 in which a magnitude bit (e.g., least significant bit) indicates whether a phase control value 778 (PCntl) maintained within accumulator 775 is to be adjusted and a sign bit that indicates whether the adjustment, if any, is to be an increment or decrement. The following table illustrates an exemplary encoding of the update signal 776:










TABLE 3







Update Signal
Update Value









X0
0: No Change



01
+1: Increase Phase Control Value



11
−1: Decrease Phase Control Value










In one embodiment, the accumulator 775 is implemented by a counter that receives the least significant bit of the update signal 776 at a count-enable input, and the most significant bit at an up/down input. By this operation, the phase control value 778 (i.e., count value) within the accumulator is adjusted up or down or held steady according to the update signal 776. The phase control value 778 is supplied to the interpolator 779 which, in response, interpolates between a selected pair of phase vectors 672 (i.e., provided by reference loop 669 in response to a reference clock signal 670) to generate sampling clock signal 210 and edge clock signal 610. Note that the accumulator 775 and interpolator 779 function in generally the manner described above in reference to interpolator 667 of FIG. 26. That is, accumulator 775 corresponds to logic within interpolator 667 for maintaining and adjusting a digital control word (i.e., shown as phase control value 778 in FIG. 35), and interpolator 779 corresponds the phase vector selection and interpolation logic within the interpolator 667.

Still referring to FIG. 34, it should be noted that the +α comparator 707 and corresponding circuitry within clock data recovery circuit 705 may be omitted instead of the -a comparator 708 and corresponding circuitry. In such an embodiment, type (1) and type (3) transitions are detected instead of type (1) and type (2) transitions. Also, while the partial response receiver 767 is described above in reference to FIG. 34 and below in reference to more detailed embodiments of component circuits of the receiver 767 as having support for both 4-PAM and partial-response operating modes, circuitry for supporting one or the other mode may be omitted in an alternative embodiment, thus establishing a dedicated partial-response receiver or dedicated 4-PAM receiver. Also, the partial response receiver may additionally or alternatively support a binary signaling (2-PAM) mode of operation in which a single decision threshold is used to distinguish between logic ‘1’ and logic ‘0’ data, and in which the partial-response circuitry (and/or 4-PAM circuitry, if present) is bypassed or disabled.
FIG. 36 illustrates embodiments of the transition detect circuit 772 and sample select circuit 773 of FIG. 35 in greater detail. As shown, the transition detect circuit 772 includes combinatorial logic circuit 7271, to generate type (1) 4-PAM and partial-response transition detect signals 7301A and 7301B, and combinatorial logic circuit 7272 to generate type (2) 4-PAM and partial-response transition detect signals 7302A and 7302B, but, due to the above-described omission of the −α comparator, does not include a combinatorial logic circuit to generate type (3) transition detect signals. As in the embodiment of FIG. 31, the data samples supplied to the combinatorial logic circuits 7271 and 7272 are depicted as having latency N, N−1 and N−2 (the N−2 sample may be obtained through an additional buffering stage, not shown), but may have any latency necessary to match the latency of the data samples output from the data receive and level sampling circuit 701 of FIG. 34.
Select circuits 7291 and 7292 are coupled to combinatorial logic circuits 7271 and 7272, respectively, and operate as described in reference to FIG. 31 to pass, as transition detect signals 7331 and 7332, either the 4-PAM transition detect signals 7301A, 7302A or partial-response transition detect signals 7301B, 7302B. The transition detect signals 7331 and 7332 are logically ORed in OR gate 736 to produce output transition detect signal 732, and are also supplied to AND gates 7411 and 7412, respectively, within sample select logic 773 to gate the zero-threshold transition sample, TN(0) and +α-threshold transition sample, TN(+α). By this arrangement, if a type (1) transition is detected, transition detect signal 7331 is asserted to enable AND gate 7411 to output the zero-threshold transition sample, and if a type (2) transition is detected, transition detect signal 7332 is asserted to enable AND gate 7412 to output the +α-threshold transition sample. The outputs of AND gates 7411 and 7412 are supplied to OR gate 744 which outputs an early/late signal 734 to accompany the transition detect signal 732.
As discussed above, the reduced phase error correction rate that results from omission of the −α comparator or +α comparator and corresponding clock recovery logic is generally tolerable in mesochronous systems, so long as the phase error correction rate is sufficient to compensate for phase drift between the sampling clock signal and desired sampling instant. In high-speed signaling systems in which phase drift occurs gradually (e.g., due to changes in temperature or supply voltage), even a worst-case 50% phase error correction rate (i.e., 50% of the total available data-state transitions are used to generate timing updates) is sufficient to maintain phase lock. By contrast, in a plesiochronous system, the reduction in phase error correction rate translates directly to a reduced frequency lock range. That is, the phase error correction rate establishes a ceiling for the frequency deviation that may be compensated by the clock data recovery circuit 770 so that omission of circuitry for detecting some data-state transitions generally reduces the frequency lock range. In plesiochronous signaling systems having a specified frequency deviation tolerance that falls within the compensation ceiling of reduced-hardware-set clock data recovery circuit 770 (i.e., worst-case 50% reduction of data-state transitions used for timing updates does not lower the compensation ceiling below the specified tolerance), the partial response receiver 767 of FIG. 34 (or above-described variants thereof) may be applied without change. By contrast, if the reduced phase error correction rate of clock data recovery circuit 770 lowers the compensation ceiling below the specified frequency deviation tolerance, the clock data recovery circuit 770 may, at least in a worst case, be unable to update the sampling clock phase quickly enough to track the phase drift caused by the frequency deviation. In one embodiment, this shortcoming is addressed by modifying the clock data recovery circuit 770 to include both phase and frequency error compensation circuitry.
FIG. 37 illustrates an embodiment of a second-order clock data recovery circuit 780 that includes dual compensation paths to correct both phase and frequency errors. As shown, the clock data recovery circuit 780 includes a phase detector 771 that operates generally as described in reference to FIGS. 35 and 36 to generate an update signal 776 that indicates whether to advance, leave unchanged or retard (−1, 0, +1) the phase of a sampling clock signal. The update signal 776 is supplied to a phase-error compensation path formed by feed-forward gain circuit 781 to generate a phase-error compensation signal 782, and is also supplied to a frequency-error compensation path formed by an integration gain circuit 783 and a frequency-error accumulator 785 that cooperate to generate a frequency-error compensation signal 786 (i.e., a frequency difference value that indicates an estimation or measure of a difference in frequency between the reference clock signal (e.g., signal 670 of FIG. 35) and a signal used to time transmission of the incoming data signal, DN). In one embodiment, one or both of the feed-forward gain and integration gain applied by the feed-forward gain circuit 781 and integration gain circuit 783, respectively, are established by configuration register settings (e.g., established through run-time or production-time programming of volatile or non-volatile storage elements), with the integration gain generally being substantially smaller than the feed-forward gain. For example, in one embodiment, the feed-forward gain circuit 781 is a digital multiplier that scales the update signal 776 by a power-of-two scaling factor that ranges from 20 to 27 (i.e., 1 to 128, though a larger or smaller range of scaling factors may be used in alternative embodiments) and outputs a signed eight-bit value as the phase-error compensation signal 782. For example, in the x4 scaling factor example shown in FIG. 37, +1 (0000 0001b, where ‘b’ denotes binary notation) is scaled to +4 (0000 0100b), and −1 (1111 1111b) is scaled to −4 (1111 1100b).
In one embodiment, the integration gain circuit 783 is implemented by a digital multiplier that scales the update signal 776 by a fixed-point power-of-two scaling factor that ranges from 2−6 to 21 (i.e., 1/64 to 2, though a larger or smaller range of scaling factors may be used) and outputs a signed eight-bit fixed-point frequency error update signal 784. Thus, in the x1⁄8 scaling factor example shown in FIG. 37, +1 (0000 0001b) is scaled to +1⁄8 (00.001000b) and −1 (1111 1111b) is scaled to −1⁄8 (11.111000b).
In one embodiment, the frequency-error accumulator 785 is triggered by a transition detect signal (e.g., signal 732 of FIG. 36 or a signal derived therefrom) to increment, decrement or leave unchanged, according to frequency-error update signal 784, an accumulated value that constitutes the frequency-error compensation signal 786. By this arrangement, if a frequency deviation exists between a reference clock signal used to generate the phase vectors that are interpolated to produce the sampling clock signal and edge clock signal, and a transmit clock used to time transmission of the incoming data signal, the resulting sequence of predominantly same-sign update signals 776 (i.e., predominantly positive or predominantly negative according to the lead/lag relationship between the two clock signals) will accumulate within phase error accumulator 785 until such time as the resulting frequency-error compensation signal 786 reaches a value sufficient to compensate for the frequency deviation, as discussed below
Still referring to FIG. 37, the frequency-error compensation signal 786 and phase-error compensation signal are summed in summing circuit 787 to generate a composite compensation signal 788 that is provided, in turn, to accumulator 789 to update the phase control value 778. In one embodiment, the summing circuit 787 performs a fixed-point summing operation to generate a fixed-point sum having sufficient precision to include the integer field of signal 782 and the fractional field of signal 784, then truncates the fractional field (e.g., by not outputting some number of the least significant bits of the sum) to generate a final N-bit composite compensation signal 788. In one embodiment, for example the composite compensation signal 788 is an eight-bit value, though a higher or lower resolution value may be generated in alternative embodiments.
During operation within a plesiochronous system, accumulated phase errors that result from a frequency deviation between the clock signal used to time data signal transmission and the reference clock signal (or frequency multiple thereof) used to generate phase vectors that are mixed to generate the edge and sample clock signals will result in accumulation of a countervailing frequency error compensation value within accumulator 785, while transient phase errors are compensated by the relatively high-gain phase error compensation path. As an example, if the feed-forward gain and integration gain are programmed (or hardwired) to effect a x4 scaling factor (−4, 0, +4) and x1⁄8 scaling factor (−1⁄8, 0, +1⁄8), respectively, as shown in FIG. 37, and the reference clock frequency (or multiple thereof) is higher than the transmit clock frequency by a frequency error, δ, then the phase detector 771 will generate a sequence of update signals 776 (i.e., +1) predominantly indicating that the phase of the edge clock signal (and therefore the sampling clock signal) leads the desired sampling instant and thus that the phase control value 778 should be adjusted to delay the phase of the sampling clock signal and edge clock signal (note that the phase control value 778 may be provided, as shown in FIG. 35, to an interpolator 779 that responds by selecting a pair of phase vectors 672 from a reference loop 669). The x1⁄8 scale factor applied by the integration gain circuit 783 will result in relatively gradual accumulation of a frequency-error compensation value 786 until the frequency error compensation value rises to a point that corresponds to the frequency error. At that point, the frequency error compensation component of the updates to the phase control value should substantially match the phase updates needed to track the steady-state frequency error, with the higher-gain phase error compensation component (i.e., 782) of the composite compensation signal 788 being applied to compensate for more transient phase errors. As discussed above, other gain settings and/or ranges of gain settings may be used within the feed-forward gain circuit 781 and integration gain circuit 783 in different applications or embodiments, and higher or lower resolution values may be used to convey the phase-error compensation signal 782, frequency-error compensation signal 784, and composite compensation signal 788.
FIG. 38 illustrates the increased lock range achieved through addition of the frequency-error compensation circuitry within the second-order clock data recovery circuit 780 of FIG. 37. That is, without the frequency-error compensation circuitry, frequency error correction is limited by the maximum phase error correction rate (i.e., product of rate at which update signal 776 is generated and scaling factor applied by gain circuit 781) to a first-order frequency-locking range 790 (i.e., from +FreqA/2 to −FreqA/2). By contrast, the addition of the frequency-error compensation circuitry generally will enable a wider, second-order frequency locking range 792 (i.e., from +FreqB/2 to −FreqB/2). As shown, an increased frequency locking range may be present regardless of the percentage of the data-state transitions that are used as timing updates so that, even in a signal receiver having hardware to detect type (1), type (2) and type (3) data-state transitions (e.g., as in FIG. 28), or even non-data-state transitions as in the ‘1’-crossing and ‘−1’-crossing transitions described in reference to FIG. 32, the second-order clock data recovery circuit 770 of FIG. 37 may be applied to increase the range of frequencies over which phase lock may be maintained. Note that, in a system having a substantially steady-state frequency difference between the reference clock (or frequency multiple thereof) and the clock signal used to time data signal transmission, the frequency-error compensation circuitry may enable phase locking up to range 792 even when the percentage of edges that become timing updates is relatively low, so long as at least a threshold level of updates is received.
Extending the Partial Response Compensation to include Additional Data History
Thus far, partial response receivers have been described in terms of a bimodal distribution based on the current symbol, DN, and the preceding symbol, DN−1. In alternative embodiments, partial responses to any number of preceding symbols may be accounted for in the generation of data samples. FIG. 39, for example, illustrates a distribution 795 of data-plus-partial-response signal levels in a system in which the two most recently received symbols are the primary source of residual channel response (i.e., the channel memory includes a partial response, α, to the immediately preceding symbol, DN−1, and a partial response, β, to the twice-removed preceding symbol, DN−2). For purposes of simplicity, the signal level constellation shown in FIG. 39 assumes a substantially equal distribution of the eight partial response signal levels: 1+α+β, 1+α−β, 1−α+β, 1−α−β, −1+α+β, −1+α−β, −1−α+β, and −1−α−β. Other signal distributions may result depending upon the channel characteristics. As shown, the constellation may be viewed as defining four signal ranges 7971-7974, each range being centered about one of the four possible partial response levels, α+β, α−β, −α+β, and −α−β.
FIG. 40 illustrates a partial response receiver 800 that operates in accordance with the partial response states shown in FIG. 39. Four comparators 8011, 8012, 8013 and 8014 are provided to compare the signal level of an incoming symbol, DN, against the four partial response threshold levels α+β, α−β, −+β and −α−β, respectively. The outputs of each of the comparators 801 are stored in a first stage of storage circuits 8021-8024 (e.g., in response to a sampling clock signal, not shown), with the sample values that correspond to the +α threshold levels (i.e., DN−1(α+β) and DN−1(α−β)) being supplied to a first select circuit 810 and the sample values that correspond to the −α threshold levels (i.e., DN−1(−α+β) and DN−1(−α−β)) being supplied to a second select circuit 812. Each of the first and second select circuits 810 and 812 selects between its respective pair of input samples according to the state of a previously resolved sample value, DN−3, stored in storage circuit 820. More specifically, if the resolved sample value, DN−3, is a ‘1’, then β, the partial response to DN−3, is a positive value and the select circuits 810 and 812 select the sample values DN−1(α+β) and DN−1(−α+β), respectively, that correspond to the positive P state. If the DN−3 sample is a logic ‘0’ value, then β is a negative value and the select circuits 810 and 812 select the sample values DN−1(α−β) and DN−1(−α−β) that correspond to the negative β state. The DN−1 sample values selected by the select circuits 810 and 812 correspond to the +α and −α partial response states, respectively, and are stored in storage circuits 814 and 816 to provide DN−2 sample values DN−2(α) and DN−2(−αa). The DN−2(α) and DN−2(−α) samples are output from the storage circuits 814 and 816 to respective inputs of select circuit 818. The state of the DN−3 sample value indicates the sign of the partial response contribution in the DN−2 signal. That is, if DN−3=1, α is positive, and if DN−3=0, α is negative. Accordingly, the DN−3 sample value is supplied to a select input of select circuit 818 to select either DN−2(+α) or DN−2(−α). Thus, the partial response receiver 800 of FIG. 40 simultaneously compares the incoming data signal against four different partial response thresholds, then selects one of the four sample values to be the output sample value (DN−3) based on the previously resolved state of the α and β partial response components. Partial response components from more than two previously received symbols may be accommodated in a similar manner by increasing the number of comparators to match the number of partial response levels to be resolved, and then selecting the desired partial response sample on the basis of the partial response components indicated by a previously resolved sample value.
FIG. 41 illustrates a partial response receiver 840 according to another embodiment of the invention. The partial response receiver 840 includes a partial response receive circuit 800, level sampler 841 and adaptive module 850. The partial response receive circuit 800 operates generally as described in reference to FIG. 40 to generate sample value DN−3, which is supplied to the adaptive module 850. The level sampler 841 operates in generally the same manner as the level sampling circuit of FIG. 14, except that eight comparators 8421-8428 are provided to error samples for each of the eight possible partial response levels depicted in FIG. 39 (i.e., E000, E001, . . . , E110, E111). The level sampler additionally includes storage circuits 844 to latency-align the error samples generated by comparators 842 with the data sample D[N−3] generated by the partial response receive circuit 800. The adaptive module 850 operates similarly to the adaptive module described in reference to FIGS. 14-16, except that control values for each of the eight partial response threshold levels applied within comparators 842 are updated in response to reception of a corresponding one of the eight possible data patterns for sample values D[N−3 N−5] (note that data samples DN−4 and DN−5 may be generated by buffering data samples received from the partial response receive circuit 800 within the adaptive module 850). That is, when D[N−3:N−5]=111, control value C1+α+β is incremented or decremented according to the state of the error sample, E111, generated by comparator 8428; when D[N−3:N−5]=110, C1+α−β is incremented or decremented according to the state of error sample E110, and so forth to error sample E000 which is used to update C−1−α−β when D[N−3:N−5]=000.
In one embodiment, each of the four threshold control values supplied to the partial response receive circuit 800 (i.e., Cα+β, Cα−β, C−α+β and C−α−β) are generated by averaging respective pairs of the control values output to the level sampler 841. That is:

    
    
        Cα+β=(C1+α+β+C−1+α+β)/2;
        Cα−β=(C1+α−β+C−1+α−β)/2;
        C−α+β=(C1−α+β+C−1−α+β)/2; and
        C−α−β=(C1−α−β+C−1−α−β)/2
    
    


Alternatively, the threshold control values supplied to the partial response receive circuit 800 may be generated by halving the difference between respective pairs of the control values output to the level sampler 841 (e.g., Cα+β=(C1+α+β−C1−−β)/2).
Partial Response, Multi-PAM Receiver
The partial response operation described above in the context of binary signaling may be extended to multi-PAM receivers. FIG. 42, for example, illustrates a constellation of possible signal levels in a 4-PAM signaling system. More specifically, assuming that a given data symbol has one of the four levels +3, +1, −1 or −3 centered about a nominal zero value, and that the primary partial response is due to the immediately preceding symbol, then sixteen partial response states become possible. That is, a symbol nominally transmitted at level +3 may have any of the states 3+3α, 3+α, 3−α, or 3−3α when observed at the receiver, depending on whether the signal level for the preceding symbol was +3, +1, −1 or −3. Similarly, a symbol nominally transmitted at levels +1, −1 or −3 may have any of the four states that correspond to the additive or subtractive effect of the preceding symbol level. As shown in FIG. 42, by grouping the possible partial response states according to the signal level of the preceding symbol, it can be seen that if the preceding symbol was a +3, the subsequently transmitted symbol will have a signal level that is offset by 3α and therefore that ranges from −3+3α to +3+3α. Similarly, if the preceding symbol was a +1, the subsequently transmitted symbol will have a signal level that is offset by 1α, and so forth for preceding symbols at −1 (offset =−1α) and −3 (offset =−3α). Accordingly, by providing four 4-PAM receive circuits each having thresholds offset by respective one of the 3α, +α, −α and −3α partial response levels, a partial response mode of operation may be enabled within a 4-PAM receiver.
FIG. 43 illustrates a 4-PAM partial response receiver 875 according to an embodiment of the invention. The receiver 875 includes four 4-PAM receive circuits 8771-8774 (i.e., each capable of resolving the signal level of an incoming symbol into one of four possible two-bit combinations) each having a threshold level that is offset according to one of the four partial response levels (3α, α, −α, or −3α). In the case of receive circuit 8774, for example, the 3α offset (corresponding to a prior symbol level of 10) is applied to each of the internal levels generated to resolve the 4-PAM signal. That is, instead of comparing the incoming signal with levels of −2, 0, and 2, the incoming signal is compared with −2+3α, 3α and 2+3a (i.e., the threshold values between the 3+3α, 1+3α, −1+3α, −3+3α constellation depicted in FIG. 42). Similarly, 4-PAM receive circuit 8773 compares the incoming signal with thresholds offset by α (i.e., −2+α, α and 2+α), comparator 8772 compares the incoming signal with thresholds offset by −α (i.e., −2−α, −α, and 2−α) and comparator 8771 compares the incoming signal with thresholds offset by −3α (i.e., −2−3α, −3α and 2−3α). By this arrangement, the incoming signal is resolved into four 2-bit sample values according to each of the four possible partial responses to the preceding symbol. The preceding symbol, MSB/LSB[N−1], having been selected according to the state of MSB/LSB[N−2], is stored in storage element 881 and applied to the select input of select circuit 879 to select the one of the four sample values generated in accordance with the incoming signal level. While the partial response operation has been described in terms of a 4-PAM receiver that enables partial response selection based on a single preceding symbol, the circuits and operation described may be extended to other PAM levels (e.g., 8-PAM, 10-PAM, etc.) and/or to include the partial response to additional preceding bits.
FIG. 44 illustrates an input circuit 885 that includes multiple partial response receivers 8871-887M according to an embodiment of the invention. Each of the partial response receivers 8871-887M is coupled to a respective one of signal lines 8831-883M to receive a corresponding one of data signals D1-DM. In one embodiment, each of the data signals D1-DM is a serial stream of data values (e.g., data eyes) that is sampled within the corresponding partial response receiver 887 to generate a corresponding one of sample values, S1-SM. The sampled values S1-SM are delayed relative to the corresponding data values by one or more symbol times, i, according to the latency introduced by the partial response receiver 887. Thus, during the symbol time in which data value DM[N] is valid at the input to partial response receiver 887M, the partial response receiver outputs sample value SM[N−i]. Partial response receivers 8871-887M−1 similarly output respective sample values S1[N−i]-SM−1[N−i] during the symbol times in which data values D1[N]-DM−1[N] are valid.
In one embodiment, each of the signal lines 8931-893M forms a unidirectional or bidirectional point-to-point signaling link between a first IC device that includes input circuit 885 and a second IC device. In the case of a bi-directional link, the first IC device may additionally include transmit circuitry coupled to the signal lines 893, and the second IC device may include a counterpart input/output circuitry having an input circuit similar to input circuit 885. The first and second IC devices may be in separate IC packages coupled to a common substrate (e.g., circuit board) or coupled to different substrates (e.g., coupled to respective daughterboards with signal paths 8931-893M formed in part by signal traces on the daughterboards and on a backplane, or the first IC device coupled to a daughterboard and the second IC device coupled to a motherboard). Alternatively, the first and second IC devices may be included within the same IC package (e.g., a multi-chip module, chip-stack package, paper-thin package or combination of integrated circuit dice within a package). In another embodiment, each of the signal lines 8931-893M forms a unidirectional or bidirectional multi-drop signaling link coupled to three or more IC devices, with the IC devices or any subset thereof being disposed on the same or different substrates, and within the same or different IC packages.
In either the point-to-point or multi-drop embodiments, the signal lines 8931-893M may constitute a parallel signaling path 894 for transmission of multi-bit data values. For example, each of the sample values S1-SM for a given symbol time (i.e., corresponding to data values D1-DM recovered from path 894) may represent a unified digital value (in which SM is a most significant bit (MSB) and sample S1 is a least significant bit (LSB), M being any integer value greater than one. Also, subsets of bits within the sample values S1-SM may constitute respective unified digital values (e.g., S1-SX being a first value ordered from LSB to MSB, SX+1-SY being a second data value ordered from LSB to MSB, and so forth to SZ+1 to SM which constitute a last data value ordered from LSB to MSB). Further, any number of successively received samples (i.e., corresponding to a packetized transmission of values) may form a unified digital value. For example, S1[N−i]-SM[N−i], S1[N−i−1]-SM[N−i−1], . . . , S1[N−i−Q]-SM[N−i−Q] may form a unified digital value having a total of Q×M bits (Q being any integer value greater than one) in which one bit is an LSB and one bit is an MSB. Alternatively, a set of successively received samples may form multiple unified digitized values, as when bits of a first digitized value are generated in successive symbol times by partial response receivers 8871-887X, bits of a second digitized value are generated in successive symbol times by partial response receivers 887X+1-887Y, and so forth.
In the embodiment of FIG. 44, each partial response receiver 887 includes a partial response receive circuit 888, level sampler 889, adaptive module 890, edge sampler 891 and clock data recovery circuit 892. The partial response receive circuit 888 may be a multi-mode receive circuit as described above (i.e., capable of being switched between a multi-level signaling mode and a partial-response mode), or may be dedicated to partial-response operation. Also, the partial response receive circuit may operate on incoming binary or multi-level signals (e.g., 2-PAM, 4-PAM, 8-PAM, 10-PAM, etc.) having any data rate (e.g., single data rate, double data rate, quad data rate, octal data rate, decade data rate, etc.). Thus, the partial response receive circuit 888 may be implemented by any of the partial response receive circuit embodiments described herein. Similarly, the level sampler 889 and adaptive module 890 may be implemented by any of the level sampler and adaptive module embodiments described herein. For example, though depicted as outputting a single error sample, EDLEV, the level sampler 889 may output multiple error samples to the adaptive module 890, and the adaptive module 890 may output any number of control values to the level sampler 889, partial response receive circuit 888 and edge sampler 891 (e.g., as shown in FIGS. 14, 28 and 36) in addition to or instead of CDLEV, Cα, /Cα and C0. Also, though depicted in FIG. 44 as recovering a sample clock signal (SCLK) and edge clock signal (ECLK), the edge sampler 891 and clock data recovery circuit 892 may recover any number of clock signals as described above in reference to FIGS. 24 and 26 (e.g., for use in multi-data rate embodiments). Further, the edge sampler 891 and clock data recovery circuit 892 may recover phase information (i.e., for adjusting the phase of the recovered clock signals) from any or all transitions of the incoming data signal 893 as described above. The edge sampler 891 and clock data recovery circuit 892 may be omitted from the partial response receiver 887 in an embodiment in which clock signals, strobe signals or other timing signals are provided by another source, such as an external or internal clock generator, or separate clock recovery circuit.
FIG. 45 illustrates an input circuit 895 according to an alternative embodiment of the invention. The input circuit 895 is similar to the input circuit 885 of FIG. 44 (and may be implemented in all the alternative embodiments described in reference to FIG. 44), except that the circuitry used to generate partial response thresholds (or representative control values) and sampling clock signals is shared among multiple partial response receive circuits 8881-888M. That is, a single level sampler 889 and corresponding adaptive module 890 are used to generate control values Cα, /Cα and C0 (and additional or different threshold control values in multi-level signaling embodiments and embodiments that do not include clock recovery circuitry) that are supplied to each of the partial response receive circuits 8881-888M, and a single edge sampler 891 and corresponding clock data recovery circuit 892 are used to generate the sampling clock signal (SCLK) that is supplied to each of the partial response receive circuits 8881-888M. Multiple sampling clock signals may be generated and shared among the partial response receive circuits 8881-888M in multi-data rate embodiments. By sharing the circuitry for generating control thresholds and/or the circuitry for generating sampling clock signals, the amount of circuitry within the input circuit 895 is substantially reduced relative to input circuit 885, reducing production and operational cost of the host integrated circuit device (i.e., due to reduced die area consumption, layout complexity, test and verification time, power consumption, etc.). Note that, in an embodiment in which the sampling clock signal is provided by circuitry other than clock data recovery circuitry (e.g., external clock source, internal clock generated), the edge sampler 891 and clock data recovery circuit 892 may be omitted. Alternatively, programmable selection of the clock source may be used to select either the recovered sampling clock (i.e., recovered by operation of the edge sampler 891 and clock data recovery circuit 892) or another clock source to provide a sampling clock signal to the partial response receive circuits 8881-888M. As in the embodiment of FIG. 44, the signal lines 8931-893M may be used to deliver distinct serial transmissions, or transmission of related groups of bits (e.g., the M bits received during a given symbol time representing one or more multi-bit digital values) as, for example, in the case of a parallel bus or any other signaling system in which the threshold control values and/or timing control signals are expected to be substantially similar (e.g., substantially same thresholds and/or clock phases) across multiple signaling paths. Also, while a single level sampler 889 and corresponding adaptive module 890 are depicted in FIG. 45 as generating threshold control values Cα, /Cα and C0 for each of the partial response receive circuits 8881-888M, in an alternative embodiment, multiple level sampler/adaptive module pairs may be used to generate threshold control values for respective subsets of the partial response receive circuits 8881-888M. Respective edge sampler/clock data recovery circuit pairs may similarly be used to generate sampling clock signals for corresponding subsets of partial response receive circuits 8881-888M.
Still referring to FIG. 45, the partial response receive circuits 8881-888M may be implemented by any of the embodiments described herein including, without limitation, the embodiments described as described in reference to FIGS. 17-19. Also, in embodiments in which a preamplifier (e.g., preamplifier 401 of FIG. 17) or offset control circuit (e.g., offset control circuit 440 of FIG. 19) is used to adjust the effective threshold of a differential comparator above or below a common mode, such preamplifier or offset control circuit may be shared among multiple partial response receive circuits 888, thereby reducing the circuitry within the partial response receive circuits 8881-888M to that of a sampling circuit (e.g., sampler 425 of FIG. 17 or sampler 452 o FIG. 19). Respective preamplifiers (or offset control circuits) may also be shared among subsets of the partial response receive circuits 8881-888M.
Transmit-Side Equalization in System with Partial Response Receiver
FIG. 46 illustrates a signaling system 950 having a transmit device 951 and receive device 953 coupled to one another via a signaling path 122. The transmit device 951 includes an equalizing transmit circuit 957 and tap control logic 955, and the receive device 953 includes a partial response receive circuit (which may, for example, be a multi-mode circuit or any other of the partial response receive circuits disclosed herein), level sampler 973 and adaptive module 975. Both the transmit device 951 and receive device 953 may include numerous other circuits not shown in FIG. 46 (e.g., application logic, additional transmit circuits and/or receive circuits, etc.). The equalizing transmit circuit 957 includes a number of output drivers 9610-961N−1 to drive a symbol onto signaling path 122 in response to a transmit timing signal (not shown) and in accordance with a set of weighting values W0-WN−1 and the state of data values D0-DN−1. Each of the data values D0-D−(N−1) is stored within a shift register 959 (or similar storage circuit) and includes a number of constituent bits in accordance to the number of bits encoded into each symbol transmission on the signaling path 102. For example, in a 4-PAM system, each of the data values, D0-D(N−1), includes two constituent bits. More generally, in a M-PAM system, each of the data values includes log2(M) constituent bits. After each symbol transmission, the contents of the shift register 959 are shifted forward so that a new data value is shifted into position D0, and the data value at position D−(N−1) is overwritten by the data value previously at position D−(N−2).
The weighting values W0-WN−1 are generated by the tap control logic 955 and are used to establish the signal drive strength of each of the output drivers 961. In one embodiment, the output driver 9610 drives the symbol to be transmitted during a given symbol time in accordance with weighting value W0, and the output drivers 9611-961N−1 constitute a set of post-tap drivers for equalizing the output signal according to the post-tap data values stored within positions D−1−D−(N−1) of the shift register 959 and the weighting values W1-WN−1. Though not shown in FIG. 46, pre-tap output drivers may also be provided to equalize the output signal according to pre-tap data values (and pre-tap weighting values), and yet other output drivers may be provided to cancel cross-talk from neighboring signal lines. Also, one or more of the output drivers 961 may be dynamically or statically allocated between pre-tap equalization, post-tap equalization and cross-talk cancellation functions, for example, through configuration register settings or externally received configuration control signals.
The partial response receive circuit 971 includes R compare circuits to generate respective partial response values according to the number of expected partial response signal levels. For example, in a system in which the least-latent symbol (i.e., the most recently received symbol, N−1−i, relative to incoming symbol N−i) is the only expected contributor to the partial response, two compare circuits are provided to generate partial response values according to the two possible states of least-latent symbol (i.e., R=2). In a system in which the K most recently received symbols are expected to contribute to the partial response, 2K compare circuits are provided to generate respective data samples based on comparisons with the K partial response threshold levels (CPR) generated by the adaptive module 975.
In one embodiment, the tap control logic 955 of transmit device 951 generates the weighting values W0-WN−1 in accordance with the number of symbols desired to contribute to the partial response observed at the receive device 953. Referring to FIG. 47, for example, in a system in which the partial response is to be limited to the least latent symbol, D−1 (i.e., K=i), the tap control logic 955 generates weighting values W0-WN−1 to equalize the dispersion-type ISI produced by symbol transmissions after D−1 and prior to D0. That is, referring to the raw pulse response shown in FIG. 47, the partial response of the signaling path 122 to symbols D+1, and D−2 to D−(N−1) is equalized by appropriate settings of the weighting values applied to a pre-tap output driver (not shown in FIG. 46) and post-tap output drivers 9612-961N−1. By this arrangement, the equalized signal observed by the receive device 953 (i.e., equalized for partial response as depicted in FIG. 47) includes a contribution from the symbol to be received, D0, and a partial response to the immediately preceding symbol, D−1, with the partial response to all other transmissions being attenuated (e.g., to a negligible or substantially reduced level). In alternative embodiments, the tap control logic 955 may enable partial response to one or more additional symbols to remain in the signal observed by the receive device 953 depending on the desired number of partial response contributors. Also, in a multi-mode circuit in which a partial response receive circuit may optionally be operated in a non-partial response mode, the tap control logic 955 may generate weighting values W0-WN−1 as necessary to cancel (or reduce) the partial response to post-tap and pre-tap data values.
Still referring to FIG. 46, the level sampler 973 within the receive device 953 operates generally as described above (e.g., in reference to the various embodiments described in reference to FIGS. 14-15 and 20-21) to compare the incoming signal with a data level threshold and generate error samples (EDLEV) that are used to adjust the data level threshold(s), CDLEV, and the partial response thresholds, CPR. As discussed above, the data level threshold and/or the partial response thresholds, CPR, may be digital values that are used to establish the desired threshold levels within compare circuits of the partial response receive circuit 971 and the level sampler 973, or any other types of control values (e.g., analog voltage and/or current levels that are themselves the threshold levels).
As discussed above in reference to FIG. 15, the adaptive module may include filtering circuitry to filter the error samples generated by the level sampler 973 such that the threshold levels generated by the adaptive module are updated based on multiple error samples, rather than on a sample-by-sample basis. For example, in one embodiment, the adaptive module includes a finite impulse response (FIR) filter to update the threshold levels based on a succession of error samples applied to the filter. Alternatively, the adaptive module may include an infinite impulse response filter (IIR) or any other type of filter for filtering the error samples.
In one embodiment, the data level error samples, EDLEV, generated by the level sampler 973 are returned to the transmit device 951 via a back channel 968 (e.g., out-of-band signaling, passage via an intermediary device such as the controller 141 of FIG. 3, or other communication path that does not consume otherwise usable bandwidth on the signaling path 122). The error samples are received within the tap control logic 955 and used to adjust the tap weights, W0-WN−1, as necessary to reduce ISI (or other sources of distortion) resulting from transmission of symbols other than symbols desired to contribute to the partial response. Referring to FIG. 48, for example, after the data level threshold generated by the adaptive module 975 converges to a nominal data level 985 (DLEVNOM), further jitter detected in the signal data level 986 may be treated as residual ISI due resulting from transmission of symbols other than symbols desired to contribute to the partial response. The tap control logic may increase and decrease the weights of the post-tap output drivers and/or pre-tap output drivers as necessary to reduce the residual ISI. In alternative embodiments, updates to the tap weights themselves (e.g., values to be added and/or subtracted from weights W0-WN−1 or a subset thereof) may be determined within the receive device (or another device such as controller 141 of FIG. 3) and provided to the transmit device for application within the tap control logic 955. In yet other embodiments, one or more replacement tap weights may be determined within the receive device (or other device such as controller 141 of FIG. 3) and provided to the transmit device for application in place of corresponding tap weights W0-WN−1.
It should be noted that the various circuits disclosed herein may be described using computer aided design tools and expressed (or represented), as data and/or instructions embodied in various computer-readable media, in terms of their behavioral, register transfer, logic component, transistor, layout geometries, and/or other characteristics. Formats of files and other objects in which such circuit expressions may be implemented include, but are not limited to, formats supporting behavioral languages such as C, Verilog, and HLDL, formats supporting register level description languages like RTL, and formats supporting geometry description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES and any other suitable formats and languages. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media) and carrier waves that may be used to transfer such formatted data and/or instructions through wireless, optical, or wired signaling media or any combination thereof. Examples of transfers of such formatted data and/or instructions by carrier waves include, but are not limited to, transfers (uploads, downloads, e-mail, etc.) over the Internet and/or other computer networks via one or more data transfer protocols (e.g., HTTP, FTP, SMTP, etc.).
When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.
In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘ <signal name>’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. The term “exemplary” is used to express an example, not a preference or requirement.
Various aspects of the subject-matter described herein are set out non-exhaustively in the following numbered clauses:
1. A method of operation within an integrated circuit device, the method comprising:


    
    
        comparing a data signal with a first threshold level and with a second threshold level to generate a first edge sample and a second edge sample, respectively;
        selecting one of the first and second edge samples to be a phase error signal that indicates whether a transition of a first clock signal is early or late relative to a desired transition time;
        adjusting a frequency difference value based, at least in part, on the phase error signal, the frequency difference value indicating a difference in frequency between a clock signal used to generate the first clock signal and a clock signal used to time transmission of the data signal; and
        adjusting a phase of the first clock signal based, at least in part, on the frequency difference value.

2. The method of clause 1 further comprising sampling a binary input signal to generate a set of data samples, and wherein selecting one of the first and second edge samples to be a phase error signal comprises selecting one of the first and second edge samples based on the set of data samples.

3. The method of clause 1 further comprising sampling a binary input signal to generate a set of data samples, and wherein selecting one of the first and second edge samples to be a phase error signal comprises selecting the first edge sample to be the phase error signal if the set of data samples matches a first data pattern and selecting the second edge sample to be the phase error signal if the set of data samples matches a second data pattern.

4. The method of clause 1 wherein adjusting a frequency difference value based, at least in part, on the phase error signal comprises:

        increasing or decreasing a phase error count according to a logic state of the phase error signal; and
        and increasing or decreasing the frequency difference value according to whether the phase error count is positive or negative.

5. The method of clause 1 wherein adjusting a phase of the first clock signal based, at least in part, on the frequency difference value comprises adding the frequency difference value to a phase control value that is used to control the phase of the first clock signal.

6. The method of clause 5 further comprising:

        increasing or decreasing a phase error count according to a logic state of the phase error signal; and
        adding a value that corresponds to the phase error count to the phase control value.

7. The method of clause 6 wherein adding a value that corresponds to the phase error count to the phase control value comprises multiplying the phase error count by a scaling factor to generate the value that corresponds to the phase error count.

8. The method of clause 6 wherein adding a value that corresponds to the phase error count to the phase control value and adding the frequency difference value to a phase control value comprises adding the frequency difference value to the value that corresponds to the phase error count to generate a composite value and then adding the composite value to the phase control value.

9. The method of clause 1 wherein adjusting a phase of the first clock signal based, at least in part, on the frequency difference value comprises:

        increasing or decreasing a phase control based, at least in part, on the frequency difference value; and
        interpolating between a pair of phase-shifted clock signals in accordance with the phase control value to generate the first clock signal.

10. An integrated circuit device comprising:

        an edge sampling circuit to generate a first edge sample in either a first logic state or a second logic state according to whether a data signal exceeds a first threshold level, and to generate a second edge sample in either the first logic state or the second logic state according to whether the data signal exceeds a second threshold level;
        a selector circuit to select one of the first and second edge samples to be a phase error signal that indicates whether a transition of a first clock signal is early or late relative to a desired transition time; and
        circuitry to adjust a frequency difference value based, at least in part, on the phase error signal, the frequency difference value indicating a difference in frequency between a clock signal used to generate the first clock signal and a clock signal used to time transmission of the data signal; and
        circuitry to adjust a phase of the first clock signal based, at least in part, on the frequency difference value.

11. The integrated circuit device of clause 10 further comprising a data sampling circuit to generate a set of data samples from the data signal, and wherein the selector circuit comprises logic circuitry to select the one of the first and second edge samples to be the phase error signal based on the set of data samples.

12. The integrated circuit device of clause 10 wherein the logic circuitry comprises circuitry to select the first edge sample to be the phase error signal if the set of data samples matches a first data pattern and to select the second edge sample to be the phase error signal if the set of data samples matches a second data pattern.

13. The integrated circuit device of clause 10 wherein the circuitry to adjust a frequency difference value based, at least in part, on the phase error signal comprises a counter to increment or decrement a phase error count according to a logic state of the phase error signal and an accumulator circuit to increase or decrease the frequency difference value according to whether the phase error count is positive or negative.

14. The integrated circuit device of clause 13 further comprising a gain circuit to generate a scaled value to be added to the frequency difference value within the accumulator, the scaled value being a positive or negative value according to whether the phase error count is positive or negative and having a magnitude according to a scaling factor.

15. The integrated circuit device of clause 14 further comprising a configuration circuit to store a value that corresponds to the scaling factor in response to an instruction from a source external to the integrated circuit device.

16. The integrated circuit device of clause 10 wherein the circuitry to adjust the phase of the first clock signal based, at least in part on the frequency difference value, comprises circuitry to add the frequency difference value to a phase control value that is used to control the phase of the first clock signal.

17. The integrated circuit device of clause 16 wherein the circuitry to adjust the phase of the first clock signal further comprises circuitry to generate a plurality of phase vectors that are phase-shifted relative to one another, and an interpolation circuit to interpolate between a selected pair of the reference phase vectors in accordance with the phase control value, .

18. The integrated circuit device of clause 16 wherein the circuitry to adjust a frequency difference value based, at least in part, on the phase error signal comprises a counter to increment or decrement a phase error count according to a logic state of the phase error signal, and wherein the integrated circuit device further comprises circuitry to add a value that corresponds to the phase error count to the phase control value.

19. The integrated circuit device of clause 18 wherein the circuitry to add a value that corresponds to the phase error count to the phase control value comprises a gain circuit to multiply the phase error count by a scaling factor to generate the value that corresponds to the phase error count.

20. The integrated circuit device of clause 19 further comprising a configuration circuit to store a value that corresponds to the scaling factor in response to an instruction from an external source.

21. An integrated circuit device comprising:

        means for generating a first edge sample in either a first logic state or a second logic state according to whether a data signal exceeds a first threshold level, and to generate a second edge sample in either the first logic state or the second logic state according to whether the data signal exceeds a second threshold level;
        means for selecting one of the first and second edge samples to be a phase error signal that indicates whether a transition of a first clock signal is early or late relative to a desired transition time; and
        means for adjusting a frequency difference value based, at least in part, on the phase error signal, the frequency difference value indicating a difference in frequency between a clock signal used to generate the first clock signal and a clock signal used to time transmission of the data signal; and
        means for adjusting a phase of the first clock signal based, at least in part, on the frequency difference value.

22. Computer-readable media having information embodied therein that includes a description of an integrated-circuit memory device, the information including descriptions of:

        an edge sampling circuit to generate a first edge sample in either a first logic state or a second logic state according to whether a data signal exceeds a first threshold level, and to generate a second edge sample in either the first logic state or the second logic state according to whether the data signal exceeds a second threshold level;
        a selector circuit to select one of the first and second edge samples to be a phase error signal that indicates whether a transition of a first clock signal is early or late relative to a desired transition time; and
        circuitry to adjust a frequency difference value based, at least in part, on the phase error signal, the frequency difference value indicating a difference in frequency between a clock signal used to generate the first clock signal and a clock signal used to time transmission of the data signal; and
        circuitry to adjust a phase of the first clock signal based, at least in part, on the frequency difference value.

23. A method of operation within an integrated circuit device, the method comprising:

        generating a sequence of data sample pairs, each data sample pair including a first data sample having a logic state according to whether an input signal exceeds a first threshold level and a second sample having a logic state according to whether the input signal exceeds a second threshold level;
        selecting either the first data sample or the second data sample of each data sample pair to be included as a selected data sample within a sequence of selected data samples;
        generating a first edge sample having one of at least two states according to whether an input signal exceeds the second threshold level;
        generating a second edge sample having one of at least two states according to whether an input signal exceeds a third threshold level;
        selecting, based on the sequence of selected data samples, one of the first and second edge samples to be a phase error signal that indicates whether a transition of a first clock signal is early or late relative to a desired transition time;
        adjusting a frequency difference value based, at least in part, on the phase error signal, the frequency difference value indicating a difference in frequency between a clock signal used to generate the first clock signal and a clock signal used to time transmission of the data signal; and
        adjusting a phase of the first clock signal based, at least in part, on the frequency difference value.
    
    


Section headings have been provided in this detailed description for convenience of reference only, and in no way define, limit, construe or describe the scope or extent of such sections. Also, while the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

## Claims

1. A method of operation within an integrated circuit device, the method comprising:
sampling a binary input signal to generate a set of data samples;
comparing the binary input signal with a first threshold level and with a second threshold level to generate a first edge sample and a second edge sample, respectively; and
adjusting the phase of a first clock signal based, at least in part, on the first edge sample if the set of data samples matches a first data pattern, and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.

2. The method of claim 1 wherein comparing the binary input signal with a first threshold level and with a second threshold level to generate a first edge sample and a second edge sample, comprises sampling a result of the comparison of the binary input signal with the first threshold in response to a transition of the first clock signal to generate the first edge sample and sampling a result of the comparison of the binary input signal with the second threshold in response to the transition of the first clock signal to generate the second edge sample.

3. The method of claim 2 wherein sampling a binary input signal to generate a set of data samples comprises sampling the binary input signal in response to transitions of a second clock signal that is phase offset relative to the first clock signal, and wherein the set of data samples includes at least two data samples generated in response to transitions of the second clock signal that precede the transition of the first clock signal and at least one data sample generated in response to a transition of the second clock signal that succeeds the transition of the first clock signal.

4. The method of claim 1 wherein sampling a binary input signal to generate a set of data samples comprises generating a set of data samples that includes two data samples generated prior to the first and second edge samples, and one data sample generated after the first and second edge samples.

5. The method of claim 1 wherein sampling a binary input signal to generate a set of data samples comprises generating first, second and third data samples in sequence, and wherein adjusting the phase of the first clock signal based at least in part on the first edge sample if the set of data samples matches a first data pattern and based at least in part on the second edge sample if the set of data samples matches a second data pattern comprises:
adjusting the phase of the first clock signal based at least in part on the first edge sample if the second data sample has a different logic state than the first data sample and a different logic state than the third data sample; and
adjusting the phase of the first clock signal based at least in part on the second edge sample if the third data sample has a first logic state and the first data sample and the second data sample have a second logic state.

6. The method of claim 1 wherein adjusting the phase of a first clock signal comprises:
adjusting an accumulated value based on a logic state of the first edge sample if the set of data samples matches the first data pattern; and
adjusting an accumulated value based on a logic state of the second edge sample if the set of data samples matches the second data pattern.

7. The method of claim 1 wherein sampling a binary input signal to generate a set of data samples comprises:
generating a first data sample having either a first logic state or a second logic state according to whether the binary input signal exceeds the second threshold level;
generating a second data sample having either the first logic state or the second logic state according to whether the binary input signal exceeds a third threshold level; and
selecting either the first data sample or the second data sample to be a data sample within the set of data samples.

8. The method of claim 7 wherein selecting either the first data sample or the second data sample to be a data sample within the set of data samples comprises selecting either the first data sample or the second data sample according to whether a third data sample, generated prior to the first and second data samples, has the first logic state or the second logic state.

9. The method of claim 1 further comprising generating the first clock signal by interpolating between a selected pair of clock signals in accordance with a phase control value, and wherein adjusting the phase of a first clock signal comprises adjusting the phase control value.

10. An integrated circuit device comprising:
a data sampling circuit to generate a set of data samples from a binary input signal;
an edge sampling circuit to generate a first edge sample in either a first logic state or a second logic state according to whether the binary input signal exceeds a first threshold level, and to generate a second edge sample in either the first logic state or the second logic state according to whether the binary input signal exceeds a second threshold level; and
a clock recovery circuit to adjust the phase of a first clock signal based, at least in part, on the first edge sample if the set of data samples matches a first data pattern, and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.

11. The integrated circuit device of claim 10 wherein the edge sampling circuit comprises:
circuitry to compare the binary input signal with the first threshold level and to latch the first edge sample, in response to a transition of the first clock signal, in either the first logic state or the second logic state according to whether the binary input signal exceeds the first threshold level; and
circuitry to compare the binary input signal with the second threshold level and to latch the second edge sample, in response to the transition of the first clock signal, in either the first logic state or the second logic state according to whether the binary input signal exceeds the second threshold level.

12. The integrated circuit device of claim 11 wherein the data sampling circuit comprises circuitry to sample the binary input signal in response to transitions of a second clock signal that is phase offset relative to the first clock signal, and wherein the set of data samples includes at least two data samples generated in response to transitions of the second clock signal that precede the transition of the first clock signal and at least one data sample generated in response to a transition of the second clock signal that succeeds the transition of the first clock signal.

13. The integrated circuit device of claim 10 wherein the set of data samples comprises two data samples generated prior to the first and second edge samples, and one data sample generated after the first and second edge samples.

14. The integrated circuit device of claim 10 wherein the data sampling circuit comprises circuitry to generate first, second and third data samples in sequence, and wherein the clock recovery circuit comprises:
circuitry to adjust the phase of the first clock signal based, at least in part, on the first edge sample if the second data sample has a different logic state than the first data sample and a different logic state than the third data sample; and
circuitry to adjust the phase of the first clock signal based, at least in part, on the second edge sample if the third data sample has the first logic state and the first data sample and the second data sample have the second logic state.

15. The integrated circuit device of claim 10 wherein the clock recovery circuit comprises circuitry to adjust a count value based on the logic state of the first edge sample if the set of data samples matches the first data pattern and to adjust the count value based on the logic state of the second edge sample if the set of data samples matches the second data pattern.

16. The integrated circuit device of claim 15 wherein the clock recovery circuit comprises:
an interpolator to interpolate between a selected pair of reference clock signals in accordance with a phase control value to generate the first clock signal; and
circuitry to occasionally adjust the phase control value according to a sign of the count value.

17. The integrated circuit device of claim 10 wherein the data sampling circuit comprises:
a first sampling circuit to generate a first data sample having either the first logic state or the second logic state according to whether the binary input signal exceeds the second threshold level;
a second sampling circuit to generate a second data sample having either the first logic state or the second logic state according to whether the binary input signal exceeds a third threshold level; and
a selector circuit coupled to receive the first and second data samples from the first and second sampling circuits and to select, according to a third data sample generated prior to the first data sample and the second data sample, either the first data sample or the second data sample to be a selected data sample within the set of data samples.

18. The integrated circuit device of claim 17 further comprising a storage circuit to store the third data sample, the storage circuit having an output coupled to a select input of the selector circuit to provide the third data sample thereto, and having an input coupled to an output of the selector circuit to receive the selected data sample.

19. A signaling system comprising:
a first integrated circuit device to transmit a data signal that conveys a sequence of binary values in respective transmission intervals; and
a second integrated circuit device coupled to receive the data signal and having:
a data sampling circuit to sample the data signal and generate, in response, a set of data samples that correspond to the sequence of binary values;
an edge sampling circuit to generate a first edge sample in either a first logic state or a second logic state according to whether the data signal exceeds a first threshold level, and to generate a second edge sample in either the first logic state or the second logic state according to whether the data signal exceeds a second threshold level; and
a clock recovery circuit to adjust the phase of a first clock signal based, at least in part, on the first edge sample if the set of data samples matches a first data pattern, and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.

20. An integrated circuit device comprising:
means for generating a set of data samples from a binary input signal;
means for generating a first edge sample in either a first logic state or a second logic state according to whether the binary input signal exceeds a first threshold level;
means for generating a second edge sample in either the first logic state or the second logic state according to whether the binary input signal exceeds a second threshold level; and
means for adjusting the phase of a first clock signal based, at least in part, on the first edge sample if the set of data samples matches a first data pattern, and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.

21. A manufacture comprising computer readable media having information embodied therein that includes a description of an integrated-circuit memory device, the information including descriptions of:
a data sampling circuit to generate a set of data samples from a binary input signal;
an edge sampling circuit to generate a first edge sample in either a first logic state or a second logic state according to whether the binary input signal exceeds a first threshold level, and to generate a second edge sample in either the first logic state or the second logic state according to whether the binary input signal exceeds a second threshold level; and
a clock recovery circuit to adjust the phase of a first clock signal based, at least in part, on the first edge sample if the set of data samples matches a first data pattern, and based, at least in part, on the second edge sample if the set of data samples matches a second data pattern.