# Patent

## Title
Method and apparatus for the parallel correlator and applications thereof

## Abstract

A fast correlator transform (FCT) algorithm and methods and systems for implementing same, correlate an encoded data word (X0-XM−1) with encoding coefficients (C0-CM−1), wherein each of (X0-XM−1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1. In accordance with the invention, X0 is multiplied by each state (C0(0)through C0(k−1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k−1). This is repeating for data bits (X1-XM−1) and corresponding coefficients (C1-CM−1), respectively. The results are grouped into N groups. Members of each of the N groups are added to one another, thereby generating a first layer of correlation results. The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated. The final layer of results includes a separate correlation output for each possible state of the complete set of coefficients (C0-CM−1). The final layer of results is compared to identify a most likely code encoded on said data word. In an embodiment, the summations are pruned to exclude summations that would result in invalid combinations of the encoding coefficients (C0-CM−1). In an embodiment, substantially the same hardware is utilized for processing in-phase and quadrature phase components of the data word (X0-XM−1). In an embodiment, the coefficients (C0-CM−1) represent real numbers. In an alternative embodiment, the coefficients (C0-CM−1) represent complex numbers. In an embodiment, the coefficients (C0-CM−1) are represented with a single bit. Alternatively, the coefficients (C0-CM−1) are represented with multiple bits (e.g., magnitude). In an embodiment, the coefficients (C0-CM−1) represent a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. Application No. 09/987,193, filed Nov. 13, 2001, entitled “Method and Apparatus for a Parallel Correlator and Applications Thereof,” which claims the benefit of U.S. provisional application, “Method and Apparatus for a Parallel Correlator and Applications Thereof,” Ser. No. 60/248,001, filed Nov. 14, 2000, each of which is incorporated herein by reference in its entirety.
The following application of common assignee is related to the present application, and is herein incorporated by reference in its entirety: U.S. non-provisional application, “Method and System for Down-Converting an Electromagnetic Signal, Transforms for Same, and Aperture Relationships,” Ser. No. 09/550,644, filed Apr. 14, 2000.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to matched filters and correlators and, more particularly, to a novel fast correlator transform (“FCT”) and to methods and systems for implementing same.
2. Related Art
Matched Filter Theory was introduced by D. O. North in 1943. Others such as Van Vleck, Middleton, Weiner, and Turin, have added to the body of knowledge and application, ranging from RADAR to SONAR and communications. Although the basic theory was originally applied to continuous time systems and linear networks, the theory has been augmented to absorb discrete sampled filters and correlator operations. Indeed Paul Green pointed out in the June 1960 IRE Transactions on Information Theory, Matched Filter Issue:
“Correlation detection was studied at first as a separate subject, but the equivalence of the two operations (meaning matched filters and correlators) was soon appreciated.”
IRE Transactions on Information Theory, New York, N.Y.: Professional Group on Information, Institute of Radio Engineers, June, 1960, incorporated herein by reference in its entirety.
More recently Van Whalen and Blahut as well as others have provided proofs of mathematical equivalence of correlation or matched filtering based on a change of variables formulation.
With the surge of DSP and proliferation of VLSI CMOS circuits as well as the universal push for software radios, many discrete matched filter realizations have evolved. The most notable digital implementation is the Transversal or Finite Impulse Response Filter which may realize the time flipped impulse response of the waveform to be processed or utilized as a correlator, both which produce the equivalent result at the optimum observation instant.
A particular concern arises when multiple filtering operations are required, concurrently, as is the case for parallel correlators. The complexity, clock speeds and signal flow control typically increase cost, size, and power.
What are needed are improved methods and systems for performing matched filtering and/or correlating functions, including concurrent and/or parallel correlations.
SUMMARY OF THE INVENTION
The present invention is directed to methods and systems for performing matched filtering and/or correlating functions, including concurrent and/or parallel correlations. More particularly, the present invention is directed to a fast correlator transform (FCT) algorithm and methods and systems for implementing same. The invention is useful for, among other things, correlating an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each coefficient is represented by one or more bits, wherein each coefficient has k possible states, and wherein M is greater than 1.
In accordance with the invention, X0 is multiplied by each state (C0(0) through C0(k-1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k-1). This is repeating for data bits (X1-XM-1) and corresponding coefficients (C1-CM-1), respectively. The results are grouped into N groups combinations within each of said N groups are added to one another, thereby generating a first layer of correlation results.
The first layer of results is grouped and the members of each group are summed with one another to generate a second layer of results. This process is repeated as necessary until a final layer of results is generated. The final layer of results includes a separate correlation output for each possible state of the complete set of coefficients (C0-CM-1). The results in the final layer are compared with one another to identify a most likely code encoded on said data word.
In an embodiment, the summations are pruned to exclude summations that would result in invalid combinations of the encoding coefficients (C0-CM-1).In an embodiment, substantially the same hardware is utilized for processing in-phase and quadrature phase components of the data word (X0-XM-1). In an embodiment, the coefficients (C0-CM-1) represent real numbers. In an alternative embodiment, the coefficients (C0-CM-1) represent complex numbers. In an embodiment, the coefficients (C0-CM-1) are represented with a single bit. Alternatively, the coefficients (C0-CM-1) are represented with multiple bits (e.g., magnitude). In an embodiment, the coefficients (C0-CM-1) represent a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.



BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES
The present invention will be described with reference to the accompanying drawings wherein:
FIG. 1 is a block diagram of an example discrete transversal matched filter or correlator, in which the present invention can be implemented;
FIG. 2 is an expanded view of the summation function illustrated in FIG. 1;
FIG. 3A illustrates example correlation kernels, in accordance with an aspect of the present invention;
FIG. 3B illustrates example first and second layers of an FCT processing hierarchy in accordance with an aspect of the invention;
FIG. 3C illustrates an example signal flow diagram for the first and second layers illustrated in FIG. 3B;
FIG. 4A illustrates a relationship between a conventional parallel correlator approach and Equation 7;
FIG. 4B illustrates an example matrix form of coefficients for a parallel correlator in accordance with an aspect of the present invention;
FIG. 5 illustrates an example complex fast Hadamard Transform;
FIG. 6 illustrates an example parallel magnitude compare operation in accordance with an aspect of the invention;
FIG. 7 illustrates an example final layer of an FCT processing hierarchy in accordance with an aspect of the invention;
FIG. 8 illustrates an example process flowchart for implementing an FCT algorithm in accordance with an aspect of the present invention.



DETAILED DESCRIPTION OF THE INVENTION










TABLE OF CONTENTS


















I.
Introduction



II.
Example Environment: 802.11



III.
Fast Correlator Transform and Correlator Kernels



IV.
Mathematical Formulation



V.
Comparisons to the Hadamard Transform



VI.
Maximum Likelihood Decoding (AWGN, no Multipath)




A. Magnitude Comparator



VII.
Example Methods for Implementing the FCT Algorithm



VIII.
CCK Chip Code Words



IX
Conclusion



I.
Introduction










FIG. 1 is a block diagram of an example discrete transversal matched filter or correlator 100, also referred to herein as a finite impulse response (“FIR”) filter 100. The FIR filter 100 includes a set of multipliers 104 that multiply data words Xi by coefficients C. The FIR filter 100 also includes a final accumulate or summation function 102. The matched filter 100 implements the following discrete sampling equation;




  
    
      
        
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In Eq. 1, Xi are typically derived from a sampling device such as an A/D converter and can be represented as signed magnitude, two's complement, or other binary representation in parallel bit format. Likewise the multiplier tap coefficients C0 . . . Cn can be 1 bit values or k bit (soft) values depending on the application. In the case of soft value implementations, the multiplier functions can represent considerable hardware or algorithmic complexity. The final summation can be implemented using discrete adder technologies or floating point processors. The entire architecture can be implemented in hardware, software, or a hybrid of each.
A particular concern arises when multiple filtering operations are required, concurrently, as is the case for parallel correlators. The complexity, clock speeds and signal flow control typically increase cost, size, and power. Hence, efficient architectures are often pursued to streamline the implementation and thereby differentiate product offerings.
The present invention is directed to a novel fast correlator transform (“FCT”) algorithm that reduces the number of additions for parallel correlation, as compared to conventional techniques. The present invention is also directed to methods and systems for implementing the novel FCT algorithm. Conventional techniques are typically of less universal application and restricted to certain signaling schemes. The present invention, on the other hand, is applicable to a variety of parallel matched filter and/or correlator operations.
The present invention is as efficient or more efficient than the Fast Walsh Transform, currently applied as the “state of the art,” and is more universally applicable to signaling schemes employing higher order signaling spaces such as MQAM, CDMA, etc. In addition, classical multi-path processor algorithms are more easily applied using the classical correlator/matched filter kernel, in accordance with the present invention, rather than the conventional modified Fast Walsh Transform.
II. Example Environment: 802.11
The present invention is described herein as implemented in an example environment of an IEEE 802.11b 11 MBPS physical layer signaling scheme. IEEE 802.11 is a well-known communications standard and is described in, for example, “Medium Access Control (MAC) and Physical (PHY) Specifications,” ANS/IEEE Std 802.11, published by IEEE, (1999Ed.), and incorporated herein by reference in its entirety.
The present invention is not, however, limited to the IEEE 802.11 communications standard. Based on the description herein, one skilled in the relevant art(s) will understand that the present invention can be implemented for a variety of other applications as well. Such other applications are within the spirit and scope of the present invention.
The 802.11 signaling scheme of interest is based on Cyclic Code Keying (“CCK”) derived from Walsh/Hadamard functions. A restricted set within the available coding space was selected so that the Fast Walsh Transform could be utilized to implement an efficient correlator architecture. Originally, both Harris and Lucent could not figure out how to apply a classical parallel matched filter or correlator, efficiently, to process the waveforms. The current coding space provides for 64 code words. Harris erroneously predicted that a classical parallel matched filter approach would require 8×64=512 complex additions since each code word is 8 bits, on I and Q and there are 64 code words. However, the true estimate is 7×64=448 complex additions as illustrated in the example 8-way adder tree illustrated in FIG. 2.
FIG. 2 is an expanded view of the final accumulate or summation function 102 in FIG. 1, part of the FIR filter 100. Notice that only 7 adders are required for the example implementation. Nevertheless, 448 complex additions represent a significant number of operations. Lucent, Harris/Intersil, and Alantro apply the Fast Walsh Transform (“FWT”) to the CCK code set to reduce the correlation operation down to 112 complex multiplies due to the restriction placed on the code set.
The FWT is actually more of a decoder than a correlator. It reduces to the performance of a correlator for this specific application if the coefficients in the butterfly branches are weighted with simple hard coded values, i.e., 1, −1, j, −j. The imaginary numbers are included for the case of complex signaling.
The FCT algorithm, according to the present invention, is truly a correlation or matched filter operation and can be applied with soft value weighting or hard value weighting. Furthermore, the present invention is intuitively satisfying, possessing direct correspondence of matched filter tap weights or coefficients maintained throughout the hierarchical structure. This permits easy extension of the matched filter concept to accommodate channel equalization, MLSE, and other adaptive applications.
III. Fast Correlator Transform and Correlator Kernels
The available coding space for a 16 bit word is 216=65536. CCK whittles this space down to a code set formed by 8 in-phase (“I”) chip and 8 quadrature phase (“Q”) chip complex symbols. 64 code words are retained, carrying 6 bits of information. 2 more bits are contained in the complex QPSK representation, for a total of 8 bits of information.
Suppose then that 8 samples of an input vector X0, X1, . . . X7 are associated with optimal sampling instants from the output of a chip matched filter. Each of these samples would normally be weighted by the coefficients C0 . . . C7 then assimilated as illustrated in FIGS. 1 and 2.
In the 802.11 example, C0 . . . . C7 correspond to samples of the CCK code set symbols. The unknowns X0 . . . X7 are noisy input samples from which a specific code must be extracted. Conceptually, 64 such complex filtering operations should be performed concurrently since a specific code word cannot be predicted a priori. The largest output from the parallel bank of correlators would then be selected as the most likely code word correlation match at that particularly symbol sample time.
In accordance with the present invention, a general philosophy for correlation is imposed for partitioned segments of code words. In an embodiment, the code word correlations are divided into sub-sets. In the illustrated example embodiment, the code word correlations are divided into sample pairs. The present invention is not, however, limited to this example embodiment. In other embodiments, the code word correlations are divided into triplets, quintuplets, and/or any other suitable sub-sets.
Combinations of the code word correlation sub-sets are then provided to correlation kernels. FIG. 3A illustrates example correlation kernels 302a-302d, in accordance with an aspect of the present invention.
The correlation kernels 302a-302d represent all or substantially all possible correlation options for the first 2 samples X0, X1. In a similar fashion the remaining groupings of double samples (X2, X3), (X4, X5), (X6, X7) will also spawn their own set of 4 correlation kernels.
The number of separate correlation kernels spawned is determined by the number of correlated samples per summation, the number of correlation variations possible, and, in an embodiment, the number of invalid combinations of correlated samples. In the present example, each coefficient has two possible states (i.e., hard value weighting). Thus each subset correlation generates 4 outputs. In alternative embodiments, soft weighting is implemented, where each coefficient is represented with multiple bits (e.g., magnitude representation).
In an embodiment, binary antipodal signaling in accordance with the present invention is implemented in accordance with Eq. 2.




  
    
      
        
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The result for the example environment described above, using 2 input summers, is shown in Eq. 3:




  
    
      
        
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wherein:

n is the number of uniquely available summer inputs;
r is the number of summing inputs per kernel; and
L is the number of invalid combinations.
Nk is thus the number of correlation kernels and therefore the number of adders or summers required. Groupings of two correlation samples provide for convenient binary expansion. As stated above, however, the present invention is not limited to groupings of two.
The term L represents the number of invalid or disallowed combinations. For instance, X0C0 and —X0C0 is an invalid combination when added and therefore can be subtracted from the total number of combinations. In an embodiment, 3 way adders or summers are utilized. In other embodiments, other algorithmic partitioning is utilized. For the current example, partitioning in powers of 2 is convenient and attractive in terms of potential hardware implementation.
FIG. 3B illustrates example first and second layers 304 and 306, respectively, of an FCT processing hierarchy in accordance with an aspect of the invention.
The second layer 306 includes 32 additions 308, of which 308a through 308p are illustrated, to process combinations of correlations from the first layer 304 of correlation kernels. The first layer 304 includes 16 additions related to the first 4 sample correlations X0C0 . . . X3C3, and 16 additions related to the 2nd 4 sample correlations. Hence, the first layer 304 of kernels includes 16 adders 302 and the second layer possesses 32 adders 308. Once the second layer 306 is accomplished, each term that results includes 4 correlation components.
Note that 4 unique samples X0 . . . X3 at the system input spawns 2 4 unique 4-tuple correlations at the second layer 306 of kernel processing. The corresponding number of additions is calculated for the 4 sample correlation sequences from Eq. 4:




  
    
      
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At this point it is important to realize that all that is required is one more level of processing to obtain correlation terms consisting of 8 components which represents a full length correlation. However, it must also be recognized that there are 16 upper 4-tuple correlations as well as 16 lower 4-tuple correlations, which if exploited for all combinations in this case would yield 256 addition operations! Fortunately the CCK code set is well defined and possesses only 64 valid 8 chip component correlations. Hence, the final layer, illustrated in FIG. 7, is pruned to perform only 64 unique addition operations. Thus, a total (upper bound) number of adders used for the algorithm are:

16 (first hierarchical layer)+32 (second layer)+64 (third layer)=112

This is a remarkable result because a conventional parallel matched filter or correlator bank would require 448 complex additions. Theoretically, 112 is the upper bound. However, in practice, the Trellis may be pruned to a maximum of 78 additions on the I and 78 and the Q.
FIG. 3C illustrates an example signal flow diagram for the FCT algorithm through the first 2 layers 304 and 306. In accordance with the example above, there are 8 input samples and 32 output correlation options through the first 2 layers 304 and 306. Correlation combinations from the upper and lower 16 4-tuples provide a final trellis with 64 8-tuple options, each representing a different CCK symbol. The option having the highest output is selected during each symbol cycle as the most likely CCK symbol. In the example embodiment, the correlation operation utilizes I and Q matched filters since the symbols are complex.
IV. Mathematical Formulation
In an embodiment, a receiver in accordance with the present invention receives a waveform and an analog-to-digital converter function samples the received waveform and converts the waveform down to baseband. The received sampled waveform may be represented from Eq. 5:

Xi=Si+Ni  (Eq. 5)

Where Si represents samples from the received signal and Ni represent noise sampled from an average white Gausian noise (“AWGN”) process. This equation does not account for multi-path. The samples can be considered as complex, with I and Q components. The receiver output can be represented by Eq. 6:




  
    
      
        
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The coefficients, Ck, are considered constant for the nominal case of an AWGN channel. n is the FIR filter or correlator depth. For a case of m correlators operating on Xi in parallel, Eq. 6 becomes Eq. 7:




  
    
      
        
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The mth correlator branch then contains correlator coefficients uniquely related to that branch.
FIG. 4A illustrates a conventional parallel correlator approach and relates it to Eq. 7. The present invention breaks the sum over n−1 into smaller sums, typically, although not necessarily, sums of 2. The present invention applies all, or substantially all potential cross correlations and carries the 4 results forward to a subsequent level of processing. An example mathematical formulation of this operation is provided in Eq. 8;




  
    
      
        
          
            
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Where l, v, p, and u may be considered as indices to select different coefficients. All indices should be considered in terms of a final valid code word correlation. In the 802.11 case, 256 correlation sequences are defined by Eq. 8, but the options are sifted to correspond only to valid CCK code words. FIG. 4B illustrates an example matrix form of coefficients for a parallel correlator according to the present invention.
The coefficients all take on the values of +/−1 for the examples herein. The indices are permitted to contain zeros for consistency with the original FIR formulation. The FCT sub-matrices however are simply;




  
    
      
        
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The indices l, v, p, u are manipulated specifically to match the coefficients to the desired code words at the Y(i)l,v,p,u outputs. The indices also uniquely specify the trajectory through the signal flow path. Breaking up the original parallel matched filter coefficient matrix into the smaller 2×2 matrix permits the FCT algorithm to exploit redundant correlation operations.
V. Comparisons to the Hadamard Transform
An FCT algorithm trellis, in accordance with the present invention, is described above. A corresponding length 4 complex fast Hadamard Transform is illustrated in FIG. 5. As with the FCT algorithm, there are two such trellis structures corresponding to 8 input samples and 32 outputs. The 32 outputs include two 16 wide 4-tuple groupings, which are then utilized in combinations to produce the final 54 8-tuple correlations.
There are distinct differences between the two algorithms. For example, the FCT algorithm can function on arbitrary correlation words, even in matched filter scenarios, while the FWT requires certain signal coding structure. Also, the FCT algorithm permits greater efficiency because the number of adds may be tailored for a specific code set or application.
Harris and Lucent advertise an efficiency of 112 complex additions for CCK demodulation, which amounts to 2×112 additions. The bounding case for 64 arbitrary correlations with the FCT was shown to be 112, maximum. It turns out that the specific case of CCK may be accommodated using a pruned FCT algorithm having 78 additions on the in-phase correlation band and 78 additions on the quadrature correlation bank. Therefore, the FCT possesses greater redundancy for the CCK application, which is exploited to implement significantly more efficient structures.
VI. Maximum Likelihood Decoding (AWGN, no Multipath)
The modified Fast Walsh/Hadamard Transform implements a complex trellis decoder for which maximum scores may be compared at the trellis output. Thus there are 64 distinct outputs of the trellis which are preferred based on Euclidean distance calculations along the trellis trajectories. Only certain specific trajectories are considered up through the second tier of the trellis. The distance properties for the decoding trellis are also Euclidean for the in-phase and quadrature phase correlators. However, it is important to realize that the total distance should be calculated within the complex plane rather than simply on I independently of Q. That is, scoring is based on Eq. 10.

Distance≡√{square root over (Iscore2+Qscore2)}  (Eq. 10)

This comes from the fact that there are pairs of I and Q chip code words which are dependent. That is the nature of the complex Walsh-Hadamard codes. Fortunately, a sufficient statistic exists which does not require the square root operation. Simply calculating the sum of the squares or estimating the vector magnitude will suffice. In this manner then the total distance or weighting through complex space is calculated. The largest output out of the 64 complex operations (weighting scenario) then becomes the most likely 8 chip complex code.
A. Magnitude Comparator
In order to determine which code symbol was most likely encoded, a magnitude compare operation is performed on the outputs from the summer 102 (FIG. 1). A variety of types of magnitude compare operations can be performed.
FIG. 6 illustrates an example parallel magnitude compare operation in accordance with an aspect of the invention. In operation, the I and Q inputs, 8 bits wide each, for example, are squared and summed at the correlator outputs to form 64 scores. These 64 scores are compared and the largest result selected as the maximum likelihood symbol estimate. Each of the 64 outputs are assigned their corresponding chip code-to-6-bit data map. An additional di-bit is decoded from the differential phase decoder. In an embodiment, the squaring operation results in 16 bit output value when the inputs from each I and Q correlator are truncated to an extent reasonable to minimize the compare tree. In an embodiment, a parallel compare tree utilizes log2 (64)−1 compares to obtain the most likely result.
In an embodiment, the magnitude compare operation illustrated in FIG. 6 utilizes a flag at each level of compare to indicate the winning local score at that level. The winning local score can be traced from the output back to one of the 64 original input correlation scores to decide which 6-bit word is most likely. In an embodiment, outcomes of tie scores at one or more levels are arbitrarily determined. In an embodiment, magnitude compare operations are performed with an adder/subtractor to create the result C=A−B, where A and B are inputs.
Another magnitude compare technique that can be utilized is referred to herein as space slicing, which includes the steps of examining the MSB of the correlator outputs, and throwing away results not active in the MSB. If none are active in the MSB then the next MSB is compared, so on and so forth. Any surviving correlator outputs are compared in the next most significant MSB in succession until all necessary compares are exhausted. This technique is useful because it requires only 1-bit compares at each level down to the final compare. In an embodiment, 1 bit compares are performed with an exclusive OR gate. Generally, there is no deterministic way to predict the number of surviving compares which may be passed on to the next level, but the maximum number typically reduces by a factor of 2 at each level. This approach relies on a statistical distribution of scores, which may permit rapid sifting. If all of the distances are similar in magnitude then sifting typically requires more operations. For instance, if all 64 distance calculations/scores possess an active MSB then the first round of sifting will not eliminate any scores and all scores are then be compared in the next MSB. Although this is not likely to occur, it should be anticipated for associated hardware realization.
VII. Example Methods for Implementing the FCT Alrgorithm
FIG. 8 illustrates an example process flowchart 800 for implementing the FCT algorithm in accordance with an aspect of the present invention. For illustrative purposes, the flowchart 800 is described herein with reference to one or more of the drawing figures described above. The invention is not, however, limited to the examples illustrated in the drawings. Based on the description herein, one skilled in the relevant art(s) will understand that the invention can be implemented in a variety of ways.
The example process flowchart 800 illustrates a method for correlating an encoded data word (X0-XM-1) with encoding coefficients (C0-CM-1), wherein each of (X0-XM-1) is represented by one or more bits and each said coefficient is represented by one or more bits, wherein each coefficient has k possible states, wherein M is greater than 1.
The process begins with step 802, which includes multiplying X0 with each state (C0(0) through C0(k-1)) of the coefficient C0, thereby generating results X0C0(0) through X0C0(k-1). This is illustrated, for example, in FIGS. 3A, 3B, and 3C just prior to the kernels 302A, B, C, and D.
Step 804 includes repeating step 802 for data bits (X1-XM-1) and corresponding coefficients (C1-CM-1), respectively. This is illustrated, for example, in FIGS. 3B, and 3C just prior to the kernels 302E through 302Q.
Step 806 includes grouping the results of steps 802 and 804 into N groups and summing combinations within each of said N groups, thereby generating a first layer of correlation results. This is illustrated, for example, in FIGS. 3A, 3B, and 3C by the kernels 302, and the resultant first layer of results 307.
Step 808 includes grouping the results of step 806 and summing combinations of results within each group to generate one or more additional layers of results, and repeating this process until a final layer of results includes a separate correlation output for each possible state of the complete set of coefficients (C0-CM-1). This is illustrated in FIG. 3C and FIG. 7, where the summers 306 generate a second layer 310, the FCT final output trellis 702 (FIG. 7) provides separate outputs for each possible state of the complete set of coefficients (C0-CM-1) in a final layer 704.
In an embodiment, steps 806 and 808 include the step of omitting summations that would result in invalid combinations of the encoding coefficients (C0-CM-1). This is illustrated, for example, in FIG. 7, wherein the second level of results 310 omits the following combinations:

    C4C5C6(—C7);
    C4C5(—C6)(—C7);
    (—C4)C5C6(—C7);
    (—C4)C5(—C6)(—C7);
    C4(—C5)C6(—C7);
    C4(—C5)(—C6)(—C7);
    (—C4)(—C5)C6(—C7); and
    (—C4)(—C5)(—C6)(—C7).


In this example, the omissions eliminate performing summations for combinations that are invalid in light of the CCK code. In other embodiments, different combinations may or may not be omitted based on particular codes.
Step 810 includes comparing magnitudes of said separate correlation outputs, thereby identifying a most likely code encoded on said data word. This is illustrated, for example, in FIG. 6, by the example parallel magnitude compare operation.
In an embodiment, the process flowchart 800 further includes the step of performing steps (1) through (5) using substantially the same hardware for in-phase and quadrature phase components of the data word (X0-XM-1).
In an embodiment, the coefficients (C0-CM-1) represent real numbers.
In an alternative embodiment, the coefficients (C0-CM-1) represent complex numbers.
In an embodiment, the coefficients (C0-CM-1) are represented with a single bit. Alternatively, the coefficients (C0-CM-1) are represented with multiple bits (e.g., magnitude).
In an embodiment, the coefficients (C0-CM-1) represent a cyclic code keying (“CCK”) code set substantially in accordance with IEEE 802.11 WLAN standard, illustrated in the tables below.
In an embodiment, as illustrated in one or more of the prior drawing figures, M equals 8, N equal 4, and the coefficients (C0-CM-1) have two states, plus and minus.
VIII. CCK Chip Code Words
Tables are provided below that illustrate source-input data symbols, 8-bits long (d0-d7), and corresponding in-phase and quadrature phase 8 chip symbols used for CCK. The complex chip notation is provided for reference. In addition the algorithm flow diagram 4-tuple sums are provided since the last level of flow diagram becomes complex and difficult to follow. B0 . . . B31 are the 4-tuple intermediate correlation results relating to the signal flow diagrams presented for the correlator algorithm. Two branch 4-tuples form the final output result for each correlator. B0 . . . B15 provide options for the first branch component to form a final output correlator 8-tuple while B16 . . . B31 provide the second branch component or second 4-tuple. For instance, Table 1 illustrates an example build-up:








TABLE 1







4-tuple Designator
4-tuple Coefficient Sequence


B6
−1, 1, 1, −1


B28
1, 1, −1, −1


4-tuple Combination
Final 8-tuple Correlator Coefficient Sequence


B6 + B28  
−1, 1, 1, −1, 1, 1, −1, −1









Logical zeros become weighted by an arithmetic value, −1. In this manner the optimum correlator trajectory for a particular chip sequence is projected through the correlator trellis. The example above corresponds to the in-phase correlator weighting for an originally transmitted data sequence d0. . . d7 of 0,0,1,0,1,0,1,0. For this example, that particular branch represents a correlation provided in Eq. 11;

Y42 =x0(−1)+x1(1)+x2(1)+x3(−1)+x4(1)+x5(1)+x6(−1)+x7(−1)  (Eq. 11)

x0 . . . x7 represent corrupted or noisy input signal samples. When the x1 match the coefficients significantly then that 8-tuple (1 of 64) output possesses maximum weighting and is declared most likely by the magnitude comparator. Another strategy seeks to minimize the distance between the x1 and c1. The process is similar in either case.
Table 2 illustrates example in-phase and quadrature 4-tuple combinations. It is noted that the examples provided in Tables 1 and 2 are provided for illustrative purposes and are not limiting. Other specific examples will be apparent to persons skilled in the relevant arts based on the teachings herein, and such other examples are within the scope and spirit of the invention.












TABLE 2





d0 d1 d2 d3

4-tuple

4-tuple



d4 d5 d6 d7
In phase
Combination
Quadrature
Combination
Complex





















D0
00000000
11101101
 B2 + B20
11101101
 B2 + B20
111−111−11


D1
00000001
00011101
B13 + B20
11101101
 B2 + B20
jjj−j11−11


D2
00000010
00011101
B13 + B20
00011101
B13 + B20
−1−1−1111−11


D3
00000011
11101101
 B2 + B20
00011101
B13 + B20
j−j−jj11−11


D4
00000100
00100001
B14 + B23
11101101
 B2 + B20
jj1−1jj−11


D5
00000101
00010001
B13 + B23
00101101
B14 + B20
−1−1j−jjj−11


D6
00000110
11010001
 B1 + B23
00011101
B13 + B20
−j−j−11jj−11


D7
00000111
11100001
 B2 + B23
11011101
 B1 + B20
11−jjjj−11


D8
00001000
00100001
B14 + B23
00100001
B14 + B23
−1−11−1−1−1−11


D9
00001001
11010001
 B1 + B23
00100001
B14 + B23
−j−jj−j−1−1−11


D10
00001010
11010001
 B1 + B23
11010001
 B1 + B23
11−11−1−1−11


D11
00001011
00100001
B14 + B23
11010001
 B1 + B23
jj−jj−1−1−11


D12
00001100
11101101
 B2 + B20
00100001
B14 + B23
−j−j1−1−j−j−11


D13
00001101
11011101
 B1 + B20
11100001
 B2 + B23
11j−j−j−j−11


D14
00001110
00011101
B13 + B20
11010001
 B1 + B23
jj−11−j−j−11


D15
00001111
00101101
B14 + B20
00010001
B13 + B23
−1−1−jj−j−j−11


D16
00010000
01000111
 B7 + B17
11101101
 B2 + B20
j1j−1j1−j1


D17
00010001
00010111
B13 + B17
01001101
 B7 + B20
−1j−1−jj1−j1


D18
00010010
10110111
 B8 + B17
00011101
B13 + B20
−j−1−j1j1−j1


D19
00010011
11100111
 B2 + B17
10111101
 B8 + B20
1−j1jj1−j1


D20
00010100
00000011
B15 + B19
01100101
 B6 + B21
−1jj−1−1j−j1


D21
00010101
10010011
 B9 + B19
00000101
B15 + B21
−j−1−1−j−1j−j1


D22
00010110
11110011
 B0 + B19
10010101
 B9 + B21
1−j−j1−1j−j1


D23
00010111
01100011
 B6 + B19
11110101
 B0 + B21
j11j−1j−j1


D24
00011000
10001011
B11 + B18
00100001
B14 + B23
−j−1j−1−j−1−j1


D25
00011001
11011011
 B1 + B18
10000001
B11 + B23
1−j−1−j−j−1−j1


D26
00011010
01111011
 B4 + B18
11010001
 B1 + B23
j1−j1−j−1−j1


D27
00011011
00101011
B14 + B18
01110001
 B4 + B23
−1j1j−j−1−j1


D28
00011100
11001111
 B3 + B16
10101001
B10 + B22
1−jj−11−j−j1


D29
00011101
01011111
 B5 + B16
11001001
 B3 + B22
j1−1−j1−j−j1


D30
00011110
00111111
B12 + B16
01011001
 B5 + B22
−1j−j11−j−j1


D31
00011111
10101111
B10 + B16
00111001
B12 + B22
−j−11j1−j−j1


D32
00100000
01000111
 B7 + B17
01000111
 B7 + B17
−11−1−1−1111


D33
00100001
10110111
 B8 + B17
01000111
 B7 + B17
−jj−j−j−1111


D34
00100010
10110111
 B8 + B17
10110111
 B8 + B17
1−111−1111


D35
00100011
01000111
 B7 + B17
10110111
 B8 + B17
j−jjj−1111


D36
00100100
10001011
B11 + B18
01000111
 B7 + B17
−jj−1−1−jj11


D37
00100101
10111011
 B8 + B18
10000111
B11 + B17
1−1−j−j−jj11


D38
00100110
01111011
 B4 + B18
10110111
 B8 + B17
j−j11−jj11


D39
00100111
01001011
 B7 + B18
01110111
 B4 + B17
−11jj−jj11


D40
00101000
10001011
B11 + B18
10001011
B11 + B18
1−1−1−11−111


D41
00101001
01111011
 B4 + B18
10001011
B11 + B18
j−j−j−j1−111


D42
00101010
01111011
 B4 + B18
01111011
 B4 + B18
−11111−111


D43
00101011
10001011
B11 + B18
01111011
 B4 + B18
−jjjj1−111


D44
00101100
01000111
 B7 + B17
10001011
B11 + B18
j−j−1−1j−j11


D45
00101101
01110111
 B4 + B17
01001011
 B7 + B18
−11−j−jj−j11


D46
00101110
10110111
 B8 + B17
01111011
 B4 + B18
−jj11j−j11


D47
00101111
10000111
B11 + B17
10111011
 B8 + B18
1−1jjj−j11


D48
00110000
11101101
 B2 + B20
01000111
 B7 + B17
−j1−j−1−j1j1


D49
00110001
10111101
 B8 + B20
11100111
 B2 + B17
1j1−j−j−j1


D50
00110010
00011101
 B3 + B20
10110111
 B8 + B17
j−1j1−j1j1


D51
00110011
01001101
 B7 + B20
00010111
 B3 + B17
−1−j−1j−j1j1


D52
00110100
10101001
B10 + B22
11001111
 B3 + B16
1j−j−11jj1


D53
00110101
00111001
B12 + B22
10101111
B10 + B16
j−11−j1jj1


D54
00110110
01011001
 B5 + B22
00111111
B12 + B16
−1−jj11jj1


D55
00110111
11001001
 B3 + B22
01011111
 B5 + B16
−j1−1j1jj1


D56
00111000
00100001
B14 + B23
10001011
B11 + B18
j−1−j−1j−1j1


D57
00111001
01110001
 B4 + B23
00101011
B14 + B18
−1−j1−jj−1j1


D58
00111010
11010001
 B1 + B23
01111011
 B4 + B18
−j1j1j−1j1


D59
00111011
10000001
B11 + B23
11011011
 B1 + B18
1j−1jj−1j1


D60
00111100
01100101
 B6 + B21
00000011
B15 + B19
−1−j−j−1−1−jj1


D61
00111101
11110101
 B0 + B21
01100011
 B6 + B19
−j11−j−1−jj1


D62
00111110
10010101
 B9 + B21
11110011
 B0 + B19
1jj1−1−jj1


D63
00111111
00000101
B15 + B21
10010011
 B9 + B19
j−1−1j−1−jj1









IX Conclusion

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Other embodiments are possible and are covered by the invention.

## Claims

1. A wireless local area network (WLAN) device, comprising:
means for generating in parallel the correlation of a data word vector (X0, . . . , XM−1) with each valid combination of a coefficient set (C0, . . . , CM−1); and
means for identifying the correlation corresponding to a code encoded on the data word.

2. The WLAN device of claim 1, wherein the means for generating in parallel the correlation of a data word vector (X0, . . . , XM−1) with each valid combination of a coefficient set (C0, . . . , CM−1) includes:
means for multiplying each element of the data word vector with each state of a corresponding coefficient in the coefficient set (C0, . . . , CM−1) to generate a plurality of outputs, wherein each coefficient in the coefficient set has one or more possible states;
means for summing a plurality of groups of multiplying means outputs to produce a set of first correlation results in parallel, wherein each group of multiplying means outputs includes a different combination of multiplying means outputs;
means for summing a plurality of groups of first correlation results to produce a set of second correlation results in parallel, wherein each group of first correlation results includes a different combination of first correlation results; and
means for summing a plurality of groups of second correction results to produce in parallel the correlation of a data word vector (X0, . . . , XM−1) with each valid combination of the coefficient set (C0, . . . , CM−1).

3. The WLAN device of claim 1, wherein the means for identifying the correlation corresponding to a code encoded on the data word includes:
means for comparing magnitudes of the correlations to select the maximum result.

4. The WLAN device of claim 1, wherein the means for summing a plurality of groups of multiplying means outputs, includes:
means for identifying valid combinations of multiplying means outputs; and
means for forming groups having valid combinations of multiplying means outputs.

5. The WLAN device of claim 1, wherein the means for summing a plurality of groups of first correlation results, includes:
means for identifying valid combinations of first correlation results; and
means for forming groups having valid combinations of first correlation results.

6. The WLAN device of claim 1, wherein the means for summing a plurality of groups of second correction results, includes:
means for identifying valid combinations of second correlation results; and
means for forming groups having valid combinations of second correlation results.

7. A wireless local area network (WLAN) device, comprising:
a plurality of inputs, one for each element of an encoded data word vector (X0, . . . , XM−1)
a multiplier module having a coefficient set (C0, . . . , CM−1), wherein each coefficient in the coefficient set has one or more possible states, wherein the multiplier module receives the plurality of inputs and multiplies each input with each state of a corresponding coefficient;
a first summation module including a plurality of summers, each summer coupled to a different group of multiplier module outputs, wherein each group of multiplier module outputs represents a valid combination of multiplier module outputs, and wherein a first set of correlation results are output in parallel from the first summation tier;
one or more additional summation modules coupled in series, each additional summation module receiving the outputs from a previous summation module, wherein the one or more additional summation modules includes a final summation module and wherein the final summation module outputs in parallel the correlation of the data word vector with each valid combination of the coefficient set; and
a comparator coupled to the final summation module.

8. The WLAN device of claim 7, wherein the one or more additional summation modules, include:
a plurality of summers, each summer coupled to a different group of outputs from the previous summer, wherein each group of outputs from the previous summer represents a valid combination of outputs from the previous summation module.

9. The WLAN device of claim 7, wherein the comparator includes:
a plurality of magnitude comparators,
wherein the plurality of magnitude comparators are arranged in a parallel tree configuration.

10. The WLAN device of claim 7, wherein the comparator is a space splicing comparator.

11. The WLAIN device of claim 7, wherein the multiplier module includes a plurality of multipliers, one for each element of the data word vector.

12. A wireless local area network (WLAN) device, comprising:
a multiplier module having a coefficient set (C0, . . . , CM−1), wherein each coefficient in the coefficient set has one or more possible states, wherein the multiplier module receives a plurality of inputs, one for each element of an encoded data word vector (X0, . . . , XM−), and multiplies each input with each state of a corresponding coefficient;
a first summation module including a plurality of adders, wherein each adder receives a valid combination of multiplier module outputs and wherein an output of each adder in the first summation module includes two correlation components;
a second summation module including a plurality of adders, wherein each adder receives a valid combination of first summation module outputs and wherein an output of each adder in the second summation module includes four correlation components; and
a final summation module including a plurality adders, wherein each adder receives a valid combination of second summation module outputs and wherein the output of the final summation module is 64 valid correlations, each correlation having eight correlation components.

13. The WLAN device of claim 12, wherein the first summation module has 16 adders, the second summation module has 32 adders, and the final summation module has 64 adders.

14. The WLAN device of claim 12, wherein the device further comprises:
a comparator coupled to the final summation module.

15. The WLAIN device of claim 14, wherein the comparator includes:
a plurality of magnitude comparators,
wherein the plurality of magnitude comparators are arranged in a parallel tree configuration.

16. The WLAN device of claim 14, wherein the comparator is a space splicing comparator.

17. The WLAIN device of claim 14, wherein the multiplier module includes a plurality of multipliers, one for each element of the data word vector.

18. The WLAN device of claim 12, wherein the coefficient states have values of +1 and −1.

19. The WLAN device of claim 12, wherein the coefficient states have values of +1, −1, +j, and −j.