# Patent

## Title
Method and apparatus for adaptive gain control and antenna load compensation

## Abstract

Methods and apparatuses are provided for adjusting a transmission gain in a transmitter of an electronic device. A transmitted signal is received at a digital signal processor (DSP) of the transmitter. The transmitted signal is also transmitted through a transmission path of the transmitter resulting in a load impedance. A looped-back signal is received at the DSP via a loop-back path of the transmitter that returns from the transmission path. The DSP estimates the load impedance from the transmitted signal and the looped-back signal. The DSP sets the transmission gain of the transmission path based on the load impedance and saturation values for a load current and a load voltage.

## Background
BACKGROUND
1. Field of the Disclosure
The present disclosure relates generally to adaptive gain control of a transmitter, and more particularly, to setting a transmission gain in a transmitter of an electronic device to maintain a constant Error Vector Magnitude (EVM) as the load impedance varies.
2. Description of the Related Art
A radio transmitter for mobile applications typically includes a source (e.g., a power amplifier) connected to a load (e.g., an antenna) via at least one of a filter and a switch. The amplifier is designed to provide best performance on a nominal load impedance of (50+j0)Ω. However, the antenna is often exposed to conditions that disrupt its radiated electromagnetic field. Such conditions may include an object in close proximity to the antenna. These conditions cause the equivalent impedance of the load to diverge significantly from the nominal value.
In order to maximize power transfer from a source to a load in an electrical circuit, the load impedance must equal the complex conjugate of the source impedance. When the load impedance is not equal to the complex conjugate of the source impedance, the power transferred to the load is not optimal, which results in mismatch power loss.
Due to the intrinsic limitations in both voltage and current swing of the amplifier, load mismatch may also cause distortion of the transmitted signal. Distortion is often measured in terms of EVM, and causes a reduction in the Signal-to-Noise Ratio (SNR) at the receiver end. This distortion, and resulting reduced SNR, causes the received signal to be unintelligible, and may eventually cause the link to fail.
Traditionally, in dealing with antenna mismatch, an isolator is inserted between the power amplifier and the antenna. The purpose of the isolator is to prevent the power reflected from the mismatched load to enter back into the amplifier, which can cause distortion of the signal and potential damage to the amplifier. In addition to an increase in the Bill Of Materials (BOM), the insertion of the isolator also reduces the radiated output power, which is equivalent to the insertion loss of the isolator.
A more elaborate approach to overcome antenna mismatch is the insertion of a tunable matching network between the power amplifier and the antenna. This robust solution to maximize the output power requires tunable discrete components that tend to be bulky, expensive, and result in non-negligible insertion losses, even when driving a perfectly matched load. Further, such components are typically not available in Complimentary Metal-Oxide Semiconductor (CMOS) integrated technologies.
A number of analog adaptive techniques have also been developed to automatically adjust transmit gain based on power or voltage that are detected to go into the load. However, these techniques require dedicated analog circuitry and do not allow for a programmable EVM target.
These adaptive techniques rely on reducing the bias current of the amplifier, which reduces the gain and prevents signal clipping. However, reducing the bias current also reduces the linear dynamic range of the amplifier, which causes increased distortion and EVM. The increased distortion and EVM have become more of a concern as requirements for supporting high data rate modulations increase.
SUMMARY
The present disclosure has been made to address at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the present disclosure provides a method for implementing a back-off policy to keep a constant EVM in the case of antenna mismatch.
According to an aspect of the present disclosure, a method is provided for adjusting a transmission gain in a transmitter of an electronic device. A transmitted signal is received at a digital signal processor (DSP) of the transmitter. The transmitted signal is also transmitted through a transmission path of the transmitter resulting in a load impedance. A looped-back signal is received at the DSP via a loop-back path of the transmitter that returns from the transmission path. The DSP estimates the load impedance from the transmitted signal and the looped-back signal. The DSP sets the transmission gain of the transmission path based on the load impedance and saturation values for a load current and a load voltage.
According to another aspect of the present disclosure, an apparatus is provided for adjusting a transmission gain in a transmitter of an electronic device. The apparatus includes a first plurality of circuit components comprising a transmission path for transmitting a transmitted signal and resulting in a load impedance. The apparatus also includes a second plurality of circuit components comprising loop-back path that returns a looped-back signal from the transmission path. The apparatus further includes a DSP configured to receive the transmitted signal and the looped-back signal, estimate the load impedance from the transmitted signal and the looped-back signal, and set the transmission gain of the transmission path based on the load impedance and saturation values for a load current and a load voltage.
According to a further aspect of the present disclosure, a non-transitory computer readable medium is provided with computer executable instructions stored thereon executed by a processor to perform the method of adjusting a transmission gain in a transmitter of an electronic device. The method includes receiving a transmitted signal. The transmitted signal is also transmitted through a transmission path of transmitter resulting in a load impedance. The method also includes receiving a looped-back signal via a loop-back path of the transmitter that returns from the transmission path. The method further includes estimating the load impedance from the transmitted signal and the looped-back signal. The method additionally includes setting the transmission gain of the transmission path based on the load impedance and saturation values for a load current and a load voltage.



BRIEF DESCRIPTION OF THE DRAWINGS
The above and other aspects, features and advantages of the present disclosure will be more apparent from the following description when taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a diagram illustrating a circuit architecture including a loop-back path, according to an embodiment of the present disclosure;
FIG. 2 is a diagram illustrating a simplified transmission path of FIG. 1, according to an embodiment of the present disclosure; and
FIG. 3 is a flowchart illustrating a method of adjusting transmission gain in a transmitter of an electronic device, according to an embodiment of the present disclosure.



DETAILED DESCRIPTION OF EMBODIMENTS OF THE PRESENT DISCLOSURE
Embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The same or similar components may be designated by the same or similar reference numerals although they are illustrated in different drawings. Detailed descriptions of constructions or processes known in the art may be omitted to avoid obscuring the subject matter of the present disclosure.
The terms and words used in the following description and claims are not limited to their dictionary meanings, but are merely used to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of embodiments of the present disclosure are provided for illustrative purposes only and not for the purpose of limiting the invention, as defined by the appended claims and their equivalents.
Although the terms including an ordinal number such as first, second, etc. may be used for describing various elements, the structural elements are not restricted by the terms. The terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first structural element may be referred to as a second structural element. Similarly, the second structural element may also be referred to as the first structural element. As used herein, the term “and/or” includes any and all combinations of one or more associated items.
It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “an identifier” includes reference to one or more such identifiers.
In the present disclosure, it should be understood that the terms “include” or “have” indicate existence of a feature, a number, a step, an operation, a structural element, parts, or a combination thereof, and do not exclude the existence or probability of additional one or more other features, numerals, steps, operations, structural elements, parts, or combinations thereof.
Embodiments of the present disclosure solve the problem of antenna mismatch using DSP techniques, which allow for a predictably-bounded and programmable transmitted EVM, while avoiding the use of dedicated matching networks and external components, such as, for example, isolators and tunable inductors or capacitors.
Specifically, embodiments of the present disclosure make use of a loop-back path that senses the voltage exercised into the load while transmitting a known signal. By measuring the time-varying amplitude of the looped-back signal, the transmitter is able to derive both the amplitude and the phase-shift of the looped-back signal. When the amplitude and the phase-shift are known, they can be used with the source impedance and the source voltage of the amplifier to derive the complex load impedance.
Load voltage and current can be derived from the load impedance. Assuming EVM that is dependent upon clipping of both voltage and current on the load, it is possible to set the transmission gain so that neither the voltage nor the current exceed their saturation values. Accordingly, a Transmit-Power-Control (TPC) policy may be defined based on meeting a target EVM requirement.
FIG. 1 is a diagram illustrating a circuit architecture including a loop-back path, according to an embodiment of the present disclosure.
The circuit architecture of FIG. 1 includes a transmitted signal 100, a transmission path 102, and a loop-back path 104. The transmission path 102 includes a Digital-to-Analog Converter (DAC) 106, a programmable gain amplifier 108, and a Power Amplifier (PA) 110. The programmable gain may be implemented in either a digital or an analog domain. The PA has a fixed nominal gain. Other components, which may be included in a radio transmitter architecture (i.e., an up-conversion mixer), may not be required for embodiments of the present invention.
The DAC 106 may be provided with a base-band waveform that is a constant-envelope complex tone generator, as shown in Equation (1), if the loop-back path 104 is a Cartesian demodulator with a quadrature downmixer. The DAC 106 may be provided with a base-band waveform that is an envelope-modulated sine wave, as shown in Equation (2), if the loop-back path 104 is an envelope demodulator.

x(t)=ejωIFt  (1)

x(t)=A(t)·sin(ωIFt)  (2)

where t is time, ωIF is an angular frequency of the intermediate frequency (IF) signal, and A(t) is envelope modulation.

A load impedance ZL 112 is applied, which is influenced by the elements of the transmission path 102 from the chip to the antenna, including matching components, switches, and filters.
The loop-back path 104 includes a multiplexer (MUX) 114, a Loop Back amplifier (LB) 116, and an Analog-to-Digital Converter (ADC) 118. The loop-back path 104 may also include a down-mixer. The loop-back path 104 detects the time-varying amplitude of an input signal, so that its amplitude and phase-shift with respect to the source signal can be evaluated. The loop-back path 104 may be a dedicated loop-back path, may use an available receiving (RX) path, or may use a dedicated envelope modulator.
The MUX 114 allows the voltage output from the PA 110 to be compared with a reference voltage (VREF) 120, by selecting one of the output voltage and the VREF 120. The VREF 120 must be stable over Process, Voltage, and Temperature (PVT) variations.
Both the transmitted signal 100, which is input to the transmission path 102, and a signal output from the feedback path 104 are provided to a DSP 122, which may be implemented as hardware, software, or a combination of hardware and software. The DSP 122 evaluates the static amplitude of the loop-back signal |VL| and the phase shift between the transmitted and the looped-back signals, φL.
The phase shift φL may be extracted by comparing the time-delay between the source generator signal VS(t) and the load voltage VL(t). The phase shift φL will contain phase shift contributions due to the delays introduced by both the transmit phase shift φTX and the loop-back phase shift φLB, which must be taken into account. The transmit phase shift φTX and the loop-back phase shift φLB can be known by design or may be measured as the round-trip delay phase shift φLO when the load is matched (ZL=ZLO), resulting in Equation (3) below.

φLO=φTX+φLB  (3)

Embodiments of the present disclosure estimate the load impedance using the amplitude and the phase of the voltage on the load. Once the load impedance is known, the load current and load voltage can also be estimated. When an EVM is assumed that is correlated to clipping both the voltage and the current on the load to VSAT and ISAT, respectively, the maximum gain that can be applied to match the target EVM can be estimated using a simple EVM model.
In order to simplify the calculation, the load amplitude is indirectly inferred in the digital domain from the gain GREF that must be applied to the transmission path 102 in order to match VREF. However, the transmit gain is sensitive to parameters other than load impedance, such as, for example, temperature, process variation, and operating frequency. Therefore, a reference measure of transmit gain in well-defined known conditions (i.e., matched impedance, T=25° C., f=2.442 GHz) is required.
In further simplifying the calculation, the load saturation voltage and the load saturation current can be expressed as gain coefficients GVSAT and GISAT, respectively, characterized under particular load conditions, when EVM matches the target EVM.
Accordingly, the transmit path of FIG. 1 may be more simplistically represented as set forth in FIG. 2, according to an embodiment of the present invention.
As shown in FIG. 2, a source voltage VS 202 has a variable amplitude controlled by the programmable gain amplifier. A source impedance ZS 204 may be known through measurement or design. A load impedance ZL 206 is to be estimated.
A complex voltage VL on the load impedance ZL 206 is expressed as set forth in Equation (4), with the source voltage Vs as a phase reference.

VL=|VL|·ej(φL−φLO)  (4)

A definition of the load impedance ZL is set forth in Equation (5) below.




  
    
      
        
          Z
          L
        
        ⁢
        
          =
          △
        
        ⁢
        
          
            V
            L
          
          
            I
            L
          
        
      
    
    
      
        (
        5
        )
      
    
  




Further, a definition of the load current IL is set forth in Equation (6) below.




  
    
      
        
          I
          L
        
        =
        
          
            
              V
              S
            
            -
            
              V
              L
            
          
          
            Z
            S
          
        
      
    
    
      
        (
        6
        )
      
    
  




Thus, the load impedance ZL is derived as a function of two measurable variables, i.e., the static amplitude |VL| of the loop-back signal and the phase shift φL between the transmitted signal and the loop-back signal, as set forth in Equation (7) below.




  
    
      
        
          Z
          L
        
        =
        
          
            
              Z
              S
            
            ·
            
              
              
                V
                L
              
              
            
            ·
            
              e
              
                j
                ⁡
                
                  (
                  
                    
                      φ
                      L
                    
                    -
                    
                      φ
                      
                        L
                        ⁢
                        
                          
                        
                        ⁢
                        0
                      
                    
                  
                  )
                
              
            
          
          
            
              V
              S
            
            -
            
              
                
                
                  V
                  L
                
                
              
              ·
              
                e
                
                  j
                  ⁡
                  
                    (
                    
                      
                        φ
                        L
                      
                      -
                      
                        φ
                        
                          L
                          ⁢
                          
                            
                          
                          ⁢
                          0
                        
                      
                    
                    )
                  
                
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




Due to PVT variations, both the source voltage VS and the source impedance ZS may vary on a per-device basis. An indirect method that characterizes the device based on the matched load ZLO tracks the variations.
Regardless of PVT, it is possible to provide an accurate RF voltage reference VREF that can be compared to the signal levels in the chain. VS can be regulated by means of the transmit gain G as set forth in Equation (8).

VS=VLSB·G  (8)

VLSB is a voltage step resulting from each gain step. Thus, GREF is defined as set forth in Equation (9).

GREFG||VS|=VVREF  (9)

Substituting GREF into Equation (8) results in Equation (10).

VREF=VLSB·GREF  (10)

From Equation (10), the gain step, or voltage step, VLSB can be derived as set forth in Equation (11).




  
    
      
        
          V
          LSB
        
        =
        
          
            V
            REF
          
          
            G
            REF
          
        
      
    
    
      
        (
        11
        )
      
    
  




By substituting Equation (11) into Equation (8) the source voltage VS can be obtained as a result of the generic applied gain G, as shown in Equation (12).




  
    
      
        
          V
          S
        
        =
        
          
            
              V
              REF
            
            
              G
              REF
            
          
          ·
          G
        
      
    
    
      
        (
        12
        )
      
    
  




Similarly, when applying the matched load ZLO, which can be chosen close to the nominal impedance value of 50Ω, to the device, a digital gain for matched load is set forth in Equation (13).

GLOG||VL|=VREF,ZL=ZLO  (13)

With the above-described conditions, which result in (φL=φLO if ZL=ZLO), the load impedance ZL of Equation (7) can be simplified as set forth in Equation (14).




  
    
      
        
          Z
          
            L
            ⁢
            
              
            
            ⁢
            0
          
        
        =
        
          
            
              Z
              S
            
            ·
            
              V
              REF
            
          
          
            
              
                
                  V
                  REF
                
                
                  G
                  REF
                
              
              ·
              
                G
                
                  L
                  ⁢
                  
                    
                  
                  ⁢
                  0
                
              
            
            -
            
              V
              REF
            
          
        
      
    
    
      
        (
        14
        )
      
    
  




Accordingly, as set forth in Equation (15):




  
    
      
        
          
            Z
            S
          
          
            Z
            
              L
              ⁢
              
                
              
              ⁢
              0
            
          
        
        =
        
          
            
              G
              
                L
                ⁢
                
                  
                
                ⁢
                0
              
            
            
              G
              REF
            
          
          -
          1
        
      
    
    
      
        (
        15
        )
      
    
  




Defining the gain GL as the gain that must be applied for VL, to match VREF (|VL|=VREF), when the generic load impedance ZL is applied, results in Equation (16). However, this may not be achievable for all load conditions, e.g., a short circuit.

GL(ZL)G||VL|=VREF  (16)

Accordingly, Equation (7) may be written as Equation (17) below.




  
    
      
        
          Z
          L
        
        =
        
          
            
              Z
              s
            
            ·
            
              V
              REF
            
            ·
            
              e
              
                j
                ⁡
                
                  (
                  
                    
                      φ
                      L
                    
                    -
                    
                      φ
                      
                        L
                        ⁢
                        
                          
                        
                        ⁢
                        0
                      
                    
                  
                  )
                
              
            
          
          
            
              
                
                  V
                  REF
                
                
                  G
                  REF
                
              
              ·
              
                G
                L
              
            
            -
            
              
                V
                REF
              
              ·
              
                e
                
                  j
                  ⁡
                  
                    (
                    
                      
                        φ
                        L
                      
                      -
                      
                        φ
                        
                          L
                          ⁢
                          
                            
                          
                          ⁢
                          0
                        
                      
                    
                    )
                  
                
              
            
          
        
      
    
    
      
        (
        17
        )
      
    
  




When both sides of Equation (17) are divided by ZLO,




  
    Z
    S
  
  
    Z
    
      L
      ⁢
      
        
      
      ⁢
      0
    
  




is substituted from Equation (15), and VREF is simplified, Equation (18) is derived, as set forth below.





  
    
      
        
          
            Z
            L
          
          
            Z
            
              L
              ⁢
              
                
              
              ⁢
              0
            
          
        
        =
        
          
            
              (
              
                
                  
                    G
                    
                      L
                      ⁢
                      
                        
                      
                      ⁢
                      0
                    
                  
                  
                    G
                    REF
                  
                
                -
                1
              
              )
            
            ·
            
              e
              
                j
                ⁡
                
                  (
                  
                    
                      φ
                      L
                    
                    -
                    
                      φ
                      
                        L
                        ⁢
                        
                          
                        
                        ⁢
                        0
                      
                    
                  
                  )
                
              
            
          
          
            
              
                G
                L
              
              
                G
                REF
              
            
            -
            
              
                e
                j
              
              ⁡
              
                (
                
                  
                    φ
                    L
                  
                  -
                  
                    φ
                    
                      L
                      ⁢
                      
                        
                      
                      ⁢
                      0
                    
                  
                
                )
              
            
          
        
      
    
    
      
        (
        18
        )
      
    
  




Using Equation (18), a generic applied impedance ZL may be estimated from the gain GL and the phase delay φL observed by the chip, provided that an initial characterization on a known reference impedance ZLO results in a similarly evaluated gain GLO and phase φLO.
In general, an amplifier can provide a limited maximum voltage VSAT and a limited maximum current ISAT, which, when exceeded by increasing the transmit gain by too much, results in higher signal distortion and increased EVM. In order to define a gain control policy that provides constant EVM over impedance variations, it is necessary to guarantee that the load voltage and the load current will not exceed the saturation values, as set forth in Equation (19).




  
    
      
        {
        
          
            
              
                
                  
                  
                    V
                    S
                  
                  
                
                <
                
                  V
                  SAT
                
              
            
          
          
            
              
                
                  
                  
                    I
                    L
                  
                  
                
                <
                
                  I
                  SAT
                
              
            
          
        
      
    
    
      
        (
        19
        )
      
    
  




Despite the fact that VSAT and ISAT could be known by design, the two saturation phenomena are always present to some extent, and depending on the likeliness of signal clipping (i.e., saturation), EVM will be degraded. Therefore, saturation values must be defined that correlate with the target EVM (EVMT).
For example, the EVM due to voltage and current may be limited to √{square root over (2)} less than the target EVM to ensure that the target EVM is not exceeded for any load conditions, as set forth in Equation (20).




  
    
      
        
          EVM
          T
        
        =
        
          
            
              
                EVM
                V
                2
              
              +
              
                EVM
                I
                2
              
            
          
          =
          
            
              2
            
            ·
            
              
                EVM
                V
              
              ⁡
              
                (
                
                  
                    assuming
                    ⁢
                    
                      
                    
                    ⁢
                    
                      EVM
                      V
                    
                  
                  =
                  
                    EVM
                    I
                  
                
                )
              
            
          
        
      
    
    
      
        (
        20
        )
      
    
  




This is further expressed in dB in Equation (21) below.

EVMV=EVMT−3 dB  (21)

Assuming EVM will be limited mostly by VSAT when ZL=ZMAX (|ZMAX|>|ZLO|), and EVM will be limited mostly by ISAT when ZL=Zmin (|Z↓MIN|<|Z↓LO|), the saturation voltages and currents are defined as set forth in Equation (22).




  
    
      
        {
        
          
            
              
                
                  V
                  SAT
                
                ⁢
                
                  =
                  △
                
                ⁢
                
                  
                    V
                    L
                  
                  ⁢
                  
                    |
                    
                      
                        EVM
                        =
                        
                          EVM
                          V
                        
                      
                      ,
                      
                        
                          Z
                          L
                        
                        =
                        
                          Z
                          MAX
                        
                      
                    
                  
                
              
            
          
          
            
              
                
                  I
                  SAT
                
                ⁢
                
                  =
                  △
                
                ⁢
                
                  
                    I
                    L
                  
                  ⁢
                  
                    |
                    
                      
                        EVM
                        =
                        
                          EVM
                          I
                        
                      
                      ,
                      
                        
                          Z
                          L
                        
                        =
                        
                          Z
                          min
                        
                      
                    
                  
                
              
            
          
        
      
    
    
      
        (
        22
        )
      
    
  




ZMAX and ZMIN can be derived by defining a maximum tolerable Voltage Standing Wave Ratio (VSWR), as set forth in Equation (23).




  
    
      
        
          
            
              Z
              MAX
            
            
              Z
              0
            
          
          =
          VSWR
        
        ,
        
          
            
              Z
              min
            
            
              Z
              0
            
          
          =
          
            1
            VSWR
          
        
      
    
    
      
        (
        23
        )
      
    
  




Thus, the saturation values may be defined as set forth in Equation (24).




  
    
      
        {
        
          
            
              
                
                  V
                  S
                
                =
                
                  
                    
                      V
                      REF
                    
                    
                      G
                      REF
                    
                  
                  ·
                  G
                
              
            
          
          
            
              
                
                  I
                  L
                
                =
                
                  
                    V
                    S
                  
                  ·
                  
                    1
                    
                      
                        Z
                        L
                      
                      +
                      
                        Z
                        S
                      
                    
                  
                
              
            
          
        
      
    
    
      
        (
        24
        )
      
    
  




Through a substitution of Equations (12), (15), and (18), Equation (25) results, as set forth below.




  
    
      
        {
        
          
            
              
                
                  
                    V
                    S
                  
                  
                    V
                    REF
                  
                
                =
                
                  G
                  
                    G
                    REF
                  
                
              
            
          
          
            
              
                
                  
                    I
                    L
                  
                  
                    (
                    
                      
                        
                          (
                          V
                          )
                        
                        REF
                      
                      
                        Z
                        
                          L
                          ⁢
                          
                            
                          
                          ⁢
                          0
                        
                      
                    
                    )
                  
                
                =
                
                  
                    G
                    
                      G
                      REF
                    
                  
                  ·
                  
                    1
                    
                      
                        (
                        
                          
                            
                              G
                              
                                L
                                ⁢
                                
                                  
                                
                                ⁢
                                0
                              
                            
                            
                              G
                              REF
                            
                          
                          -
                          1
                        
                        )
                      
                      +
                      
                        
                          Z
                          L
                        
                        
                          Z
                          
                            L
                            ⁢
                            
                              
                            
                            ⁢
                            0
                          
                        
                      
                    
                  
                
              
            
          
        
      
    
    
      
        (
        25
        )
      
    
  




By applying Equation (22), VSAT and ISAT may be indirectly estimated in Equation (28) from the saturation gains in Equation (27).




  
    
      
        {
        
          
            
              
                
                  G
                  VSAT
                
                ⁢
                
                  =
                  △
                
                ⁢
                
                  G
                  ⁢
                  
                    |
                    
                      
                        EVM
                        =
                        
                          EVM
                          V
                        
                      
                      ,
                      
                        
                          Z
                          L
                        
                        =
                        
                          Z
                          MAX
                        
                      
                    
                  
                
              
            
          
          
            
              
                
                  G
                  ISAT
                
                ⁢
                
                  =
                  △
                
                ⁢
                
                  G
                  ⁢
                  
                    |
                    
                      
                        EVM
                        =
                        
                          EVM
                          I
                        
                      
                      ,
                      
                        
                          Z
                          L
                        
                        =
                        
                          Z
                          min
                        
                      
                    
                  
                
              
            
          
        
      
    
    
      
        (
        27
        )
      
    
  








  
    
      
        {
        
          
            
              
                
                  
                    V
                    S
                  
                  
                    V
                    REF
                  
                
                =
                
                  
                    G
                    VSAT
                  
                  
                    G
                    REF
                  
                
              
            
          
          
            
              
                
                  
                    I
                    SAT
                  
                  
                    (
                    
                      
                        
                          (
                          V
                          )
                        
                        REF
                      
                      
                        Z
                        
                          L
                          ⁢
                          
                            
                          
                          ⁢
                          0
                        
                      
                    
                    )
                  
                
                =
                
                  
                    
                      
                        G
                        ISAT
                      
                      
                        G
                        REF
                      
                    
                    ·
                    
                      1
                      
                        
                          (
                          
                            
                              
                                G
                                
                                  L
                                  ⁢
                                  
                                    
                                  
                                  ⁢
                                  0
                                
                              
                              
                                G
                                REF
                              
                            
                            -
                            1
                          
                          )
                        
                        +
                        
                          
                            Z
                            min
                          
                          
                            Z
                            
                              L
                              ⁢
                              
                                
                              
                              ⁢
                              0
                            
                          
                        
                      
                    
                  
                  ≈
                  
                    
                      
                        G
                        ISAT
                      
                      
                        G
                        REF
                      
                    
                    
                      
                        
                          G
                          
                            L
                            ⁢
                            
                              
                            
                            ⁢
                            0
                          
                        
                        
                          G
                          REF
                        
                      
                      -
                      1
                    
                  
                
              
            
          
        
      
    
    
      
        (
        
          ...
          ⁡
          
            (
            28
            )
          
        
      
    
  




The condition of Equation (29) is imposed, which is normalized as shown in Equation (30).




  
    
      
        {
        
          
            
              
                
                  
                  
                    
                      V
                      S
                    
                    ⁡
                    
                      (
                      G
                      )
                    
                  
                  
                
                <
                
                  V
                  SAT
                
              
            
          
          
            
              
                
                  
                  
                    
                      I
                      L
                    
                    ⁡
                    
                      (
                      G
                      )
                    
                  
                  
                
                <
                
                  I
                  SAT
                
              
            
          
        
      
    
    
      
        (
        29
        )
      
    
  








  
    
      
        {
        
          
            
              
                
                  
                    
                    
                      
                        V
                        S
                      
                      ⁡
                      
                        (
                        G
                        )
                      
                    
                    
                  
                  
                    V
                    REF
                  
                
                <
                
                  
                    G
                    VSAT
                  
                  
                    G
                    REF
                  
                
              
            
          
          
            
              
                
                  
                    
                    
                      
                        I
                        L
                      
                      ⁡
                      
                        (
                        G
                        )
                      
                    
                    
                  
                  
                    (
                    
                      
                        
                          (
                          V
                          )
                        
                        REF
                      
                      
                        Z
                        
                          L
                          ⁢
                          
                            
                          
                          ⁢
                          0
                        
                      
                    
                    )
                  
                
                <
                
                  
                    
                      G
                      ISAT
                    
                    
                      G
                      REF
                    
                  
                  
                    
                      
                        G
                        
                          L
                          ⁢
                          
                            
                          
                          ⁢
                          0
                        
                      
                      
                        G
                        REF
                      
                    
                    -
                    1
                  
                
              
            
          
        
      
    
    
      
        (
        30
        )
      
    
  




By substituting Equation (18) into Equation (25), Equation (31) is obtained, as set forth below.




  
    
      
        
          
            I
            L
          
          
            (
            
              
                
                  (
                  V
                  )
                
                REF
              
              
                Z
                
                  L
                  ⁢
                  
                    
                  
                  ⁢
                  0
                
              
            
            )
          
        
        =
        
          
            
              G
              
                G
                L
              
            
            
              (
              
                
                  
                    G
                    
                      L
                      ⁢
                      
                        
                      
                      ⁢
                      0
                    
                  
                  
                    G
                    REF
                  
                
                -
                1
              
              )
            
          
          ·
          
            [
            
              
                
                  G
                  L
                
                
                  G
                  REF
                
              
              -
              
                e
                
                  j
                  ⁡
                  
                    (
                    
                      
                        φ
                        L
                      
                      -
                      
                        φ
                        
                          L
                          ⁢
                          
                            
                          
                          ⁢
                          0
                        
                      
                    
                    )
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        31
        )
      
    
  




By replacing the left side of Equation (30) with the right side of Equation (31) and rearranging, Equation (32) is obtained, as set forth below.




  
    
      
        {
        
          
            
              
                G
                <
                
                  G
                  VSAT
                
              
            
          
          
            
              
                G
                <
                
                  
                    G
                    ISAT
                  
                  ·
                  
                    
                    
                      
                        
                          G
                          L
                        
                        
                          G
                          REF
                        
                      
                      
                        
                          
                            G
                            L
                          
                          
                            G
                            REF
                          
                        
                        -
                        
                          e
                          
                            j
                            ⁡
                            
                              (
                              
                                
                                  φ
                                  L
                                
                                -
                                
                                  φ
                                  
                                    L
                                    ⁢
                                    
                                      
                                    
                                    ⁢
                                    0
                                  
                                
                              
                              )
                            
                          
                        
                      
                    
                    
                  
                
              
            
          
        
      
    
    
      
        (
        32
        )
      
    
  




Therefore, Equation (33) can be defined, from which an EVM-compliant target gain GT may be chosen, as set forth in Equation (34).




  
    
      
        {
        
          
            
              
                
                  G
                  VSAT
                
                ⁢
                
                  =
                  △
                
                ⁢
                
                  G
                  VMAX
                
              
            
          
          
            
              
                
                  
                    G
                    ISAT
                  
                  ·
                  
                    
                    
                      
                        
                          G
                          L
                        
                        
                          G
                          REF
                        
                      
                      
                        
                          
                            G
                            L
                          
                          
                            G
                            REF
                          
                        
                        -
                        
                          e
                          
                            j
                            ⁡
                            
                              (
                              
                                
                                  φ
                                  L
                                
                                -
                                
                                  φ
                                  
                                    L
                                    ⁢
                                    
                                      
                                    
                                    ⁢
                                    0
                                  
                                
                              
                              )
                            
                          
                        
                      
                    
                    
                  
                
                ⁢
                
                  =
                  △
                
                ⁢
                
                  G
                  IMAX
                
              
            
          
        
      
    
    
      
        (
        33
        )
      
    
  




GT=min(GVMAX,GIMAX)  (34)

The above-described equations are valid in a general case where the phase variation φL-φLO between the voltage on the generic load ZL and the reference load ZLO may be estimated. However, retrieving the phase information requires dedicated hardware components, such as, for example, a quadrature feedback path (i.e., a down-conversion mixer), and DSP processing capabilities allowing for a coherent input-output operation, which may not be as easily available as simple amplitude-feedback (which could be obtained by a less complex Amplitude Modulation (AM)-demodulator). Therefore, in another embodiment of the present disclosure, pessimistic assumptions are made with respect to the phase information, and thus, the phase information is not required.
Accordingly, the minimum possible value is chosen for GIMAX in Equation (33), which becomes Equation (35) below, and the control policy of Equation (34) is still valid.




  
    
      
        {
        
          
            
              
                
                  G
                  VSAT
                
                ⁢
                
                  =
                  △
                
                ⁢
                
                  G
                  VMAX
                
              
            
          
          
            
              
                
                  
                    G
                    ISAT
                  
                  ·
                  
                    
                      G
                      L
                    
                    
                      
                        G
                        L
                      
                      +
                      
                        G
                        REF
                      
                    
                  
                
                ⁢
                
                  =
                  △
                
                ⁢
                
                  G
                  IMAX
                
              
            
          
        
      
    
    
      
        (
        35
        )
      
    
  




FIG. 3 is a flowchart illustrating a method of adjusting transmission gain in a transmitter of an electronic device, according to an embodiment of the present disclosure.
Referring to FIG. 3, it is assumed that a system is calibrated with a known load, allowing GREF and φLO to be determined. The DSP of the transmitter receives a transmit signal prior to a transmission path, in step 302. The transmit signal is also transmitted through a transmission path of the transmitter. In step 304, the DSP receives a looped-back signal via a loop-back path of the transmitter. The loop-back path returns from the transmission path, and the looped-back signal is chosen from an output of the power amplifier of the transmission path and a reference voltage, as shown in FIG. 1.
In step 306, the DSP measures a time-varying amplitude of the looped-back signal. Steps 304 and 306 are iterative, and the gain will be adjusted until the amplitude of the looped signal matches VREF. The final gain is GL. In step 308, the DSP derives an amplitude and a phase shift of the looped-back signal from the time-varying amplitude.
In step 310, the DSP obtains a source impedance and a source voltage from the transmitted signal. In step 312, the DSP estimates the load impedance from the amplitude of the looped-back signal, the phase shift of the looped-back signal, the source impedance, and the source voltage. In step 314, the DSP derives the load voltage and the load current of the transmitted signal from the load impedance. Steps 310, 312, and 314 may not be explicitly performed, when just the gain and phase measurements are required to set an appropriate gain, as shown above in Equations (33) and (34).
In step 316, the transmission gain is set so that the saturation values for the load current and the load voltage are not exceeded.
Embodiments of the present disclosure correct antenna mismatch using DSP techniques, allowing for predictably-bounded and programmable transmitted EVM, while avoiding the use of dedicated matching networks, and external components, such as, for example, isolators and tunable inductors/capacitors.
Embodiments of the present disclosure are advantageous in that there are no external components required, there is no dedicated analog circuitry required, and the PA bias current is not used to modulate transmission gain.
A hardware implementation of a computer system may be implemented in accordance with a processor, a memory, input/output devices, a network interface, and a computer bus.
The term “processor”, as used herein, is intended to include any processing device, such as, for example, one that includes a Central Processing Unit (CPU) and/or other processing circuitry. It is also to be understood that the term “processor” may refer to more than one processing device and that various elements associated with a processing device may be shared by other processing devices.
The term “memory”, as used herein, is intended to include a memory associated with a processor or CPU, such as, for example a Random Access Memory (RAM), a Read Only Memory (ROM), a fixed memory device (e.g., a hard drive), a removable memory device, a flash memory, etc.
In addition, the phrase “input/output devices”, as used herein, is intended to include, for example, one or more input devices for entering information, and/or one or more output devices for outputting information.
Software components including instructions or code for performing the methodologies described herein, may be stored in one or more of the associated memory devices (e.g., ROM), and when ready to be utilized, loaded in part or in whole (e.g., into the RAM) and executed by a CPU. Specifically, a non-transitory computer readable medium may be provided with computer executable instructions stored thereon and executed by a processor to perform the methods of embodiments of the present invention.
The present disclosure may be utilized in conjunction with the manufacture of integrated circuits, which are considered part of this invention.
While the disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

## Claims

1. A method of adjusting a transmission gain in a transmitter of an electronic device, the method comprising:
receiving a transmitted signal at a digital signal processor (DSP) of the transmitter, the transmitted signal also being transmitted through a transmission path of the transmitter resulting in a load impedance;
receiving a looped-back signal at the DSP via a loop-back path of the transmitter that returns from the transmission path;
estimating, at the DSP, the load impedance from the transmitted signal and the looped-back signal; and
setting, by the DSP, the transmission gain of the transmission path based on the load impedance and saturation values for a load current and a load voltage.

2. The method of claim 1, wherein the transmission path comprises at least a digital-to-analog converter, a programmable gain amplifier, and a power amplifier.

3. The method of claim 2, wherein the looped-back path comprises at least a multiplexer and an analog-to-digital converter.

4. The method of claim 3, wherein the multiplexer allows a comparison of output of the power amplifier and a reference voltage, by selecting the looped-back signal from one of the output of the power amplifier and the reference voltage.

5. The method of claim 1, wherein estimating the load impedance comprises:
measuring a time-varying amplitude of the looped-back signal;
deriving an amplitude and a phase shift of the looped-back signal from the time-varying amplitude;
setting the transmit gain based on the amplitude of the looped-back signal, the phase shift of the looped-back signal, a source impedance, and a source voltage.

6. The method of claim 1, wherein setting the transmission gain comprises:
deriving the load current of the transmitted signal from the load impedance; and
setting the transmission gain so that the resulting saturation values for the load current and the load voltage are not exceeded.

7. The method of claim 6, wherein the transmission gain is set to a maximum value permitted to match a target Error Vector Magnitude (EVM) without exceeding the resulting saturation values for the load current and the load voltage.

8. The method of claim 1, wherein the loop-back path is one of a dedicated loop-back path, a receiving path, and a dedicated envelope demodulator.

9. The method of claim 5, wherein the amplitude is inferred from a gain applied to the transmission path to match a reference voltage.

10. The method of claim 1, wherein a constant Error Vector Magnitude (EVM) is provided over load impedance variations.

11. An apparatus for adjusting a transmission gain in a transmitter of an electronic device, the apparatus comprising:
a first plurality of circuit components comprising a transmission path for transmitting a transmitted signal and resulting in a load impedance;
a second plurality of circuit components comprising a loop-back path that returns a looped-back signal from the transmission path; and
a digital signal processor (DSP) configured to receive the transmitted signal and the looped-back signal, estimate the load impedance from the transmitted signal and the looped-back signal, and set the transmission gain of the transmission path based on the load impedance and saturation values for a load current and a load voltage.

12. The apparatus of claim 11, wherein the first plurality of circuit components comprises at least a digital-to-analog converter, a programmable gain amplifier, and a power amplifier.

13. The apparatus of claim 12, wherein the second plurality of circuit components comprises at least a multiplexer and an analog-to-digital converter.

14. The apparatus of claim 13, wherein the multiplexer is configured to allow comparison of output of the power amplifier and a reference voltage, by selecting the looped-back signal from one of the output of the power amplifier and the reference voltage.

15. The apparatus of claim 11, wherein, in estimating the load impedance, the DSP is further configured to:
measure a time-varying amplitude of the looped-back signal;
derive an amplitude and a phase shift of the looped-back signal from the time-varying amplitude; and
setting the transmit gain based on the amplitude of the looped-back signal, the phase shift of the looped-back signal, the source impedance, and the source voltage.

16. The apparatus of claim 11, wherein, in setting the transmission gain, the DSP is further configured to:
derive the load current resulting from the transmitted signal from the load impedance; and
set the transmission gain so that the saturation values for the load current and the load voltage are not exceeded.

17. The apparatus of claim 16, wherein the transmission gain is set to a maximum value permitted to match a target Error Vector Magnitude (EVM) without exceeding the saturation values for the load current and the load voltage.

18. The apparatus of claim 11, wherein the loop-back path is one of a dedicated loop-back path, a receiving path, and a dedicated envelope demodulator.

19. The apparatus of claim 15, wherein the amplitude is inferred from a gain applied to the transmission path to match a reference voltage.

20. A non-transitory computer readable medium with computer executable instructions stored thereon executed by a processor to perform the method of adjusting a transmission gain in a transmitter of an electronic device, the method comprising:
receiving a transmitted signal, the transmitted signal also being transmitted through a transmission path of the transmitter resulting in a load impedance;
receiving a looped-back signal via a loop-back path of the transmitter that returns from the transmission path;
estimating the load impedance from the transmitted signal and the looped-back signal; and
setting the transmission gain of the transmission path based on the load impedance and saturation values for a load current and a load voltage.