# Patent

## Title
Efficient packet handling, redirection, and inspection using offload processors

## Abstract

A packet handling system is disclosed that can include at least one main processor; a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, the virtual switch configured to receive memory read/write data over the memory bus.

## Background
PRIORITY CLAIMS
This application claims the benefit of U.S. Provisional Patent Application 61/650,373 filed May 22, 2012, the contents of which are incorporated by reference herein.


TECHNICAL FIELD
The present disclosure relates generally to servers capable of efficiently handling routine packet inspection or other tasks without direction from a main processor. More particularly, systems supporting offload or auxiliary processing modules that can be physically connected to a system memory bus to process packet data independent of a host processor of the server are described.
BACKGROUND
Packet handling and security applications can require a significant amount of scarce computational resources in enterprise server or cloud based data systems. These can include services such as packet repeaters, intrusion detection systems (IDS), intrusion protection systems (IPS), and routing mechanisms for virtual private networks (VPNs). Many proprietary and incompatible hardware systems are available for such packet handling and transport services, but cost and a desire for standardization pushes enterprise data storage and processing providers toward software defined stacks running on commodity (e.g., x86 architecture) hardware.
Unfortunately, processors based on x86 architectures are ill-equipped to handle such high volume applications. Even idling, x86 processors use a significant amount of power, and near continuous operation for high bandwidth packet analysis functionality make the processor energy costs one of the dominate price factors. In addition, issues with the high cost of context switching, the limited parallelism, and the security implications associated with running encryption/decryption modules on x86 processors have reduced the effectiveness of enterprise or cloud data security.
SUMMARY
A packet handling system can include at least one main processor; a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, the virtual switch configured to receive memory read/write data over the memory bus.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows an embodiment with two computers which can be rack servers connected over a network interface such as an Ethernet-type interface.
FIG. 2 shows module according to an embodiment (referred to as a XIMM module) in more detail acting as a part of the second server.
FIG. 3-1 illustrates an embodiment with software stacks respectively running on a XIMM module and an x86-based server processor.
FIG. 3-2 illustrates an embodiment with software stacks described in FIG. 3-1 operating in the context of two servers communicating over an Ethernet-type connection
FIG. 4-1 shows a cartoon schematically illustrating a data processing system according to an embodiment, including a removable computation module for offload of data processing.
FIG. 4-2 shows an example layout of a XIMM module according to an embodiment.
FIG. 4-3 shows two possible architectures for a XIMM module in a simulation (Xockets MAX and MIN).
FIG. 4-4 shows a representative the power budget for an example of a Xockets XIMM.
FIG. 4-5 illustrates data flow operations of one embodiment using an ARM A9 architecture according to an embodiment.



DETAILED DESCRIPTION
Packet handling and security applications for enterprise server or cloud based data systems can be efficiently implemented on offload processing modules connected to a memory bus, for example, by insertion into a socket for a Dual In-line Memory Module (DIMM). Such modules can be referred to as a XocketTM In-line Memory Modules (XIMMs), and can have multiple “wimpy” cores associated with a memory channel. Using one or more XIMMs it is possible to execute lightweight packet handling tasks without intervention from a main server processor. As will be discussed, XIMM modules can have high efficiency context switching, high parallelism, and can solve security problems associated with running encryption/decryption modules on x86 processors. Such systems as a whole are able to handle high network bandwidth traffic at a lower latency and at a very low power when compared to traditional high power ‘brawny’ server cores. XIMMs can provide services such as firewall packet repeaters, intrusion detection systems (IDS), intrusion protection systems (IPS), and routing mechanisms for virtual private networks with low power costs and high reliability.
FIG. 1 illustrates an embodiment with two computers which can be rack servers (100a, 100b) connected over a network interface such as Ethernet (108). It is seen that both contain a central processing unit (104a, 104b), a network interface controller (106a, 106b) and a number of connectors (102a, 102b, 102c, 102d, 102e, 102f) which can be dual-inline memory module (DIMM) connectors. It is further seen that the second server (100b) has a removable computation module (110) which can be inserted into one of the connector slots (102d). In an example, this computation module is a XIMM. Packets can be sent bi-directionally between the two servers, through the shown NICs and over the connection (108), and a variety of offload packet handling services can be performed by the XIMM in the second server, including but not limited to virtual private network (VPN) tunneling and signature detection and packet filtering as an intrusion prevention system (IPS).
FIG. 2 shows a different view of the XIMM module in the context of the second server shown above in FIG. 1. Network packets flow from a top-of-rack (TOR) switch (200) to the server, where a first virtual switch (202), in this case a network interface card with single root IO virtualization (SR-IOV), receives the packets and determines which XIMM module (206) to send them to. The packet is passed to the XIMM by way of an input-out memory management unit (IOMMU 204). On the XIMM 206, a first of a number of offload processors can act as a virtual switch (208).
The virtual switch 208 can be created with virtual switching software such as OpenFlow. OpenFlow is an open standard network protocol used to manage traffic between commercial Ethernet switches, routers and wireless access points. OpenFlow enables software-defined networking (SDN) for programmable networks and typically emulates a hardware Ethernet switch. Using a configurable data flow table it is possible to connect multiple switches and/or networks together to create a data flow, and then flexibly managing the entire infrastructure, setting policies and managing traffic type as needed. It allows for deployment of innovative routing and switching protocols in a network for many different applications, including virtual machine and high-security networks. The software stack running on a processor of the server also provides control plane provisioning (216) which includes a variety of packet handling services including but not limited to virtual private network (VPN) encryption/decryption through an open source technology such as OpenVPN, as but one example. Upon receipt, a decrypted packet is arbitrated by said processor acting as a switch to a second of a plurality of other offload processors (210). The second offload processor 210 can be running an operating system such as Apache, and may utilize a software stack for packet handling services. It reassembles decrypted packet data and performs intrusion prevention systems (IPS) signature detection in order to detect malicious incoming packet traffic. Optionally, a connection can also be established between the XIMM 206 and another server processor (e.g., a x86 processor) (214) through a high speed bus. Packets may be sent to the x86 processor 214 via a bus, including but limited to memory busses such as a double data rate (DDR, DDR2, DDR3, DDR4) bus. In this example, an Ethernet tunnel (212) exists over a DDR bus between the XIMM and the server's x86 processor (214) for the transmission of packets or other information between the two.
Advantageously, such a system can greatly improve computational and power efficiency for management of simultaneously running IPS and VPN services. Traditionally, IPS protocols require the assembly of data for signature detection before traffic is allowed to access a server, but VPN protocols mandate decryption on the server to produce signature detection data. In practice, many cloud service providers are forced to use proprietary hardware or simply disallow IPS services to a server core (limiting IPS to between an enterprise router and a gateway). Use of XIMMs allows the problems associated with simultaneous IPS and VPN to be avoided, since signature detection can occur on the XIMM (for example, with the aid of Advanced Encryption Standard (AES) cores implementable on FPGA cores in a XIMM), while VPN interconnection is maintained.
FIG. 3-1 illustrates exemplary software stacks respectively running on a XIMM and an x86-based server processor. A XIMM can include multiple offload processors, and each of the offload processors on the XIMMs can have an operating system such as Apache (300) which runs a stack of software for the packet handling services as described herein, or equivalents. One or more of the offload processors on the XIMM may be dedicated to arbitrating packets between the other offload processors, and may utilize a virtual switching software such as OpenFlow to do so (310). An arbitrating processor can also provide header services (308) by classifying packets by session identifier in preparation for packet-level applications such as signature detection and preprocessing. An arbitration processor can also manage VPN encryption and decryption services (302) using virtual private networking software such as OpenVPN. Input-output memory management software (e.g., IOMMU of 306) can be provided in order to facilitate safe sharing and usage of physical memory when the arbitration processor switches between virtual sessions for incoming packets. Direct memory access (e.g., R/DMA of 306) can allow for direct read/write to an internal memory of a XIMM. Queuing and reassembly functions (320) can take decrypted incoming fragments of data, assemble them into their original form and queue them for processing on one of multiple offload processors onboard the XIMM. Another software function can handle zero-overhead context switching (e.g., ZOCS of 304) in synergy with memory-mapped IO (e.g., MMIO of 304). As packets belonging to different sessions ingress, the offload processors can rapidly switch contexts and read from different parts of memory in order to service them. MMIO and ZOCS can also be crucial in hardware accelerating the signature detection in the IPS portion of the Xockets stack, as the offload processors context switch between each of the input queues representing different signatures without incurring additional overhead. The VPN/IPS services layer (302) provides the algorithms for packet encryption and decryption, as well as signature detection for malicious packet traffic.
On the x86 server processor, an operating system is also present and can run database and analytics software (318, 322), such as a Hadoop and MySQL as but two possible examples. A software hypervisor such as SessionVisor may run as well, providing virtualization services to a plurality of guest OS sessions (312). The hypervisor is responsible for the provisioning of hardware resources to the guest sessions, and also runs virtual switching software such as OpenFlow for directing packets to their destination sessions. An x86 software stack can also include one or more software applications related to the XIMM. In the particular embodiment shown, two XIMM specific software applications are also present. A software application socket (314) facilitates communication between the CPU and the XIMM offload processors, and a NIC driver (316) provides Ethernet-over-DDR tunneling and packet transmission from the NIC to the XIMM.
FIG. 3-2 shows the software stacks described in FIG. 3-1 operating in the context of two servers (340, 342) communicating over an Ethernet-type connection (338). A packet is instantiated in the first server (342) and a kernel command (344) is given to send it through the software stack and over the network. Memory mapped input-output (346) (MMIO) is used to write the packet data into a XIMM on the first server (348), and a software stack prepares the packet for transmission using secure socket layer (SSL) VPN encryption. A VPN tunnel is established between the two servers (350) and the packet is transmitted from the first server's NIC (352) over the network (338). Upon receipt of the packet, the second server's NIC (352′) forwards it to a XIMM by way of a custom driver (334). The input-output memory management unit (332) (IOMMU) determines which session the packet belongs to and passes it to the TCP offload stack (336) for header detection (330). An SSL service such as OpenSSL (328) decrypts the packet under the control of VPN software such as OpenVPN (326). An IPS software such as a Suricata (324) then performs signature detection on the packet in order to detect a possible threat, and upon clearance passes it to the kernel.
The following example(s) provide illustration and discussion of exemplary hardware and data processing systems suitable for implementation and operation of the foregoing discussed systems and methods. In particular, hardware and operation of wimpy cores or computational elements connected to a memory bus and mounted in DIMM or other conventional memory socket is discussed.
FIG. 4-1 is a cartoon schematically illustrating a data processing system 400 including a removable computation module 402 for offload of data processing from x86 or similar main/server processors 403 to memory bus 405 connected modules, as described herein or equivalents. Such modules 402 can be XIMM modules as described herein, or an equivalent, and can have multiple computation elements that can be referred to as “offload processors” because they offload various “light touch” processing tasks from the main processors (or x86 server), including but not limited to HTML, video, packet level services, security, or data analytics. This is of particular advantage for applications that require frequent random access or application context switching, since many server processors incur significant power usage or have data throughput limitations that can be greatly reduced by transfer of the computation to lower power and more memory efficient offload processors.
The computation elements or offload processors are accessible through memory bus 405. In this embodiment, the module can be inserted into a Dual Inline Memory Module (DIMM) slot on a commodity computer or server using a DIMM connector (407), providing a significant increase in effective computing power to system 400. The XIMM may communicate with other components in the commodity computer or server via one of a variety of busses including but not limited to any version of existing double data rate standards (e.g., DDR, DDR2, DDR3, etc.)
This illustrated embodiment of the XIMM contains five offload processors (400a, 400b, 400c, 400d, 400e) however other embodiments containing greater or fewer numbers of processors are contemplated. The offload processors can be custom manufactured or one of a variety of commodity processors including but not limited to field-programmable grid arrays (FPGA), microprocessors, reduced instruction set computers (RISC), microcontrollers or ARM processors. The computation elements or offload processors can include combinations of computational FPGAs such as those based on Altera, Xilinx (e.g., Artix class), or Zynq architecture (e.g., Zynq 7020), and/or conventional processors such as those based on Intel Atom or ARM architecture (e.g., ARM A9). For many applications, ARM processors having advanced memory handling features such as snoop control unit (SCU) are preferred, since this allows coherent read and write of memory. Other preferred advanced memory features can include processors that support an accelerator coherency port (ACP) that can allow for coherent supplementation of the cache through an FPGA fabric or computational element.
Each offload processor on the XIMM may run one of a variety of operating systems including but not limited to Apache or Linux. In addition, the offload processors may have access to a plurality of dedicated or shared storage methods. In this embodiment, each offload processor connects to two dedicated storage units (404a, 404b, 404c, 404d, 404e) which can be of a variety of storage types, including but not limited to random access memory (RAM), dynamic random access memory (DRAM), sequential access memory (SAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), reduced latency dynamic random access memory (RLDRAM), flash memory, or other emerging memory standards such as those based on DDR4 or hybrid memory cubes (HMC).
FIG. 4-2 shows an example layout of a XIMM module such as that described in FIG. 4-1, as well as a connectivity diagram between the components of the XIMM module. In this example, five XilinxTM Zynq 7020 (416a, 416b, 416c, 416d, 416e) programmable systems-on-a-chip (SoC) are used as computational FPGAs/offload processors. These offload processors communicate with each other using memory-mapped input-output (MMIO) (412). The types of storage units used in this example are SDRAM (SD, one shown as 408) and RLDRAM (RLD, three shown as 406a, 406b, 406c) and an InphiTM iMB02 memory buffer 418. Down conversion of 3.3 V to 2.5 volt is required to connect the RLDRAM with the Zynq components. The components are connected to the offload processors and to each other via a DDR3 (414) memory bus. Advantageously, the indicated layout maximizes memory resources availability without requiring a violation of the number of pins available under the DIMM standard.
In this embodiment, one of the Zynq computational FPGAs can act as arbiter providing a memory cache, giving an ability to have peer to peer sharing of data (via memcached or OMQ memory formalisms) between the other Zynq computational FPGAs. All traffic departing for the computational FPGAs is controlled through memory mapped I/O. The arbiter queues session data for use, and when a computational FPGA asks for address outside of the provided session, the arbiter is the first level of retrieval, external processing determination, and predictors set.
FIG. 4-3 shows two possible architectures for a XIMM in a simulation (Xockets MAX and MIN). Xockets MIN (420a) can be used in low-end public cloud servers, containing twenty ARM cores (420b) spread across fourteen DIMM slots in a commodity server which has two Opteron x86 processors and two network interface cards (NICs) (420c). This architecture provides a minimal benefit per Watt of power used. Xockets MAX (422a) contains eighty ARM cores (422b) across eight DIMM slots, in a server with two Opteron x86 processors and four NICs (422c). This architecture can provide a maximum benefit per Watt of power used.
FIG. 4-4 shows a representative power budget for an example of a XIMM according to a particular embodiment. Each component is listed (424a, 424b, 424c, 424d) along with its power profile. Average total and total wattages are also listed (426a, 426b). In total, especially for I/O packet processing with packet sizes on the order 1 KB in size, a low average power budget that is easily able to be provided by the 22 Vdd pins per DIMM. Additionally, the expected thermal output can be handled by inexpensive conductive heat spreaders, without requiring additional convective, conductive, or thermoelectric cooling. In certain situations, digital thermometers can be implemented to dynamically reduce performance (and consequent heat generation) if needed.
Operation of one embodiment of a XIMM module 430 using an ARM A9 architecture is illustrated with respect to FIG. 4-5. Use of ARM A9 architecture in conjunction with an FPGA fabric and memory, in this case shown as reduced latency DRAM (RLDRAM), can simplify or makes possible zero-overhead context switching, memory compression and CPI, in part by allowing hardware context switching synchronized with network queuing. In this way, there is a one to one mapping between thread and queues. As illustrated, the ARM A9 architecture includes a Snoop Control Unit 432 (SCU). This unit allows one to read out and write in memory coherently. Additionally, the Accelerator Coherency Port 434 (ACP) allows for coherent supplementation of the cache throughout the FPGA 436. The RLDRAM 438 provides the auxiliary bandwidth to read and write the ping-pong cache supplement (435): Block1$ and Block2$ during packet-level meta-data processing.
The following table (Table 1) illustrates potential states that can exist in the scheduling of queues/threads to XIMM processors and memory such as illustrated in FIG. 4-5.








TABLE 1





Queue/Thread State
HW treatment







Waiting for Ingress
All ingress data has been processed and thread


Packet
awaits further communication.


Waiting for MMIO
A functional call to MM hardware (such as HW



encryption or transcoding) was made.


Waiting for Rate-limit
The thread's resource consumption exceeds limit,



due to other connections idling.


Currently being
One of the ARM cores is already processing this


processed
thread, cannot schedule again.


Ready for Selection
The thread is ready for context selection.









These states help coordinate the complex synchronization between processes, network traffic, and memory-mapped hardware. When a queue is selected by a traffic manager a pipeline coordinates swapping in the desired L2 cache (440), transferring the reassembled IO data into the memory space of the executing process. In certain cases, no packets are pending in the queue, but computation is still pending to service previous packets. Once this process makes a memory reference outside of the data swapped, a scheduler can require queued data from the network interface card (NIC) to continue scheduling the thread. To provide fair queuing to a process not having data, the maximum context size is assumed as data processed. In this way, a queue must be provisioned as the greater of computational resource and network bandwidth resource, for example, each as a ratio of an 800 MHz A9 and 3 Gbps of bandwidth. Given the lopsidedness of this ratio, the ARM core is generally indicated to be worthwhile for computation having many parallel sessions (such that the hardware's prefetching of session-specific data and TCP/reassembly offloads a large portion of the CPU load) and those requiring minimal general purpose processing of data.
Essentially zero-overhead context switching is also possible using XIMM modules as disclosed in FIG. 4-5. Because per packet processing has minimum state associated with it, and represents inherent engineered parallelism, minimal memory access is needed, aside from packet buffering. On the other hand, after packet reconstruction, the entire memory state of the session can be accessed, and so requires maximal memory utility. By using the time of packet-level processing to prefetch the next hardware scheduled application-level service context in two different processing passes, the memory can always be available for prefetching. Additionally, the FPGA 436 can hold a supplemental “ping-pong” cache (435) that is read and written with every context switch, while the other is in use. As previously noted, this is enabled in part by the SCU 432, which allows one to read out and write in memory coherently, and ACP 434 for coherent supplementation of the cache throughout the FPGA 436. The RLDRAM 438 provides for read and write to the ping-pong cache supplement (435): Block1$ and Block2$ during packet-level meta-data processing. In the embodiment shown, only locally terminating queues can prompt context switching.
In operation, metadata transport code can relieve a main or host processor from tasks including fragmentation and reassembly, and checksum and other metadata services (e.g., accounting, IPSec, SSL, Overlay, etc.). As IO data streams in and out, L1 cache 437 can be filled during packet processing. During a context switch, the lockdown portion of a translation lookaside buffer (TLB) of an L1 cache can be rewritten with the addresses corresponding to the new context. In one very particular implementation, the following four commands can be executed for the current memory space.
MRC p15,0,r0,c10,c0,0; read the lockdown register
BIC r0,r0,#1; clear preserve bit
MCR p15,0,r0,c10,c0,0; write to the lockdown register;
write to the old value to the memory mapped Block RAM
Bandwidths and capacities of the memories can be precisely allocated to support context switching as well as applications such as Openflow processing, billing, accounting, and header filtering programs.
For additional performance improvements, the ACP 434 can be used not just for cache supplementation, but hardware functionality supplementation, in part by exploitation of the memory space allocation. An operand is written to memory and the new function called, through customizing specific Open Source libraries, so putting the thread to sleep and the hardware scheduler validates it for scheduling again once the results are ready. For example, OpenVPN uses the OpenSSL library, where the encrypt/decrypt functions can be memory mapped. Large blocks are then available to be exported without delay, or consuming the L2 cache 440, using the ACP. Hence, a minimum number of calls are needed within the processing window of a context switch, improving overall performance.
It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.
Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.

## Claims

1. A packet handling system, comprising:
a system memory;
a memory controller coupled to a memory bus;
at least one main processor in communication with the system memory by operation of the memory controller;
at least one hardware module physically connected to the memory bus that includes
a virtual switch in communication with the main processor and a plurality of offload processors over the memory bus by operation of the memory controller, the virtual switch configured to receive packet data as writes to the system memory by the memory controller, and to transmit packet data as reads from system memory by the memory controller, and
the plurality of offload processors are connected to the memory bus and configured to provide security related services on packet data and allow the packet data to be transmitted to the main processor after the security related services have been completed; and

a network interface card, configured to receive the packet data and direct the packet data to the virtual switch by operation of the memory controller; wherein
the memory controller, the memory bus, and the at least one main processor are not included in the at least one hardware module.

2. The packet handling system of claim 1, wherein the offload processors are configured to support signature detection by an intrusion prevention system.

3. The packet handling system of claim 1, wherein the offload processors are configured to support encryption/decryption.

4. The packet handling system of claim 1, further comprising an input-out memory management unit (IOMMU); wherein the IOMMU is configured to pass the packet data from the network interface card to the virtual switch.

5. The packet handling system of claim 4, wherein the network interface card includes single root IO virtualization (SR-IOV).

6. The packet handling system of claim 1, wherein the offload processors are connected to a module memory mounted on the at least one hardware module, and further include a snoop control unit for coherent read out and write in to the module memory.

7. The packet handling system of claim 1, wherein the offload processors are connected to a module memory mounted on the at least one hardware module and configured for zero-overhead context switching between threads of a networked application.

8. The packet handling system of claim 1, wherein the offload processors are connected to a module memory and a computational field programmable gate array (FPGA), all mounted together on an in-line module configured for insertion into a dual-in-line-memory-module (DIMM) socket.