# Patent

## Title
Method for manufacturing semiconductor device

## Abstract

A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to, for example, a transistor or a semiconductor device. The present invention relates to, for example, a method for manufacturing a transistor or a semiconductor device. The present invention relates to, for example, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, or an electronic device. The present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device. The present invention relates to a driving method of a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device.
Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter.
In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases.
2. Description of the Related Art
A technique for forming a transistor by using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is applied to a wide range of semiconductor devices such as an integrated circuit and a display device. Silicon is known as a semiconductor applicable to a transistor.
As silicon which is used as a semiconductor of a transistor, either amorphous silicon or polycrystalline silicon is used depending on the purpose. For example, in the case of a transistor included in a large display device, it is preferable to use amorphous silicon, which can be used to form a film on a large substrate with the established technique. On the other hand, in the case of a transistor included in a high-performance display device where driver circuits are formed over the same substrate, it is preferred to use polycrystalline silicon, which can form a transistor having high field-effect mobility. As a method for forming polycrystalline silicon, high-temperature heat treatment or laser light treatment which is performed on amorphous silicon has been known.
In recent years, transistors including oxide semiconductors (typically, In—Ga—Zn oxide) have been actively developed. Oxide semiconductors have been researched since early times. In 1988, it was disclosed to use a crystal In—Ga—Zn oxide for a semiconductor element (see Patent Document 1). In 1995, a transistor including an oxide semiconductor was invented, and its electrical characteristics were disclosed (see Patent Document 2).
In 2010, a transistor containing a crystalline In—Ga—Zn oxide that has more excellent electrical characteristics and higher reliability than a transistor containing an amorphous In—Ga—Zn oxide has been developed (see Patent Document 3). The crystalline In—Ga—Zn oxide has c-axis alignment and thus is called a c-axis aligned crystalline oxide semiconductor (CAAC-OS) or the like.
The transistor containing the CAAC-OS, since its discovery, has been reported to have excellent electrical characteristics. The transistor containing the CAAC-OS has characteristics superior to those of a transistor containing silicon in the following respects, for example.
It has been reported that the transistor containing the CAAC-OS is less likely to be affected by phonon scattering even with a short channel; thus, the field-effect mobility is less likely to be decreased (see Non-Patent Document 1). It has been also reported that a transistor containing the CAAC-OS and having a surrounded channel (s-channel) structure exhibits favorable switching characteristics even with a short channel (see Non-Patent Document 2). The transistor containing the CAAC-OS operates at high speed. For example, Non-Patent Document 3 reports a cutoff frequency of 20 GHz. Furthermore, it has been reported that the transistor containing the CAAC-OS has high withstand voltage characteristics (see Patent Document 4) and has little variation in characteristics due to temperature (see Patent Document 5).
The transistor including an oxide semiconductor has different features from a transistor including amorphous silicon or polycrystalline silicon. For example, a display device in which a transistor including an oxide semiconductor is used is known to have low power consumption. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used in a transistor included in a large display device. A transistor including an oxide semiconductor has high field-effect mobility; therefore, a high-performance display device where driver circuits are formed over the same substrate can be obtained. In addition, there is an advantage that capital investment can be reduced because part of production equipment for a transistor including amorphous silicon can be retrofitted and utilized.
REFERENCE
Patent Documents


    [Patent Document 1] Japanese Published Patent Application No. S63-239117
    [Patent Document 2] Japanese translation of PCT international application No. H11-505377
    [Patent Document 3] Japanese Published Patent Application No. 2011-086923
    [Patent Document 4] Japanese Published Patent Application No. 2012-256838
    [Patent Document 5] Japanese Published Patent Application No. 2013-250262


Non-Patent Documents


    [Non-Patent Document 1] S. Matsuda et al., Extended Abstracts International Conference on Solid State Devices and Materials, 2014, pp. 138-139
    [Non-Patent Document 2] Y. Kobayashi et al., IEEE ELECTRON DEVICE LETTERS, April 2015, Vol. 36, No. 4, pp. 309-311
    [Non-Patent Document 3] Y. Yakubo et al., Extended Abstracts International Conference on Solid State Devices and Materials, 2014, pp. 648-649


SUMMARY OF THE INVENTION
An object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor having a low leakage current in an off state. Another object is to provide a transistor having a high on-state current. Another object is to provide a transistor with normally-off electrical characteristics. Another object is to provide a transistor with a small subthreshold swing value. Another object is to provide a highly reliable transistor.
Another object is to provide a semiconductor device including any of the transistors. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module. Another object is to provide a novel semiconductor device. Another object is to provide a novel module. Another object is to provide a novel electronic device.
Note that the description of these objects does not preclude the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.
(1) One embodiment of the present invention is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask.
(2) One embodiment of the present invention is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then heat treatment is performed to cause gettering of hydrogen in the second region.
(3) One embodiment of the present invention is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then a fourth insulator in contact with a side surface of the first conductor is formed and hydrogen is added to the oxide semiconductor using the first conductor and the fourth insulator as a mask.
In the above method for manufacturing a semiconductor device, an oxygen vacancy is preferably formed at least in the oxide semiconductor by the ion implantation.
In the above method for manufacturing a semiconductor device, a helium ion, a neon ion, an argon ion, a krypton ion, or a xenon ion is preferably implanted through the ion implantation.
In the above method for manufacturing a semiconductor device, the ion implantation preferably has a first step and a second step. In the first step, an ion is implanted at an incident angle of greater than or equal to 10° and less than or equal to 60° with respect to a normal of a surface of the substrate. In the second step, an ion is implanted at an incident angle of greater than or equal to −60° and less than or equal to −10° with respect to the normal of the surface of the substrate.
In the above method for manufacturing a semiconductor device, the second region preferably includes a region whose carrier density is less than 1×109/cm3.
In the above method for manufacturing a semiconductor device, the first insulator, the second insulator, and the oxide semiconductor may contain oxygen and gallium.
A transistor with stable electrical characteristics can be provided. A transistor having a low leakage current in an off state can be provided. A transistor having a high on-state current can be provided. A transistor with normally-off electrical characteristics can be provided. A transistor with a small subthreshold swing value can be provided. A highly reliable transistor can be provided.
A semiconductor device including the transistor can be provided. A module including the semiconductor device can be provided. An electronic device including the semiconductor device or the module can be provided. A novel semiconductor device can be provided. A novel module can be provided. A novel electronic device can be provided.
Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects listed above. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.



BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1A to 1D are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention.
FIGS. 2A to 2F are cross-sectional views illustrating transistors of embodiments of the present invention.
FIGS. 3A to 3C are cross-sectional views illustrating transistors of embodiments of the present invention.
FIGS. 4A to 4F are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.
FIGS. 5A to 5F are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.
FIGS. 6A and 6B are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.
FIGS. 7A1, 7A2, 7B, and 7C each illustrate ion incidence.
FIG. 8 illustrates a crystal structure of InGaZnO4.
FIGS. 9A and 9B each show formation energies of defects due to hydrogen.
FIG. 10 shows relative energy to the VO-H distance.
FIGS. 11A and 11B each show formation energies of defects due to hydrogen.
FIGS. 12A and 12B show paths through which hydrogen is released from VO and energy changes.
FIGS. 13A and 13B show paths through which hydrogen is diffused, and FIG. 13C shows energy changes.
FIGS. 14A to 14D are a top view and cross-sectional views illustrating a transistor of one embodiment of the present invention.
FIGS. 15A to 15F are cross-sectional views illustrating transistors of embodiments of the present invention.
FIGS. 16A to 16C are cross-sectional views illustrating transistors of embodiments of the present invention.
FIGS. 17A to 17F are cross-sectional views illustrating transistors of embodiments of the present invention.
FIGS. 18A to 18F are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.
FIGS. 19A to 19F are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.
FIGS. 20A to 20D are cross-sectional views illustrating a method for manufacturing a transistor of one embodiment of the present invention.
FIGS. 21A to 21D are Cs-corrected high-resolution TEM images of a cross section of a CAAC-OS and a cross-sectional schematic view of a CAAC-OS.
FIGS. 22A to 22D are Cs-corrected high-resolution TEM images of a plane of a CAAC-OS.
FIGS. 23A to 23C show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD.
FIGS. 24A and 24B show electron diffraction patterns of a CAAC-OS.
FIG. 25 shows a change of crystal parts of an In—Ga—Zn oxide due to electron irradiation.
FIGS. 26A and 26B are circuit diagrams each illustrating a semiconductor device of one embodiment of the present invention.
FIG. 27 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 28 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 29 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 30 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 31 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 32 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 33A and 33B are circuit diagrams each illustrating a memory device of one embodiment of the present invention.
FIG. 34 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 35 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 36 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 37 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 38 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 39 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 40 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 41 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIG. 42 is a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 43A to 43E are circuit diagrams each illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 44A and 44B are top views each illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 45A and 45B are block diagrams each illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 46A and 46B are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 47A and 47B are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention.
FIG. 48 is a cross-sectional view of a semiconductor device of one embodiment of the present invention.
FIGS. 49A1, 49A2, 49A3, 49B1, 49B2, and 49B3 are perspective views and cross-sectional views illustrating semiconductor devices of embodiments of the present invention.
FIG. 50 is a block diagram illustrating a semiconductor device of one embodiment of the present invention.
FIG. 51 is a circuit diagram illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 52A to 52C are a circuit diagram, a top view, and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 53A and 53B are a circuit diagram and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 54A and 54B are cross-sectional views each illustrating a semiconductor device of one embodiment of the present invention.
FIGS. 55A to 55F are perspective views each illustrating an electronic device of one embodiment of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments and examples of the present invention will be described in detail with the reference to the drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways. Furthermore, the present invention is not construed as being limited to description of the embodiments. In describing structures of the present invention with reference to the drawings, common reference numerals are used for the same portions in different drawings. Note that the same hatched pattern is applied to similar parts, and the similar parts are not denoted by reference numerals in some cases.
A structure in one of the following embodiments can be appropriately applied to, combined with, or replaced with another structure in another embodiment, for example, and the resulting structure is also one embodiment of the present invention.
Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.
In this specification, the terms “film” and “layer” can be interchanged with each other.
A voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a source potential or a ground potential (GND)). A voltage can be referred to as a potential. Note that in general, a potential (a voltage) is relative and is determined depending on the amount relative to a reference potential. Therefore, a potential that is represented as a “ground potential” or the like is not always 0 V. For example, the lowest potential in a circuit may be represented as a “ground potential.” Alternatively, a substantially intermediate potential in a circuit may be represented as a “ground potential.” In these cases, a positive potential and a negative potential are set using the potential as a reference.
Note that the ordinal numbers such as “first” and “second” are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second,” “third,” or the like as appropriate. In addition, the ordinal numbers in this specification and the like do not correspond to the ordinal numbers which specify one embodiment of the present invention in some cases.
Note that impurities in a semiconductor refer to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of lower than 0.1 atomic % is an impurity. When an impurity is contained, the density of states (DOS) may be formed in a semiconductor, the carrier mobility may be decreased, or the crystallinity may be decreased. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specifically, there are hydrogen (included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. In the case of an oxide semiconductor, oxygen vacancies may be formed by entry of impurities such as hydrogen. In the case where the semiconductor is silicon, examples of an impurity which changes characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.
Note that the channel length refers to, for example, the distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed. In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.
Note that depending on a transistor structure, a channel width in a region where a channel is formed actually (hereinafter referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width) in some cases. For example, in a transistor having a three-dimensional structure, an effective channel width is greater than an apparent channel width shown in a top view of the transistor, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel region formed in a side surface of a semiconductor is high in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view.
In a transistor having a three-dimensional structure, an effective channel width is difficult to measure in some cases. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately.
Therefore, in this specification, in a top view of a transistor, an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like.
Note that in the case where field-effect mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, the values might be different from those calculated by using an effective channel width.
In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. A term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. A term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.
In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.
Embodiment 1
In this embodiment, structures of semiconductor devices of embodiments of the present invention will be described with reference to FIGS. 1A to 1D, FIGS. 2A to 2F, and FIGS. 3A to 3C.
<Structure 1 of Transistor>
Structures of transistors, which are examples of the semiconductor devices of embodiments of the present invention, will be described below.
A structure of a transistor 10 will be described with reference to FIGS. 1A to 1C. FIG. 1A is a top view of the transistor 10. FIG. 1B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 1A. FIG. 1C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 1A. A region along dashed-dotted line A1-A2 shows a structure of the transistor 10 in the channel length direction, and a region along dashed-dotted line A3-A4 shows a structure of the transistor 10 in the channel width direction. The channel length direction of a transistor refers to a direction in which carriers move between a source (source region or source electrode) and a drain (drain region or drain electrode). The channel width direction refers to a direction perpendicular to the channel length direction in a plane parallel to a substrate. Note that in FIG. 1A, some components (e.g., an insulating film functioning as a protective insulating film) of the transistor 10 are not illustrated to avoid complexity. As in FIG. 1A, some components are not illustrated in some cases in top views of transistors described below.
The transistor 10 includes a semiconductor 106b, a conductor 114, an insulator 106a, an insulator 106c, an insulator 112, and an insulator 116. The semiconductor 106b is over the insulator 106a, the insulator 106c is over the semiconductor 106b, the insulator 112 is over the insulator 106c, the conductor 114 is over the insulator 112, and the insulator 116 is over the conductor 114. The insulator 116 has a region in contact with the top surface of the insulator 106c. The semiconductor 106b has a region overlapping with the conductor 114 with the insulators 106c and 112 provided therebetween. It is preferable that, when seen from the top, the periphery of the insulator 106a be substantially aligned with the periphery of the semiconductor 106b and the periphery of the insulator 106c be positioned outward from the peripheries of the insulator 106a and the semiconductor 106b as in FIG. 1A.
As illustrated in FIGS. 1A to 1C, for example, the transistor 10 includes an insulator 101, a conductor 102, an insulator 103, and an insulator 104 formed over a substrate 100; the insulator 106a, the semiconductor 106b, and the insulator 106c formed over the insulator 104; the insulator 112 and the conductor 114 formed over the insulator 106c; and the insulator 116, an insulator 118, a conductor 108a, a conductor 108b, a conductor 109a, and a conductor 109b formed over the conductor 114.
Each of the insulators 101, 103, 104, 106a, 106c, 112, 116, and 118 can also be referred to as an insulating film or an insulating layer. Each of the conductors 102, 108a, 108b, 109a, 109b, and 114 can also be referred to as a conductive film or a conductive layer. The semiconductor 106b can also be referred to as a semiconductor film or a semiconductor layer.
The insulator 103 is formed over the insulator 101 formed over the substrate 100, and the conductor 102 is formed to be embedded in the insulator 103. The insulator 104 is formed over the insulator 103 and the conductor 102. Here, the insulator 101 is preferably formed using an insulator that has an effect of blocking oxygen, hydrogen, water, and the like. The insulator 104 is preferably formed using an insulator containing oxygen.
The insulator 106a is formed over the insulator 104. The semiconductor 106b is formed in contact with the top surface of the insulator 106a. The insulator 106c is formed in contact with a side surface of the insulator 106a and the top surface of the semiconductor 106b. Note that the semiconductor 106b is preferably formed to overlap with at least part of the conductor 102. An end portion of a side surface of the insulator 106a and an end portion of a side surface of the semiconductor 106b, especially those in the channel width direction, are substantially aligned with each other. Furthermore, the end portion of the side surface of the semiconductor 106b, especially that in the channel width direction, is in contact with the insulator 106c. In this manner, the semiconductor 106b of the transistor 10 described in this embodiment is surrounded by the insulator 106a and the insulator 106c. 
Although the periphery of the insulator 106c is positioned outward from the periphery of the insulator 106a in FIGS. 1B and 1C, the structure of the transistor described in this embodiment is not limited thereto. For example, the periphery of the insulator 106a may be positioned outward from the periphery of the insulator 106c, or the end portion of the side surface of the insulator 106a may be substantially aligned with an end portion of a side surface of the insulator 106c. 
A region 126a, a region 126b, and a region 126c are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c of the transistor 10 described in this embodiment. The regions 126b and 126c have higher dopant concentration than the region 126a, and the resistances of the regions 126b and 126c are reduced. The dopant concentration in the region 126a is, for example, less than or equal to 5%, less than or equal to 2%, or less than or equal to 1%, of the maximum dopant concentration in the region 126b or the region 126c. Note that the term “dopant” may be changed into the term “donor,” “acceptor,” “impurity,” or “element.”
FIG. 1D is an enlarged view of the conductor 114 and the vicinity thereof in the transistor 10 illustrated in FIG. 1B. As illustrated in FIG. 1D, the region 126a almost corresponds to a region overlapping with the conductor 114, and the regions 126b and 126c are regions except the region 126a in the insulator 106a, the semiconductor 106b, and the insulator 106c. It is preferable that the regions 126b and 126c partly overlap with a region (channel formation region) where the semiconductor 106b overlaps with the conductor 114. For example, end portions of side surfaces of the regions 126b and 126c in the channel length direction are preferably inward from an end portion of a side surface of the conductor 114 by a distance d. In that case, the distance d preferably satisfies 0.25t<d<t, where t represents the thickness of the insulator 112.
As described above, the regions 126b and 126c are partly formed in a region where the insulator 106a, the semiconductor 106b, and the insulator 106c overlap with the conductor 114. Accordingly, the channel formation region of the transistor 10 is in contact with the regions 126b and 126c having low resistance and thus, offset regions with high resistance are not formed between the region 126a and the regions 126b and 126c. As a result, the on-state current of the transistor 10 can be increased. Furthermore, when the end portions of the side surfaces of the regions 126b and 126c in the channel length direction are positioned such that 0.25t<d<t is satisfied, the regions 126b and 126c can be prevented from being spread inward too much in the channel formation region and thus the transistor 10 can be prevented from being constantly in an on state.
As described in detail later, the regions 126b and 126c are formed by ion doping treatment such as an ion implantation method. For this reason, as the depth from the top surface of the insulator 106c increases, the end portions of the side surfaces of the regions 126b and 126c in the channel length direction might shift toward the end portions of the side surfaces of the insulator 106a, the semiconductor 106b, and the insulator 106c in the channel length direction as illustrated in FIG. 1D. In that case, the distance d is the distance between the end portion of the side surface of the conductor 114 in the channel length direction and each of the end portions of the side surfaces of the regions 126b and 126c in the channel length direction, which are the closest to the conductor 114 and are positioned inward from the end portion of the side surface of the conductor 114.
In some cases, the regions 126b and 126c in the insulator 106a are not formed to overlap with the conductor 114, for example. In that case, the regions 126b and 126c in the semiconductor 106b are preferably formed to partly overlap with the conductor 114.
A low-resistance region 107a and a low-resistance region 107b are preferably formed in the insulator 106a, the semiconductor 106b, and the insulator 106c in the vicinity of the interface with the insulator 116 (indicated with a dotted line in FIG. 1B). The low-resistance region 107a and the low-resistance region 107b contain at least one of the elements contained in the insulator 116. It is preferable that the low-resistance region 107a and the low-resistance region 107b be partly and substantially in contact with a region of the semiconductor 106b overlapping with the conductor 114 (channel formation region) or partly overlap with the region.
Since a large region of the insulator 106c is in contact with the insulator 116, the low-resistance region 107a and the low-resistance region 107b are easily formed in the insulator 106c. The concentration of the element contained in the insulator 116 is higher in the low-resistance region 107a and the low-resistance region 107b included in the insulator 106c than in a region of the insulator 106c other than the low-resistance region 107a and the low-resistance region 107b (e.g., a region of the insulator 106c overlapping with the conductor 114).
The low-resistance region 107a is formed in the region 126b and the low-resistance region 107b is formed in the region 126c. In the ideal structure, the low-resistance regions 107a and 107b, regions in the regions 126b and 126c except the low-resistance regions 107a and 107b, and the region 126a have high concentration of an additional element in this order. Note that the additional element includes the dopant used for forming the regions 126b and 126c and the element added to the low-resistance regions 107a and 107b from the insulator 116.
The formation of the regions 126b and 126c and the low-resistance regions 107a and 107b leads to a reduction in contact resistance between the conductor 108a or 108b and the insulator 106a, the semiconductor 106b, or the insulator 106c, whereby the transistor 10 can have high on-state current.
Although the low-resistance regions 107a and 107b are formed in the transistor 10 illustrated in FIGS. 1A to 1D, the structure of the semiconductor device described in this embodiment is not necessarily limited thereto. For example, in the case where the regions 126b and 126c have sufficiently low resistance, the low-resistance regions 107a and 107b do not need to be formed.
The insulator 112 is formed over the insulator 106c, and the conductor 114 is formed over the insulator 112. At least part of each of the insulator 112 and the conductor 114 overlaps with the conductor 102 and the semiconductor 106b. It is preferable that an end portion of a side surface of the conductor 114 in the channel length direction be substantially aligned with an end portion of a side surface of the insulator 112 in the channel length direction. Here, the insulator 112 serves as a gate insulating film of the transistor 10 and the conductor 114 serves as a gate electrode of the transistor 10.
The insulator 116 is formed over the conductor 114, the insulator 106c, and the insulator 104. The insulator 116 is preferably in contact with a region of the insulator 106c that does not overlap with the insulator 112. The insulator 116 may be in contact with at least part of the insulator 104. The insulator 118 is formed over the insulator 116. Here, the insulator 116 serves as a protective insulating film of the transistor 10 and the insulator 118 serves as an interlayer insulating film of the transistor 10. The insulator 116 is preferably formed using an insulator that has an effect of blocking oxygen.
The thickness of the insulator 106a is preferably larger than the total thickness of the insulator 106c and the insulator 112. In other words, it is preferable to satisfy h1=h2 or h1>h2, where h1 is the height from the top surface of the substrate 100 to the bottom surface of the semiconductor 106b and h2 is the height from the top surface of the substrate 100 to the bottom surface of the conductor 114 in a region overlapping with the insulator 106c. For example, h1 may be greater than h2 by 5% or more, preferably 10% or more, further preferably 20% or more, and still further preferably 50% or more of an apparent channel width W of the transistor 10. With such a structure, almost the entire side surface of the semiconductor 106b in the channel width direction can be made to face the conductor 114 with the insulators 106c and 112 provided therebetween.
With the above structure, as illustrated in FIG. 1C, the semiconductor 106b can be electrically surrounded by an electric field of the conductor 114 (a structure in which a semiconductor is electrically surrounded by an electric field of a conductor is referred to as a surrounded channel (s-channel) structure). Therefore, a channel is formed in the entire semiconductor 106b in some cases. In the s-channel structure, a large amount of current can flow between a source and a drain of a transistor, so that a high on-state current can be obtained.
In the case where the transistor has the s-channel structure, a channel is formed also in the side surface of the semiconductor 106b. Thus, as the thickness of the semiconductor 106b becomes larger, the channel region becomes larger. In other words, the thicker the semiconductor 106b is, the higher the on-state current of the transistor is. In addition, as the thickness of the semiconductor 106b becomes larger, the proportion of the region with a high carrier controllability increases, leading to a smaller subthreshold swing value. The semiconductor 106b has, for example, a region with a thickness greater than or equal to 10 nm, preferably greater than or equal to 20 nm, further preferably greater than or equal to 30 nm, and still further preferably greater than or equal to 50 nm. Since the productivity of the semiconductor device might be decreased, the semiconductor 106b has, for example, a region with a thickness less than or equal to 300 nm, preferably less than or equal to 200 nm, and further preferably less than or equal to 150 nm. In some cases, when the channel formation region is reduced in size, electrical characteristics of the transistor with a smaller thickness of the semiconductor 106b may be improved. Thus, the semiconductor 106b may have a thickness less than 10 nm.
The s-channel structure is suitable for a miniaturized transistor because a high on-state current can be obtained. A semiconductor device including the miniaturized transistor can have a high integration degree and high density. For example, the transistor includes a region having a channel length of preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, and still further preferably less than or equal to 20 nm and a region having a channel width of preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, and still further preferably less than or equal to 20 nm.
The conductor 108a and the conductor 108b are formed in openings provided in the insulators 118, 116, and 106c so as to be in contact with the low-resistance region 107a and the low-resistance region 107b. Over the insulator 118, the conductor 109a is formed in contact with the top surface of the conductor 108a and the conductor 109b is formed in contact with the top surface of the conductor 108b. The conductor 108a and the conductor 108b are spaced from each other, and are preferably opposed to each other with the conductor 114 positioned therebetween as illustrated in FIG. 1B. The conductor 108a functions as one of a source electrode and a drain electrode of the transistor 10 and the conductor 108b functions as the other of the source electrode and the drain electrode of the transistor 10. The conductor 109a functions as a wiring connected to one of the source electrode and the drain electrode of the transistor 10 and the conductor 109b functions as a wiring connected to the other of the source electrode and the drain electrode of the transistor 10. Although the conductor 108a and the conductor 108b are in contact with the semiconductor 106b in FIG. 1B, this embodiment is not limited to this structure. As long as the contact resistance with the low-resistance regions 107a and 107b is sufficiently low, the conductor 108a and the conductor 108b may be in contact with the insulator 106c. 
<Semiconductor>
A detailed structure of the semiconductor 106b will be described below.
In this section, a detailed structure of each of the insulator 106a and the insulator 106c will be described in addition to that of the semiconductor 106b. 
The semiconductor 106b is an oxide semiconductor containing indium, for example. The semiconductor 106b can have high carrier mobility (electron mobility) by containing indium. The semiconductor 106b preferably contains an element M. The element M is preferably Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf. Note that two or more of the above elements may be used in combination as the element M in some cases. The element M is an element having high bonding energy with oxygen, for example. The element M is an element whose bonding energy with oxygen is higher than that of indium, for example. The element M is an element that can increase the energy gap of the oxide semiconductor, for example. Furthermore, the semiconductor 106b preferably contains zinc. When the oxide semiconductor contains zinc, the oxide semiconductor is easily crystallized, in some cases.
Note that the semiconductor 106b is not limited to the oxide semiconductor containing indium. The semiconductor 106b may be, for example, an oxide semiconductor which does not contain indium and contains zinc, an oxide semiconductor which does not contain indium and contains gallium, or an oxide semiconductor which does not contain indium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide.
The insulators 106a and 106c each include one or more elements, or two or more elements other than oxygen included in the semiconductor 106b. Since the insulators 106a and 106c each include one or more elements, or two or more elements other than oxygen included in the semiconductor 106b, a defect state is less likely to be formed at the interface between the insulator 106a and the semiconductor 106b and the interface between the semiconductor 106b and the insulator 106c. 
The insulator 106a, the semiconductor 106b, and the insulator 106c preferably contain at least indium. In the case of using an In-M-Zn oxide as the insulator 106a, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, and further preferably less than 25 atomic % and greater than 75 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor 106b, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be greater than 25 atomic % and less than 75 atomic %, respectively, and further preferably greater than 34 atomic % and less than 66 atomic %, respectively. In the case of using an In-M-Zn oxide as the insulator 106c, when the summation of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than 50 atomic %, respectively, and further preferably less than 25 atomic % and greater than 75 atomic %, respectively. Note that the insulator 106a or the insulator 106c does not necessarily contain indium in some cases. For example, the insulator 106a or the insulator 106c may be gallium oxide or a Ga—Zn oxide. Note that the atomic ratio between the elements included in the insulator 106a, the semiconductor 106b, and the insulator 106c is not necessarily a simple integer ratio.
In the case of deposition using a sputtering method, typical examples of the atomic ratio between the metal elements of a target that is used for the insulator 106a or the insulator 106c include In:M:Zn=1:2:4, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn=1:3:6, In:M:Zn=1:3:8, In:M:Zn=1:4:3, In:M:Zn=1:4:4, In:M:Zn=1:4:5, In:M:Zn=1:4:6, In:M:Zn=1:6:3, In:M:Zn=1:6:4, In:M:Zn=1:6:5, In:M:Zn=1:6:6, In:M:Zn=1:6:7, In:M:Zn=1:6:8, and In:M:Zn=1:6:9. The atomic ratio between the metal elements of the target that is used for the insulator 106a may be M:Zn=10:1.
In the case of deposition using a sputtering method, typical examples of the atomic ratio between the metal elements of a target that is used for the semiconductor 106b include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, and In:M:Zn=4:2:4.1. In particular, when a sputtering target containing In, Ga, and Zn at an atomic ratio of 4:2:4.1 is used, the deposited semiconductor 106b may contain In, Ga, and Zn at an atomic ratio of around 4:2:3.
An indium gallium oxide has small electron affinity and a high oxygen-blocking property. Therefore, the insulator 106c preferably includes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, higher than or equal to 70%, preferably higher than or equal to 80%, further preferably higher than or equal to 90%.
For the semiconductor 106b, an oxide with a wide energy gap may be used, for example. For example, the energy gap of the semiconductor 106b is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, further preferably greater than or equal to 3 eV and less than or equal to 3.5 eV. Here, the energy gap of the insulator 106a is larger than that of the semiconductor 106b. The energy gap of the insulator 106c is larger than that of the semiconductor 106b. 
As the semiconductor 106b, an oxide having an electron affinity larger than that of the insulator 106a or the insulator 106c is used. For example, as the semiconductor 106b, an oxide having an electron affinity larger than that of the insulator 106a or the insulator 106c by 0.07 eV or higher and 1.3 eV or lower, preferably 0.1 eV or higher and 0.7 eV or lower, and further preferably 0.15 eV or higher and 0.4 eV or lower is used. Note that the electron affinity refers to an energy difference between the vacuum level and the conduction band minimum. In that case, the conduction band minimum of the insulator 106a or the insulator 106c is closer to the vacuum level than that of the semiconductor 106b is.
In such a case, gate voltage application results in channel formation not in the insulator 106a or the insulator 106c but in the semiconductor 106b having a higher electron affinity.
The insulator 106a and the insulator 106c are formed using a substance that can function as a conductor, a semiconductor, or an insulator when they are used alone. However, when the transistor is formed using a stack including the insulator 106a, the semiconductor 106b, and the insulator 106c, electrons flow in the semiconductor 106b, at and in the vicinity of the interface between the semiconductor 106b and the insulator 106a, and at and in the vicinity of the interface between the semiconductor 106b and the insulator 106c; thus, the insulator 106a and the insulator 106c have a region not functioning as a channel of the transistor. For that reason, in this specification and the like, the insulator 106a and the insulator 106c are not referred to as a semiconductor but an insulator. Note that the reason why the insulator 106a and the insulator 106c are referred to as an insulator is because they are closer to an insulator than the semiconductor 106b is in terms of their functions in the transistor; thus, a substance that can be used for the semiconductor 106b is used for the insulator 106a and the insulator 106c in some cases.
Here, in some cases, there is a mixed region of the insulator 106a and the semiconductor 106b between the insulator 106a and the semiconductor 106b. Furthermore, in some cases, there is a mixed region of the insulator 106c and the semiconductor 106b between the insulator 106c and the semiconductor 106b. The mixed region has a low density of defect states. For that reason, the stack including the insulator 106a, the semiconductor 106b, and the insulator 106c has a band structure where energy is changed continuously at each interface and in the vicinity of the interface (continuous junction). Note that the boundary between the insulator 106a and the semiconductor 106b and the boundary between the insulator 106c and the semiconductor 106b are not clear in some cases.
At this time, electrons move mainly in the semiconductor 106b, not in the insulator 106a and the insulator 106c. As described above, when the density of defect states at the interface between the insulator 106a and the semiconductor 106b and the density of defect states at the interface between the insulator 106c and the semiconductor 106b are decreased, electron movement in the semiconductor 106b is less likely to be inhibited and the on-state current of the transistor can be increased.
As factors in inhibiting electron movement are decreased, the on-state current of the transistor can be increased. For example, in the case where there is no factor in inhibiting electron movement, electrons are assumed to be efficiently moved. Electron movement is inhibited, for example, in the case where physical unevenness of the channel formation region is large.
To increase the on-state current of the transistor, for example, root mean square (RMS) roughness with a measurement area of 1 μm×1 μm of the top or bottom surface of the semiconductor 106b (a formation surface; here, the top surface of the insulator 106a) is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) with the measurement area of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, further preferably less than 0.5 nm, still further preferably less than 0.4 nm. The maximum difference (P−V) with the measurement area of 1 μm×1 μm is less than 10 nm, preferably less than 9 nm, further preferably less than 8 nm, still further preferably less than 7 nm. RMS roughness, Ra, and P−V can be measured using a scanning probe microscope SPA-500 manufactured by SII Nano Technology Inc.
Moreover, the thickness of the insulator 106c is preferably as small as possible to increase the on-state current of the transistor. It is preferable that the thickness of the insulator 106c is smaller than that of the insulator 106a and smaller than that of the semiconductor 106b. For example, the insulator 106c is formed to include a region having a thickness of less than 10 nm, preferably less than or equal to 5 nm, further preferably less than or equal to 3 nm. Meanwhile, the insulator 106c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the semiconductor 106b where a channel is formed. For this reason, it is preferable that the insulator 106c have a certain thickness. For example, the insulator 106c is formed to include a region having a thickness of greater than or equal to 0.3 nm, preferably greater than or equal to 1 nm, further preferably greater than or equal to 2 nm.
To improve reliability, the insulator 106a is preferably thick. For example, the insulator 106a includes a region with a thickness of, for example, greater than or equal to 10 nm, preferably greater than or equal to 20 nm, further preferably greater than or equal to 40 nm, still further preferably greater than or equal to 60 nm. When the thickness of the insulator 106a is made large, a distance from the interface between the adjacent insulator and the insulator 106a to the semiconductor 106b in which a channel is formed can be large. Since the productivity of the semiconductor device might be decreased, the insulator 106a has a region with a thickness of, for example, less than or equal to 200 nm, preferably less than or equal to 120 nm, further preferably less than or equal to 80 nm.
Silicon in the oxide semiconductor might serve as a carrier trap or a carrier generation source, for example. Thus, the silicon concentration in the semiconductor 106b is preferably as low as possible. For example, between the semiconductor 106b and the insulator 106a, a region with a silicon concentration measured by secondary ion mass spectrometry (SIMS) of higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 1×1019 atoms/cm3, preferably higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 5×1018 atoms/cm3, and further preferably higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 2×1018 atoms/cm3 is provided. Furthermore, between the semiconductor 106b and the insulator 106c, a region with a silicon concentration measured by SIMS of higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 1×1019 atoms/cm3, preferably higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 5×1018 atoms/cm3, further preferably higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 2×1018 atoms/cm3 is provided.
It is preferable to reduce the hydrogen concentration in the insulator 106a and the insulator 106c in order to reduce the hydrogen concentration in the semiconductor 106b. The insulator 106a and the insulator 106c each include a region with a hydrogen concentration measured by SIMS of higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 2×1020 atoms/cm3, preferably higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 5×1019 atoms/cm3, further preferably higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 1×1019 atoms/cm3, or still further preferably higher than or equal to 1×1016 atoms/cm3 and lower than or equal to 5×1018 atoms/cm3. It is preferable to reduce the nitrogen concentration in the insulator 106a and the insulator 106c in order to reduce the nitrogen concentration in the semiconductor 106b. The insulator 106a and the insulator 106c each include a region with a nitrogen concentration measured by SIMS of higher than or equal to 1×1015 atoms/cm3 and lower than or equal to 5×1019 atoms/cm3, preferably higher than or equal to 1×1015 atoms/cm3 and lower than or equal to 5×1018 atoms/cm3, further preferably higher than or equal to 1×1015 atoms/cm3 and lower than or equal to 1×1018 atoms/cm3, or still further preferably higher than or equal to 1×1015 atoms/cm3 and lower than or equal to 5×1017 atoms/cm3.
Each of the insulator 106a, the semiconductor 106b, and the insulator 106c described in this embodiment, especially the semiconductor 106b, is an oxide semiconductor with a low impurity concentration and a low density of defect states (a small number of oxygen vacancies) and thus can be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Since a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has few carrier generation sources, the carrier density can be low. Thus, a transistor in which a channel region is formed in the oxide semiconductor rarely has a negative threshold voltage (is rarely normally on). A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a low density of defect states and accordingly has a low density of trap states in some cases. Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has an extremely low off-state current; the off-state current can be less than or equal to the measurement limit of a semiconductor parameter analyzer, i.e., less than or equal to 1×10−13 A, at a voltage (drain voltage) between a source electrode and a drain electrode of from 1 V to 10 V even when an element has a channel width (W) of 1×106 μm and a channel length (L) of 10 μm.
Accordingly, the transistor in which the channel region is formed in the highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor can have a small change in electrical characteristics and high reliability. Charges trapped by the trap states in the oxide semiconductor take a long time to be released and may behave like fixed charges. Thus, the transistor whose channel region is formed in the oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases. Examples of impurities are hydrogen, nitrogen, alkali metal, and alkaline earth metal.
Hydrogen contained in the insulator 106a, the semiconductor 106b, and the insulator 106c reacts with oxygen bonded to a metal atom to be water, and also causes an oxygen vacancy in a lattice from which oxygen is released (or a portion from which oxygen is released). Due to entry of hydrogen into the oxygen vacancy, an electron serving as a carrier is generated in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Hydrogen trapped by an oxygen vacancy might form a shallow donor level in a band structure of a semiconductor. Thus, a transistor including an oxide semiconductor that contains hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen be reduced as much as possible in the insulator 106a, the semiconductor 106b, and the insulator 106c. Specifically, the hydrogen concentration in the insulator 106a, the semiconductor 106b, and the insulator 106c, which is measured by SIMS, is lower than or equal to 2×1020 atoms/cm3, preferably lower than or equal to 5×1019 atoms/cm3, further preferably lower than or equal to 1×1019 atoms/cm3, still further preferably lower than or equal to 5×1018 atoms/cm3, yet further preferably lower than or equal to 1×1018 atoms/cm3, even further preferably lower than or equal to 5×1017 atoms/cm3, and further preferably lower than or equal to 1×1016 atoms/cm3.
When the insulator 106a, the semiconductor 106b, and the insulator 106c contain silicon or carbon, which is one of elements belonging to Group 14, oxygen vacancies in the insulator 106a, the semiconductor 106b, and the insulator 106c are increased, which makes the insulator 106a, the semiconductor 106b, and the insulator 106c n-type. Thus, the concentration of silicon or carbon (measured by SIMS) in the insulator 106a, the semiconductor 106b, and the insulator 106c or the concentration of silicon or carbon (measured by SIMS) at and in the vicinity of the interface with the insulator 106a, the semiconductor 106b, and the insulator 106c is set to be lower than or equal to 2×1018 atoms/cm3, preferably lower than or equal to 2×1017 atoms/cm3.
In addition, the concentration of an alkali metal or alkaline earth metal in the insulator 106a, the semiconductor 106b, and the insulator 106c, which is measured by SIMS, is set to be lower than or equal to 1×1018 atoms/cm3, preferably lower than or equal to 2×1016 atoms/cm3. An alkali metal and an alkaline earth metal might generate carriers when bonded to an oxide semiconductor, in which case the off-state current of the transistor might be increased. Thus, it is preferable to reduce the concentration of an alkali metal or alkaline earth metal in the insulator 106a, the semiconductor 106b, and the insulator 106c. 
Furthermore, when containing nitrogen, the insulator 106a, the semiconductor 106b, and the insulator 106c easily become n-type by generation of electrons serving as carriers and an increase of carrier density. Thus, a transistor including an oxide semiconductor film which contains nitrogen is likely to have normally-on characteristics. For this reason, nitrogen in the oxide semiconductor film is preferably reduced as much as possible; the concentration of nitrogen which is measured by SIMS is preferably set to be, for example, lower than or equal to 5×1018 atoms/cm3.
As described above, the insulator 106a, the semiconductor 106b, and the insulator 106c described in this embodiment are oxides that have a low impurity concentration and a low density of defect states (few oxygen vacancies) and thus, the insulator 106a, the semiconductor 106b, and the insulator 106c have a low carrier density. As a result, contact resistance with the conductors 108a and 108b serving as the source and drain electrodes easily becomes high. In view of this, in the transistor 10 described in this embodiment, the conductor 108a or the conductor 108b is connected to the insulator 106a, the semiconductor 106b, or the insulator 106c through the low-resistance region 107a in the region 126b or the low-resistance region 107b in the region 126c to reduce contact resistance.
As described above, the regions 126a, 126b, and 126c are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c. The regions 126b and 126c have higher dopant concentration than the region 126a, and the resistances of the regions 126b and 126c are reduced. The region 126a almost corresponds to a region overlapping with the conductor 114, and the regions 126b and 126c are regions except the region 126a in the insulator 106a, the semiconductor 106b, and the insulator 106c. It is preferable that the regions 126b and 126c partly overlap with a region (channel formation region) where the semiconductor 106b overlaps with the conductor 114.
The low-resistance regions 107a and 107b are preferably formed in the insulator 106a, the semiconductor 106b, and the insulator 106c in the vicinity of the interface with the insulator 116. In the regions 126b and 126c and the low-resistance regions 107a and 107b, a dopant and an element contained in the insulator 116 are added to cause formation of a defect. Such a defect is formed in such a manner that, for example, oxygen is extracted owing to the added dopant or the element added from the insulator 116 and an oxygen vacancy is formed, or the dopant or the element added from the insulator 116 serves as a carrier generation source. Such a defect forms a donor level and carrier density is increased; thus, the regions to which the dopant or the element contained in the insulator 116 is added serve as the regions 126b and 126c and the low-resistance regions 107a and 107b. 
The regions 126b and 126c, especially the low-resistance regions 107a and 107b, include many oxygen vacancies and thus have lower oxygen concentration than the region 126a when measured by SIMS. Furthermore, the regions 126b and 126c, especially the low-resistance regions 107a and 107b, include many defects and thus have lower crystallinity than the region 126a. 
Although details are described later, the regions 126b and 126c are formed by adding a dopant. Thus, the concentration of the dopant measured by SIMS is higher in the regions 126b and 126c than in the region 126a. 
Examples of the dopant added to the regions 126b and 126c include hydrogen, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. Among these elements, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, and boron are preferable because these elements can be added relatively easily by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.
Because the element contained in the insulator 116 is added to the low-resistance region 107a and the low-resistance region 107b, the concentration of the element measured by SIMS in these regions is higher than that in the region of the semiconductor 106b other than the low-resistance region 107a and the low-resistance region 107b (e.g., a region of the semiconductor 106b that overlaps with the conductor 114).
The element added to the low-resistance region 107a and the low-resistance region 107b is preferably boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, or tungsten, for example. These elements relatively easily form an oxide that can serve as a semiconductor or an insulator and thus, these elements are favorable as the element added to the insulator 106a, the semiconductor 106b, or the insulator 106c. For example, the low-resistance region 107a and the low-resistance region 107b preferably contain the above element at higher than or equal to 1×1014/cm2 and lower than or equal to 2×1016/cm2. The concentration of the above element is higher in the low-resistance region 107a and the low-resistance region 107b included in the insulator 106c than in a region of the insulator 106c other than the low-resistance region 107a and the low-resistance region 107b (e.g., a region of the insulator 106c overlapping with the conductor 114).
Because the addition of nitrogen to the low-resistance region 107a and the low-resistance region 107b makes these regions become n-type, the concentration of nitrogen measured by SIMS in these regions is higher than that in the region of the semiconductor 106b other than the low-resistance region 107a and the low-resistance region 107b (e.g., a region of the semiconductor 106b that overlaps with the conductor 114).
The formation of the low-resistance region 107a and the low-resistance region 107b leads to a reduction in contact resistance between the conductor 108a or 108b and the insulator 106a, the semiconductor 106b, or the insulator 106c, whereby the transistor 10 can have high on-state current.
As illustrated in FIG. 1B, it is preferable that the end portion of the side surface of the conductor 114 in the channel length direction be substantially aligned with the end portion of the side surface of the insulator 112 in the channel length direction. With such a structure, the low-resistance regions 107a and 107b are substantially in contact with the region of the semiconductor 106b that overlaps with the conductor 114 (channel formation region), whereby on-state current can be increased.
In the transistor 10, the semiconductor 106b is surrounded by the insulator 106a and the insulator 106c. Accordingly, the semiconductor 106b is in contact with the insulator 106a and the insulator 106c at the end portion of the side surface, especially around the end portion of the side surface in the channel width direction, of the semiconductor 106b. As a result, in the vicinity of the end portion of the side surface of the semiconductor 106b, continuous junction is formed between the insulator 106a and the semiconductor 106b or between the insulator 106c and the semiconductor 106b and the density of defect states is reduced. Thus, even when on-state current easily follows owing to the regions 126b and 126c and the low-resistance regions 107a and 107b, the end portion of the side surface of the semiconductor 106b in the channel width direction does not serve as a parasitic channel, which enables stable electrical characteristics.
Note that the three-layer structure including the insulator 106a, the semiconductor 106b, and the insulator 106c is an example. For example, a two-layer structure not including the insulator 106a or the insulator 106c may be employed. Alternatively, a single-layer structure not including the insulator 106a and the insulator 106c may be employed. Further alternatively, it is possible to employ an n-layer structure (n is an integer of four or more) that includes any of the insulator, semiconductor, and conductor given as examples of the insulator 106a, the semiconductor 106b, and the insulator 106c. 
Note that an oxide semiconductor that can be used for the insulator 106a, the semiconductor 106b, and the insulator 106c will be described in detail in Embodiment 5.
<Substrate, Insulator, Conductor>
Components other than the semiconductor of the transistor 10 will be described in detail below.
As the substrate 100, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), or a resin substrate is used, for example. As the semiconductor substrate, a single material semiconductor substrate formed using silicon, germanium, or the like or a semiconductor substrate formed using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like is used, for example. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate or the like is used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is used. A substrate including a metal nitride, a substrate including a metal oxide, or the like is used. An insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like is used. Alternatively, any of these substrates over which an element is provided may be used. As the element provided over the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like is used.
Alternatively, a flexible substrate resistant to heat treatment performed in manufacture of the transistor may be used as the substrate 100. As a method for providing the transistor over a flexible substrate, there is a method in which the transistor is formed over a non-flexible substrate and then the transistor is separated and transferred to the substrate 100 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. As the substrate 100, a sheet, a film, or a foil containing a fiber may be used. The substrate 100 may have elasticity. The substrate 100 may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate 100 may have a property of not returning to its original shape. The thickness of the substrate 100 is, for example, greater than or equal to 5 μm and less than or equal to 700 μm, preferably greater than or equal to 10 μm and less than or equal to 500 μm, and further preferably greater than or equal to 15 μm and less than or equal to 300 μm. When the substrate 100 has a small thickness, the weight of the semiconductor device can be reduced. When the substrate 100 has a small thickness, even in the case of using glass or the like, the substrate 100 may have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate 100, which is caused by dropping or the like, can be reduced. That is, a durable semiconductor device can be provided.
For the substrate 100 which is a flexible substrate, metal, an alloy, resin, glass, or fiber thereof can be used, for example. The flexible substrate 100 preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate 100 is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10−3/K, lower than or equal to 5×10−5/K, or lower than or equal to 1×10−5/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate 100 because of its low coefficient of linear expansion.
As the insulator 101, an insulator having a function of blocking hydrogen or water is used. Hydrogen or water in the insulator provided near the insulator 106a, the semiconductor 106b, and the insulator 106c is one of the factors of carrier generation in the insulator 106a, the semiconductor 106b, and the insulator 106c containing an oxide semiconductor. Because of this, the reliability of the transistor 10 might be decreased. When a substrate provided with a silicon-based semiconductor element such as a switching element is used as the substrate 100, hydrogen might be used to terminate a dangling bond in the semiconductor element and then be diffused into the transistor 10. However, if such a structure includes the insulator 101 having a function of blocking hydrogen or water, diffusion of hydrogen or water from below the transistor 10 can be inhibited, leading to an improvement in the reliability of the transistor 10.
The insulator 101 preferably has a function of blocking oxygen. If oxygen diffused from the insulator 104 can be blocked by the insulator 101, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c. 
The insulator 101 can be formed using, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, or hafnium oxynitride. The use of such a material enables the insulator 101 to function as an insulating film blocking diffusion of oxygen, hydrogen, or water. The insulator 101 can be formed using, for example, silicon nitride or silicon nitride oxide. The use of such a material enables the insulator 101 to function as an insulating film blocking diffusion of hydrogen or water. Note that silicon nitride oxide means a substance that contains more nitrogen than oxygen and silicon oxynitride means a substance that contains more oxygen than nitrogen in this specification and the like.
At least part of the conductor 102 preferably overlaps with the semiconductor 106b in a region positioned between the conductor 108a and the conductor 108b. The conductor 102 functions as a back gate of the transistor 10. The conductor 102 can control the threshold voltage of the transistor 10. Control of the threshold voltage can prevent the transistor 10 from being turned on when voltage applied to the gate (conductor 114) of the transistor 10 is low, e.g., 0 V or lower. Thus, the electrical characteristics of the transistor 10 can be easily made normally-off characteristics.
The conductor 102 may be connected to the conductor 114 serving as the gate of the transistor 10 through an opening provided in the insulator 104 and the insulator 116.
The conductor 102 may be formed to have a single-layer structure or a stacked-layer structure using a conductor containing, for example, one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.
Although the transistor 10 includes the conductor 102 and the insulator 103, a structure of a semiconductor device in this embodiment is not limited to this structure. For example, a structure without the conductor 102 and the insulator 103 may be employed.
The insulator 103 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator 103 preferably includes silicon oxide or silicon oxynitride, for example.
The top surfaces of the insulator 103 and the conductor 102 preferably have improved planarity as illustrated in FIG. 1B by being subjected to planarization treatment performed by a chemical mechanical polishing (CMP) method or the like. In that case, the planarity of the surface over which the semiconductor 106b is formed is not lowered by the conductor 102 serving as the back gate; thus, carrier mobility can be improved and the transistor 10 can have increased on-state current.
Although the conductor 102 is embedded in the insulator 103, the semiconductor device described in this embodiment is not limited to the above structure; for example, the insulator 103 may be provided to cover the conductor 102. In that case, the insulator 103 preferably has a function of blocking oxygen. Providing the insulator 103 can prevent oxidation of the conductor 102, or extraction of oxygen from the insulator 104 by the conductor 102. Accordingly, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c. 
The insulator 104 contains oxygen and preferably contains excess oxygen. Furthermore, the insulator 104 preferably transmits more oxygen than the insulator 101. Such insulator 104 makes it possible to supply oxygen from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c. The supplied oxygen can reduce oxygen vacancies which are to be defects in the semiconductor 106b which is an oxide semiconductor. Accordingly, the density of defect states in the semiconductor 106b can be reduced, whereby the semiconductor 106b can be an oxide semiconductor with stable characteristics.
In this specification and the like, excess oxygen refers to oxygen in excess of the stoichiometric composition, for example. Alternatively, excess oxygen refers to oxygen released from a film or layer containing excess oxygen by heating, for example. Excess oxygen can move inside a film or a layer. Excess oxygen moves between atoms in a film or a layer, or replaces oxygen that is a constituent of a film or a layer and moves like a billiard ball, for example.
The insulator 104 may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator 104 preferably includes, for example, silicon oxide or silicon oxynitride.
The insulator 104 containing excess oxygen preferably includes a region that releases oxygen molecules, the number of which is greater than or equal to 1.0×1014 molecules/cm2 and less than or equal to 1.0×1016 molecules/cm2 and preferably greater than or equal to 1.0×1015 molecules/cm2 and less than or equal to 5.0×1015 molecules/cm2 in thermal desorption spectroscopy (TDS) analysis in the range of a surface temperature of 100° C. to 700° C. or 100° C. to 500° C.
The method for measuring the amount of released oxygen using TDS analysis will be described below.
The total amount of gas released from a measurement sample in TDS analysis is proportional to the integral value of the ion intensity of the released gas. Then, comparison with a reference sample is made, whereby the total amount of released gas can be calculated.
For example, the number of oxygen molecules (NO2) released from a measurement sample can be calculated according to the following formula using the TDS results of a silicon substrate containing hydrogen at a predetermined density, which is a reference sample, and the TDS results of the measurement sample. Here, all gases having a mass-to-charge ratio of 32 which are obtained in the TDS analysis are assumed to originate from an oxygen molecule. Note that CH3OH, which is a gas having the mass-to-charge ratio of 32, is not taken into consideration because it is unlikely to be present. Furthermore, an oxygen molecule including an oxygen atom having a mass number of 17 or 18 which is an isotope of an oxygen atom is not taken into consideration either because the proportion of such a molecule in the natural world is negligible.

NO2=NH2/SH2×SO2×α

The value NH2 is obtained by conversion of the number of hydrogen molecules desorbed from the standard sample into densities. The value SH2 is the integral value of ion intensity when the standard sample is subjected to the TDS analysis. Here, the reference value of the standard sample is set to NH2/SH2. SO2 is the integral value of ion intensity when the measurement sample is analyzed by TDS. The value α is a coefficient affecting the ion intensity in the TDS analysis. Refer to Japanese Published Patent Application No. H6-275697 for details of the above formula. The amount of released oxygen was measured with a thermal desorption spectroscopy apparatus produced by ESCO Ltd., EMD-WA1000S/W, using a silicon substrate containing a certain amount of hydrogen atoms as the reference sample.
Furthermore, in the TDS analysis, oxygen is partly detected as an oxygen atom. The ratio between oxygen molecules and oxygen atoms can be calculated from the ionization rate of the oxygen molecules. Note that since the above a includes the ionization rate of the oxygen molecules, the number of the released oxygen atoms can also be estimated through the measurement of the number of the released oxygen molecules.
Note that NO2 is the number of the released oxygen molecules. The number of released oxygen in the case of being converted into oxygen atoms is twice the number of the released oxygen molecules.
Furthermore, the insulator 104 containing excess oxygen may contain a peroxide radical. Specifically, the spin density attributed to the peroxide radical is greater than or equal to 5×1017 spins/cm3. Note that the insulator containing a peroxide radical may have an asymmetric signal with a g factor of approximately 2.01 in electron spin resonance (ESR).
The insulator 104 may have a function of preventing diffusion of impurities from the substrate 100. The insulator 104 may be an insulator that has a hydrogen trap.
As described above, the top surface or the bottom surface of the semiconductor 106b preferably has high planarity. Thus, to improve the planarity, the top surface of the insulator 104 may be subjected to planarization treatment performed by a CMP method or the like.
The insulator 112 functions as a gate insulating film of the transistor 10. Like the insulator 104, the insulator 112 may be an insulator containing excess oxygen. Such insulator 112 makes it possible to supply oxygen from the insulator 112 to the insulator 106a, the semiconductor 106b, and the insulator 106c. As a result, the semiconductor 106b can be an oxide semiconductor with a low density of defect states and stable characteristics.
The insulator 112 may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator 112 may be formed using, for example, aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide.
The conductor 114 functions as the gate electrode of the transistor 10. The conductor 114 may be formed to have a single-layer structure or a stacked-layer structure using a conductor containing, for example, one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound of the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.
It is preferable that the end portion of the side surface of the conductor 114 in the channel length direction be substantially aligned with the end portion of the side surface of the insulator 112 in the channel length direction. With such a structure, the low-resistance regions 107a and 107b are substantially in contact with or partly overlap with the region of the semiconductor 106b that overlaps with the conductor 114 (channel formation region), whereby on-state current can be increased.
The insulator 116 functions as the protective insulating film of the transistor 10 and has a function of adding an element to the insulator 106a, the semiconductor 106b, and the insulator 106c. As described above, the insulator 116 adds an element to the insulator 106a, the semiconductor 106b, and the insulator 106c in the vicinity of the interface, so that the low-resistance region 107a and the low-resistance region 107b are formed. This leads to a reduction in contact resistance between the conductor 108a or 108b and the insulator 106a, the semiconductor 106b, or the insulator 106c, whereby the transistor 10 can have high on-state current.
The insulator 116 preferably has a function of blocking oxygen. Providing the insulator 118 can prevent oxygen from being externally released to above the insulator 104 at the time of supply of oxygen from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c. Accordingly, oxygen can be effectively supplied from the insulator 104 to the insulator 106a, the semiconductor 106b, and the insulator 106c. Here, the thickness of the insulator 116 can be greater than or equal to 5 nm, or greater than or equal to 20 nm, for example. The insulator 116 is preferably formed by a sputtering method or the like.
The insulator 116 can be formed using, for example, an oxide, an oxynitride, a nitride oxide, or a nitride containing one or more elements selected from boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. Note that in this specification, “oxynitride” refers to a material that contains oxygen at a higher proportion than nitrogen, and “nitride oxide” refers to a material that contains nitrogen at a higher proportion than oxygen.
These elements relatively easily form an oxide that can serve as a semiconductor or an insulator and thus, these elements are favorable as the element added to the insulator 106a, the semiconductor 106b, or the insulator 106c. 
In the case where the insulator 116 is formed using a nitride or a nitride oxide, aluminum, silicon, titanium, nickel, zinc, gallium, molybdenum, indium, tin, tungsten, or the like is preferably used, in which case the nitride or nitride oxide can have a stable physical property or a stable structure.
The insulator 116 is preferably formed using an insulator containing oxygen and aluminum, e.g., aluminum oxide. Aluminum oxide is suitable for the insulator 116 because it is highly effective in preventing transmission of both oxygen and impurities such as hydrogen and moisture.
The insulator 116 preferably has a blocking effect against oxygen, hydrogen, water, alkali metal, alkaline earth metal, copper, and the like. As such an insulator, for example, a nitride insulating film can be used. As examples of the nitride insulating film, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, an aluminum nitride oxide film, and the like can be given. Note that instead of the nitride insulating film, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like, may be provided. As examples of the oxide insulating film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, and the like can be given.
The above-described oxide that can be used for the insulator 106a or the insulator 106c can also be used for the insulator 116. The insulator 116 is preferably formed using an oxide insulator containing In, such as an In—Al oxide, an In—Ga oxide, or an In—Ga—Zn oxide. An oxide insulator containing In can be favorably used for the insulator 116 because the number of particles generated at the time of the deposition by a sputtering method is small.
The insulator 118 functions as the interlayer insulating film. The insulator 118 may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
The conductors 108a and 108b serve as a source electrode and a drain electrode of the transistor 10.
Each of the conductors 108a and 108b may be formed to have a single-layer structure or a stacked-layer structure using a conductor containing, for example, one or more of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound may also be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.
In the case where the conductors 108a and 108b are embedded in the insulator 118 and are connected to the conductors 109a and 109b over the insulator 118, the top surfaces of the insulator 118, the conductor 108a, and the conductor 108b are preferably subjected to planarization by a CMP method or the like to increase the planarity.
The conductor 109a and the conductor 109b each function as a wiring connected to either of the source electrode and the drain electrode of the transistor 10. For the conductors 109a and 109b, the conductor that can be used for the conductors 108a and 108b can be used.
With such a structure, a transistor with stable electrical characteristics, a transistor having a high on-state current, a transistor with normally-off electrical characteristics, a transistor with a small subthreshold swing value, or a highly reliable transistor can be provided.
Modification Example 1 of Transistor
Modification examples of the transistor 10 will be described below with reference to FIGS. 2A to 2F and FIGS. 3A to 3C. FIGS. 2A to 2F and FIGS. 3A to 3C are cross-sectional views of the transistors in the channel length direction and those in the channel width direction like FIGS. 1B and 1C. Note that the components in the following modification examples of the transistor 10 can be combined with each other as appropriate.
A transistor 11 illustrated in FIGS. 2A and 2B is different from the transistor 10 in that the end portion of the side surface of the semiconductor 106b is positioned inward from the end portion of the side surface of the insulator 106a. In other words, in the transistor 11, the peripheries of the insulators 106a and 106c are positioned outward from the periphery of the semiconductor 106b, and the semiconductor 106b is surrounded by the insulators 106a and 106c. Furthermore, the end portion of the side surface of the insulator 106a and the end portion of the side surface of the insulator 106c, especially those in the channel width direction, are preferably substantially aligned with each other.
Patterning is performed such that the end portion of the side surface of the semiconductor 106b is located inward from the end portion of the side surface of the insulator 106a as in the transistor 11 illustrated in FIGS. 2A and 2B, whereby the number of times of etching the insulator 104 at the time of etching the insulator 106a or the semiconductor 106b can be reduced. A portion of a surface of the insulator 104 that is to be etched can be away from the conductor 102, leading to an increase in withstand voltage of the transistor 11.
In the transistor 11 illustrated in FIGS. 2A and 2B or the like, the end portion of the side surface of the conductor 114 in the channel length direction is substantially aligned with the end portion of the side surface of the insulator 112 in the channel length direction; however, the structure of the semiconductor device described in this embodiment is not limited to the above structure. For example, as in a transistor 12 illustrated in FIGS. 2C and 2D, the width of the conductor 114 in the channel length direction may be smaller than the width of the insulator 112 in the channel length direction.
Although the conductor 102 and the insulator 103 are formed in the transistor 11 illustrated in FIGS. 2A and 2B or the like, the structure of the semiconductor device described in this embodiment is not limited thereto. For example, as in a transistor 13 illustrated in FIGS. 2E and 2F, a structure not including the conductor 102 and the insulator 103 may be employed.
A transistor 14 illustrated in FIGS. 3A and 3B is different from the transistor 11 in that part of the insulator 104 has a larger thickness. An end portion of a side surface of the thick region of the insulator 104 in the channel width direction is preferably located inward from the end portion of the side surface of the semiconductor 106b in the channel width direction. In other words, the insulator 104 has a projection and when seen from above, the periphery of the projection is located inward from the periphery of the semiconductor 106b. It is further preferable that the end portion of the side surface of the thick region of the insulator 104 in the channel width direction be located inward from the end portion of the side surface of the semiconductor 106b in the channel width direction by a distance approximately equal to the thickness of the insulator 106a. Here, a difference between the thickness of the thick region of the insulator 104 and the thin region thereof is preferably larger than the sum of the thicknesses of the insulator 106c and the insulator 112. With such a structure, substantially the entire side surface of the semiconductor 106b in the channel width direction can face the conductor 114 with the insulator 106c and the insulator 112 positioned therebetween.
With the above structure, the transistor 14 can have an s-channel structure similarly to the above transistor 10. Thus, in the transistor 14, a large amount of current can flow between a source and a drain, so that a high on-state current can be obtained.
Although the thick region of the insulator 104 extends in the channel length direction in the transistor 14 illustrated in FIG. 3A, the structure described in this embodiment is not limited to the above structure. For example, as illustrated in FIG. 3C, the end portion of the side surface of the thick region of the insulator 104 in the channel length direction may be located inward from the end portion of the side surface of the semiconductor 106b in the channel length direction.
The structure and method described in this embodiment can be implemented by being combined as appropriate with any of the other structures and methods described in the other embodiments.
Embodiment 2
In this embodiment, a method for manufacturing the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 4A to 4F and FIGS. 5A to 5F.
<Method 1 for Manufacturing Transistor>
A method for manufacturing the transistor 10 illustrated in FIGS. 1A to 1D will be described below.
First, the substrate 100 is prepared. Any of the above-mentioned substrates can be used for the substrate 100.
Next, the insulator 101 is formed. Any of the above-mentioned insulators can be used for the insulator 101.
The insulator 101 may be formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.
CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Depending on a source gas, CVD methods can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method.
A PECVD method allows formation of a high quality film at relatively low temperatures. A TCVD method does not use plasma and thus causes less plasma damage to an object. For example, a wiring, an electrode, an element (e.g., transistor or capacitor), or the like included in a semiconductor device might be charged up by receiving electric charges from plasma. In that case, accumulated electric charges might break the wiring, electrode, element, or the like included in the semiconductor device. Such plasma damage is not caused in the case of using a TCVD method, and thus the yield of a semiconductor device can be increased. In addition, since plasma damage does not occur in the deposition by a TCVD method, a film with few defects can be obtained.
An ALD method also causes less plasma damage to an object. Thus, a film with few defects can be formed by an ALD method.
Unlike in a deposition method in which particles ejected from a target or the like are deposited, in a CVD method and an ALD method, a film is formed by a reaction at a surface of an object. Thus, a CVD method and an ALD method can provide favorable step coverage almost regardless of the shape of an object. In particular, an ALD method can provide excellent step coverage and excellent thickness uniformity and can be favorably used for covering a surface of an opening with a high aspect ratio, for example. For that reason, a formed film is less likely to have a pinhole or the like. On the other hand, an ALD method has a relatively low deposition rate; thus, it is sometimes preferable to combine an ALD method with another deposition method with a high deposition rate such as a CVD method.
When a CVD method or an ALD method is used, composition of a film to be formed can be controlled with the flow rate ratio of source gases. For example, by the CVD method or the ALD method, a film with a desired composition can be formed by adjusting the flow rate ratio of source gases. Moreover, by a CVD method or an ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of source gases while forming the film. In the case where the film is formed while changing the flow rate ratio of the source gases, as compared to the case where the film is formed using a plurality of deposition chambers, time taken for the deposition can be reduced because time taken for transfer and pressure adjustment is omitted. Thus, semiconductor devices can be manufactured with improved productivity.
In a conventional deposition apparatus utilizing a CVD method, one or a plurality of source gases for reaction are supplied to a chamber at the same time at the time of deposition. In a deposition apparatus utilizing an ALD method, a source gas (also called precursor) for reaction and a gas serving as a reactant are alternately introduced into a chamber, and then the gas introduction is repeated. Note that the gases to be introduced can be switched using the respective switching valves (also referred to as high-speed valves).
For example, deposition is performed in the following manner. First, precursors are introduced into a chamber and adsorbed onto a substrate surface (first step). Here, the precursors are adsorbed onto the substrate surface, whereby a self-limiting mechanism of surface chemical reaction works and no more precursors are adsorbed onto a layer of the precursors over the substrate. Note that the proper range of substrate temperatures at which the self-limiting mechanism of surface chemical reaction works is also referred to as an ALD window. The ALD window depends on the temperature characteristics, vapor pressure, decomposition temperature, and the like of a precursor. Next, an inert gas (e.g., argon or nitrogen) or the like is introduced into the chamber, so that excessive precursors, a reaction product, and the like are released from the chamber (second step). Instead of introduction of an inert gas, vacuum evacuation can be performed to release excessive precursors, a reaction product, and the like from the chamber. Then, a reactant (e.g., an oxidizer such as H2O or O3) is introduced into the chamber to react with the precursors adsorbed onto the substrate surface, whereby part of the precursors is removed while the molecules of the film are adsorbed onto the substrate (third step). After that, introduction of an inert gas or vacuum evacuation is performed, whereby excessive reactant, a reaction product, and the like are released from the chamber (fourth step).
A first single layer can be formed on the substrate surface in the above manner. By performing the first to fourth steps again, a second single layer can be stacked over the first single layer. With the introduction of gases controlled, the first to fourth steps are repeated plural times until a film having a desired thickness is obtained, whereby a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times; therefore, an ALD method makes it possible to adjust a thickness accurately and thus is suitable for manufacturing a minute transistor.
In an ALD method, a film is formed through reaction of the precursor using thermal energy. An ALD method in which the reactant becomes a radical state with the use of plasma in the above-described reaction of the reactant is sometimes called a plasma ALD method. An ALD method in which reaction between the precursor and the reactant is performed using thermal energy is sometimes called a thermal ALD method.
By an ALD method, an extremely thin film can be formed to have a uniform thickness. In addition, the coverage of an uneven surface with the film is high.
When the plasma ALD method is employed, the film can be formed at a lower temperature than when the thermal ALD method is employed. With the plasma ALD method, for example, the film can be formed without decreasing the deposition rate even at 100° C. or lower. Furthermore, in the plasma ALD method, any of a variety of reactants, including a nitrogen gas, can be used without being limited to an oxidizer; therefore, it is possible to form various kinds of films of not only an oxide but also a nitride, a fluoride, a metal, and the like.
In the case where the plasma ALD method is employed, as in an inductively coupled plasma (ICP) method or the like, plasma can be generated apart from a substrate. When plasma is generated in this manner, plasma damage can be minimized.
Then, the insulator 103 is deposited. For the insulator 103, the above-described insulator can be used. The insulator 103 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Next, a resist or the like is formed over the insulator 103 and an opening is formed in the insulator 103. Note that the case where the resist is simply formed also includes the case where an anti-reflective layer is formed below the resist.
The resist or the like is removed after the object is processed by etching or the like. For the removal of the resist or the like, plasma treatment and/or wet etching are/is used. Note that as the plasma treatment, plasma ashing is preferable. In the case where the removal of the resist or the like is not enough, the remaining resist or the like may be removed using ozone water and/or hydrofluoric acid at a concentration higher than or equal to 0.001 weight % and lower than or equal to 1 weight %, and the like.
Next, a conductor to be the conductor 102 is formed. For the conductor to be the conductor 102, the above-described conductor can be used. The conductor to be the conductor 102 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Next, the conductor to be the conductor 102 over the insulator 103 is removed by CMP treatment. As a result, the conductor 102 remains only in the opening formed in the insulator 103.
Then, the insulator 104 is formed (see FIGS. 4A and 4B). For the insulator 104, the above-described insulator can be used. The insulator 104 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
The top surface or the bottom surface of the semiconductor 106b to be formed later preferably has high planarity. Thus, to improve the planarity, the top surface of the insulator 104 may be subjected to planarization treatment such as CMP.
Then, an insulator to be the insulator 106a in a later step is formed. For the insulator, the above-described insulator, semiconductor, or conductor that can be used for the insulator 106a can be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Here, it is preferable that the insulator to be the insulator 106a be formed by a sputtering method and it is further preferable that the insulator to be the insulator 106a be formed by a sputtering method in an atmosphere containing oxygen. For the sputtering, a parallel-plate-type sputtering apparatus or a facing-targets sputtering apparatus may be used. As will be described later, deposition using a facing-targets sputtering apparatus causes less damage to a formation surface and thus facilitates the formation of a film with high crystallinity. For this reason, a facing-targets sputtering apparatus is preferably used for the deposition of the CAAC-OS described later in some cases.
Deposition using a parallel-plate-type sputtering apparatus can also be referred to as parallel electrode sputtering (PESP), and deposition using a facing-targets sputtering apparatus can also be referred to as vapor deposition sputtering (VDSP).
When the insulator to be the insulator 106a is formed by a sputtering method, oxygen is sometimes added to a surface of the insulator 104 (interface between the insulator 106a and the insulator 104, after the deposition of the insulator 106a) and the vicinity thereof during the formation. Although the oxygen is added to the insulator 104 as an oxygen radical here, for example, the state of the oxygen at the time of being added is not limited thereto. The oxygen may be added to the insulator 104 as an oxygen atom, an oxygen ion, or the like. Oxygen addition to the insulator 104 enables the insulator 104 to contain excess oxygen.
A mixed region might be formed in a region in the vicinity of the interface between the insulator 104 and the insulator to be the insulator 106a. The mixed region contains a component of the insulator 104 and a component of the insulator to be the insulator 106a. 
Next, a semiconductor to be the semiconductor 106b in a later step is formed. For the semiconductor, the above-described semiconductor that can be used for the semiconductor 106b can be used. The semiconductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A PESP method or a VDSP method can be employed. Note that successive formation of the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b without exposure to the air can reduce entry of impurities into the films and their interface.
It is preferable to use, as a deposition gas, a mixed gas of a rare gas such as argon (other examples include helium, neon, krypton, and xenon) and oxygen. For example, the proportion of oxygen in the whole deposition gas is less than 50 volume %, preferably less than or equal to 33 volume %, further preferably less than or equal to 20 volume %, and still further preferably less than or equal to 15 volume %.
When deposition is performed by a sputtering method, the substrate temperature may be set high. By setting the substrate temperature high, migration of sputtered particles at the top surface of the substrate can be promoted. Thus, an oxide with higher density and higher crystallinity can be deposited. Note that the substrate temperature is, for example, higher than or equal to 100° C. and lower than or equal to 450° C., preferably higher than or equal to 150° C. and lower than or equal to 400° C., further preferably higher than or equal to 170° C. and lower than or equal to 350° C.
Next, heat treatment is preferably performed. The heat treatment can reduce the hydrogen concentration in the insulator 106a and the semiconductor 106b formed in later steps in some cases. The heat treatment can reduce oxygen vacancies in the insulator 106a and the semiconductor 106b formed in later steps in some cases. The heat treatment is performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 450° C. and lower than or equal to 600° C., and further preferably higher than or equal to 520° C. and lower than or equal to 570° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate desorbed oxygen. The heat treatment can increase the crystallinity of the insulator 106a and the semiconductor 106b formed in later steps and can remove impurities, such as hydrogen and water, for example. For the heat treatment, lamp heating can be performed with the use of an RTA apparatus.
By the heat treatment, oxygen can be supplied from the insulator 104 to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b. Owing to the heat treatment performed on the insulator 104, oxygen can be supplied to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b very easily.
Here, the insulator 101 functions as a barrier film that blocks oxygen. The insulator 101 is provided below the insulator 104, thereby preventing the oxygen diffused in the insulator 104 from being diffused below the insulator 104.
Oxygen is supplied to the insulator to be the insulator 106a and the semiconductor to be the semiconductor 106b to reduce oxygen vacancies in this manner, whereby a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor with a low density of defect states can be obtained.
Furthermore, high-density plasma treatment or the like may be performed. High-density plasma may be generated using microwaves. For the high-density plasma treatment, an oxidation gas such as oxygen or nitrous oxide may be used, for example. Alternatively, a mixed gas of an oxidation gas and a rare gas such as He, Ar, Kr, or Xe may be used. In the high-density plasma treatment, a bias may be applied to the substrate, in which case oxygen ions or the like in the plasma can be attracted to the substrate side. The high-density plasma treatment may be performed while the substrate is heated. In the case where the high-density plasma treatment is performed instead of the heat treatment, for example, an effect similar to that of the heat treatment can be obtained at lower temperatures. The high-density plasma treatment may be performed before the deposition of the insulator to be the insulator 106a, after the deposition of the insulator 112, or after the deposition of the insulator 116.
Next, a resist or the like is formed over the semiconductor to be the semiconductor 106b and processing is performed using the resist or the like, whereby the insulator 106a and the semiconductor 106b are formed. As illustrated in FIGS. 4C and 4D, an exposed surface of the insulator 104 is removed at the time of formation of the semiconductor 106b in some cases.
Then, an insulator to be the insulator 106c in a later step is formed. For the insulator, the above-described insulator, semiconductor, or conductor can be used. The insulator can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A PESP method or a VDSP method can be employed.
Next, a resist or the like is formed over the insulator to be the insulator 106c and processing is performed using the resist or the like, whereby the insulator 106c is formed (see FIGS. 4C and 4D). As illustrated in FIGS. 4C and 4D, an exposed surface of the insulator 104 is removed at the time of formation of the insulator 106c in some cases.
Here, patterning is performed such that the end portion of the side surface of the insulator 106c is located outward from the end portion of the side surface of the semiconductor 106b. It is particularly preferable that as illustrated in FIG. 4D, patterning be performed such that the end portion of the side surface of and the insulator 106c in the channel width direction is located outward from the end portion of the side surface of the semiconductor 106b in the channel width direction. When the insulator 106c is formed in the above manner, the semiconductor 106b is surrounded by the insulator 106a and the insulator 106c. 
In the above structure, the end portion of the side surface of the semiconductor 106b, especially the end portion of the side surface thereof in the channel width direction, is in contact with the insulator 106a and the insulator 106c. As a result, in the end portion of the side surface of the semiconductor 106b, continuous junction is formed between the insulator 106a and the semiconductor 106b or between the insulator 106c and the semiconductor 106b and the density of defect states is reduced. Thus, even when on-state current easily follows owing to the low-resistance region 107a and the low-resistance region 107b, the end portion of the side surface of the semiconductor 106b in the channel width direction does not serve as a parasitic channel, which enables stable electrical characteristics.
Next, an insulator to be the insulator 112 in a later step is deposited. For the insulator, the above-described insulator that can be used for the insulator 112 can be used. The insulator can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, for the deposition of the insulator 112, an ALD method at a substrate temperature during the deposition of higher than or equal to 400° C. and lower than or equal to 520° C., preferably higher than or equal to 450° C. and lower than or equal to 500° C., may be employed. Deposition at high substrate temperatures allows a reduction in the concentration of impurities contained in the insulator 112. For example, since a carbon compound, water, or the like contained in a deposition gas or a deposition chamber can be reduced, the concentration of carbon and/or hydrogen can be reduced. Deposition at high substrate temperatures also allows an increase in the density (or film density) of the insulator 112. An increase in the density of the insulator 112 can reduce the density of defect states of the insulator 112; thus, a transistor to be manufactured can have stable electrical characteristics.
Next, a conductor to be the conductor 114 in a later step is formed. For the conductor, the above-described conductor that can be used for the conductor 114 can be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Next, a resist or the like is formed over the conductor to be the conductor 114 and processing is performed with the resist or the like, whereby the insulator 112 and the conductor 114 are formed (see FIGS. 4E and 4F). Here, after the insulator 112 and the conductor 114 are formed such that the end portion of the side surface of the conductor 114 in the channel length direction is substantially aligned with the end portion of the side surface of the insulator 112 in the channel length direction, only the conductor 114 may be selectively etched by wet etching or the like using the same mask. When such etching is performed, as in the transistor 12 illustrated in FIGS. 2C and 2D, the width of the conductor 114 in the channel length direction can be smaller than the width of the insulator 112 in the channel length direction.
Next, a dopant 119 is added to the insulator 106a, the semiconductor 106b, and the insulator 106c using the conductor 114 and the insulator 112 as a mask (see FIGS. 4E and 4F). As a result, the region 126a, a region 136b, and a region 136c are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c. Note that the regions 136b and 136c become the regions 126b and 126c in the later step. Thus, the concentration of the dopant 119 measured by SIMS is higher in the region 136b and the region 136c than in the region 126a. For the addition of the dopant 119, an ion implantation method by which an ionized source gas is subjected to mass separation and then added, an ion doping method by which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used. In the case of performing mass separation, ion species to be added and its concentration can be controlled properly. In contrast, in the case of not performing mass separation, ions at a high concentration can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be employed. Note that the term “dopant” may be changed into the term “ion,” “donor,” “acceptor,” “impurity,” or “element.”
The addition of the dopant 119 may be controlled by setting the addition conditions such as the acceleration voltage and the dosage as appropriate. The dosage of the dopant 119 is, for example, greater than or equal to 1×1012 ions/cm2 and less than or equal to 1×1016 ions/cm2, and preferably greater than or equal to 1×1013 ions/cm2 and less than or equal to 1×1015 ions/cm2. The acceleration voltage at the time of the addition of the dopant 119 is higher than or equal to 2 kV and lower than or equal to 50 kV, and preferably higher than or equal to 5 kV and lower than or equal to 30 kV.
The dopant 119 may be added while the substrate is heated. The substrate temperature is, for example, higher than or equal to 200° C. and lower than or equal to 700° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., and further preferably higher than or equal to 350° C. and lower than or equal to 450° C.
Examples of the dopant 119 include hydrogen, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. Among these elements, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, and boron are preferable because these elements can be added relatively easily by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.
After the addition of the dopant 119, heat treatment may be performed. The heat treatment may be performed at 250° C. or higher and 650° C. or lower and preferably 350° C. or higher and 450° C. or lower in a nitrogen atmosphere, or under reduced pressure or air (ultra dry air), for example.
In the case where oxygen vacancies are formed in the regions 136b and 136c by the addition of the dopant 119, for example, heat treatment performed after the addition of the dopant 119 can cause gettering of hydrogen 122 around the regions 136b and 136c at the sites of the oxygen vacancies (see FIGS. 6A and 6B). Accordingly, the resistances of the regions 136b and 136c can be reduced and thus, the regions 126b and 126c can be formed. Since a donor level formed in such a manner is stable, the resistances are hardly increased later. Note that in the case where the resistances of the regions 126b and 126c can be sufficiently reduced by the heat treatment, a step of adding a dopant 120 described below can be skipped.
Next, the dopant 120 is added to the insulator 106a, the semiconductor 106b, and the insulator 106c using the conductor 114 and the insulator 112 as a mask (see FIGS. 5A and 5B). As a result, the resistances of the regions 136b and 136c can be reduced and thus, the regions 126b and 126c can be formed. Thus, the concentration of the dopant 120 measured by SIMS is higher in the region 126b and the region 126c than in the region 126a. Examples of a method for adding the dopant 120 include an ion implantation method, an ion doping method, and a plasma immersion ion implantation method. Note that the term “dopant” may be changed into the term “ion,” “donor,” “acceptor,” “impurity,” or “element.”
The addition of the dopant 120 may be controlled by setting the addition conditions such as the acceleration voltage and the dosage as appropriate. The dosage of the dopant 120 is, for example, greater than or equal to 1×1012 ions/cm2 and less than or equal to 1×1016 ions/cm2, preferably greater than or equal to 1×1013 ions/cm2 and less than or equal to 1×1015 ions/cm2. The acceleration voltage at the time of the addition of the dopant 120 is higher than or equal to 2 kV and lower than or equal to 50 kV, preferably higher than or equal to 5 kV and lower than or equal to 30 kV.
The dopant 120 may be added while the substrate is heated. The substrate temperature is, for example, higher than or equal to 200° C. and lower than or equal to 700° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., and further preferably higher than or equal to 350° C. and lower than or equal to 450° C. If the dopant 120 is added while heated as described here, a decrease in the crystallinity of the insulator 106a, the semiconductor 106b, and the insulator 106c due to the addition of the dopant 120 can be inhibited.
As the dopant 120, a dopant other than that added as the dopant 119 may be added. For example, hydrogen, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten are given. Among these elements, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, and boron are preferable because these elements can be added relatively easily by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.
After the addition of the dopant 120, heat treatment may be performed. The heat treatment may be performed at higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 350° C. and lower than or equal to 450° C. in a nitrogen atmosphere, or under reduced pressure or air (ultra dry air), for example.
Hereinafter, methods for adding the dopant 119 and the dopant 120 will be described with reference to FIGS. 7A1, 7A2, 7B, and 7C. Here, an ion implantation method or an ion doping method in which an ion is used as a dopant will be described in detail.
Although ion addition by ion doping treatment can be performed at a specific angle (e.g., a right angle) with respect to a sample surface, any of the methods described with reference to FIGS. 7A1, 7A2, 7B, and 7C is preferable. FIGS. 7A1, 7A2, 7B, and 7C each schematically illustrate the state where one ion is incident on a sample surface at an angle θ and an angle φ.
The x-axis, the y-axis, and the z-axis in each of FIGS. 7A1, 7A2, 7B, and 7C are straight lines intersecting with each other at an incident point of a certain ion. The x-axis is a given straight line on the sample surface. The y-axis is a straight line that is on the sample surface and intersects with the x-axis at right angles. The z-axis is the normal to the sample surface that passes through the incident point. The angle θ is an angle formed by the ion incident direction and the z-axis in a cross-sectional direction. The angle φ is an angle formed by the ion incident direction and the x-axis when seen from the top.
In the case where an ion is incident on the sample surface at a specific angle (θ, φ) using an object as a mask, the ion can also be added to part of the sample under the object.
In the case where an ion is incident on the sample surface only at a specific angle (θ, φ), a region where the ion is not added might exist on the opposite side of the ion incident side, because of the height of the object. A region where an ion is not added can be referred to as the shade of an object. For this reason, the ion is preferably incident at a plurality of angles, in which case an influence of the shade on the sample surface can be reduced.
As illustrated in FIGS. 7A1 and 7A2, the ion is preferably incident on the sample surface at a first angle (θ, φ) and then incident thereon at a second angle (θ, φ). Note that at least one of the angles θ and φ of the first angle (θ, φ) is different from that of the second angle (θ, φ).
The angle θ of the first angle (θ, φ) is, for example, greater than or equal to 10° and less than or equal to 60°, preferably greater than or equal to 15° and less than or equal to 45°, and further preferably greater than or equal to 20° and less than or equal to 40°. The angle θ of the second angle (θ, φ) is, for example, greater than or equal to 10° and less than or equal to 60°, preferably greater than or equal to 15° and less than or equal to 45°, and further preferably greater than or equal to 20° and less than or equal to 40°. Note that the angle θ of the second angle (θ, φ) and the angle θ of the first angle (θ, φ) are symmetric about the z-axis. Thus, the angle θ of the second angle (θ, φ) can be expressed by negative values. Specifically, the angle θ of the second angle (θ, φ) can be, for example, greater than or equal to −60° and less than or equal to −10°, preferably greater than or equal to −45° and less than or equal to −15°, and further preferably greater than or equal to −40° and less than or equal to −20°.
In the case where an ion is incident on the sample surface at a specific angle as described above, the thickness t of the insulator 112 in FIG. 1D is correlated with the distance d. When an ion is incident through an upper end portion of the side surface of the insulator 112, for example, a point where the ion is incident on the insulator 106c is t·tan θ away from the end portion of the side surface of the conductor 114. The conductor 114 contains a metal in many cases and is hardly permeable to the ion. Accordingly, the penetration length of the ion into the channel formation region in the channel length direction becomes maximum when the ion is incident through the upper end portion of the side surface of the insulator 112. In this way, the distance t·tan θ serves as an indication of the distance d illustrated in FIG. 1D, which means that the thickness t is correlated with the distance d. For example, when the incident angle θ of the ion is set greater than or equal to 15° and less than or equal to 45° as described above, tan 15° is 0.2679 and tan 45° is 1, which is well correspondent with 0.25t<d<t described above.
The angle φ of the second angle (θ, φ) is larger than the angle co of the first angle (θ, φ) by 90° or more and 270° or less and preferably 135° or more and 225° or less, for example, and specifically by 180°. Note that the ranges of the first angle (θ, φ) and the second angle (θ, φ) described here are just examples, and are not limited to the above ranges.
The ion incident angle is not limited to the two kinds of angles: the first angle (θ, φ) and the second angle (θ, φ). For example, the ion incident angle may be the first angle (θ, φ) to an n-th angle (θ, φ) (n is a natural number of 2 or more). The angles θ and/or the angles φ of the first angle (θ, φ) to the n-th angle (θ, φ) are different angles.
Alternatively, the ion may be incident on the sample surface at the first angle (θ, φ) and then scanning in the θ direction (also referred to as θ scanning) may be performed from the first angle (θ, φ) to the second angle (θ, φ) such that the angle θ passes through 0°, as illustrated in FIG. 7B. Note that the ion incident angle φ is not limited to one kind of angle and may be a first angle φ to an n-th angle φ (n is a natural number of 2 or more).
The angle θ of the first angle (θ, φ) is, for example, greater than or equal to 10° and less than or equal to 60°, preferably greater than or equal to 15° and less than or equal to 45°, and further preferably greater than or equal to 20° and less than or equal to 40°. The angle θ of the second angle (θ, φ) is, for example, greater than or equal to 10° and less than or equal to 60°, preferably greater than or equal to 15° and less than or equal to 45°, and further preferably greater than or equal to 20° and less than or equal to 40°. The angle θ of the first angle (θ, φ) may be equal to the angle θ of the second angle (θ, φ).
Note that the θ scanning may be performed continuously or stepwise, that is, in steps of, for example, 0.5°, 1°, 2°, 3°, 4°, 5°, 6°, 10°, 12°, 18°, 20°, 24°, or 30°.
Alternatively, the ion may incident on the sample surface at the first angle (θ, φ) and then scanning in the φ direction (also referred to as φ scanning) may be performed so that the ion incident angle is changed from the first angle (θ, φ) to the second angle (θ, φ) as illustrated in FIG. 7C. Note that the ion incident angle θ is not limited to one kind of angle and may be any of a first angle θ to an n-th angle θ (n is a natural number of 2 or more).
The angle θ of the first angle (θ, φ) and the second angle (θ, φ) is, for example, greater than or equal to 10° and less than or equal to 60°, preferably greater than or equal to 15° and less than or equal to 45°, and further preferably greater than or equal to 20° and less than or equal to 40°. The angle φ of the first angle (θ, φ) may be equal to the angle φ of the second angle (θ, φ).
Note that the φ scanning may be performed continuously or stepwise, that is, in steps of, for example, 0.5°, 1°, 2°, 3°, 4°, 5°, 6°, 10°, 12°, 18°, 20°, 24°, or 30°.
Although not illustrated, the θ scanning and the φ scanning may be performed in combination.
In the above manner, the regions 126b and 126c to which an ion is added are formed.
With the use of any of the methods described with reference to FIGS. 7A1, 7A2, 7B, and 7C, the regions 126b and 126c can be formed not only in a region not overlapping with the conductor 114 but also in a region partly overlapping with the conductor 114. In that case, an offset region having high resistance is not formed between the region 126a and each of the region 126b and the region 126c, leading to an increase in the on-state current of the transistor.
The addition of the dopant 119 and the dopant 120 can reduce the resistances of the regions 126b and 126c. The mechanism of a reduction in the resistances of the regions 126b and 126c depends on the combination of the dopant 119 and the dopant 120.
For example, if the dopant 119 and the dopant 120 form different donor levels, the resistances of the regions 126b and 126c can be reduced.
The resistances of the regions 126b and 126c can be reduced also in the following manner, for example: the dopant 119 is added first, and then the dopant 120 is added to form a donor level. In that case, to form the donor level, for example, oxygen vacancies are formed in the regions 126b and 126c by the addition of the dopant 119 and then the dopant 120 is added. Alternatively, to form the donor level, for example, oxygen vacancies are formed in the regions 126b and 126c by the addition of the dopant 119 followed by the addition of the dopant 120, and then the dopant 119 or the dopant 120 is transferred to the sites of the oxygen vacancies by heat treatment or the like. The donor level might be formed when hydrogen enters the sites of the oxygen vacancies, for example. The donor level formed in such a manner is stable and thus, the resistance is hardly increased later.
Described below is the reason why the resistivity of an oxide semiconductor is reduced when the oxide semiconductor contains oxygen vacancies and hydrogen. Here, a state in which a hydrogen atom H is at the site of an oxygen vacancy (VO) is expressed as VOH.
<1-a: Calculation Method>
The influence of the coexistence of VO and hydrogen in an In—Ga—Zn oxide was investigated by first-principles calculations. First, an oxygen site where VO is likely to be formed, and an existing form of a hydrogen atom were investigated. Then, the stability of the hydrogen atom inside or outside VO was investigated. Lastly, the transition level of a defect that easily exists stably was calculated.
The Vienna Ab initio Simulation Package (VASP) was used in the first-principles calculations. The Heyd-Scuseria-Ernzerhof (HSE) functional was used as a hybrid functional, the Perdew-Burke-Ernzerhof (PBE) generalized gradient approximation (GGA) was used for an exchange-correlation potential, and a projector augmented-wave (PAW) method was used for a pseudopotential. GGA was used in the calculation for the stability of the hydrogen atom inside or outside VO, and the HSE functional was used to calculate the formation energy and the transition level because the energy gap value needs to be accurate. For GGA, the energy cutoff was 500 eV, and a 2×2×3 Monkhorst-Pack mesh was used for k-point sampling. For the HSE functional, the energy cutoff was 800 eV, and Γ-only k-point sampling was used. In addition, the screening parameter of the HSE functional was 2 nm−1, and the fraction of the Hartree-Fock exchange term was 0.25.
<1-b: Formation Energy of Defect>
A defect concentration c is calculated using a formation energy (Eform(D)) of a defect D and Equation (1).

c=Nsitesexp{−Eform(D)/kBT}  (1)

In Equation (1), Nsites represents the number of sites where defects D can be formed, kB represents the Boltzmann constant, and T represents temperature. From Equation (1), the lower the formation energy is, the more likely it is that the defect D is formed. The formation energy was thus calculated from Equation (2).




  
    
      
        
          
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In Equation (2), Etot(Dq) represents the total energy of a cell containing the defect D with charge q, Etot(bulk) represents the total energy of a perfect crystal, Δni represents the difference in the number of atoms i, μi represents the chemical potential of an atom i, ∈VBM represents the valence band maximum (VBM), ΔVq represents the correction term related to a reference potential, and EF represents the Fermi energy. VBM at this time is expressed as a Fermi energy of 0 eV. The chemical potential depends on the environment. Thus, the upper limit of the chemical potential of oxygen (μO), which corresponds to an oxygen-rich condition, was set at half of the total energy of an oxygen molecule. The chemical potential of hydrogen (μH) under such a condition was set at half of a value obtained by subtracting the chemical potential of oxygen from the total energy of a water molecule.
Note that the oxygen-rich condition is, when an oxygen vacancy is generated for example, a condition where oxygen easily enters the oxygen vacancy, that is, a condition where formation of an oxygen vacancy is prevented.
Meanwhile, the chemical potential of hydrogen (μH) under a hydrogen-rich condition was set at half of the total energy of a hydrogen molecule. The chemical potential of oxygen under such a condition was the lower limit (oxygen-poor condition), which was obtained by subtracting a value twice as large as μH from the total energy of a water molecule.
Note that the oxygen-poor condition is a condition where formation of an oxygen vacancy is promoted when the oxygen vacancy is generated.
<1-c: Transition Level of Defect>
A level involving transition to a different charge state, which is also called a transition level, exists in an energy gap depending on the kind of defect. This causes capture or release of carriers depending on the depth of the level and the position of the Fermi level. The transition level (∈(q/q′)) of the defect D was calculated from Equation (3).




  
    
      
        
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The value of ∈(q/q′) obtained from Equation (3) corresponds to the transition level when the valence band maximum is set to 0.0 eV. In other words, a value obtained by subtracting the transition level from the energy gap equals the depth from the conduction band minimum (CBM). When the Fermi level is closer to the valence band than (∈(q/q′)), the defect is stable in the charge state q. In contrast, when the Fermi level is closer to the conduction band than (∈(q/q′)), the defect is stable in the charge state q′.
<1-d: Diffusion of Atoms>
Next, a path and an activation barrier in a diffusion process of atoms were investigated by a nudged elastic band (NEB) method. The NEB method is used to determine a path that requires the lowest energy among paths between the initial state and the final state. A calculation for relaxing the atomic coordinates to reduce the force applied to the atoms to 0.5 eV/nm or lower was performed.
<1-e: Structure for Calculation>
In general, a cell that includes a defect is formed such that one defect exists in a perfect crystal. To set a three-dimensional periodic boundary condition, the distance between defects, i.e., the lattice size needs to be increased in order to reduce the interaction between the defects. In an InGaO3(ZnO)m crystal that has a homologous structure, the lattice constant a (and the lattice constant b) is much smaller than the lattice constant c. For that reason, rendering the lattice sizes in the a-axis direction and the b-axis direction substantially equal to the lattice constant c causes an extremely large number of atoms. Thus, a super cell (InGaZnO4) with 112 atoms was prepared (see FIG. 8). The super cell was obtained by setting the lattice vectors at (420), (040), and (211) when m=1 and then reducing the lattice constant c to one-third. In that case, the distance between defects can be 0.8 nm or more in the direction of the shortest axis.
In InGaO3(ZnO)m (m=1), two layers formed of Ga, Zn, and O (i.e., (Ga, Zn)O layers) exist between an InO2 layer and its adjacent InO2 layer. The arrangement of Ga and Zn in the two layers is determined such that the energy becomes the lowest. In that case, there are four types of oxygen sites, which are represented by O(1) to O(4) in FIG. 8, depending on the combination of the metal atoms closest to oxygen. The four sites are specifically, an O site (O(1)) that is bonded to three In atoms and one Zn atom, an O site (O(2)) that is bonded to three In atoms and one Ga atom, an O site (O(3)) that is bonded to one Ga atom and two Zn atoms in the a-b plane direction, and an O site (O(4)) that is bonded to two Ga atoms and one Zn atom in the a-b plane direction.
The lattice constant and the atomic coordinates of the perfect crystal were optimized by using GGA or the HSE functional. Table below shows the obtained lattice constants and energy gaps. The table also shows the lattice constants and the energy gap obtained by an experiment for comparison. Compared to the experimental values, the lattice constants are overestimated and the energy gap is underestimated when GGA is used. When the HSE functional is used, the lattice constants and the energy gap are close to the experimental values. Note that a slight difference between the lattice constants a and b obtained by the calculation is attributed to the arrangement of Ga and Zn.












TABLE 1







a [Å]
b [Å]
c [Å]
Energy gap [eV]






















GGA
3.337
3.372
26.260
1.10



HSE
3.300
3.327
25.868
3.08













Experimental
3.295

26.071
3.15



data










<2-a: Site where VO is Likely to be Formed>

Before the investigation of the influence of the coexistence of VO and hydrogen, the influence of VO or hydrogen alone is investigated.
First, a site where VO is likely to be formed was investigated. A cell including VO was prepared by removing one oxygen atom from a perfect crystal, and relaxation of atomic arrangement was performed using the HSE functional. Table below shows the formation energies of VO calculated under oxygen-rich condition. Note that nM represents the coordination number of a metal atom M (=In, Ga, and Zn) adjacent to oxygen.














TABLE 2





Oxygen



Formation energy
ε (2+/+)
ε (+/0)
ε (2+/0)


site
nIn
nGa
nZn
[eV]
[eV]
[eV]
[eV]







O(1)
3
0
1
3.87
2.24
2.28
2.26


O(2)
3
1
0
4.09
2.47
2.69
2.56


O(3)
0
1
2
3.85
2.42
2.17
2.29


O(4)
0
2
1
4.27
2.34
2.14
2.24









The formation energy of VO in O(1) is lower than that in O(2). The oxygen atoms in O(1) and O(2) are each a tetracoordinate oxygen atom and bonded to three In atoms. The other bonding partner is Zn in O(1), and the other bonding partner is Ga in O(2). If this difference is a significant factor for the difference in the formation energy, it is assumed that Ga is more strongly bonded to oxygen than Zn. In addition, the formation energy of VO in O(3) is lower than that in O(4). The number of bonded Ga atoms in the a-b plane direction in O(3) is smaller than that in O(4); consequently, the bond between Ga and O is strong in O(3). Thus, VO is probably likely to be formed in O(1) and O(3) where the coordination number of Ga is small.
The transition levels of VO are shown in Table 2. In O(3) and O(4), the ∈(2+/+) transition level of VO is closer to the conduction band than the ∈(+/0) transition level. In O(1), the ∈(2+/+) transition level of VO is substantially equal to the ∈(+/0) transition level. This indicates that when the Fermi level is shifted from the valence band side to the conduction band side, the transition from VO2+ to VO0 occurs without passing through VO+. That is, VO exhibits negative-U behavior, which is known to be exhibited in the case of zinc oxide. Furthermore, the ∈(2+/0) transition levels of VO in O(1) and O(3) where the formation energies are low are as deep as approximately 0.8 eV below the conduction band minimum (the Fermi energy: 3.15 eV). This indicates that VO in an In—Ga—Zn oxide is a deep-level donor. The results agree with results of an InGaO3(ZnO)m crystal (m=3).
<2-b: Existing Form of Hydrogen>
Next, existing forms of hydrogen were examined. In an In—Ga—Zn oxide, hydrogen exists in three possible modes: a hydrogen atom in an interstitial site; a hydrogen molecule in an interstitial site; and hydrogen bonded to oxygen. In view of this, three cells were prepared: a cell in which a hydrogen atom (Hoct) was arranged at an octahedral interstitial site (Int(5) in FIG. 8) between the InO2 layer and the (Ga, Zn)O layer; a cell in which a hydrogen molecule ((H2)oct) was arranged at an octahedral interstitial site (Int(5) in FIG. 8) between the InO2 layer and the (Ga, Zn)O layer; and a cell in which a hydrogen atom (bonded-H) was bonded to an oxygen atom of the Ga—O bond parallel to the c-axis on the side opposite to Ga. Atomic relaxation was performed using the HSE functional.
FIGS. 9A and 9B show changes in formation energy with respect to the Fermi energy. FIG. 9A shows the formation energies calculated under the oxygen-rich condition, and FIG. 9B shows the formation energies calculated under the oxygen-poor condition. For comparison of the formation energy per hydrogen atom, a half value of the formation energy of (H2)oct is shown in each of FIGS. 9A and 9B. Here, VBM is expressed as a Fermi energy of 0 eV, and CBM is expressed as a Fermi energy of 3.15 eV. In FIGS. 9A and 9B, a straight line with no slope indicates that the charge state of each defect is neutral, a straight line with a negative slope indicates that the charge state is negative, and a straight line with a positive slope indicates that the charge state is positive.
The hydrogen molecule (H2)oct was neutrally charged from VBM to less than 2.82 eV and was negatively charged from greater than or equal to 2.82 eV to CBM.
The hydrogen molecule Hoct was neutrally charged from VBM to less than 2.17 eV and was negatively charged from greater than or equal to 2.17 eV to CBM. Note that no stable Hoct+ was observed.
The hydrogen atom (bonded-H) bonded to the oxygen atom was positively charged from VBM to less than 2.82 eV and was neutrally charged from greater than or equal to 2.82 eV to CBM.
The results of comparison of the formation energies indicate that hydrogen in the In—Ga—Zn oxide is likely to exist stably as a hydrogen atom (bonded-H) bonded to an oxygen atom in all regions in the energy gap regardless of the oxygen condition.
<2-c: Stable Structure for Coexistence of VO and H>
In Sections 2-a and 2-b, the stabilities of VO and hydrogen were examined individually. When VO and a hydrogen atom coexist in one cell, a state where VO and the hydrogen atom separately exist, and a state where the hydrogen atom is trapped in VO (VOH) are considered. Here, which of the two states was more stable was determined.
Cells where VO was located in O(1) and one hydrogen atom was located at any position and cells where VO was located in O(3) and one hydrogen atom was located at any position were prepared. Atomic relaxation was performed on each cell. Here, GGA was used for an exchange-correlation potential. In FIG. 10, relative values of the total energy are plotted as with respect to the distance from the center of VO to the hydrogen atom. Note that the center of VO corresponds to the position of the bonded oxygen atom before being released. The energy when a hydrogen atom entered VO (VOH), i.e., when the distance is 0 nm, is used as a reference of the energy. In FIG. 10, a square represents the case where VO existed in O(1), and a triangle represents the case where VO existed in O(3). Relative values of the energies of cells where one hydrogen atom entered VO are surrounded by a dashed line A, and relative values of the energies of cells where one hydrogen atom was arranged near various oxygen atoms are surrounded by a dashed line B. The calculation results reveal that VOH was more stable than when VO and the hydrogen atom existed separately because the plotted energy surrounded by the dashed line A is lower than that surrounded by the dashed line B in both O(1) and O(3).
The bonding energy (Eb), which is determined by formation energy (Eform), was calculated from Equation (4) in order to examine which of the two states where VO and a hydrogen atom separately existed and where a hydrogen atom entered VO (VOH) was more stable by a method different from the above calculation using GGA. Here, the HSE functional was used for an exchange-correlation potential.

Eb=Eform(VO)+Eform(bonded-H)−Eform(VOH)  (4)

In Equation (4), “Eform(VO)+Eform(bonded-H)” is the formation energy in the state where VO and a hydrogen atom separately exist, and Eform(VOH) is the formation energy in the state where a hydrogen atom enters VO (VOH).
In FIGS. 11A and 11B, the formation energy of VO existing in O(3), which is represented by a thin solid line, the formation energy of a hydrogen atom (bonded-H) bonded to an oxygen atom, which is represented by a dashed-dotted line, the formation energy of VOH formed in O(3), which is represented by a dashed line, and the bonding energy (Eb), which is represented by a thick solid line, were plotted as a function of the Fermi energy. FIGS. 11A and 11B show results of calculations performed under the oxygen-rich condition and the oxygen-poor condition, respectively.
According to Equation (4), when the bonding energy Eb is positive, the state where a hydrogen atom enters VO (VOH) is stable. In FIGS. 11A and 11B, when the Fermi level is greater than or equal to 1.85 eV, Eb is positive. In consideration of high carrier concentration, the Fermi level is close to the conduction band minimum and is greater than or equal to 1.85 eV. Thus, the state where a hydrogen atom enters VO (VOH) is more stable than the state where a hydrogen atom and VO separately exist.
As shown in FIG. 10, when VO and a hydrogen atom coexist, they are stable in the form of VOH. However, if a hydrogen atom in VOH is easily released from VO, the hydrogen atom diffuses throughout the In—Ga—Zn oxide without remaining in VO. Thus, the diffusion path in which a hydrogen atom in VOH is released from VO to be bonded to oxygen near VO and the associated activation barrier were investigated by the NEB method. Here, GGA was used for an exchange-correlation potential.
Here, the initial state was defined by a cell including VOH, and the final state was defined by a cell including VO and a hydrogen atom bonded to an oxygen atom near VO (i.e., the state where the hydrogen atom and VO separately exist in the calculation in FIG. 10). The activation barrier was calculated by subtracting the initial state or final state energy from the highest energy in the path. FIGS. 12A and 12B show paths through which hydrogen is released from VO and changes in energy. In O(1), paths A and B were assumed as diffusion paths through which hydrogen is released from VO (see FIG. 12A). Calculation of the activation barriers of the paths revealed that the activation barrier of the path A was 1.52 eV, which was lower than that of the path B.
In O(3), paths C and D were assumed as diffusion paths through which hydrogen is released from VO (see FIG. 12B). Calculation of the activation barriers of the paths revealed that the activation barrier of the path C was 1.61 eV, which was lower than that of the path D.
After being released from VO, hydrogen returns to VO or diffuses to another oxygen. Hydrogen returns to VO in directions opposite to A and C (A′ and C′ (see FIGS. 13A to 13C)). Paths E and F through which hydrogen diffuses to another oxygen were calculated by the NEB method by setting the final states of the paths A and C as the initial states. FIGS. 13A to 13C show the diffusion paths and changes in energy.
The activation barriers of the paths A′, C′, E, and F were 0.46 eV, 0.34 eV, 0.38 eV, and 0.03 eV, respectively.
Next, from the activation barriers obtained as described above, the reaction frequency Γ of hydrogen diffusion was calculated by Equation (5).

Γ=vexp(−Ea/kBT)  (5)

In Equation (5), v is a frequency factor, and Ea is an activation barrier.
Table below shows the frequency of release of hydrogen from VO, the frequency of hydrogen entering VO, and the frequency of diffusion of hydrogen to another oxygen at 350° C., assuming that v is 1.0×1013/sec.










TABLE 3





Oxygen site
Diffusion path of hydrogen
Ea [eV]
Γ (350° C.) [/sec]







Oxygen site
Release from VO (A)
1.52
5.52 × 100 


O(1)
Enter VO (A′)
0.46
1.82 × 109 



Move to
0.38
8.30 × 109 



another oxygen (E)


Oxygen site
Release from VO (C)
1.61
8.77 × 10−1


O(3)
Enter VO (C′)
0.34
1.89 × 1010



Move to
0.03
5.64 × 1012



another oxygen (F)









It is found that hydrogen enters VO at O(1) and O(3) with a high frequency but is unlikely to be released from VO at 350° C. This suggests that VOH exists stably.
The above indicates that a region including VO traps hydrogen but does not release the hydrogen. Thus, a region including VO can also be referred to as a region that blocks hydrogen or a region that causes gettering. When heat treatment or the like is performed on the regions 126b and 126c including VO, for example, gettering of hydrogen in the region 126a is caused in the regions 126b and 126c. In addition, because of the regions 126b and 126c, hydrogen is less likely to approach the region 126a. As a result, the carrier density of the region 126a can be lower than 1×109/cm3, and preferably lower than 1×107/cm3, in some cases.
<2-d: Transition Level of VOH>
As described in <2-c: Stable structure for coexistence of VO and H>, when VO and hydrogen coexist, they exist stably as VOH. In view of this, the transition level of VOH was calculated. The ∈(+/0) transition level of VOH was 3.03 eV when VOH existed at O(1) and was 2.97 eV when VOH existed at O(3). The ∈(+/0) transition level of VOH at each site is located near the conduction band minimum. This indicates that VOH is a shallow-level donor. Since VOH behaves as a donor, the In—Ga—Zn oxide including VOH has reduced resistivity and increased conductivity.
Then, the insulator 116 is formed (see FIGS. 5C and 5D). For the insulator 116, the above-described insulator can be used. The insulator 116 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. By the formation of the insulator 116, the low-resistance regions 107a and 107b are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c in the vicinity of the interface with the insulator 116.
When the insulator 116 is formed by a sputtering method, a metal target or an oxide target may be used. When a metal target is used for the deposition, the flow rate of oxygen is preferably intermediate between the flow rate of oxygen for forming a film of an element that is contained in the metal target and the flow rate of oxygen for forming an oxide film satisfying the stoichiometric composition including an element that is contained in the metal target. When formed with the flow rate of oxygen set in the above manner, the insulator 116 can be an oxide film including a suboxide, so that oxygen in the insulator 106a, the semiconductor 106b, and the insulator 106c is extracted and the low-resistance region 107a and the low-resistance region 107b can be easily formed. Here, the suboxide is an intermediate formed in the reaction process for forming the oxide. Thus, the suboxide is more deficient in oxygen than the oxide is. Specifically, the oxygen concentration of a suboxide is lower than that of an oxide by 1 at % or more, 2 at % or more, 5 at % or more, or 10 at % or more.
When the insulator 116 is formed by a sputtering method using an oxide target, the oxygen concentration of the deposition atmosphere is preferably low. When the oxygen concentration of the deposition atmosphere is low, oxygen vacancies are easily formed in the insulator 106a, the semiconductor 106b, and the insulator 106c, whereby the low-resistance region 107a and the low-resistance region 107b can be easily formed. For example, the oxygen concentration of the deposition atmosphere for the insulator 116 is lower than that of the deposition atmosphere for the semiconductor 106b, and the proportion of oxygen in the whole deposition atmosphere is less than 5 volume %, preferably less than 2 volume %, further preferably less than 1 volume %, still further preferably less than 0.5 volume %. Furthermore, when formed using an oxide target, the insulator 116 may be formed in an atmosphere not containing oxygen. In that case, for example, deposition can be performed using a rare gas (e.g., argon, krypton, or xenon) as a deposition gas.
When deposition is performed by a sputtering method, the substrate temperature may be set high. By setting the substrate temperature high, the addition of an element contained in the insulator 116 to the insulator 106a, the semiconductor 106b, and the insulator 106c can be promoted. Note that the substrate temperature is, for example, higher than or equal to 100° C. and lower than or equal to 450° C., preferably higher than or equal to 150° C. and lower than or equal to 400° C., further preferably higher than or equal to 170° C. and lower than or equal to 350° C.
When deposition is performed by a sputtering method or the like, an atmosphere containing nitrogen is preferably used because nitrogen is added to the insulator 106a, the semiconductor 106b, and the insulator 106c and thus the insulator 106a, the semiconductor 106b, and the insulator 106c become n-type.
It is also possible to directly deposit, as the insulator 116, the above-described oxide, oxynitride, nitride oxide, or nitride containing boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or the like by a reactive sputtering method or the like. Alternatively, the oxide or oxynitride containing any of the above elements may be obtained in such a manner that a film containing any of the above elements is formed and then heat treatment is performed. The heat treatment here may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 350° C. and lower than or equal to 450° C., for example.
The insulator 116 is preferably formed using an insulator containing oxygen and aluminum, e.g., aluminum oxide (AlOx). Aluminum oxide has an effect of blocking oxygen, hydrogen, water, and the like.
The above-described oxide that can be used for the insulator 106a or the insulator 106c can also be used for the insulator 116. The insulator 116 is preferably formed using an oxide insulator containing In, such as an In—Al oxide, an In—Ga oxide, or an In—Ga—Zn oxide. An oxide insulator containing In can be favorably used for the insulator 116 because the number of particles generated at the time of the deposition by a sputtering method is small.
An element that can be used as the dopant 120 may be added after the deposition of the insulator 116, whereby the resistances of the regions 126a and 126b and the low-resistance regions 107a and 107b are further reduced. By the above addition, an element contained in the insulator 116 can be pushed in (knocked on) the insulator 106a, the semiconductor 106b, and the insulator 106c. Examples of the method for the addition include an ion implantation method, an ion doping method, and a plasma immersion ion implantation method.
Next, heat treatment is preferably performed. By the heat treatment, oxygen can be supplied from the insulator 104 or the like to the insulator 106a, the semiconductor 106b, and the insulator 106c. The heat treatment is performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 350° C. and lower than or equal to 450° C. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed under a reduced pressure. For the heat treatment, lamp heating can be performed with the use of an RTA apparatus.
This heat treatment is preferably performed at a temperature lower than that of the heat treatment performed after formation of the semiconductor to be the semiconductor 106b. A temperature difference between the heat treatment and the heat treatment performed after formation of the semiconductor to be the semiconductor 106b is to be 20° C. or more and 150° C. or less, preferably 40° C. or more and 100° C. or less. Accordingly, superfluous release of excess oxygen (oxygen) from the insulator 104 and the like can be inhibited. Note that in the case where heating at the time of formation of the layers (e.g., heating at the time of formation of the insulator 116) doubles as the heat treatment after formation of the insulator 116, the heat treatment after formation of the insulator 116 is not necessarily performed.
At that time, since the insulator 106a, the semiconductor 106b, and the insulator 106c are surrounded by the insulator 101 and the insulator 116 having a function of blocking oxygen, outward diffusion of oxygen can be prevented. Accordingly, oxygen can be effectively supplied to the insulator 106a, the semiconductor 106b, and the insulator 106c, especially a region of the semiconductor 106b where a channel is formed. Oxygen is supplied to the insulator 106a, the semiconductor 106b, and the insulator 106c to reduce oxygen vacancies in this manner, whereby a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor with a low density of defect states can be obtained.
Then, the insulator 118 is formed. For the insulator 118, the above-described insulator can be used. The insulator 118 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Next, a resist or the like is formed over the insulator 118, and openings are formed in the insulator 118, the insulator 116, and the insulator 106c. Then, a conductor to be the conductors 108a and 108b is formed. For the conductor to be the conductors 108a and 108b, the above-described conductor can be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Next, the conductor to be the conductors 108a and 108b over the insulator 118 is partly removed by CMP treatment. As a result, the conductors 108a and 108b are formed only in the openings formed in the insulator 118, the insulator 116, and the insulator 106c. 
Then, a conductor to be the conductors 109a and 109b is deposited over the insulator 118, the conductor 108a, and the conductor 108b. For the conductor to be the conductors 109a and 109b, the above-described conductor can be used. The conductor can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Then, a resist or the like is formed over the conductor to be the conductors 109a and 109b, and the conductor is processed with the use of the resist or the like; thus, the conductor 109a and the conductor 109b are formed (see FIGS. 5E and 5F).
Through the above steps, the transistor 10 of one embodiment of the present invention can be manufactured.
As described above, in the method for manufacturing a semiconductor device described in this embodiment, the conductive film or the like is in contact with the top surface of the region 126a, which can prevent a portion functioning as the channel formation region of the transistor 10 from being damaged. Accordingly, a reduction in the reliability of the transistor 10 by the damage can be prevented.
When the above-described manufacturing method is employed, in a line where top-gate transistors are formed by a gate-first method using low-temperature polysilicon (LTPS), LTPS can be easily replaced with an oxide semiconductor. Here, the gate-first method is a transistor manufacturing process in which a gate is formed before formation of a source region and a drain region.
With such a structure, a transistor with stable electrical characteristics, a transistor having a high on-state current, a transistor with normally-off electrical characteristics, a transistor with a small subthreshold swing value, or a highly reliable transistor can be provided.
The structure and method described in this embodiment can be implemented by being combined as appropriate with any of the other structures and methods described in the other embodiments.
Embodiment 3
In this embodiment, structures of semiconductor devices of embodiments of the present invention will be described with reference to FIGS. 14A to 14D, FIGS. 15A to 15F, FIGS. 16A to 16C, and FIGS. 17A to 17F.
<Structure of Transistor>
Structures of transistors, which are examples of the semiconductor devices of embodiments of the present invention, will be described below.
A structure of a transistor 20 will be described with reference to FIGS. 14A to 14C. FIG. 14A is a top view of the transistor 20. FIG. 14B is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 14A. FIG. 14C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 14A. A region along dashed-dotted line A1-A2 shows a structure of the transistor 20 in the channel length direction, and a region along dashed-dotted line A3-A4 shows a structure of the transistor 20 in the channel width direction.
The transistor 20 includes the semiconductor 106b, the conductor 114, the insulator 106a, the insulator 106c, the insulator 112, an insulator 115, and the insulator 116. The semiconductor 106b is over the insulator 106a, the insulator 106c is over the semiconductor 106b, the insulator 112 is over the insulator 106c, the conductor 114 is over the insulator 112, the insulator 115 is in contact with the side surface of the conductor 114, and the insulator 116 is over the conductor 114 and the insulator 115. The insulator 115 and the insulator 116 each have a region in contact with the top surface of the insulator 106c. The semiconductor 106b has a region overlapping with the conductor 114 with the insulators 106c and 112 provided therebetween. It is preferable that, when seen from the top, the periphery of the insulator 106a be substantially aligned with the periphery of the semiconductor 106b and the periphery of the insulator 106c be positioned outward from the peripheries of the insulator 106a and the semiconductor 106b as in FIG. 14A. The transistor 20 is different from the transistor 10 described in the above embodiment in that the insulator 115 is provided.
As illustrated in FIGS. 14A to 14C, for example, the transistor 20 includes the insulator 101, the conductor 102, the insulator 103, and the insulator 104 formed over the substrate 100; the insulator 106a, the semiconductor 106b, and the insulator 106c formed over the insulator 104; the insulator 112, the conductor 114, and the insulator 115 formed over the insulator 106c; and the insulator 116, the insulator 118, the conductor 108a, the conductor 108b, the conductor 109a, and the conductor 109b formed over the conductor 114 and the insulator 115.
Here, the substrate 100, the insulator 101, the insulator 103, the insulator 104, the insulator 106a, the insulator 106c, the insulator 112, the insulator 115, the insulator 116, the insulator 118, the conductor 102, the conductor 108a, the conductor 108b, the conductor 109a, the conductor 109b, the conductor 114, and the semiconductor 106b can be similar to those described in the above embodiment. Thus, the above embodiment can be referred to for the details.
The insulator 115 can be formed using an insulator similar to that of the insulator 112.
The insulator 103 is formed over the insulator 101 formed over the substrate 100, and the conductor 102 is formed to be embedded in the insulator 103. The insulator 104 is formed over the insulator 103 and the conductor 102. Here, the insulator 101 is preferably formed using an insulator that has an effect of blocking oxygen, hydrogen, water, and the like. The insulator 104 is preferably formed using an insulator containing oxygen.
The insulator 106a is formed over the insulator 104. The semiconductor 106b is formed in contact with the top surface of the insulator 106a. The insulator 106c is formed in contact with the side surface of the insulator 106a and the top surface of the semiconductor 106b. Note that the semiconductor 106b is preferably formed to overlap with at least part of the conductor 102. The end portion of the side surface of the insulator 106a and the end portion of the side surface of the semiconductor 106b, especially those in the channel width direction, are substantially aligned with each other. Furthermore, the end portion of the side surface of the semiconductor 106b, especially that in the channel width direction, is in contact with the insulator 106c. In this manner, the semiconductor 106b of the transistor 20 described in this embodiment is surrounded by the insulator 106a and the insulator 106c. The insulator 106a, the semiconductor 106b, and the insulator 106c are preferably formed using an oxide semiconductor.
Although the periphery of the insulator 106c is positioned outward from the periphery of the insulator 106a in FIGS. 14B and 14C, the structure of the transistor described in this embodiment is not limited thereto. For example, the periphery of the insulator 106a may be positioned outward from the periphery of the insulator 106c, or the end portion of the side surface of the insulator 106a may be substantially aligned with the end portion of the side surface of the insulator 106c. 
FIG. 14D is an enlarged view of the conductor 114 and the vicinity thereof in the transistor 20 illustrated in FIG. 14B. As illustrated in FIG. 14D, the region 126a, the region 126b, the region 126c, a region 126d, and a region 126e are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c of the transistor 20 described in this embodiment. The regions 126b, 126c, 126d, and 126e have higher dopant concentration than the region 126a, and the resistances of the regions 126b, 126c, 126d, and 126e are reduced. In addition, the regions 126b and 126c have higher hydrogen concentration and lower resistance than the regions 126d and 126e. The dopant concentration in the region 126a is, for example, less than or equal to 5%, less than or equal to 2%, or less than or equal to 1%, of the maximum dopant concentration in the region 126b or the region 126c. Note that the term “dopant” may be changed into the term “donor,” “acceptor,” “impurity,” or “element.”
As illustrated in FIG. 14D, the region 126a is a region substantially overlapping with the conductor 114, and the regions 126b, 126c, 126d, and 126e are regions except the region 126a in the insulator 106a, the semiconductor 106b, and the insulator 106c. The top surface of the insulator 106c is in contact with the insulator 116 in the regions 126b and 126c, and is in contact with the insulator 115 and the insulator 112 in the regions 126d and 126e. Thus, as illustrated in FIG. 14D, the boundary between the region 126b and the region 126d overlaps with the boundary between the insulator 116 and an end portion of a side surface of the insulator 115. The same applies to the case of the boundary between the region 126c and the region 126e. It is preferable that the regions 126d and 126e partly overlap with a region (channel formation region) where the semiconductor 106b overlaps with the conductor 114. For example, end portions of side surfaces of the regions 126d and 126e in the channel length direction is preferably inward from the end portion of the side surface of the conductor 114 by the distance d. In that case, the distance d preferably satisfies 0.25t<d<t, where t represents the thickness of the insulator 112.
As described above, the regions 126d and 126e are partly formed in a region where the insulator 106a, the semiconductor 106b, and the insulator 106c overlap with the conductor 114. Accordingly, the channel formation region of the transistor 20 is in contact with the regions 126d and 126e having low resistance and thus, offset regions with high resistance are not formed between the region 126a and the regions 126d and 126e. As a result, the on-state current of the transistor 20 can be increased. Furthermore, when the end portions of the side surfaces of the regions 126d and 126e in the channel length direction are positioned such that 0.25t<d<t is satisfied, the regions 126d and 126e can be prevented from being spread inward too much in the channel formation region and thus the transistor 20 can be prevented from being constantly in an on state.
As described in detail later, the regions 126b, 126c, 126d, and 126e are formed by ion doping treatment such as an ion implantation method. For this reason, as the depth from the top surface of the insulator 106c increases, the end portions of the side surfaces of the regions 126d and 126e in the channel length direction might shift toward the end portions of the side surfaces of the insulator 106a, the semiconductor 106b, and the insulator 106c in the channel length direction as illustrated in FIG. 14D. In that case, the distance d is the distance between the end portion of the side surface of the conductor 114 in the channel length direction and each of the end portions of the side surfaces of the regions 126d and 126e in the channel length direction, which are the closest to the conductor 114 and are positioned inward the end portion of the side surface of the conductor 114.
In some cases, the regions 126d and 126e in the insulator 106a are not formed to overlap with the conductor 114, for example. In that case, the regions 126d and 126e in the semiconductor 106b are preferably formed to partly overlap with the conductor 114.
The low-resistance region 107a and the low-resistance region 107b are preferably formed in the insulator 106a, the semiconductor 106b, and the insulator 106c in the vicinity of the interface with the insulator 116 (indicated with a dotted line in FIG. 14B). The low-resistance region 107a and the low-resistance region 107b contain at least one of the elements contained in the insulator 116. It is preferable that the low-resistance region 107a and the low-resistance region 107b be partly and substantially in contact with a region of the semiconductor 106b overlapping with the conductor 114 (channel formation region) or partly overlap with the region.
Since a large region of the insulator 106c is in contact with the insulator 116, the low-resistance region 107a and the low-resistance region 107b are easily formed in the insulator 106c. The concentration of the element contained in the insulator 116 is higher in the low-resistance region 107a and the low-resistance region 107b included in the insulator 106c than in a region of the insulator 106c other than the low-resistance region 107a and the low-resistance region 107b (e.g., a region of the insulator 106c overlapping with the conductor 114).
The low-resistance region 107a is formed in the region 126b and the low-resistance region 107b is formed in the region 126c. In the ideal structure, the low-resistance regions 107a and 107b, regions in the regions 126b, 126c, 126d, and 126e except the low-resistance regions 107a and 107b, and the region 126a have high concentration of an additional element in this order. Note that the additional element includes the dopant used for forming the regions 126b and 126c and the element added to the low-resistance regions 107a and 107b from the insulator 116.
The formation of the regions 126b, 126c, 126d, and 126e and the low-resistance regions 107a and 107b leads to a reduction in contact resistance between the conductor 108a or 108b and the insulator 106a, the semiconductor 106b, or the insulator 106c, whereby the transistor 20 can have high on-state current.
Although the low-resistance regions 107a and 107b are formed in the transistor 20 illustrated in FIGS. 14A to 14D, the structure of the semiconductor device described in this embodiment is not necessarily limited thereto. For example, in the case where the regions 126b and 126c have sufficiently low resistance, the low-resistance regions 107a and 107b do not need to be formed.
The insulator 112 is formed over the insulator 106c, and the conductor 114 is formed over the insulator 112. The insulator 115 is formed to be in contact with the side surface of the conductor 114. At least part of each of the insulator 112 and the conductor 114 overlaps with the conductor 102 and the semiconductor 106b. It is preferable that an end portion of a side surface of the conductor 114 in the channel length direction be substantially aligned with the end portion of the side surface of the insulator 112 in the channel length direction. Here, the insulator 112 serves as a gate insulating film of the transistor 20, the conductor 114 serves as a gate electrode of the transistor 20, and the insulator 115 serves as a sidewall insulating film of the transistor 20.
It is preferable that an end portion of a side surface of the conductor 114 in the channel length direction be substantially aligned with an end portion of a side surface of the insulator 112 in the channel length direction. With such a structure, the regions 126d and 126e are substantially in contact with or partly overlap with the region of the semiconductor 106b that overlaps with the conductor 114 (channel formation region), whereby on-state current can be increased.
The insulator 116 is formed over the conductor 114, the insulator 115, the insulator 106c, and the insulator 104. The insulator 116 is preferably in contact with a region of the insulator 106c that does not overlap with the insulator 112 or the insulator 115. The insulator 116 may be in contact with at least part of the insulator 104. The insulator 118 is formed over the insulator 116. Here, the insulator 116 serves as a protective insulating film of the transistor 20 and the insulator 118 serves as an interlayer insulating film of the transistor 20. The insulator 116 is preferably formed using an insulator that has an effect of blocking oxygen.
The thickness of the insulator 106a is preferably larger than the total thickness of the insulator 106c and the insulator 112. In other words, it is preferable to satisfy h1=h2 or h1>h2, where h1 is the height from the top surface of the substrate 100 to the bottom surface of the semiconductor 106b and h2 is the height from the top surface of the substrate 100 to the bottom surface of the conductor 114 in a region overlapping with the insulator 106c. For example, h1 may be greater than h2 by 5% or more, preferably 10% or more, further preferably 20% or more, and still further preferably 50% or more of an apparent channel width W of the transistor 20. With such a structure, almost the entire side surface of the semiconductor 106b in the channel width direction can be made to face the conductor 114 with the insulators 106c and 112 provided therebetween.
With the above structure, as illustrated in FIG. 14C, the semiconductor 106b can be electrically surrounded by an electric field of the conductor 114 (a structure in which a semiconductor is electrically surrounded by an electric field of a conductor is referred to as a surrounded channel (s-channel) structure). Therefore, a channel is formed in the entire semiconductor 106b in some cases. In the s-channel structure, a large amount of current can flow between a source and a drain of a transistor, so that a high on-state current can be obtained.
In the case where the transistor has the s-channel structure, a channel is formed also in the side surface of the semiconductor 106b. Thus, as the thickness of the semiconductor 106b becomes larger, the channel region becomes larger. In other words, the thicker the semiconductor 106b is, the higher the on-state current of the transistor is. In addition, as the thickness of the semiconductor 106b becomes larger, the proportion of the region with a high carrier controllability increases, leading to a smaller subthreshold swing value. The semiconductor 106b has, for example, a region with a thickness greater than or equal to 10 nm, preferably greater than or equal to 20 nm, further preferably greater than or equal to 30 nm, and still further preferably greater than or equal to 50 nm. Since the productivity of the semiconductor device might be decreased, the semiconductor 106b has, for example, a region with a thickness less than or equal to 300 nm, preferably less than or equal to 200 nm, and further preferably less than or equal to 150 nm. In some cases, when the channel formation region is reduced in size, electrical characteristics of the transistor with a smaller thickness of the semiconductor 106b may be improved. Thus, the semiconductor 106b may have a thickness less than 10 nm.
The s-channel structure is suitable for a miniaturized transistor because a high on-state current can be obtained. A semiconductor device including the miniaturized transistor can have a high integration degree and high density. For example, the transistor includes a region having a channel length of preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, and still further preferably less than or equal to 20 nm and a region having a channel width of preferably less than or equal to 40 nm, further preferably less than or equal to 30 nm, and still further preferably less than or equal to 20 nm.
The conductor 108a and the conductor 108b are formed in openings provided in the insulators 118, 116, and 106c so as to be in contact with the low-resistance region 107a and the low-resistance region 107b. Over the insulator 118, the conductor 109a is formed in contact with the top surface of the conductor 108a and the conductor 109b is formed in contact with the top surface of the conductor 108b. The conductor 108a and the conductor 108b are spaced from each other, and are preferably opposed to each other with the conductor 114 positioned therebetween as illustrated in FIG. 14B. The conductor 108a functions as one of a source electrode and a drain electrode of the transistor 20 and the conductor 108b functions as the other of the source electrode and the drain electrode of the transistor 20. The conductor 109a functions as a wiring connected to one of the source electrode and the drain electrode of the transistor 20 and the conductor 109b functions as a wiring connected to the other of the source electrode and the drain electrode of the transistor 20. Although the conductor 108a and the conductor 108b are in contact with the semiconductor 106b in FIG. 14B, this embodiment is not limited to this structure. As long as the contact resistance with the low-resistance region 107a and the low-resistance region 107b is sufficiently low, the conductor 108a and the conductor 108b may be in contact with the insulator 106c. 
The insulator 106a, the semiconductor 106b, and the insulator 106c described in this embodiment are oxides that have a low impurity concentration and a low density of defect states (few oxygen vacancies) and thus, the insulator 106a, the semiconductor 106b, and the insulator 106c have a low carrier density. As a result, contact resistance with the conductors 108a and 108b serving as the source and drain electrodes easily becomes high. In view of this, in the transistor 20 described in this embodiment, the conductor 108a or the conductor 108b is connected to the insulator 106a, the semiconductor 106b, or the insulator 106c through the low-resistance region 107a in the regions 126b and 126d or the low-resistance region 107b in the regions 126c and 126e to reduce contact resistance.
As described above, the regions 126a, 126b, 126c, 126d, and 126e are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c. The regions 126b, 126c, 126d, and 126e have higher dopant concentration than the region 126a, and the resistances of the regions 126b, 126c, 126d, and 126e are reduced. In addition, the regions 126b and 126c have higher hydrogen concentration and lower resistance than the regions 126d and 126e. The region 126a almost corresponds to a region overlapping with the conductor 114, and the regions 126b, 126c, 126d, and 126e are regions except the region 126a in the insulator 106a, the semiconductor 106b, and the insulator 106c. It is preferable that the regions 126b and 126c partly overlap with a region (channel formation region) where the semiconductor 106b overlaps with the conductor 114.
The low-resistance regions 107a and 107b are preferably formed in the insulator 106a, the semiconductor 106b, and the insulator 106c in the vicinity of the interface with the insulator 116. In the regions 126b, 126c, 126d, and 126e and the low-resistance regions 107a and 107b, a dopant and an element contained in the insulator 116 are added to cause formation of a defect. Such a defect is formed in such a manner that, for example, oxygen is extracted owing to the added dopant or the element added from the insulator 116 and an oxygen vacancy is formed, or the dopant or the element added from the insulator 116 serves as a carrier generation source. Such a defect forms a donor level and carrier density is increased; thus, the regions to which the dopant or the element contained in the insulator 116 is added serve as the regions 126b, 126c, 126d, and 126e and the low-resistance regions 107a and 107b. When hydrogen added as a dopant enters the sites of the oxygen vacancies formed in those regions, a shallow donor level is formed; thus, the carrier density can be further increased.
The regions 126b, 126c, 126d, and 126e, especially the low-resistance regions 107a and 107b, include many oxygen vacancies and thus have lower oxygen concentration than the region 126a when measured by SIMS. Furthermore, the regions 126b, 126c, 126d, and 126e, especially the low-resistance regions 107a and 107b, include many defects and thus have lower crystallinity than the region 126a. 
Although details are described later, the regions 126b, 126c, 126d, and 126e are formed by adding a dopant. Thus, the concentration of the dopant measured by SIMS is higher in the regions 126b, 126c, 126d, and 126e than in the region 126a. 
Examples of the dopant added to the regions 126b and 126c include hydrogen, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. Among these elements, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, and boron are preferable because these elements can be added relatively easily by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.
The formation of the regions 126b and 126c leads to a reduction in contact resistance between the conductor 108a or 108b and the insulator 106a, the semiconductor 106b, or the insulator 106c, whereby the transistor 20 can have high on-state current. Furthermore, the channel formation region of the transistor 20 is in contact with the regions 126d and 126e having low resistance and thus, offset regions with high resistance are not formed between the region 126a and the regions 126d and 126e. As a result, the on-state current of the transistor 20 can be further increased.
As described in detail later, for the transistors described in this embodiment, dopant addition is performed at least twice to form the regions 126b, 126c, 126d, and 126e. Oxygen vacancies are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c by the first dopant addition, and hydrogen, which is added by the second dopant addition, enters the sites of the oxygen vacancies; as a result, a shallow donor level is formed. The second dopant addition is performed after the formation of the insulator 115. Thus, hydrogen, which is added by the second dopant addition, is directly added to the regions 126b and 126c not overlapping with the insulator 115. Meanwhile, hydrogen, which is added by the second dopant addition, is not directly added to the regions 126d and 126e overlapping with the insulator 115 or the insulator 112; hydrogen is diffused and supplied to the regions 126d and 126e after the hydrogen addition. Accordingly, the regions 126b and 126c have higher hydrogen concentration than the regions 126d and 126e when measured by SIMS.
In this manner, dopant addition is performed before and after the formation of the insulator 115 functioning as a sidewall insulating film, in which case the amount of hydrogen supplied to the regions 126d and 126e can be smaller than that supplied to the regions 126b and 126c. Hydrogen which is supplied mainly to the regions 126b and 126c by the second dopant addition is diffused mainly into the regions 126d and 126e from the regions 126b and 126c, and enters the sites of the oxygen vacancies, which are formed in the regions 126d and 126e by the first dopant addition. Thus, hydrogen is hardly diffused into the region 126a that functions as the channel formation region of the transistor. That is, with the region 126d between the region 126a and the region 126b and the region 126e between the region 126a and the region 126c, hydrogen diffusion into the region 126a and a reduction in the resistance of the region 126a, which make the transistor constantly on, can be prevented.
Because the element contained in the insulator 116 is added to the low-resistance region 107a and the low-resistance region 107b, the concentration of the element measured by SIMS in these regions is higher than that in the region of the semiconductor 106b other than the low-resistance region 107a and the low-resistance region 107b (e.g., a region of the semiconductor 106b that overlaps with the conductor 114).
The element added to the low-resistance region 107a and the low-resistance region 107b is preferably boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, or tungsten, for example. These elements relatively easily form an oxide that can serve as a semiconductor or an insulator and thus, these elements are favorable as the element added to the insulator 106a, the semiconductor 106b, or the insulator 106c. For example, the low-resistance region 107a and the low-resistance region 107b preferably contain the above element at higher than or equal to 1×1014/cm2 and lower than or equal to 2×1016/cm2. The concentration of the above element is higher in the low-resistance region 107a and the low-resistance region 107b included in the insulator 106c than in a region of the insulator 106c other than the low-resistance region 107a and the low-resistance region 107b (e.g., a region of the insulator 106c overlapping with the conductor 114).
Because the addition of nitrogen to the low-resistance region 107a and the low-resistance region 107b makes these regions become n-type, the concentration of nitrogen measured by SIMS in these regions is higher than that in the region of the semiconductor 106b other than the low-resistance region 107a and the low-resistance region 107b (e.g., a region of the semiconductor 106b that overlaps with the conductor 114).
The formation of the low-resistance region 107a and the low-resistance region 107b leads to a reduction in contact resistance between the conductor 108a or 108b and the insulator 106a, the semiconductor 106b, or the insulator 106c, whereby the transistor 20 can have high on-state current.
As illustrated in FIG. 14B, it is preferable that the end portion of the side surface of the conductor 114 in the channel length direction be substantially aligned with the end portion of the side surface of the insulator 112 in the channel length direction. With such a structure, the regions 126d and 126e are substantially in contact with the region of the semiconductor 106b that overlaps with the conductor 114 (channel formation region), whereby on-state current can be increased.
In the transistor 20, the semiconductor 106b is surrounded by the insulator 106a and the insulator 106c. Accordingly, the end portion of the side surface of the semiconductor 106b, especially the vicinity of the end portion of the side surface thereof in the channel width direction, is in contact with the insulator 106a and the insulator 106c. As a result, in the vicinity of the end portion of the side surface of the semiconductor 106b, continuous junction is formed between the insulator 106a and the semiconductor 106b or between the insulator 106c and the semiconductor 106b and the density of defect states is reduced. Thus, even when on-state current easily follows owing to the regions 126b and 126c and the low-resistance regions 107a and 107b, the end portion of the side surface of the semiconductor 106b in the channel width direction does not serve as a parasitic channel, which enables stable electrical characteristics.
Note that the three-layer structure including the insulator 106a, the semiconductor 106b, and the insulator 106c is an example. For example, a two-layer structure not including the insulator 106a or the insulator 106c may be employed. Alternatively, a single-layer structure not including the insulator 106a and the insulator 106c may be employed. Further alternatively, it is possible to employ an n-layer structure (n is an integer of four or more) that includes any of the insulator, semiconductor, and conductor given as examples of the insulator 106a, the semiconductor 106b, and the insulator 106c. 
With such a structure, a transistor with stable electrical characteristics, a transistor having a high on-state current, a transistor with normally-off electrical characteristics, a transistor with a small subthreshold swing value, or a highly reliable transistor can be provided.
Modification Example 2 of Transistor
Modification examples of the transistor 20 will be described below with reference to FIGS. 15A to 15F and FIGS. 16A to 16C. FIGS. 15A to 15F and FIGS. 16A to 16C are cross-sectional views of the transistors in the channel length direction and those in the channel width direction like FIGS. 14B and 14C. Note that the components in the following modification examples of the transistor 20 can be combined with each other as appropriate.
A transistor 21 illustrated in FIGS. 15A and 15B is different from the transistor 20 in that the end portion of the side surface of the semiconductor 106b is positioned inward from the end portion of the side surface of the insulator 106a. In other words, in the transistor 21, the peripheries of the insulators 106a and 106c are positioned outward from the periphery of the semiconductor 106b, and the semiconductor 106b is surrounded by the insulators 106a and 106c. Furthermore, the end portion of the side surface of the insulator 106a and the end portion of the side surface of the insulator 106c, especially those in the channel width direction, are preferably substantially aligned with each other.
Patterning is performed such that the end portion of the side surface of the semiconductor 106b is located inward from the end portion of the side surface of the insulator 106a as in the transistor 21 illustrated in FIGS. 15A and 15B, whereby the number of times of etching the insulator 104 at the time of etching the insulator 106a or the semiconductor 106b can be reduced. A portion of the surface of the insulator 104 that is to be etched can be away from the conductor 102, leading to an increase in withstand voltage of the transistor 21.
In the transistor 21 illustrated in FIGS. 15A and 15B or the like, the end portion of the side surface of the conductor 114 in the channel length direction is substantially aligned with the end portion of the side surface of the insulator 112 in the channel length direction; however, the structure of the semiconductor device described in this embodiment is not limited to the above structure. For example, as in a transistor 22 illustrated in FIGS. 15C and 15D, the width of the conductor 114 in the channel length direction may be smaller than the width of the insulator 112 in the channel length direction.
Although the conductor 102 and the insulator 103 are formed in the transistor 21 illustrated in FIGS. 15A and 15B or the like, the structure of the semiconductor device described in this embodiment is not limited thereto. For example, as in a transistor 23 illustrated in FIGS. 15E and 15F, a structure not including the conductor 102 and the insulator 103 may be employed.
A transistor 24 illustrated in FIGS. 16A and 16B is different from the transistor 21 in that part of the insulator 104 has a larger thickness. The end portion of the side surface of the thick region of the insulator 104 in the channel width direction is preferably located inward from the end portion of the side surface of the semiconductor 106b in the channel width direction. In other words, the insulator 104 has a projection and when seen from above, the periphery of the projection is located inward from the periphery of the semiconductor 106b. It is further preferable that the end portion of the side surface of the thick region of the insulator 104 in the channel width direction be located inward from the end portion of the side surface of the semiconductor 106b in the channel width direction by a distance approximately equal to the thickness of the insulator 106a. Here, a difference between the thickness of the thick region of the insulator 104 and the thin region thereof is preferably larger than the sum of the thicknesses of the insulator 106c and the insulator 112. With such a structure, substantially the entire side surface of the semiconductor 106b in the channel width direction can face the conductor 114 with the insulator 106c and the insulator 112 positioned therebetween.
With the above structure, the transistor 24 can have an s-channel structure similarly to the above transistor 20. Thus, in the transistor 24, a large amount of current can flow between a source and a drain, so that a high on-state current can be obtained.
Although the thick region of the insulator 104 extends in the channel length direction in the transistor 24 illustrated in FIG. 16A, the structure described in this embodiment is not limited to the above structure. For example, as illustrated in FIG. 16C, the end portion of the side surface of the thick region of the insulator 104 in the channel length direction may be located inward from the end portion of the side surface of the semiconductor 106b in the channel length direction.
Although the insulator 115 is in contact with the top surface of the insulator 106c and the side surfaces of the insulator 112 and the conductor 114 in the transistor 20 illustrated in FIGS. 14A to 14C or the like, the structure of the semiconductor device described in this embodiment is not limited thereto. For example, as in a transistor 25 illustrated in FIGS. 17A and 17B, the insulator 115 may be in contact with the top surface of the insulator 112 and the side surface of the conductor 114.
Furthermore, although the end portion of the side surface of the insulator 112 is substantially aligned with the end portion of the side surface of the conductor 114 in the transistor 20 illustrated in FIGS. 14A to 14C or the like, the structure of the semiconductor device described in this embodiment is not limited thereto. For example, as in a transistor 26 illustrated in FIGS. 17C and 17D, a structure in which the insulator 112 is not subjected to patterning may be employed. In that case, the insulator 115 and the insulator 116 are in contact with the top surface of the insulator 112, as illustrated in FIGS. 17C and 17D. In such a structure, the insulator 116 is not in direct contact with the insulator 106a, the semiconductor 106b, and the insulator 106c; thus, the low-resistance regions 107a and 107b are not formed in some cases.
Moreover, although the thickness of the insulator 106c is shown substantially uniform in the transistor 20 illustrated in FIGS. 14A to 14C or the like, the structure of the semiconductor device described in this embodiment is not limited thereto. For example, as in a transistor 27 illustrated in FIGS. 17E and 17F, the thickness of the insulator 106c might be larger in a region in contact with the insulator 112 than in any other regions.
The structure and method described in this embodiment can be implemented by being combined as appropriate with any of the other structures and methods described in the other embodiments.
Embodiment 4
In this embodiment, a method for manufacturing the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 18A to 18F and FIGS. 19A to 19F.
<Method 2 for Manufacturing Transistor>
A method for manufacturing the transistor 20 illustrated in FIGS. 14A to 14D will be described below.
First, the substrate 100 is prepared. Any of the above-mentioned substrates can be used for the substrate 100.
Next, the insulator 101 is formed. For the formation of the insulator 101, the description of the above embodiment can be referred to.
Then, the insulator 103 is formed. For the formation of the insulator 103, the description of the above embodiment can be referred to.
Subsequently, a resist or the like is formed over the insulator 103 and an opening is formed in the insulator 103. For the formation of the resist, the description of the above embodiment can be referred to.
Next, a conductor to be the conductor 102 is formed. For the formation of the conductor to be the conductor 102, the description of the above embodiment can be referred to.
Next, the conductor to be the conductor 102 over the insulator 103 is removed by CMP treatment. As a result, the conductor 102 remains only in the opening formed in the insulator 103.
Then, the insulator 104 is formed (see FIGS. 18A and 18B). For the formation of the insulator 104, the description of the above embodiment can be referred to.
After that, an insulator to be the insulator 106a in a later step is formed. For the formation of the insulator, the description of the above embodiment can be referred to.
Subsequently, a semiconductor to be the semiconductor 106b in a later step is formed. For the formation of the semiconductor, the description of the above embodiment can be referred to.
Next, heat treatment is preferably performed. The heat treatment can reduce the hydrogen concentration of the insulator 106a and the semiconductor 106b formed in later steps in some cases. The heat treatment can reduce oxygen vacancies in the insulator 106a and the semiconductor 106b formed in later steps in some cases. For the heat treatment, the description of the above embodiment can be referred to.
Furthermore, high-density plasma treatment or the like may be performed. High-density plasma may be generated using microwaves. For the high-density plasma treatment, the description of the above embodiment can be referred to.
Next, a resist or the like is formed over the semiconductor to be the semiconductor 106b and processing is performed using the resist or the like, whereby the insulator 106a and the semiconductor 106b are formed. As illustrated in FIGS. 18C and 18D, an exposed surface of the insulator 104 is removed at the time of formation of the semiconductor 106b in some cases.
Then, an insulator to be the insulator 106c in a later step is formed. For the formation of the insulator, the description of the above embodiment can be referred to.
Next, a resist or the like is formed over the insulator to be the insulator 106c and processing is performed using the resist or the like, whereby the insulator 106c is formed (see FIGS. 18C and 18D). As illustrated in FIGS. 18C and 18D, an exposed surface of the insulator 104 is removed at the time of formation of the insulator 106c in some cases. For the patterning for forming the insulator 106a and the insulator 106c, the description of the above embodiment can be referred to.
After that, an insulator to be the insulator 112 in a later step is formed. For the formation of the insulator, the description of the above embodiment can be referred to.
Next, a conductor to be the conductor 114 is formed. For the formation of the conductor, the description of the above embodiment can be referred to.
Next, a resist or the like is formed over the conductor to be the conductor 114 and processing is performed with the resist or the like, whereby the insulator 112 and the conductor 114 are formed. Here, after the insulator 112 and the conductor 114 are formed such that the end portion of the side surface of the conductor 114 in the channel length direction is substantially aligned with the end portion of the side surface of the insulator 112 in the channel length direction, only the conductor 114 may be selectively etched by wet etching or the like using the same mask. When such etching is performed, as in the transistor 22 illustrated in FIGS. 15C and 15D, the width of the conductor 114 in the channel length direction can be smaller than the width of the insulator 112 in the channel length direction.
In the case where the insulator that can be used for the insulator 112 and the insulator that can be used for the insulator 106c are selected such that the etching selectivity ratio between the insulator that can be used for the insulator 112 and the insulator that can be used for the insulator 106c becomes low, the insulator 106c might be partly etched at the time of etching for the insulator 112. As a result of the etching, the thickness of the insulator 106c becomes larger in a region in contact with the insulator 112 than in any other regions, as in the transistor 27 illustrated in FIGS. 17E and 17F.
Note that the etching selectivity ratio is, in the case of etching a layer A and a layer B, for example, the ratio between etching rates of the layer A and the layer B. Thus, a high etching selectivity ratio indicates a sufficient difference between etching rates, and a low etching selectivity ratio indicates an insufficient difference between etching rates.
In the case where the conductor that can be used for the conductor 114 and the insulator that can be used for the insulator 112 are selected such that the etching selectivity ratio between the conductor that can be used for the conductor 114 and the insulator that can be used for the insulator 112 becomes high, only patterning for the conductor 114 can be performed without performing patterning for the insulator 112. When the insulator 112 is not etched in such a manner, the insulator 115 and the insulator 116 are in contact with the top surface of the insulator 112, as in the transistor 26 illustrated in FIGS. 17C and 17D. Note that a region not overlapping with the conductor 114 or the insulator 115 in the insulator 112 may be removed after the formation of the insulator 115, which is described later. In that case, the insulator 115 is in contact with the top surface of the insulator 112 and the insulator 116 is in contact with the insulator 106c in a region not overlapping with the conductor 114 or the insulator 115, as in the transistor 25 illustrated in FIGS. 17A and 17B.
In particular, with the use of a high-k material (high dielectric constant material) for the insulator 112, the etching selectivity ratio with respect to the conductor 114 can be high. Examples of the high-k material include hafnium oxide, yttrium oxide, hafnium silicate (HfSixOy (x>0, y>0)), hafnium silicate to which nitrogen is added (HfSiOxNy (x>0, y>0)), hafnium aluminate (HfAlxOy (x>0, y>0)), hafnium aluminate to which nitrogen is added (HfAlxOyNz (x>0, y>0, z>0)), and lanthanum oxide. The use of such a high-k material enables a reduction in gate leakage current. A stack including any of the above high-k materials and the insulator (e.g., silicon oxide or silicon oxynitride) which has been given as a material that can be used for the insulator 112 may be used for the insulator 112.
Since the etching selectivity ratio of a high-k material with respect to the insulator 106c can be easily made high, the use of a high-k material for the insulator 112 can prevent a surface of the insulator 106c in a region not overlapping with the insulator 112 from being etched unlike in the transistor 27; accordingly, the thickness of the insulator 106c can be substantially uniform.
Next, a dopant 119 is added to the insulator 106a, the semiconductor 106b, and the insulator 106c using the conductor 114 and the insulator 112 as a mask (see FIGS. 18E and 18F). As a result, the region 126a, a region 136b, and a region 136c are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c. Thus, the concentration of the dopant 119 measured by SIMS is higher in the region 136b and the region 136c than in the region 126a. The addition of the dopant 119 can form oxygen vacancies in the regions 136b and 136c. When hydrogen described later enters the sites of the oxygen vacancies, a shallow donor level is formed.
Note that the region 136b almost corresponds to the combined region of the region 126b and the region 126d, and the region 136c almost corresponds to the combined region of the region 126c and the region 126e. For this reason, similarly to the regions 126d and 126e, it is preferable that the regions 136b and 136c partly overlap with a region (channel formation region) of the semiconductor 106b which overlaps with the conductor 114.
For the addition of the dopant 119, an ion implantation method by which an ionized source gas is subjected to mass separation and then added, an ion doping method by which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used. In the case of performing mass separation, ion species to be added and its concentration can be controlled properly. In contrast, in the case of not performing mass separation, ions at a high concentration can be added in a short time. Alternatively, an ion doping method in which atomic or molecular clusters are generated and ionized may be employed. Note that the term “dopant” may be changed into the term “ion,” “donor,” “acceptor,” “impurity,” or “element.”
The addition of the dopant 119 may be controlled by setting the addition conditions such as the acceleration voltage and the dosage as appropriate. The dosage of the dopant 119 is, for example, greater than or equal to 1×1012 ions/cm2 and less than or equal to 1×1016 ions/cm2, preferably greater than or equal to 1×1013 ions/cm2 and less than or equal to 1×1015 ions/cm2. The acceleration voltage at the time of the addition of the dopant 119 is higher than or equal to 2 kV and lower than or equal to 50 kV, preferably higher than or equal to 5 kV and lower than or equal to 30 kV.
The dopant 119 may be added while the substrate is heated. The substrate temperature is, for example, higher than or equal to 200° C. and lower than or equal to 700° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., and further preferably higher than or equal to 350° C. and lower than or equal to 450° C.
Examples of the dopant 119 include helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, boron, magnesium, aluminum, silicon, titanium, vanadium, chromium, nickel, zinc, gallium, germanium, yttrium, zirconium, niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum, and tungsten. Among these elements, helium, neon, argon, krypton, xenon, nitrogen, fluorine, phosphorus, chlorine, arsenic, and boron are preferable because these elements can be added relatively easily by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.
After the addition of the dopant 119, heat treatment may be performed. The heat treatment may be performed at higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 350° C. and lower than or equal to 450° C. in a nitrogen atmosphere, or under reduced pressure or air (ultra dry air), for example.
Note that in the case where only patterning for the conductor 114 is performed without performing patterning for the insulator 112 as described above, the dopant 119 is added through the insulator 112 as illustrated in FIGS. 20A and 20B. Adding the dopant 119 in this manner can protect the insulator 106c from damage caused by the collision of the dopant 119.
Then, an insulator to be the insulator 115 in a later step is formed. For the insulator, the above-described insulator can be used. The insulator 115 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
Next, the insulator to be the insulator 115 is subjected to anisotropic etching, so that the insulator 115 is formed to be in contact with a side surface of the conductor 114 in a self-aligned manner. Here, the etching of the insulator to be the insulator 115 can be performed by, for example, a reactive ion etching (RIE) method.
After that, the dopant 120 is added to the insulator 106a, the semiconductor 106b, and the insulator 106c using the conductor 114, the insulator 112, and the insulator 115 as a mask (see FIGS. 19A and 19B). Note that the following description is made on the assumption that hydrogen is used as the dopant 120. The resistances of the regions 136b and 136c are reduced, and the regions 126b, 126c, 126d, and 126e are formed.
By the addition of the dopant 120, hydrogen enters the sites of the oxygen vacancies formed in the regions 136b and 136c and a shallow donor level is formed. At this time, regions to which the dopant 120 is directly added in the regions 136b and 136c become the regions 126b and 126c, and regions below the insulator 115 or the insulator 112 where the dopant 120 is not directly added and hydrogen enters the sites of the oxygen vacancies by the diffusion of the dopant 120 after the addition become the regions 126d and 126e. For this reason, the regions 126b and 126c have higher hydrogen concentration than the regions 126d and 126e when measured by SIMS.
The boundary between the region 126b and the region 126d overlaps with the boundary between the insulator 116 and the end portion of the side surface of the insulator 115. The same applies to the case of the boundary between the region 126c and the region 126e. Similarly to the case of the regions 136b and 136c, it is preferable that the regions 126d and 126e partly overlap with a region (channel formation region) where the semiconductor 106b overlaps with the conductor 114. For example, the end portions of the side surfaces of the regions 126d and 126e in the channel length direction is preferably inward from the end portion of the side surface of the conductor 114 by the distance d. In that case, the distance d preferably satisfies 0.25t<d<t, where t represents the thickness of the insulator 112.
As described above, the regions 126d and 126e are partly formed in a region where the insulator 106a, the semiconductor 106b, and the insulator 106c overlap with the conductor 114. Accordingly, the channel formation region of the transistor 20 is in contact with the regions 126d and 126e having low resistance and thus, offset regions with high resistance are not formed between the region 126a and the regions 126d and 126e. As a result, the on-state current of the transistor 20 can be increased. Furthermore, when the end portions of the side surfaces of the regions 126d and 126e in the channel length direction are positioned such that 0.25t<d<t is satisfied, the regions 126d and 126e can be prevented from being spread inward too much in the channel formation region and thus the transistor 20 can be prevented from being constantly in an on state.
Examples of a method for adding the dopant 120 include an ion implantation method, an ion doping method, and a plasma immersion ion implantation method. Note that the term “dopant” may be changed into the term “ion,” “donor,” “acceptor,” “impurity,” or “element.”
The addition of the dopant 120 may be controlled by setting the addition conditions such as the acceleration voltage and the dosage as appropriate. The dosage of the dopant 120 is, for example, greater than or equal to 1×1012 ions/cm2 and less than or equal to 1×1016 ions/cm2, preferably greater than or equal to 1×1013 ions/cm2 and less than or equal to 1×1015 ions/cm2. The acceleration voltage at the time of the addition of the dopant 120 is higher than or equal to 2 kV and lower than or equal to 50 kV, preferably higher than or equal to 5 kV and lower than or equal to 30 kV.
The dopant 120 may be added while the substrate is heated. The substrate temperature is, for example, higher than or equal to 200° C. and lower than or equal to 700° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., and further preferably higher than or equal to 350° C. and lower than or equal to 450° C. If the dopant 120 is added while heated as described here, a decrease in the crystallinity of the insulator 106a, the semiconductor 106b, and the insulator 106c due to the addition of the dopant 120 can be inhibited.
As the dopant 120, a dopant other than that added as the dopant 119 is preferably used. For example, hydrogen that enters the sites of oxygen vacancies and easily forms a shallow donor level is preferably used.
After the addition of the dopant 120, heat treatment may be performed. The heat treatment may be performed at higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 350° C. and lower than or equal to 450° C. in a nitrogen atmosphere, or under reduced pressure or air (ultra dry air), for example.
Note that in the case where only patterning for the conductor 114 is performed without performing patterning for the insulator 112 as described above, the dopant 120 is added through the insulator 112 as illustrated in FIGS. 20C and 20D. Adding the dopant 120 in this manner can protect the insulator 106c from damage caused by the collision of the dopant 120.
Note that the description for FIGS. 7A1, 7A2, 7B, and 7C in the above embodiment can be referred to for the addition of the dopant 119 and the dopant 120.
As described in the above embodiment, when an ion is incident on the sample surface at a specific angle, part of a low-resistance region can be easily formed in a region overlapping with the conductor 114, of the semiconductor 106b. Thus, the dopant 119 is preferably added such that an ion is incident on the sample surface at a specific angle as described above. Note that the dopant 120 is preferably added substantially perpendicular to the sample surface so that the regions 126b and 126c are not formed in a region where the semiconductor 106b overlaps with the insulator 115. Note that the method for manufacturing a semiconductor device of this embodiment is not limited to the above example; the ion incident angle can be set as appropriate depending on the area of the regions 126a, 126b, 126c, 126d, and 126e or the like.
In the above manner, the regions 126b, 126c, 126d, and 126e to which an ion is added are formed.
With the use of any of the methods described with reference to FIGS. 7A1, 7A2, 7B, and 7C, the regions 126d and 126e can be formed not only in a region not overlapping with the conductor 114 but also in a region partly overlapping with the conductor 114. In that case, an offset region having high resistance is not formed between the region 126a and each of the regions 126d and 126e, leading to an increase in the on-state current of the transistor.
The addition of the dopant 119 and the dopant 120 can reduce the resistances of the regions 126b and 126c. The resistances of the regions 126b, 126c, 126d, and 126e can be reduced in the following manner, for example: the dopant 119 is added first, and then the dopant 120 is added to form a donor level. In that case, to form the donor level in the regions 126b, 126c, 126d, and 126e, for example, oxygen vacancies are formed in the regions 136b and 136c by the addition of the dopant 119 and then the dopant 120 is added. The donor level might be formed when hydrogen enters the sites of the oxygen vacancies, for example. The donor level formed in such a manner is stable and thus, the resistance is hardly increased later.
After the addition of the dopant 119, heat treatment may be performed. The heat treatment may be performed at higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 350° C. and lower than or equal to 450° C. in a nitrogen atmosphere, or under reduced pressure or air (ultra dry air), for example. In the case where oxygen vacancies are formed in the regions 136b and 136c by the addition of the dopant 119, for example, heat treatment performed after the addition of the dopant 119 can cause gettering of hydrogen around the regions 136b and 136c at the sites of the oxygen vacancies. Since a donor level formed in such a manner is stable, the resistances are hardly increased later. After the addition of the dopant 120, the above heat treatment may be performed. Such heat treatment can effectively cause gettering of hydrogen added to the regions 126b and 126c at the sites of the oxygen vacancies in the regions 126d and 126e. 
Then, the insulator 116 is formed (see FIGS. 19C and 19D). For the formation of the insulator 116, the description of the above embodiment can be referred to. By the formation of the insulator 116, the low-resistance regions 107a and 107b are formed in the insulator 106a, the semiconductor 106b, and the insulator 106c in the vicinity of the interface with the insulator 116.
An element that can be used as the dopant 120 may be added after the deposition of the insulator 116, whereby the resistances of the regions 126a and 126b and the low-resistance regions 107a and 107b are further reduced. By the above addition, an element contained in the insulator 116 can be pushed in (knocked on) the insulator 106a, the semiconductor 106b, and the insulator 106c. For the addition, the description of the above embodiment can be referred to.
Next, heat treatment is preferably performed. By the heat treatment, oxygen can be supplied from the insulator 104 or the like to the insulator 106a, the semiconductor 106b, and the insulator 106c. For the heat treatment, the description of the above embodiment can be referred to.
Then, the insulator 118 is formed. For the formation of the insulator 118, the description of the above embodiment can be referred to.
Next, a resist or the like is formed over the insulator 118, and openings are formed in the insulator 118, the insulator 116, and the insulator 106c. Then, a conductor to be the conductors 108a and 108b is formed. For the formation of the conductor to be the conductors 108a and 108b, the description of the above embodiment can be referred to.
After that, the conductor to be the conductors 108a and 108b over the insulator 118 is partly removed by CMP treatment. As a result, the conductors 108a and 108b are formed only in the openings formed in the insulator 118, the insulator 116, and the insulator 106c. 
Then, a conductor to be the conductors 109a and 109b is deposited over the insulator 118, the conductor 108a, and the conductor 108b. For the formation of the conductor to be the conductors 109a and 109b, the description of the above embodiment can be referred to.
Then, a resist or the like is formed over the conductor to be the conductor 109a and the conductor 109b, and the conductor is processed with the use of the resist or the like; thus, the conductor 109a and the conductor 109b are formed (see FIGS. 19C and 19D).
Through the above steps, the transistor 20 of one embodiment of the present invention can be manufactured.
As described above, in the method for manufacturing a semiconductor device described in this embodiment, the conductive film or the like is in contact with the top surface of the region 126a, which can prevent a portion functioning as the channel formation region of the transistor 20 from being damaged. Accordingly, a reduction in the reliability of the transistor 20 by the damage can be prevented.
When the above-described manufacturing method is employed, in a line where top-gate transistors are formed by a gate-first method using LTPS, LTPS can be easily replaced with an oxide semiconductor. Here, the gate-first method is a transistor manufacturing process in which a gate is formed before formation of a source region and a drain region.
With the above structure, a transistor with stable electrical characteristics can be provided. A transistor having a low leakage current in an off state can be provided. A transistor having a high on-state current can be provided. A transistor with normally-off electrical characteristics can be provided. A transistor with a small subthreshold swing value can be provided. A highly reliable transistor can be provided.
The structure and method described in this embodiment can be implemented by being combined as appropriate with any of the structures and methods described in the other embodiments.
Embodiment 5
In this embodiment, the oxide semiconductor included in a semiconductor device of one embodiment of the present invention will be described in detail below.
<Structure of Oxide Semiconductor>
A structure of an oxide semiconductor will be described below.
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
It is known that an amorphous structure is generally defined as being metastable and unfixed, and being isotropic and having no non-uniform structure. In other words, an amorphous structure has a flexible bond angle and a short-range order but does not have a long-range order.
This means that an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. Note that an a-like OS has a periodic structure in a microscopic region, but at the same time has a void and has an unstable structure. For this reason, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.
<CAAC-OS>
First, a CAAC-OS is described.
A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).
In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.
A CAAC-OS observed with TEM is described below. FIG. 21A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
FIG. 21B is an enlarged Cs-corrected high-resolution TEM image of a region (1) in FIG. 21A. FIG. 21B shows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration reflecting unevenness of a surface over which the CAAC-OS is formed (hereinafter, the surface is referred to as a formation surface) or the top surface of the CAAC-OS, and is arranged parallel to the formation surface or the top surface of the CAAC-OS.
As shown in FIG. 21B, the CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is denoted by an auxiliary line in FIG. 21C. FIGS. 21B and 21C prove that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC).
Here, according to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120 is illustrated by such a structure in which bricks or blocks are stacked (see FIG. 21D). The part in which the pellets are tilted as observed in FIG. 21C corresponds to a region 5161 shown in FIG. 21D.
FIG. 22A shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 22B, 22C, and 22D are enlarged Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in FIG. 22A, respectively. FIGS. 22B, 22C, and 22D indicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets.
Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO4 crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in FIG. 23A. This peak is derived from the (009) plane of the InGaZnO4 crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS.
Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when 2θ is around 36°, in addition to the peak at 2θ of around 31°. The peak at 2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. It is preferable that in the CAAC-OS analyzed by an out-of-plane method, a peak appear when 2θ is around 31° and that a peak not appear when 2θ is around 36°.
On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray beam is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when 28 is around 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. In the case of the CAAC-OS, when analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector of the sample surface as an axis (φ axis), as shown in FIG. 23B, a peak is not clearly observed. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO4, when φ scan is performed with 2θ fixed at around 56°, as shown in FIG. 23C, six peaks which are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS.
Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO4 crystal in a direction parallel to the sample surface, a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shown in FIG. 24A can be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO4 crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, FIG. 24B shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 24B, a ring-like diffraction pattern is observed. Thus, the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring in FIG. 24B is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO4 crystal. The second ring in FIG. 24B is considered to be derived from the (110) plane and the like.
As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).
Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. Impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources, for example. Furthermore, oxygen vacancies in the oxide semiconductor serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein.
The CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with low carrier density (specifically, lower than 8×1011/cm3, preferably lower than 1×1011/cm3, further preferably lower than 1×1010/cm3, and is higher than or equal to 1×10−9/cm3). Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics.
<nc-OS>
Next, an nc-OS will be described.
An nc-OS has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description.
In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. For example, when the nc-OS is analyzed by an out-of-plane method using an X-ray beam having a diameter larger than the size of a pellet, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet. Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots is shown in a ring-like region in some cases.
Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).
The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
<a-Like OS>
An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.
In a high-resolution TEM image of the a-like OS, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed.
The a-like OS has an unstable structure because it includes a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.
An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In—Ga—Zn oxide.
First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.
Note that which part is regarded as a crystal part is determined as follows. It is known that a unit cell of an InGaZnO4 crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO4. Each of lattice fringes corresponds to the a-b plane of the InGaZnO4 crystal.
FIG. 25 shows change in the average size of crystal parts (at 22 points to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 25 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by (1) in FIG. 25, a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2×108 e−/nm2. In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×108 e−/nm2. Specifically, as shown by (2) and (3) in FIG. 25, the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose.
In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
The a-like OS has a lower density than the nc-OS and the CAAC-OS because it includes a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.
For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g/cm3. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm3 and lower than 5.9 g/cm3. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm3 and lower than 6.3 g/cm3.
Note that there is a possibility that an oxide semiconductor having a certain composition cannot exist in a single crystal structure. In that case, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.
As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
The structures and methods described in this embodiment can be implemented by being combined as appropriate with any of the other structures and methods described in the other embodiments.
Embodiment 6
In this embodiment, an example of a circuit of a semiconductor device including a transistor or the like of one embodiment of the present invention will be described.
<CMOS Inverter>
A circuit diagram in FIG. 26A shows a configuration of what is called a CMOS inverter in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected to each other in series and in which gates of them are connected to each other.
<Structure of Semiconductor Device>
FIG. 27 is a cross-sectional view of the semiconductor device of FIG. 26A. The semiconductor device shown in FIG. 27 includes the transistor 2200 and the transistor 2100. The transistor 2100 is placed above the transistor 2200. Any of the transistors described in Embodiment 1 or 2 can be used as the transistor 2100. Furthermore, any of the transistors described in Embodiments 3 and 4 can be used as the transistor 2100 as illustrated in FIG. 28. Thus, the description regarding the above-mentioned transistors can be referred to for the transistor 2100 as appropriate.
The transistor 2200 shown in FIG. 27 is a transistor using a semiconductor substrate 450. The transistor 2200 includes a region 472a in the semiconductor substrate 450, a region 472b in the semiconductor substrate 450, an insulator 462, and a conductor 454.
In the transistor 2200, the regions 472a and 472b have functions of a source region and a drain region. The insulator 462 serves as a gate insulator. The conductor 454 serves as a gate electrode. Thus, the resistance of a channel formation region can be controlled by a potential applied to the conductor 454. In other words, conduction or non-conduction between the region 472a and the region 472b can be controlled by the potential applied to the conductor 454.
For the semiconductor substrate 450, a single-material semiconductor substrate formed using silicon, germanium, or the like or a semiconductor substrate formed using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like may be used, for example. A single crystal silicon substrate is preferably used as the semiconductor substrate 450.
For the semiconductor substrate 450, a semiconductor substrate including impurities imparting n-type conductivity is used. However, a semiconductor substrate including impurities imparting p-type conductivity may be used as the semiconductor substrate 450. In that case, a well including impurities imparting the n-type conductivity may be provided in a region where the transistor 2200 is formed. Alternatively, the semiconductor substrate 450 may be an i-type semiconductor substrate.
The top surface of the semiconductor substrate 450 preferably has a (110) plane. Thus, on-state characteristics of the transistor 2200 can be improved.
The regions 472a and 472b are regions including impurities imparting the p-type conductivity. Accordingly, the transistor 2200 has a structure of a p-channel transistor.
Note that the transistor 2200 is apart from an adjacent transistor by a region 460 and the like. The region 460 is an insulating region.
The semiconductor device illustrated in FIG. 27 includes an insulator 464, an insulator 466, an insulator 468, a conductor 480a, a conductor 480b, a conductor 480c, a conductor 478a, a conductor 478b, a conductor 478c, a conductor 476a, a conductor 476b, a conductor 474a, a conductor 474b, a conductor 474c, a conductor 496a, a conductor 496b, a conductor 496c, a conductor 496d, a conductor 498a, a conductor 498b, a conductor 498c, an insulator 489, an insulator 490, an insulator 491, an insulator 492, an insulator 493, an insulator 494, and an insulator 495.
The insulator 464 is placed over the transistor 2200. The insulator 466 is placed over the insulator 464. The insulator 468 is placed over the insulator 466. The insulator 489 is placed over the insulator 468. The transistor 2100 is placed over the insulator 489. The insulator 493 is placed over the transistor 2100. The insulator 494 is placed over the insulator 493.
The insulator 464 includes an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454. In the openings, the conductor 480a, the conductor 480b, and the conductor 480c are embedded.
The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In the openings, the conductor 478a, the conductor 478b, and the conductor 478c are embedded.
The insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In the openings, the conductor 476a and the conductor 476b are embedded.
The insulator 489 includes an opening overlapping with a channel formation region of the transistor 2100, an opening reaching the conductor 476a, and an opening reaching the conductor 476b. In the openings, the conductor 474a, the conductor 474b, and the conductor 474c are embedded.
The conductor 474a may serve as a gate electrode of the transistor 2100. The electrical characteristics of the transistor 2100, such as the threshold voltage, may be controlled by application of a predetermined potential to the conductor 474a, for example. The conductor 474a may be electrically connected to the conductor 504 having a function of the gate electrode of the transistor 2100, for example. In that case, on-state current of the transistor 2100 can be increased. Furthermore, a punch-through phenomenon can be suppressed; thus, the electrical characteristics of the transistor 2100 in a saturation region can be stable. Note that the conductor 474a corresponds to the conductor 102 in the above embodiment and thus, the description of the conductor 102 can be referred to for details about the conductor 474a. 
The insulator 490 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that the insulator 490 can be formed using the insulator that is used for the insulator 101 in the above embodiment. The insulator 490 is provided to cover the conductors 474a to 474c except for the openings, whereby extraction of oxygen from the insulator 491 by the conductors 474a to 474c can be prevented. Accordingly, oxygen can be effectively supplied from the insulator 491 to an oxide semiconductor of the transistor 2100.
The insulator 491 includes the opening reaching the conductor 474b and the opening reaching the conductor 474c. Note that the insulator 491 corresponds to the insulator 104 in the above embodiment and thus, the description of the insulator 104 can be referred to for details about the insulator 491.
The insulator 495 includes the opening reaching the conductor 474b through a region 507b that is one of a source and a drain of the transistor 2100, an opening reaching a region 507a that is the other of the source and the drain of the transistor 2100, an opening reaching the conductor 504 that is the gate electrode of the transistor 2100, and the opening reaching the conductor 474c. Note that the insulator 495 corresponds to the insulator 116 in the above embodiment and thus, the description of the insulator 116 can be referred to for details about the insulator 495.
The insulator 493 includes the opening reaching the conductor 474b through the region 507b that is one of the source and the drain of the transistor 2100, the opening reaching the region 507a that is the other of the source and the drain of the transistor 2100, the opening reaching the conductor 504 that is the gate electrode of the transistor 2100, and the opening reaching the conductor 474c. In the openings, the conductor 496a, the conductor 496b, the conductor 496c, and the conductor 496d are embedded. Note that in some cases, an opening provided in a component of the transistor 2100 or the like is positioned between openings provided in other components. Note that the insulator 493 corresponds to the insulator 118 in the above embodiment and thus, the description of the insulator 118 can be referred to for details about the insulator 493.
The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b and the conductor 496d, and an opening reaching the conductor 496c. In the openings, the conductor 498a, the conductor 498b, and the conductor 498c are embedded.
The insulators 464, 466, 468, 489, 493, and 494 may each be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
The insulator that has a function of blocking oxygen and impurities such as hydrogen is preferably included in at least one of the insulators 464, 466, 468, 489, 493, and 494. When an insulator that has a function of blocking oxygen and impurities such as hydrogen is placed near the transistor 2100, the electrical characteristics of the transistor 2100 can be stable.
An insulator with a function of blocking oxygen and impurities such as hydrogen may be formed to have a single-layer structure or a stacked-layer structure including an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.
Each of the conductor 480a, the conductor 480b, the conductor 480c, the conductor 478a, the conductor 478b, the conductor 478c, the conductor 476a, the conductor 476b, the conductor 474a, the conductor 474b, the conductor 474c, the conductor 496a, the conductor 496b, the conductor 496c, the conductor 496d, the conductor 498a, the conductor 498b, and the conductor 498c may be formed to have, for example, a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds selected from boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound containing the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.
Note that a semiconductor device in FIG. 29 is the same as the semiconductor device in FIG. 27 except for the structure of the transistor 2200. A semiconductor device in FIG. 30 is the same as the semiconductor device in FIG. 28 except for the structure of the transistor 2200. Therefore, the description of the semiconductor device in FIG. 27 is referred to for the semiconductor devices in FIG. 29 and FIG. 30. In the semiconductor devices in FIG. 29 and FIG. 30, the transistor 2200 is a Fin-type transistor. The effective channel width is increased in the Fin-type transistor 2200, whereby the on-state characteristics of the transistor 2200 can be improved. In addition, since contribution of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 2200 can be improved.
Note that a semiconductor device in FIG. 31 is the same as the semiconductor device in FIG. 27 except for the structure of the transistor 2200. Note that a semiconductor device in FIG. 32 is the same as the semiconductor device in FIG. 28 except for the structure of the transistor 2200. Therefore, the description of the semiconductor device in FIG. 27 is referred to for the semiconductor devices in FIG. 31 and FIG. 32. Specifically, in the semiconductor devices in FIG. 31 and FIG. 32, the transistor 2200 is formed in the semiconductor substrate 450 that is an SOI substrate. In the structures in FIG. 31 and FIG. 32, a region 456 is apart from the semiconductor substrate 450 with an insulator 452 provided therebetween. Since the SOI substrate is used as the semiconductor substrate 450, a punch-through phenomenon and the like can be suppressed; thus, the off-state characteristics of the transistor 2200 can be improved. Note that the insulator 452 can be formed by turning the semiconductor substrate 450 into an insulator. For example, silicon oxide can be used as the insulator 452.
In each of the semiconductor devices shown in FIG. 27, FIG. 28, FIG. 29, FIG. 30, FIG. 31, and FIG. 32, a p-channel transistor is formed utilizing a semiconductor substrate, and an n-channel transistor is formed above that; therefore, an occupation area of the element can be reduced. That is, the integration degree of the semiconductor device can be improved. In addition, the manufacturing process can be simplified compared to the case where an n-channel transistor and a p-channel transistor are formed utilizing the same semiconductor substrate; therefore, the productivity of the semiconductor device can be increased. Moreover, the yield of the semiconductor device can be improved. For the p-channel transistor, some complicated steps such as formation of LDD regions, formation of a shallow trench structure, or distortion design can be omitted in some cases. Therefore, the productivity and yield of the semiconductor device can be increased in some cases, compared to a semiconductor device where an n-channel transistor is formed utilizing the semiconductor substrate.
<CMOS Analog Switch>
A circuit diagram in FIG. 26B shows a configuration in which sources of the transistors 2100 and 2200 are connected to each other and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, the transistors can function as what is called a CMOS analog switch.
<Memory Device 1>
An example of a semiconductor device (memory device) which includes the transistor of one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is shown in FIGS. 33A and 33B.
The semiconductor device illustrated in FIG. 33A includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. Note that a transistor similar to the transistor 2100 can be used as the transistor 3300.
Note that the transistor 3300 is preferably a transistor with a low off-state current. For example, a transistor using an oxide semiconductor can be used as the transistor 3300. Since the off-state current of the transistor 3300 is low, stored data can be retained for a long period at a predetermined node of the semiconductor device. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low.
In FIG. 33A, a first wiring 3001 is electrically connected to a source of the transistor 3200. A second wiring 3002 is electrically connected to a drain of the transistor 3200. A third wiring 3003 is electrically connected to one of a source and a drain of the transistor 3300. A fourth wiring 3004 is electrically connected to a gate of the transistor 3300. A gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to one electrode of the capacitor 3400. A fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400.
The semiconductor device in FIG. 33A has a feature that the potential of the gate of the transistor 3200 can be retained, and thus enables writing, retaining, and reading of data as follows.
Writing and retaining of data are described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to a node FG where the gate of the transistor 3200 and the one electrode of the capacitor 3400 are electrically connected to each other. That is, a predetermined electric charge is supplied to the gate of the transistor 3200 (writing). Here, one of two kinds of electric charges providing different potential levels (hereinafter referred to as a low-level electric charge and a high-level electric charge) is supplied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is off, so that the transistor 3300 is turned off. Thus, the electric charge is held at the node FG (retaining).
Since the off-state current of the transistor 3300 is low, the electric charge of the node FG is retained for a long time.
Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the fifth wiring 3005 while a predetermined potential (a constant potential) is supplied to the first wiring 3001, whereby the potential of the second wiring 3002 varies depending on the amount of electric charge retained in the node FG. This is because in the case of using an n-channel transistor as the transistor 3200, an apparent threshold voltage Vth_H at the time when the high-level electric charge is given to the gate of the transistor 3200 is lower than an apparent threshold voltage Vth_L at the time when the low-level electric charge is given to the gate of the transistor 3200. Here, an apparent threshold voltage refers to the potential of the fifth wiring 3005 which is needed to make the transistor 3200 be in “on state.” Thus, the potential of the fifth wiring 3005 is set to a potential V0 which is between Vth_H and Vth_L, whereby electric charge supplied to the node FG can be determined. For example, in the case where the high-level electric charge is supplied to the node FG in writing and the potential of the fifth wiring 3005 is V0 (>Vth_H), the transistor 3200 is brought into “on state.” In the case where the low-level electric charge is supplied to the node FG in writing, even when the potential of the fifth wiring 3005 is V0 (<Vth_L), the transistor 3200 still remains in “off state.” Thus, the data retained in the node FG can be read by determining the potential of the second wiring 3002.
Note that in the case where memory cells are arrayed, it is necessary that data of a desired memory cell be read in read operation. For example, a configuration in which only data of a desired memory cell can be read by supplying a potential at which the transistor 3200 is brought into an “off state” regardless of the charge supplied to the node FG, that is, a potential lower than Vth_H to the fifth wiring 3005 of memory cells from which data is not read may be employed. Alternatively, a configuration in which only data of a desired memory cell can be read by supplying a potential at which the transistor 3200 is brought into an “on state” regardless of the charge supplied to the node FG, that is, a potential higher than Vth_L to the fifth wiring 3005 of memory cells from which data is not read may be employed.
Although an example in which two kinds of electric charges are retained in the node FG, the semiconductor device of the present invention is not limited to this example. For example, a structure in which three or more kinds of electric charges can be retained in the node FG of the semiconductor device may be employed. With such a structure, the semiconductor device can be multi-valued and the storage capacity can be increased.
<Structure of Memory Device 1>
FIG. 34 is a cross-sectional view of the semiconductor device of FIG. 33A. The semiconductor device shown in FIG. 34 includes the transistor 3200, the transistor 3300, and the capacitor 3400. The transistor 3300 and the capacitor 3400 are placed above the transistor 3200. Note that for the transistor 3300, the description of the above transistor 2100 is referred to. Here, as the transistor 2100, the transistor described in Embodiment 1 or 2 may be used as illustrated in FIG. 34 or alternatively, the transistor described in Embodiment 3 or 4 may be used as illustrated in FIG. 35. Furthermore, for the transistor 3200, the description of the transistor 2200 in FIG. 27 is referred to. Note that although the transistor 2200 is illustrated as a p-channel transistor in FIG. 27, the transistor 3200 may be an n-channel transistor.
The transistor 3200 illustrated in FIG. 34 is a transistor using the semiconductor substrate 450. The transistor 3200 includes the region 472a in the semiconductor substrate 450, the region 472b in the semiconductor substrate 450, the insulator 462, and the conductor 454.
The semiconductor device illustrated in FIG. 34 includes the insulator 464, the insulator 466, the insulator 468, the conductor 480a, the conductor 480b, the conductor 480c, the conductor 478a, the conductor 478b, the conductor 478c, the conductor 476a, the conductor 476b, the conductor 474a, the conductor 474b, the conductor 474c, the conductor 496a, the conductor 496b, the conductor 496c, the conductor 496d, the conductor 498a, the conductor 498b, the conductor 498c, the insulator 489, the insulator 490, the insulator 491, the insulator 492, the insulator 493, the insulator 494, and the insulator 495.
The insulator 464 is provided over the transistor 3200. The insulator 466 is provided over the insulator 464. The insulator 468 is provided over the insulator 466. The insulator 489 is provided over the insulator 468. The transistor 3300 is provided over the insulator 489. The insulator 493 is provided over the transistor 3300. The insulator 494 is provided over the insulator 493.
The insulator 464 has an opening reaching the region 472a, an opening reaching the region 472b, and an opening reaching the conductor 454. In the openings, the conductor 480a, the conductor 480b, and the conductor 480c are embedded.
The insulator 466 includes an opening reaching the conductor 480a, an opening reaching the conductor 480b, and an opening reaching the conductor 480c. In the openings, the conductor 478a, the conductor 478b, and the conductor 478c are embedded.
The insulator 468 includes an opening reaching the conductor 478b and an opening reaching the conductor 478c. In the openings, the conductor 476a and the conductor 476b are embedded.
The insulator 489 includes an opening overlapping with a channel formation region of the transistor 3300, an opening reaching the conductor 476a, and an opening reaching the conductor 476b. In the openings, the conductor 474a, the conductor 474b, and the conductor 474c are embedded.
The conductor 474a may serve as a bottom gate electrode of the transistor 3300. Alternatively, for example, electrical characteristics such as the threshold voltage of the transistor 3300 may be controlled by application of a constant potential to the conductor 474a. Further alternatively, for example, the conductor 474a and the conductor 504 that is a top gate electrode of the transistor 3300 may be electrically connected to each other. Thus, the on-state current of the transistor 3300 can be increased. A punch-through phenomenon can be suppressed; thus, stable electrical characteristics in a saturation region of the transistor 3300 can be obtained.
The insulator 490 includes an opening reaching the conductor 474b and an opening reaching the conductor 474c. Note that the insulator 490 can be formed using the insulator that is used for the insulator 101 in the above embodiment. The insulator 490 is provided to cover the conductors 474a to 474c except for the openings, whereby extraction of oxygen from the insulator 491 by the conductors 474a to 474c can be prevented. Accordingly, oxygen can be effectively supplied from the insulator 491 to an oxide semiconductor of the transistor 3300.
The insulator 491 includes the opening reaching the conductor 474b and the opening reaching the conductor 474c. Note that the insulator 491 corresponds to the insulator 104 in the above embodiment and thus, the description of the insulator 104 can be referred to for details about the insulator 491.
The insulator 495 includes the opening reaching the conductor 474b through the region 507b that is one of the source and the drain of the transistor 3300, an opening reaching the conductor 514 that overlaps with the region 507a that is the other of the source and the drain of the transistor 3300, with an insulator 511 positioned therebetween, an opening reaching the conductor 504 that is the gate electrode of the transistor 3300, and the opening reaching the conductor 474c through the region 507a that is the other of the source and the drain of the transistor 3300. Note that the insulator 495 corresponds to the insulator 116 in the above embodiment and thus, the description of the insulator 116 can be referred to for details about the insulator 495.
The insulator 493 includes the opening reaching the conductor 474b through the region 507b that is one of the source and the drain of the transistor 3300, an opening reaching the conductor 514 that overlaps with the region 507a that is the other of the source and the drain of the transistor 3300, with an insulator 511 positioned therebetween, an opening reaching the conductor 504 that is the gate electrode of the transistor 3300, and the opening reaching the conductor 474c through the region 507a that is the other of the source and the drain of the transistor 3300. In the openings, the conductor 496a, the conductor 496b, the conductor 496c, and the conductor 496d are embedded. Note that in some cases, an opening provided in a component of the transistor 3300 or the like is positioned between openings provided in other components. Note that the insulator 493 corresponds to the insulator 118 in the above embodiment and thus, the description of the insulator 118 can be referred to for details about the insulator 493.
The insulator 494 includes an opening reaching the conductor 496a, an opening reaching the conductor 496b, and an opening reaching the conductor 496c. In the openings, the conductors 498a, 498b, and 498c are embedded.
At least one of the insulators 464, 466, 468, 489, 493, and 494 preferably has a function of blocking oxygen and impurities such as hydrogen. When an insulator that has a function of blocking oxygen and impurities such as hydrogen is placed near the transistor 3300, the electrical characteristics of the transistor 3300 can be stable.
The source or drain of the transistor 3200 is electrically connected to the region 507b that is one of the source and the drain of the transistor 3300 through the conductor 480b, the conductor 478b, the conductor 476a, the conductor 474b, and the conductor 496c. The conductor 454 that is the gate electrode of the transistor 3200 is electrically connected to the region 507a that is the other of the source and the drain of the transistor 3300 through the conductor 480c, the conductor 478c, the conductor 476b, the conductor 474c, and the conductor 496d. 
The capacitor 3400 includes the region 507a that is the other of the source and the drain of the transistor 3300, the conductor 514, and the insulator 511. The insulator 511 is preferably used in some cases because the insulator 511 can be formed in the same step as the insulator functioning as a gate insulator of the transistor 3300, leading to an increase in productivity. A layer formed in the same step as the conductor 504 functioning as the gate electrode of the transistor 3300 is preferably used as the conductor 514 in some cases, leading to an increase in productivity.
For the structures of other components, the description of FIG. 27 and the like can be referred to as appropriate.
A semiconductor device in FIG. 36 is the same as the semiconductor device in FIG. 34 except for the structure of the transistor 3200. Note that a semiconductor device in FIG. 37 is the same as the semiconductor device in FIG. 35 except for the structure of the transistor 3200. Therefore, the description of the semiconductor device in FIG. 34 is referred to for the semiconductor devices in FIG. 36 and FIG. 37. Specifically, in the semiconductor devices in FIG. 36 and FIG. 37, the transistor 3200 is a Fin-type transistor. For the Fin-type transistor 3200, the description of the transistor 2200 in FIG. 29 is referred to. Note that although the transistor 2200 is illustrated as a p-channel transistor in FIG. 29, the transistor 3200 may be an n-channel transistor.
A semiconductor device in FIG. 38 is the same as the semiconductor device in FIG. 34 except for the structure of the transistor 3200. A semiconductor device in FIG. 39 is the same as the semiconductor device in FIG. 35 except for the structure of the transistor 3200. Therefore, the description of the semiconductor device in FIG. 34 is referred to for the semiconductor devices in FIG. 38 and FIG. 39. Specifically, in the semiconductor devices in FIG. 38 and FIG. 39, the transistor 3200 is provided in the semiconductor substrate 450 that is an SOI substrate. For the transistor 3200, which is provided in the semiconductor substrate 450 (SOI substrate), the description of the transistor 2200 in FIG. 31 is referred to. Note that although the transistor 2200 is illustrated as a p-channel transistor in FIG. 31, the transistor 3200 may be an n-channel transistor.
<Memory Device 2>
The semiconductor device in FIG. 33B is different from the semiconductor device in FIG. 33A in that the transistor 3200 is not provided. Also in this case, data can be written and retained in a manner similar to that of the semiconductor device in FIG. 33A.
Reading of data in the semiconductor device in FIG. 33B is described. When the transistor 3300 is brought into an on state, the third wiring 3003 which is in a floating state and the capacitor 3400 are brought into conduction, and the electric charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 is changed. The amount of change in the potential of the third wiring 3003 varies depending on the potential of the one electrode of the capacitor 3400 (or the electric charge accumulated in the capacitor 3400).
For example, the potential of the third wiring 3003 after the charge redistribution is (CB×VB0+C×V)/(CB+C), where V is the potential of the one electrode of the capacitor 3400, C is the capacitance of the capacitor 3400, CB is the capacitance component of the third wiring 3003, and VB0 is the potential of the third wiring 3003 before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the one electrode of the capacitor 3400 is V1 and V0 (V1>V0), the potential of the third wiring 3003 in the case of retaining the potential V1 (=(CB×VB0+C×V1)/(CB+C)) is higher than the potential of the third wiring 3003 in the case of retaining the potential V0 (=(CB×VB0+C×V0)/(CB+C)).
Then, by comparing the potential of the third wiring 3003 with a predetermined potential, data can be read.
In this case, a transistor including the first semiconductor may be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor may be stacked over the driver circuit as the transistor 3300.
When including a transistor using an oxide semiconductor and having a low off-state current, the semiconductor device described above can retain stored data for a long time. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).
In the semiconductor device, high voltage is not needed for writing data and deterioration of elements is less likely to occur. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, the semiconductor device of one embodiment of the present invention does not have a limit on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, data is written depending on the on/off state of the transistor, whereby high-speed operation can be achieved.
<Memory Device 3>
A modification example of the semiconductor device (memory device) illustrated in FIG. 33A will be described with reference to a circuit diagram in FIG. 40.
The semiconductor device illustrated in FIG. 40 includes a transistor 4100, a transistor 4200, a transistor 4300, a transistor 4400, a capacitor 4500, and a capacitor 4600. Here, a transistor similar to the transistor 3200 can be used as the transistor 4100, and transistors similar to the transistor 3300 can be used as the transistors 4200, 4300, and 4400. Although not illustrated in FIG. 40, a plurality of semiconductor devices in FIG. 40 are provided in a matrix. The semiconductor devices in FIG. 40 can control writing and reading of a data voltage in accordance with a signal or a potential supplied to a wiring 4001, a wiring 4003, a wiring 4005, a wiring 4006, a wiring 4007, a wiring 4008, and a wiring 4009.
One of a source and a drain of the transistor 4100 is connected to the wiring 4003. The other of the source and the drain of the transistor 4100 is connected to the wiring 4001. Although the transistor 4100 is a p-channel transistor in FIG. 40, the transistor 4100 may be an n-channel transistor.
The semiconductor device in FIG. 40 includes two data retention portions. For example, a first data retention portion retains an electric charge between one of a source and a drain of the transistor 4400, one electrode of the capacitor 4600, and one of a source and a drain of the transistor 4200 which are connected to a node FG1. A second data retention portion retains an electric charge between a gate of the transistor 4100, the other of the source and the drain of the transistor 4200, one of a source and a drain of the transistor 4300, and one electrode of the capacitor 4500 which are connected to a node FG2.
The other of the source and the drain of the transistor 4300 is connected to the wiring 4003. The other of the source and the drain of the transistor 4400 is connected to the wiring 4001. A gate of the transistor 4400 is connected to the wiring 4005. A gate of the transistor 4200 is connected to the wiring 4006. A gate of the transistor 4300 is connected to the wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the capacitor 4500 is connected to the wiring 4009.
The transistors 4200, 4300, and 4400 each function as a switch for control of writing a data voltage and retaining an electric charge. Note that, as each of the transistors 4200, 4300, and 4400, it is preferable to use a transistor having a low current that flows between a source and a drain in an off state (low off-state current). As an example of the transistor with a low off-state current, a transistor including an oxide semiconductor in its channel formation region (an OS transistor) is preferably used. An OS transistor has a low off-state current and can be manufactured to overlap with a transistor including silicon, for example. Although the transistors 4200, 4300, and 4400 are n-channel transistors in FIG. 40, the transistors 4200, 4300, and 4400 may be p-channel transistors.
The transistors 4200 and 4300 and the transistor 4400 are preferably provided in different layers even when the transistors 4200, 4300, and 4400 are transistors including oxide semiconductors. In other words, the semiconductor device in FIG. 40 preferably includes, as illustrated in FIG. 40, a first layer 4021 where the transistor 4100 is provided, a second layer 4022 where the transistors 4200 and 4300 are provided, and a third layer 4023 where the transistor 4400 is provided. By stacking layers where transistors are provided, the circuit area can be reduced, so that the size of the semiconductor device can be reduced.
Next, operation of writing data to the semiconductor device illustrated in FIG. 40 is described.
First, operation of writing data voltage to the data retention portion connected to the node FG1 (hereinafter referred to as writing operation 1) is described. In the following description, data voltage written to the data retention portion connected to the node FG1 is VD1, and the threshold voltage of the transistor 4100 is Vth.
In the writing operation 1, the potential of the wiring 4003 is set at VD1, and after the potential of the wiring 4001 is set at a ground potential, the wiring 4001 is brought into an electrically floating state. The wirings 4005 and 4006 are set at a high level. The wirings 4007 to 4009 are set at a low level. Then, the potential of the node FG2 in the electrically floating state is increased, so that a current flows through the transistor 4100. The current flows through the transistor 4100, so that the potential of the wiring 4001 is increased. The transistors 4400 and 4200 are turned on. Thus, as the potential of the wiring 4001 is increased, the potentials of the nodes FG1 and FG2 are increased. When the potential of the node FG2 is increased and a voltage (Vgs) between the gate and the source of the transistor 4100 becomes the threshold voltage Vth of the transistor 4100, the current flowing through the transistor 4100 is decreased. Accordingly, the potentials of the wiring 4001 and the nodes FG1 and FG2 stop increasing, so that the potentials of the nodes FG1 and FG2 are fixed at “VD1−Vth” in which VD1 is decreased by Vth.
When a current flows through the transistor 4100, VD1 supplied to the wiring 4003 is supplied to the wiring 4001, so that the potentials of the nodes FG1 and FG2 are increased. When the potential of the node FG2 becomes “VD1−Vth” with the increase in the potentials, Vgs of the transistor 4100 becomes Vth, so that the current flow is stopped.
Next, operation of writing data voltage to the data retention portion connected to the node FG2 (hereinafter referred to as writing operation 2) is described. In the following description, data voltage written to the data retention portion connected to the node FG2 is VD2.
In the writing operation 2, the potential of the wiring 4001 is set at VD2, and after the potential of the wiring 4003 is set at a ground potential, the wiring 4003 is brought into an electrically floating state. The wiring 4007 is set at the high level. The wirings 4005, 4006, 4008, and 4009 are set at the low level. The transistor 4300 is turned on, so that the wiring 4003 is set at the low level. Thus, the potential of the node FG2 is decreased to the low level, so that the current flows through the transistor 4100. By the current flow, the potential of the wiring 4003 is increased. The transistor 4300 is turned on. Thus, as the potential of the wiring 4003 is increased, the potential of the node FG2 is increased. When the potential of the node FG2 is increased and Vgs of the transistor 4100 becomes Vth of the transistor 4100, the current flowing through the transistor 4100 is decreased. Accordingly, an increase in the potentials of the wiring 4003 and the node FG2 is stopped, so that the potential of the node FG2 is fixed at “VD2−Vth” in which VD2 is decreased by Vth.
In other words, when a current flows through the transistor 4100, VD2 supplied to the wiring 4001 is supplied to the wiring 4003, so that the potential of the node FG2 is increased. When the potential of the node FG2 becomes “VD2−Vth” with the increase in the potential, Vgs of the transistor 4100 becomes Vth, so that the current flow is stopped. At this time, the transistors 4200 and 4400 are off and the potential of the node FG1 remains at “VD1−Vth” written in the writing operation 1.
In the semiconductor device in FIG. 40, after data voltages are written to the plurality of data retention portions, the wiring 4009 is set at the high level, so that the potentials of the nodes FG1 and FG2 are increased. Then, the transistors are turned off to stop movement of electric charges; thus, the written data voltages are retained.
By the above-described writing operation of the data voltage to the nodes FG1 and FG2, the data voltages can be retained in the plurality of data retention portions. Although examples where “VD1−Vth” and “VD2−Vth” are used as the written potentials are described, they are data voltages corresponding to multilevel data. Therefore, in the case where the data retention portions each retain 4-bit data, 16-value “VD1−Vth” and 16-value “VD2−Vth” can be obtained.
Next, operation of reading data from the semiconductor device illustrated in FIG. 40 is described.
First, operation of reading data voltage to the data retention portion connected to the node FG2 (hereinafter referred to as reading operation 1) is described.
In the reading operation 1, after precharge is performed, the wiring 4003 in an electrically floating state is discharged. The wirings 4005 to 4008 are set low. When the wiring 4009 is set low, the potential of the node FG2 which is electrically floating is set at “VD2−Vth.” The potential of the node FG2 is decreased, so that a current flows through the transistor 4100. By the current flow, the potential of the wiring 4003 which is electrically floating is decreased. As the potential of the wiring 4003 is decreased, Vgs of the transistor 4100 is decreased. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, the current flowing through the transistor 4100 is decreased. In other words, the potential of the wiring 4003 becomes “VD2” which is larger than the potential of the node FG2, “VD2−Vth,” by Vth. The potential of the wiring 4003 corresponds to the data voltage of the data retention portion connected to the node FG2. The data voltage of the read analog value is subjected to A/D conversion, so that data of the data retention portion connected to the node FG2 is obtained.
In other words, the wiring 4003 after precharge is brought into a floating state and the potential of the wiring 4009 is changed from high to low, whereby a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 which is in a floating state is decreased to be “VD2.” In the transistor 4100, Vgs between “VD2−Vth” of the node FG2 and “VD2” of the wiring 4003 becomes Vth, so that the current stops. Then, “VD2” written in the writing operation 2 is read to the wiring 4003.
After data in the data retention portion connected to the node FG2 is obtained, the transistor 4300 is turned on to discharge “VD2−Vth” of the node FG2.
Then, the electric charges retained in the node FG1 are distributed between the node FG1 and the node FG2, data voltage in the data retention portion connected to the node FG1 is transferred to the data retention portion connected to the node FG2. The wirings 4001 and 4003 are set low. The wiring 4006 is set high. The wiring 4005 and the wirings 4007 to 4009 are set low. When the transistor 4200 is turned on, the electric charges in the node FG1 are distributed between the node FG1 and the node FG2.
Here, the potential after the electric charge distribution is decreased from the written potential, “VD1−Vth.” Thus, the capacitance of the capacitor 4600 is preferably larger than the capacitance of the capacitor 4500. Alternatively, the potential written to the node FG1, “VD1−Vth,” is preferably larger than the potential corresponding to the same data, “VD2−Vth.” By changing the ratio of the capacitances and setting the written potential larger in advance as described above, a decrease in potential after the electric charge distribution can be suppressed. The change in potential due to the electric charge distribution is described later.
Next, operation of reading data voltage to the data retention portion connected to the node FG1 (hereinafter referred to as reading operation 2) is described.
In the reading operation 2, the wiring 4003 which is brought into an electrically floating state after precharge is discharged. The wirings 4005 to 4008 are set low. The wiring 4009 is set high at the time of precharge and then, set low. When the wiring 4009 is set low, the potential of the node FG2 which is electrically floating is set at “VD1−Vth.” The potential of the node FG2 is decreased, so that a current flows through the transistor 4100. The current flows, so that the potential of the wiring 4003 which is electrically floating is decreased. As the potential of the wiring 4003 is decreased, Vgs of the transistor 4100 is decreased. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, the current flowing through the transistor 4100 is decreased. In other words, the potential of the wiring 4003 becomes “VD1” which is larger than the potential of the node FG2, “VD1−Vth,” by Vth. The potential of the wiring 4003 corresponds to the data voltage of the data retention portion connected to the node FG1. The data voltage of the read analog value is subjected to A/D conversion, so that data of the data retention portion connected to the node FG1 is obtained. The above is the reading operation of the data voltage of the data retention portion connected to the node FG1.
In other words, the wiring 4003 after precharge is brought into a floating state and the potential of the wiring 4009 is changed from high to low, whereby a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 which is in a floating state is decreased to be “VD1.” In the transistor 4100, Vgs between “VD1−Vth” of the node FG2 and “VD1” of the wiring 4003 becomes Vth, so that the current stops. Then, “VD1” written in the writing operation 1 is read to the wiring 4003.
In the above-described reading operation of data voltages from the nodes FG1 and FG2, the data voltages can be read from the plurality of data retention portions. For example, 4-bit (16-level) data is retained in each of the node FG1 and the node FG2, whereby 8-bit (256-level) data can be retained in total. Although the first to third layers 4021 to 4023 are provided in the structure illustrated in FIG. 40, the storage capacity can be increased by adding layers without increasing the area of the semiconductor device.
The read potential can be read as a voltage larger than the written data voltage by Vth. Therefore, Vth of “VD1−Vth” and Vth of “VD2−Vth” written in the writing operation can be canceled to be read. As a result, the memory capacity per memory cell can be improved and read data can be close to accurate data; thus, the data reliability becomes excellent.
FIG. 41 is a cross-sectional view of a semiconductor device that corresponds to FIG. 40. The semiconductor device illustrated in FIG. 41 includes the transistors 4100, 4200, 4300, and 4400 and the capacitors 4500 and 4600. Here, the transistor 4100 is formed in the first layer 4021, the transistors 4200 and 4300 and the capacitor 4500 are formed in the second layer 4022, and the transistor 4400 and the capacitor 4600 are formed in the third layer 4023. In the semiconductor device illustrated in FIG. 41, the transistor described in Embodiment 1 or 2 is used as each of the transistors 4200, 4300, and 4400. As illustrated in FIG. 42, the transistor described in Embodiment 3 or 4 may be used as each of the transistors 4200, 4300, and 4400.
Here, the description of the transistor 3300 can be referred to for the transistors 4200, 4300, and 4400, and the description of the transistor 3200 can be referred to for the transistor 4100. The description made with reference to FIG. 34 can be appropriately referred to for other wirings, other insulators, and the like.
Note that the capacitors 4500 and 4600 are formed by including the conductive layers each having a trench-like shape, while the conductive layer of the capacitor 3400 in the semiconductor device in FIG. 34 is parallel to the substrate. With this structure, a larger capacity can be obtained without increasing the occupation area.
<FPGA>
One embodiment of the present invention can also be applied to an LSI such as a field programmable gate array (FPGA).
FIG. 43A illustrates an example of a block diagram of an FPGA. The FPGA includes a routing switch element 521 and a logic element 522. The logic element 522 can switch functions of a logic circuit, such as a combination circuit or a sequential circuit, in accordance with configuration data stored in a configuration memory.
FIG. 43B is a schematic view illustrating a function of the routing switch element 521. The routing switch element 521 can switch a connection between the logic elements 522 in accordance with configuration data stored in a configuration memory 523. Note that although FIG. 43B illustrates one switch which switches a connection between a terminal IN and a terminal OUT, in an actual FPGA, a plurality of switches are provided between a plurality of the logic elements 522.
FIG. 43C illustrates a configuration example of a circuit serving as the configuration memory 523. The configuration memory 523 includes a transistor M11 that is an OS transistor and a transistor M12 that is a silicon (Si) transistor. Configuration data DSW is supplied to a node FNSW through the transistor M11. A potential of the configuration data DSW can be retained by turning off the transistor M11. The on and off states of the transistor M12 can be switched depending on the potential of the retained configuration data DSW, so that the connection between the terminal IN and the terminal OUT can be switched.
FIG. 43D is a schematic view illustrating a function of the logic element 522. The logic element 522 can switch a potential of a terminal OUTmem in accordance with configuration data stored in a configuration memory 527. A lookup table 524 can switch functions of a combination circuit that processes a signal of the terminal IN in accordance with the potential of the terminal OUTmem. The logic element 522 includes a register 525 that is a sequential circuit and a selector 526 that switches signals of the terminal OUT. The selector 526 can select to output a signal of the lookup table 524 or to output a signal of the register 525 in accordance with the potential of the terminal OUTmem, which is output from the configuration memory 527.
FIG. 43E illustrates a configuration example of a circuit serving as the configuration memory 527. The configuration memory 527 includes a transistor M13 and a transistor M14 that are OS transistors, and a transistor M15 and a transistor M16 that are Si transistors. Configuration data DLE is supplied to a node FNLE through the transistor M13. Configuration data DBLE is supplied to a node FNBLE through the transistor M14. The configuration data DBLE corresponds to a potential of the configuration data DLE whose logic is inverted. The potential of the configuration data DLE and the potential of the configuration data DBLE can be retained by turning off the transistor M13 and the transistor M14, respectively. The on and off states of one of the transistors M15 and M16 are switched in accordance with the retained potential of the configuration data DLE or the configuration data DBLE, so that a potential VDD or a potential VSS can be supplied to the terminal OUTmem.
For the configuration illustrated in FIGS. 43A to 43E, any of the structures described in this embodiment can be used. For example, Si transistors are used as the transistors M12, M15, and M16, and OS transistors are used as the transistors M11, M13, and M14. In this case, a wiring for connecting the Si transistors provided in a lower layer can be formed with a low-resistance conductive material. Therefore, a circuit with high access speed and low power consumption can be obtained.
The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.
Embodiment 7
In this embodiment, an example of an imaging device including the transistor or the like of one embodiment of the present invention will be described.
<Configuration of Imaging Device>
FIG. 44A is a plan view illustrating an example of an imaging device 200 of one embodiment of the present invention. The imaging device 200 includes a pixel portion 210 and peripheral circuits for driving the pixel portion 210 (a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290). The pixel portion 210 includes a plurality of pixels 211 arranged in a matrix with p rows and q columns (p and q are each an integer of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to the plurality of pixels 211, and a signal for driving the plurality of pixels 211 is supplied. In this specification and the like, in some cases, a “peripheral circuit” or a “driver circuit” indicate all of the peripheral circuits 260, 270, 280, and 290. For example, the peripheral circuit 260 can be regarded as part of the peripheral circuit.
The imaging device 200 preferably includes a light source 291. The light source 291 can emit detection light P1.
The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a converter circuit. The peripheral circuit may be formed over a substrate where the pixel portion 210 is formed. A semiconductor device such as an IC chip may be used as part or the whole of the peripheral circuit. Note that as the peripheral circuit, one or more of the peripheral circuits 260, 270, 280, and 290 may be omitted.
As illustrated in FIG. 44B, the pixels 211 may be provided to be inclined in the pixel portion 210 included in the imaging device 200. When the pixels 211 are obliquely arranged, the distance between pixels (pitch) can be shortened in the row direction and the column direction. Accordingly, the quality of an image taken with the imaging device 200 can be improved.
Configuration Example 1 of Pixel
The pixel 211 included in the imaging device 200 is formed with a plurality of subpixels 212, and each subpixel 212 is combined with a filter (color filter) which transmits light in a specific wavelength range, whereby data for achieving color image display can be obtained.
FIG. 45A is a top view showing an example of the pixel 211 with which a color image is obtained. The pixel 211 illustrated in FIG. 45A includes a subpixel 212 provided with a color filter that transmits light in a red (R) wavelength range (also referred to as a subpixel 212R), a subpixel 212 provided with a color filter that transmits light in a green (G) wavelength range (also referred to as a subpixel 212G), and a subpixel 212 provided with a color filter that transmits light in a blue (B) wavelength range (also referred to as a subpixel 212B). The subpixel 212 can function as a photosensor.
The subpixel 212 (the subpixel 212R, the subpixel 212G, and the subpixel 212B) is electrically connected to a wiring 231, a wiring 247, a wiring 248, a wiring 249, and a wiring 250. In addition, the subpixel 212R, the subpixel 212G, and the subpixel 212B are connected to respective wirings 253 which are independently provided. In this specification and the like, for example, the wiring 248 and the wiring 249 that are connected to the pixel 211 in the n-th row are referred to as a wiring 248[n] and a wiring 249[n]. For example, the wiring 253 connected to the pixel 211 in the m-th column is referred to as a wiring 253[m]. Note that in FIG. 45A, the wirings 253 connected to the subpixel 212R, the subpixel 212G, and the subpixel 212B in the pixel 211 in the m-th column are referred to as a wiring 253[m]R, a wiring 253[m]G, and a wiring 253[m]B. The subpixels 212 are electrically connected to the peripheral circuit through the above wirings.
The imaging device 200 has a structure in which the subpixel 212 is electrically connected to the subpixel 212 in an adjacent pixel 211 which is provided with a color filter transmitting light in the same wavelength range as the subpixel 212, via a switch. FIG. 45B shows a connection example of the subpixels 212: the subpixel 212 in the pixel 211 arranged in the n-th (n is an integer greater than or equal to 1 and less than or equal to p) row and the m-th (m is an integer greater than or equal to 1 and less than or equal to q) column and the subpixel 212 in the adjacent pixel 211 arranged in an (n+1)-th row and the m-th column. In FIG. 45B, the subpixel 212R arranged in the n-th row and the m-th column and the subpixel 212R arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 201. The subpixel 212G arranged in the n-th row and the m-th column and the subpixel 212G arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 202. The subpixel 212B arranged in the n-th row and the m-th column and the subpixel 212B arranged in the (n+1)-th row and the m-th column are connected to each other via a switch 203.
The color filter used in the subpixel 212 is not limited to red (R), green (G), and blue (B) color filters, and color filters that transmit light of cyan (C), yellow (Y), and magenta (M) may be used. By provision of the subpixels 212 that sense light in three different wavelength ranges in one pixel 211, a full-color image can be obtained.
The pixel 211 including the subpixel 212 provided with a color filter transmitting yellow (Y) light may be provided, in addition to the subpixels 212 provided with the color filters transmitting red (R), green (G), and blue (B) light. The pixel 211 including the subpixel 212 provided with a color filter transmitting blue (B) light may be provided, in addition to the subpixels 212 provided with the color filters transmitting cyan (C), yellow (Y), and magenta (M) light. When the subpixels 212 sensing light in four different wavelength ranges are provided in one pixel 211, the reproducibility of colors of an obtained image can be increased.
For example, in FIG. 45A, in regard to the subpixel 212 sensing light in a red wavelength range, the subpixel 212 sensing light in a green wavelength range, and the subpixel 212 sensing light in a blue wavelength range, the pixel number ratio (or the light receiving area ratio) thereof is not necessarily 1:1:1. For example, the Bayer arrangement in which the pixel number ratio (the light receiving area ratio) is set at red:green:blue=1:2:1 may be employed. Alternatively, the pixel number ratio (the light receiving area ratio) of red and green to blue may be 1:6:1.
Although the number of subpixels 212 provided in the pixel 211 may be one, two or more subpixels are preferably provided. For example, when two or more subpixels 212 sensing light in the same wavelength range are provided, the redundancy is increased, and the reliability of the imaging device 200 can be increased.
When an infrared (IR) filter that transmits infrared light and absorbs or reflects visible light is used as the filter, the imaging device 200 that senses infrared light can be achieved.
Furthermore, when a neutral density (ND) filter (dark filter) is used, output saturation which occurs when a large amount of light enters a photoelectric conversion element (light-receiving element) can be prevented. With a combination of ND filters with different dimming capabilities, the dynamic range of the imaging device can be increased.
Besides the above-described filter, the pixel 211 may be provided with a lens. An arrangement example of the pixel 211, a filter 254, and a lens 255 is described with cross-sectional views in FIGS. 46A and 46B. With the lens 255, the photoelectric conversion element can receive incident light efficiently. Specifically, as illustrated in FIG. 46A, light 256 enters a photoelectric conversion element 220 through the lens 255, the filter 254 (a filter 254R, a filter 254G, and a filter 254B), a pixel circuit 230, and the like which are provided in the pixel 211.
As indicated by a region surrounded with dashed double-dotted lines, however, part of the light 256 indicated by arrows might be blocked by some wirings 257. Thus, a preferable structure is such that the lens 255 and the filter 254 are provided on the photoelectric conversion element 220 side as illustrated in FIG. 46B, whereby the photoelectric conversion element 220 can efficiently receive the light 256. When the light 256 enters the photoelectric conversion element 220 from the photoelectric conversion element 220 side, the imaging device 200 with high sensitivity can be provided.
As the photoelectric conversion element 220 illustrated in FIGS. 46A and 46B, a photoelectric conversion element in which a p-n junction or a p-i-n junction is formed may be used.
The photoelectric conversion element 220 may be formed using a substance that has a function of absorbing a radiation and generating electric charges. Examples of the substance that has a function of absorbing a radiation and generating electric charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.
For example, when selenium is used for the photoelectric conversion element 220, the photoelectric conversion element 220 can have a light absorption coefficient in a wide wavelength range, such as visible light, ultraviolet light, infrared light, X-rays, and gamma rays.
One pixel 211 included in the imaging device 200 may include the subpixel 212 with a first filter in addition to the subpixel 212 illustrated in FIGS. 45A and 45B.
Configuration Example 2 of Pixel
An example of a pixel including a transistor using silicon and a transistor using an oxide semiconductor will be described below.
FIGS. 47A and 47B are each a cross-sectional view of an element included in an imaging device. The imaging device illustrated in FIG. 47A includes a transistor 351 including silicon over a silicon substrate 300, transistors 352 and 353 which include an oxide semiconductor and are stacked over the transistor 351, and a photodiode 360 provided in a silicon substrate 300. The transistors and the photodiode 360 are electrically connected to various plugs 370 and wirings 371. In addition, an anode 361 of the photodiode 360 is electrically connected to the plug 370 through a low-resistance region 363. Note that as the transistors 352 and 353 which include an oxide semiconductor, the transistor described in Embodiment 1 or 2 may be used as illustrated in FIG. 47A or alternatively, the transistor described in Embodiment 3 or 4 may be used as illustrated in FIG. 48.
The imaging device includes a layer 310 including the transistor 351 provided on the silicon substrate 300 and the photodiode 360 provided in the silicon substrate 300, a layer 320 which is in contact with the layer 310 and includes the wirings 371, a layer 330 which is in contact with the layer 320 and includes the transistors 352 and 353, and a layer 340 which is in contact with the layer 330 and includes a wiring 372 and a wiring 373.
In the example of cross-sectional view in FIG. 47A, a light-receiving surface of the photodiode 360 is provided on the side opposite to a surface of the silicon substrate 300 where the transistor 351 is formed. With this structure, a light path can be secured without an influence of the transistors and the wirings. Thus, a pixel with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode 360 can be the same as the surface where the transistor 351 is formed.
In the case where a pixel is formed with use of only transistors using an oxide semiconductor, the layer 310 may include the transistor using an oxide semiconductor. Alternatively, the layer 310 may be omitted, and the pixel may include only transistors using an oxide semiconductor.
In the case where a pixel is formed with use of only transistors using silicon, the layer 330 may be omitted. An example of a cross-sectional view in which the layer 330 is not provided is shown in FIG. 47B.
Note that the silicon substrate 300 may be an SOI substrate. Furthermore, the silicon substrate 300 can be replaced with a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor.
Here, an insulator 380 is provided between the layer 310 including the transistor 351 and the photodiode 360 and the layer 330 including the transistors 352 and 353. However, there is no limitation on the position of the insulator 380.
Hydrogen in an insulator provided in the vicinity of a channel formation region of the transistor 351 terminates dangling bonds of silicon; accordingly, the reliability of the transistor 351 can be improved. In contrast, hydrogen in the insulator provided in the vicinity of the transistor 352, the transistor 353, and the like becomes one of factors generating a carrier in the oxide semiconductor. Thus, the hydrogen may cause a reduction of the reliability of the transistor 352, the transistor 353, and the like. Therefore, in the case where the transistor using an oxide semiconductor is provided over the transistor using a silicon-based semiconductor, it is preferable that the insulator 380 having a function of blocking hydrogen be provided between the transistors. When the hydrogen is confined below the insulator 380, the reliability of the transistor 351 can be improved. In addition, the hydrogen can be prevented from being diffused from a part below the insulator 380 to a part above the insulator 380; thus, the reliability of the transistor 352, the transistor 353, and the like can be increased.
As the insulator 380, an insulator having a function of blocking oxygen or hydrogen is used, for example.
In the cross-sectional view in FIG. 47A, the photodiode 360 in the layer 310 and the transistor in the layer 330 can be formed so as to overlap with each other. Thus, the degree of integration of pixels can be increased. In other words, the resolution of the imaging device can be increased.
As illustrated in FIG. 49A1 and FIG. 49B1, part or the whole of the imaging device can be bent. FIG. 49A1 illustrates a state in which the imaging device is bent in the direction of a dashed-dotted line X1-X2. FIG. 49A2 is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X1-X2 in FIG. 49A1. FIG. 49A3 is a cross-sectional view illustrating a portion indicated by a dashed-dotted line Y1-Y2 in FIG. 49A1.
FIG. 49B1 illustrates a state where the imaging device is bent in the direction of a dashed-dotted line X3-X4 and the direction of a dashed-dotted line Y3-Y4. FIG. 49B2 is a cross-sectional view illustrating a portion indicated by the dashed-dotted line X3-X4 in FIG. 49B1. FIG. 49B3 is a cross-sectional view illustrating a portion indicated by the dashed-dotted line Y3-Y4 in FIG. 49B1.
The bent imaging device enables the curvature of field and astigmatism to be reduced. Thus, the optical design of lens and the like, which is used in combination of the imaging device, can be facilitated. For example, the number of lenses used for aberration correction can be reduced; accordingly, a reduction of size or weight of electronic devices using the imaging device, and the like, can be achieved. In addition, the quality of a captured image can be improved.
The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.
Embodiment 8
In this embodiment, examples of CPUs including semiconductor devices such as the transistor of one embodiment of the present invention and the above-described memory device will be described.
<Configuration of CPU>
FIG. 50 is a block diagram illustrating a configuration example of a CPU including any of the above-described transistors as a component.
The CPU illustrated in FIG. 50 includes, over a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1198, a rewritable ROM 1199, and a ROM interface 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The ROM 1199 and the ROM interface 1189 may be provided over a separate chip. Needless to say, the CPU in FIG. 50 is just an example in which the configuration has been simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in FIG. 50 or an arithmetic circuit is considered as one core; a plurality of such cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example.
An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.
The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 in accordance with the state of the CPU.
The timing controller 1195 generates signals for controlling operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator for generating an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the above circuits.
In the CPU illustrated in FIG. 50, a memory cell is provided in the register 1196. For the memory cell of the register 1196, any of the above-described transistors, the above-described memory device, or the like can be used.
In the CPU illustrated in FIG. 50, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register 1196. When data retention by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When data retention by the capacitor is selected, the data is rewritten in the capacitor, and supply of a power supply voltage to the memory cell in the register 1196 can be stopped.
FIG. 51 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatile when power supply is stopped, a circuit 1202 in which stored data is nonvolatile even when power supply is stopped, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a circuit 1220 having a selecting function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include another element such as a diode, a resistor, or an inductor, as needed.
Here, the above-described memory device can be used as the circuit 1202. When supply of a power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 in the circuit 1202 is turned off continues to be input to a gate of the transistor 1209. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.
Shown here is an example in which the switch 1203 is a transistor 1213 having one conductivity type (e.g., an n-channel transistor) and the switch 1204 is a transistor 1214 having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor). A first terminal of the switch 1203 corresponds to one of a source and a drain of the transistor 1213, a second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and conduction or non-conduction between the first terminal and the second terminal of the switch 1203 (i.e., the on/off state of the transistor 1213) is selected by a control signal RD input to a gate of the transistor 1213. A first terminal of the switch 1204 corresponds to one of a source and a drain of the transistor 1214, a second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and conduction or non-conduction between the first terminal and the second terminal of the switch 1204 (i.e., the on/off state of the transistor 1214) is selected by the control signal RD input to a gate of the transistor 1214.
One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection portion is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a line which can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch 1203 (the one of the source and the drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214). The second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a line which can supply a power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207 are electrically connected to each other. Here, the connection portion is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1207 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1207 is electrically connected to the line which can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor 1208 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1208 can be supplied with the low power supply potential (e.g., GND) or the high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1208 is electrically connected to the line which can supply a low power supply potential (e.g., a GND line).
The capacitor 1207 and the capacitor 1208 are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized.
A control signal WE is input to the gate of the transistor 1209. As for each of the switch 1203 and the switch 1204, a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state.
A signal corresponding to data retained in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 51 illustrates an example in which a signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. The logic value of a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is inverted by the logic element 1206, and the inverted signal is input to the circuit 1201 through the circuit 1220.
In the example of FIG. 51, a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220; however, one embodiment of the present invention is not limited thereto. The signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without its logic value being inverted. For example, in the case where the circuit 1201 includes a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained, the signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) can be input to the node.
In FIG. 51, the transistors included in the memory element 1200 except the transistor 1209 can each be a transistor in which a channel is formed in a film formed using a semiconductor other than an oxide semiconductor or in the substrate 1190. For example, the transistor can be a transistor whose channel is formed in a silicon film or a silicon substrate. Alternatively, all the transistors in the memory element 1200 may be a transistor in which a channel is formed in an oxide semiconductor. Further alternatively, in the memory element 1200, a transistor in which a channel is formed in an oxide semiconductor may be included besides the transistor 1209, and a transistor in which a channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or in the substrate 1190 can be used for the rest of the transistors.
As the circuit 1201 in FIG. 51, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter or a clocked inverter can be used.
In a period during which the memory element 1200 is not supplied with the power supply voltage, the semiconductor device of one embodiment of the present invention can retain data stored in the circuit 1201 by the capacitor 1208 which is provided in the circuit 1202.
The off-state current of a transistor in which a channel is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when the transistor is used as the transistor 1209, a signal held in the capacitor 1208 is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element 1200. The memory element 1200 can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped.
Since the above-described memory element performs pre-charge operation with the switch 1203 and the switch 1204, the time required for the circuit 1201 to retain original data again after the supply of the power supply voltage is restarted can be shortened.
In the circuit 1202, a signal retained by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after supply of the power supply voltage to the memory element 1200 is restarted, the signal retained by the capacitor 1208 can be converted into the one corresponding to the state (the on state or the off state) of the transistor 1210 to be read from the circuit 1202. Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor 1208 varies to some degree.
By applying the above-described memory element 1200 to a memory device such as a register or a cache memory included in a processor, data in the memory device can be prevented from being lost owing to the stop of the supply of the power supply voltage. Furthermore, shortly after the supply of the power supply voltage is restarted, the memory device can be returned to the same state as that before the power supply is stopped. Therefore, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor, resulting in lower power consumption.
Although the memory element 1200 is used in a CPU, the memory element 1200 can also be used in an LSI such as a digital signal processor (DSP) or a custom LSI, and a radio frequency (RF) device. The memory element 1200 can also be used in an LSI such as a programmable logic circuit (or a programmable logic device (PLD)) including a field programmable gate array (FPGA) or a complex programmable logic device (CPLD).
The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.
Embodiment 9
In this embodiment, display devices each including the transistor or the like of one embodiment of the present invention will be described with reference to FIGS. 52A to 52C, FIGS. 53A and 53B, and FIGS. 54A and 54B.
<Configuration of Display Device>
Examples of a display element provided in the display device include a liquid crystal element (also referred to as a liquid crystal display element) and a light-emitting element (also referred to as a light-emitting display element). The light-emitting element includes, in its category, an element whose luminance is controlled by a current or voltage, and specifically includes, in its category, an inorganic electroluminescent (EL) element, an organic EL element, and the like. A display device including an EL element (EL display device) and a display device including a liquid crystal element (liquid crystal display device) are described below as examples of the display device.
Note that the display device described below includes in its category a panel in which a display element is sealed and a module in which an IC such as a controller is mounted on the panel.
The display device described below refers to an image display device or a light source (including a lighting device). The display device includes any of the following modules: a module provided with a connector such as an FPC or TCP; a module in which a printed wiring board is provided at the end of TCP; and a module in which an integrated circuit (IC) is mounted directly on a display element by a COG method.
FIGS. 52A to 52C illustrate an example of an EL display device of one embodiment of the present invention. FIG. 52A is a circuit diagram of a pixel in an EL display device. FIG. 52B is a plan view showing the whole of the EL display device. FIG. 52C is a cross-sectional view taken along part of dashed-dotted line M-N in FIG. 52B.
FIG. 52A illustrates an example of a circuit diagram of a pixel used in an EL display device.
Note that in this specification and the like, it might be possible for those skilled in the art to constitute one embodiment of the invention even when portions to which all the terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected are not specified. In other words, one embodiment of the invention can be clear even when connection portions are not specified. Furthermore, in the case where a connection portion is disclosed in this specification and the like, it can be determined that one embodiment of the invention in which a connection portion is not specified is disclosed in this specification and the like, in some cases. Particularly in the case where the number of portions to which a terminal is connected might be more than one, it is not necessary to specify the portions to which the terminal is connected. Therefore, it might be possible to constitute one embodiment of the invention by specifying only portions to which some of terminals of an active element (e.g., a transistor or a diode), a passive element (e.g., a capacitor or a resistor), or the like are connected.
Note that in this specification and the like, it might be possible for those skilled in the art to specify the invention when at least the connection portion of a circuit is specified. Alternatively, it might be possible for those skilled in the art to specify the invention when at least a function of a circuit is specified. In other words, when a function of a circuit is specified, one embodiment of the present invention can be clear. Furthermore, it can be determined that one embodiment of the present invention whose function is specified is disclosed in this specification and the like in some cases. Therefore, when a connection portion of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a function is not specified, and one embodiment of the invention can be constituted. Alternatively, when a function of a circuit is specified, the circuit is disclosed as one embodiment of the invention even when a connection portion is not specified, and one embodiment of the invention can be constituted.
The EL display device illustrated in FIG. 52A includes a switching element 743, a transistor 741, a capacitor 742, and a light-emitting element 719.
Note that FIG. 52A and the like each illustrate an example of a circuit structure; therefore, a transistor can be provided additionally. In contrast, for each node in FIG. 52A, it is possible not to provide an additional transistor, switch, passive element, or the like.
A gate of the transistor 741 is electrically connected to one terminal of the switching element 743 and one electrode of the capacitor 742. A source of the transistor 741 is electrically connected to the other electrode of the capacitor 742 and one electrode of the light-emitting element 719. A drain of the transistor 741 is supplied with a power supply potential VDD. The other terminal of the switching element 743 is electrically connected to a signal line 744. A constant potential is supplied to the other electrode of the light-emitting element 719. The constant potential is a ground potential GND or a potential lower than the ground potential GND.
It is preferable to use a transistor as the switching element 743. When the transistor is used as the switching element, the area of a pixel can be reduced, so that the EL display device can have high resolution. As the switching element 743, a transistor formed through the same step as the transistor 741 can be used, so that EL display devices can be manufactured with high productivity. Note that as the transistor 741 and/or the switching element 743, any of the above-described transistors can be used, for example.
FIG. 52B is a plan view of the EL display device. The EL display device includes a substrate 700, a substrate 750, a sealant 734, a driver circuit 735, a driver circuit 736, a pixel 737, and an FPC 732. The sealant 734 is provided between the substrate 700 and the substrate 750 so as to surround the pixel 737, the driver circuit 735, and the driver circuit 736. Note that the driver circuit 735 and/or the driver circuit 736 may be provided outside the sealant 734.
FIG. 52C is a cross-sectional view of the EL display device taken along part of dashed-dotted line M-N in FIG. 52B.
FIG. 52C illustrates the transistor 741 that includes an insulator 701 over the substrate 700, a conductor 702a over the insulator 701, an insulator 704 over the conductor 702a, an insulator 706a provided over the insulator 704 and overlapping with the conductor 702a, a semiconductor 706b over the insulator 706a, an insulator 706c over the semiconductor 706b, a region 707a and a region 707b provided in the insulator 706c and the semiconductor 706b, an insulator 712 over the insulator 706c, a conductor 714a over the insulator 712, and an insulator 716 over the insulator 706c and the conductor 714a. Note that the structure of the transistor 741 is just an example; the transistor 741 may have a structure different from that illustrated in FIG. 52C. For example, as the transistor 741, the transistor described in Embodiment 1 or 2 may be used as illustrated in FIG. 52C or alternatively, the transistor described in Embodiment 3 or 4 may be used as illustrated in FIG. 54A.
Thus, in the transistor 741 illustrated in FIG. 52C, the conductor 702a functions as a gate electrode, the insulator 712 functions as a gate insulator, the region 707a functions as a source, the region 707b functions as a drain, the insulator 712 functions as a gate insulator, and the conductor 714a functions as a gate electrode. Note that in some cases, electrical characteristics of the semiconductor 706b change if light enters the semiconductor 706b. To prevent this, it is preferable that one or more of the conductor 702a and the conductor 714a have a light-blocking property.
FIG. 52C illustrates the capacitor 742 that includes a conductor 702b over the insulator 701, the insulator 704 over the conductor 702b, the region 707a provided over the insulator 704 and overlapping with the conductor 702b, an insulator 711 over the region 707a, and a conductor 714b provided over the insulator 711 and overlapping with the region 707a. 
In the capacitor 742, each of the conductor 702b and the conductor 714b functions as one electrode, and the region 707a functions as the other electrode.
Thus, the capacitor 742 can be formed using a film of the transistor 741. The conductor 702a and the conductor 702b are preferably conductors of the same kind, in which case the conductor 702a and the conductor 702b can be formed through the same step. Furthermore, the conductor 714a and the conductor 714b are preferably conductors of the same kind, in which case the conductor 714a and the conductor 714b can be formed through the same step. The insulator 712 and the insulator 711 are preferably insulators of the same kind, in which case the insulator 712 and the insulator 711 can be formed through the same step.
The capacitor 742 illustrated in FIG. 52C has a large capacitance per area occupied by the capacitor. Therefore, the EL display device illustrated in FIG. 52C has high display quality.
An insulator 720 is provided over the transistor 741 and the capacitor 742. Here, the insulator 716 and the insulator 720 may have an opening portion reaching the region 707a that serves as the source of the transistor 741. A conductor 781 is provided over the insulator 720. The conductor 781 is electrically connected to the transistor 741 through the opening in the insulator 720.
A partition wall 784 having an opening reaching the conductor 781 is provided over the conductor 781. A light-emitting layer 782 in contact with the conductor 781 through the opening provided in the partition wall 784 is provided over the partition wall 784. A conductor 783 is provided over the light-emitting layer 782. A region where the conductor 781, the light-emitting layer 782, and the conductor 783 overlap with one another functions as the light-emitting element 719.
So far, examples of the EL display device are described. Next, an example of a liquid crystal display device is described.
FIG. 53A is a circuit diagram illustrating a configuration example of a pixel of a liquid crystal display device. A pixel shown in FIGS. 53A and 53B includes a transistor 751, a capacitor 752, and an element (liquid crystal element) 753 in which a space between a pair of electrodes is filled with a liquid crystal.
One of a source and a drain of the transistor 751 is electrically connected to a signal line 755, and a gate of the transistor 751 is electrically connected to a scan line 754.
One electrode of the capacitor 752 is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode of the capacitor 752 is electrically connected to a wiring to which a common potential is supplied.
One electrode of the liquid crystal element 753 is electrically connected to the other of the source and the drain of the transistor 751, and the other electrode of the liquid crystal element 753 is electrically connected to a wiring to which a common potential is supplied. The common potential supplied to the wiring electrically connected to the other electrode of the capacitor 752 may be different from that supplied to the other electrode of the liquid crystal element 753.
Note that the description of the liquid crystal display device is made on the assumption that the plan view of the liquid crystal display device is similar to that of the EL display device. FIG. 53B is a cross-sectional view of the liquid crystal display device taken along dashed-dotted line M-N in FIG. 52B. In FIG. 53B, the FPC 732 is connected to the wiring 733a via the terminal 731. Note that the wiring 733a may be formed using the same kind of conductor as the conductor of the transistor 751 or using the same kind of semiconductor as the semiconductor of the transistor 751.
For the transistor 751, the description of the transistor 741 is referred to. As in the case of the transistor 741, as the transistor 751, the transistor described in Embodiment 1 or 2 may be used as illustrated in FIG. 53B or alternatively, the transistor described in Embodiment 3 or 4 may be used as illustrated in FIG. 54B. For the capacitor 752, the description of the capacitor 742 is referred to. Note that the structure of the capacitor 752 in FIG. 53B corresponds to, but is not limited to, the structure of the capacitor 742 in FIG. 52C.
Note that in the case where an oxide semiconductor is used as the semiconductor of the transistor 751, the off-state current of the transistor 751 can be extremely small. Therefore, an electric charge held in the capacitor 752 is unlikely to leak, so that the voltage applied to the liquid crystal element 753 can be maintained for a long time. Accordingly, the transistor 751 can be kept off during a period in which moving images with few motions or a still image are/is displayed, whereby power for the operation of the transistor 751 can be saved in that period; accordingly a liquid crystal display device with low power consumption can be provided. Furthermore, the area occupied by the capacitor 752 can be reduced; thus, a liquid crystal display device with a high aperture ratio or a high-resolution liquid crystal display device can be provided.
An insulator 721 is provided over the transistor 751 and the capacitor 752. The insulator 721 has an opening reaching the transistor 751. A conductor 791 is provided over the insulator 721. The conductor 791 is electrically connected to the transistor 751 through the opening in the insulator 721.
An insulator 792 functioning as an alignment film is provided over the conductor 791. A liquid crystal layer 793 is provided over the insulator 792. An insulator 794 functioning as an alignment film is provided over the liquid crystal layer 793. A spacer 795 is provided over the insulator 794. A conductor 796 is provided over the spacer 795 and the insulator 794. A substrate 797 is provided over the conductor 796.
Note that the following methods can be employed for driving the liquid crystal: a twisted nematic (TN) mode, a super twisted nematic (STN) mode, an in-plane-switching (IPS) mode, a fringe field switching (FFS) mode, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an advanced super view (ASV) mode, an axially symmetric aligned microcell (ASM) mode, an optically compensated birefringence (OCB) mode, an electrically controlled birefringence (ECB) mode, an ferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, a polymer dispersed liquid crystal (PDLC) mode, a guest-host mode, and a blue phase mode. Note that the present invention is not limited to these examples, and various driving methods can be used.
Owing to the above-described structure, a display device including a capacitor occupying a small area, a display device with high display quality, or a high-resolution display device can be provided.
For example, in this specification and the like, a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element can employ various modes or can include various elements. For example, the display element, the display device, the light-emitting element, or the light-emitting device includes at least one of a light-emitting diode (LED) for white, red, green, blue, or the like, a transistor (a transistor that emits light depending on current), an electron emitter, a liquid crystal element, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using micro electro mechanical systems (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical-interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, and a display element including a carbon nanotube. Display media whose contrast, luminance, reflectivity, transmittance, or the like is changed by electrical or magnetic effect may be included.
Note that examples of display devices having EL elements include an EL display. Examples of a display device including an electron emitter include a field emission display (FED), an SED-type flat panel display (SED: surface-conduction electron-emitter display), and the like. Examples of display devices including liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of a display device including electronic ink, or an electrophoretic element include electronic paper. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes. Thus, the power consumption can be further reduced.
Note that in the case of using an LED, graphene or graphite may be provided under an electrode or a nitride semiconductor of the LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. As described above, provision of graphene or graphite enables easy formation of a nitride semiconductor thereover, such as an n-type GaN semiconductor including crystals. Furthermore, a p-type GaN semiconductor including crystals or the like can be provided thereover, and thus the LED can be formed. Note that an AlN layer may be provided between the n-type GaN semiconductor including crystals and graphene or graphite. The GaN semiconductors included in the LED may be formed by MOCVD. Note that when the graphene is provided, the GaN semiconductors included in the LED can also be formed by a sputtering method.
The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.
Embodiment 10
In this embodiment, electronic devices each including the transistor or the like of one embodiment of the present invention will be described.
<Electronic Device>
The semiconductor device of one embodiment of the present invention can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices which reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Other examples of electronic devices that can be equipped with the semiconductor device of one embodiment of the present invention are mobile phones, game machines including portable game consoles, portable data terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines. FIGS. 55A to 55F illustrate specific examples of these electronic devices.
FIG. 55A illustrates a portable game console including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, an operation key 907, a stylus 908, and the like. Although the portable game console in FIG. 55A has the two display portions 903 and 904, the number of display portions included in a portable game console is not limited to this.
FIG. 55B illustrates a portable data terminal including a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a joint 915, an operation key 916, and the like. The first display portion 913 is provided in the first housing 911, and the second display portion 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected to each other with the joint 915, and the angle between the first housing 911 and the second housing 912 can be changed with the joint 915. An image on the first display portion 913 may be switched in accordance with the angle at the joint 915 between the first housing 911 and the second housing 912. A display device with a position input function may be used as at least one of the first display portion 913 and the second display portion 914. Note that the position input function can be added by providing a touch panel in a display device. Alternatively, the position input function can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.
FIG. 55C illustrates a notebook personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.
FIG. 55D illustrates an electric refrigerator-freezer, which includes a housing 931, a door for a refrigerator 932, a door for a freezer 933, and the like.
FIG. 55E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a joint 946, and the like. The operation keys 944 and the lens 945 are provided for the first housing 941, and the display portion 943 is provided for the second housing 942. The first housing 941 and the second housing 942 are connected to each other with the joint 946, and the angle between the first housing 941 and the second housing 942 can be changed with the joint 946. Images displayed on the display portion 943 may be switched in accordance with the angle at the joint 946 between the first housing 941 and the second housing 942.
FIG. 55F illustrates a car including a car body 951, wheels 952, a dashboard 953, lights 954, and the like.
The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.
Embodiments of the present invention have been described in the above embodiments. Note that one embodiment of the present invention is not limited thereto. That is, various embodiments of the invention are described in this embodiment and the like, and one embodiment of the present invention is not limited to a particular embodiment. For example, an example in which a channel formation region, source and drain regions, and the like of a transistor include an oxide semiconductor is described as one embodiment of the present invention; however, one embodiment of the present invention is not limited to this example. Alternatively, depending on circumstances or conditions, various semiconductors may be included in various transistors, a channel formation region of a transistor, a source region or a drain region of a transistor, or the like of one embodiment of the present invention. Depending on circumstances or conditions, at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, and the like may be included in various transistors, a channel formation region of a transistor, a source region or a drain region of a transistor, or the like of one embodiment of the present invention. Alternatively, depending on circumstances or conditions, an oxide semiconductor is not necessarily included in various transistors, a channel formation region of a transistor, a source region or a drain region of a transistor, or the like of one embodiment of the present invention, for example.
This application is based on Japanese Patent Application serial no. 2015-060420 filed with Japan Patent Office on Mar. 24, 2015, Japanese Patent Application serial no. 2015-060421 filed with Japan Patent Office on Mar. 24, 2015, and Japanese Patent Application serial no. 2015-066943 filed with Japan Patent Office on Mar. 27, 2015, the entire contents of which are hereby incorporated by reference.

## Claims

1. A method for manufacturing a semiconductor device, comprising:
forming an oxide semiconductor over a substrate;
forming a first insulator over the oxide semiconductor;
forming a first conductor overlapping with the oxide semiconductor with the first insulator interposed therebetween;
after forming the first conductor, implanting an ion into the oxide semiconductor from the first conductor side; and
after implanting the ion, implanting hydrogen into the oxide semiconductor from the first conductor side,
wherein the ion is any of a helium ion, a neon ion, an argon ion, a krypton ion, and a xenon ion.

2. The method according to claim 1, wherein an oxygen vacancy is formed in the oxide semiconductor by implanting the ion.

3. The method according to claim 1, wherein implanting the ion comprises:
a first step of implanting the ion at an incident angle of greater than or equal to 10° and less than or equal to 60° with respect to a normal of a surface of the substrate; and
a second step of implanting the ion at an incident angle of greater than or equal to −60° and less than or equal to −10° with respect to the normal of the surface of the substrate.

4. The method according to claim 1, comprising:
forming a second insulator comprising an opening, over the substrate; and
forming a second conductor in the opening,
wherein the oxide semiconductor is formed over the second insulator and the second conductor, and
wherein the first conductor and the second conductor are overlapped with each other with the oxide semiconductor interposed therebetween.

5. The method according to claim 1, wherein the first conductor is a gate electrode.

6. The method according to claim 1, wherein part of the oxide semiconductor is exposed from the first insulator and the first conductor in implanting the ion into the oxide semiconductor.

7. A method for manufacturing a semiconductor device, comprising:
forming an oxide semiconductor over a substrate;
forming a first insulator over the oxide semiconductor;
forming a first conductor overlapping with the oxide semiconductor with the first insulator interposed therebetween;
after forming the first conductor, implanting an ion into the oxide semiconductor from the first conductor side;
after implanting the ion, implanting hydrogen into the oxide semiconductor from the first conductor side; and
after implanting hydrogen, performing a heat treatment on the oxide semiconductor.

8. The method according to claim 7, wherein an oxygen vacancy is formed in the oxide semiconductor by implanting the ion.

9. The method according to claim 7, wherein the ion is any of a helium ion, a neon ion, an argon ion, a krypton ion, and a xenon ion.

10. The method according to claim 7, wherein implanting the ion comprises:
a first step of implanting the ion at an incident angle of greater than or equal to 10° and less than or equal to 60° with respect to a normal of a surface of the substrate; and
a second step of implanting the ion at an incident angle of greater than or equal to −60° and less than or equal to −10° with respect to the normal of the surface of the substrate.

11. The method according to claim 7, comprising:
forming a second insulator comprising an opening, over the substrate; and
forming a second conductor in the opening,
wherein the oxide semiconductor is formed over the second insulator and the second conductor, and
wherein the first conductor and the second conductor are overlapped with each other with the oxide semiconductor interposed therebetween.

12. The method according to claim 7, wherein the first conductor is a gate electrode.

13. The method according to claim 7, wherein part of the oxide semiconductor is exposed from the first insulator and the first conductor in implanting the ion into the oxide semiconductor.

14. A method for manufacturing a semiconductor device, comprising:
forming an oxide semiconductor over a substrate;
forming a first insulator over the oxide semiconductor;
forming a first conductor overlapping with the oxide semiconductor with the first insulator interposed therebetween;
after forming the first conductor, implanting an ion into the oxide semiconductor from the first conductor side;
after implanting the ion, forming a second insulator on a side surface of the first conductor so that part of the oxide semiconductor is not overlapped with the second insulator; and
after forming the second insulator, implanting hydrogen into the oxide semiconductor from the first conductor side.

15. The method according to claim 14, wherein an oxygen vacancy is formed in the oxide semiconductor by implanting the ion.

16. The method according to claim 14, wherein the ion is any of a helium ion, a neon ion, an argon ion, a krypton ion, and a xenon ion.

17. The method according to claim 14, wherein implanting the ion comprises:
a first step of implanting the ion at an incident angle of greater than or equal to 10° and less than or equal to 60° with respect to a normal of a surface of the substrate; and
a second step of implanting the ion at an incident angle of greater than or equal to −60° and less than or equal to −10° with respect to the normal of the surface of the substrate.

18. The method according to claim 14, comprising:
forming a third insulator comprising an opening, over the substrate; and
forming a second conductor in the opening,
wherein the oxide semiconductor is formed over the third insulator and the second conductor, and
wherein the first conductor and the second conductor are overlapped with each other with the oxide semiconductor interposed therebetween.

19. The method according to claim 14, wherein the first conductor is a gate electrode.

20. The method according to claim 14, wherein part of the oxide semiconductor is exposed from the first insulator and the first conductor in implanting the ion into the oxide semiconductor.