# Patent

## Title
Slew-rate enhanced energy efficient source follower circuit

## Abstract

This invention pertains to a source follower circuit suitable for receiving and buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch. The source follower circuit employs a slew enhancement circuit which enables the source follower to have fast settling for both high-to-low and low-to-high transitions.

## Background
GOVERNMENT LICENSE RIGHTS
This invention was made with Government support. The Government has certain rights in this invention.


BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to source follower circuits, and more particularly to circuitry for enhancing the slew rate of a source follower circuit used for buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch.
Description of the Related Art
Transistor source follower circuits are commonly used as simple voltage buffers in applications that do not require very high linearity. The DC characteristics of source follower circuits are such that the buffered output voltage tracks the input voltage except for a voltage shift equal to the gate-to-source voltage of the source follower transistor. The advantages of source follower circuits as buffers are low device count, low noise, unconditional stability and a relatively large signal swing. However, the transient response of source follower circuits suffers from an asymmetry in the settling speed. For example, an NMOS source follower has fast settling for a low-to-high transition and slow settling for a high-to-low transition; in the latter case the settling time is limited by the available bias current. This is explained in more detail in the following paragraph.
Consider the schematic and timing diagrams shown in FIGS. 1A and 1B, respectively. In FIG. 1A, a source follower circuit is formed from an NMOS input FET M1 which is connected in series with an NMOS bias FET M2 as shown. An input voltage to be buffered (Vin) is applied to the gate of M1, a bias voltage (Vbias) is applied to the gate of M2 (causing it to conduct a current Ibias), and the output (Vout) of the source follower circuit is provided at a junction 10 of M1 and M2. In this example, Vout is sampled on a sampling capacitor Cs when switch SAMPLE is closed; the voltage on Cs is referred to as Vs.
The operation of the circuitry is shown in FIG. 1B. Within every sampling period Δt, switch SAMPLE is closed for time Δtsample while the input voltage is periodically switched between levels Vin,min and Vin,max when switch SAMPLE is open. Each time switch SAMPLE is closed, the voltage Vs on the sampling capacitor must settle from the previous sampled value to the new one. The settled voltage output levels corresponding to Vin,min and Vin,max sampled on Cs are Vs,min and Vs,max. If Vs is at a minimum voltage Vs,min, then when switch SAMPLE closes Vs increases from voltage Vs,min to a voltage Vs,max. This illustrates the relatively fast settling for a low-to-high transition. Note that the transient current pulling Vs from Vs,min to Vs,max is a function of the drive strength of M1 and can be substantially higher than the bias current Ibias. If Vs is at maximum voltage Vs,max, then when switch SAMPLE closes, Vs decreases from Vs,max to Vs,min. The settling for a high-to-low transition is significantly slower because the transient current pulling Vs from Vs,max to Vs,min (known also as the slew current Islew) is limited by the bias current Ibias provided by M2. Since Islew=Ibias=const, Vs(t) decreases linearly at a rate known as the slew rate and given by Islew/Cs. This portion of the settling time is known as slewing time. If the slewing time is assumed to be, for example, 80% of the available settling time Δtsample, then the required source follower bias current is:




  
    
      
        
          I
          bias
        
        =
        
          
            I
            slew
          
          =
          
            
              
                
                  C
                  s
                
                ⁡
                
                  (
                  
                    
                      V
                      
                        s
                        ,
                        max
                      
                    
                    -
                    
                      V
                      
                        s
                        ,
                        min
                      
                    
                  
                  )
                
              
              
                0.8
                ⁢
                Δ
                ⁢
                
                  
                
                ⁢
                
                  t
                  sample
                
              
            
            .
          
        
      
    
    
      
        (
        1
        )
      
    
  




Equation (1) shows that the bias current must be sized to achieve settling within Δtsample for the largest expected voltage swing Vs,max−Vs,min. Given randomly distributed input voltages, the signal swing will be less than that on average, but the bias current must be set high enough to satisfy the worst case. This highlights the energy inefficiency of the classic source follower circuit. It can be shown that the static and dynamic energies (E) consumed from the supply per period Δt by the source follower circuit of FIG. 1A are as follows:





  
    
      
        
          
            Static
            ⁢
            
              
            
            ⁢
            E
          
          =
          
            
              
                (
                
                  I
                  bias
                
                )
              
              ⁢
              
                (
                
                  V
                  dd
                
                )
              
              ⁢
              
                (
                
                  Δ
                  ⁢
                  
                    
                  
                  ⁢
                  
                    t
                    sample
                  
                
                )
              
            
            =
            
              
                
                  
                    C
                    S
                  
                  ⁡
                  
                    (
                    
                      
                        V
                        
                          s
                          ,
                          max
                        
                      
                      -
                      
                        V
                        
                          s
                          ,
                          min
                        
                      
                    
                    )
                  
                
                ⁢
                
                  V
                  dd
                
              
              0.8
            
          
        
        ;
      
    
    
      
        (
        
          2
          ⁢
          a
        
        )
      
    
  




Dynamic E=0(on average).  (2b)

The high-to-low transition can be improved by ‘precharging’ sampling capacitor Cs to ground before the SAMPLE switch closes; this is illustrated in FIGS. 2A and 2B. The precharging is accomplished with a switch CLR connected across capacitor Cs. As shown in FIG. 2B, switch CLR is closed —and thus Cs is precharged (or reset) to ground —before switch SAMPLE is closed. When so arranged, Cs does not have to be discharged by the source follower bias transistor M2 when Vin falls, thereby eliminating the slew-limited settling and the slow high-to-low transition exhibited by the circuit of FIG. 1A. The static and dynamic energies (E) consumed from the supply per period Δt by the source follower circuit of FIG. 2A are as follows:

Static E=(Ibias)(Vdd)(Δtsample);  (3a)

Dynamic E=CsVsVdd  (3b)

While at first glance the static energy given by (3a) appears to be the same as (2a), it is in fact significantly lower because Ibias no longer needs to equal the slew current defined by equation (1) and is in fact much smaller (typically set so that the transconductance of M1 achieves the small-signal time constant for the targeted settling time).

The dynamic energy term given by equation (3b) is proportional to the sampled voltage on the capacitor Vs. For the largest input voltage (and hence largest Vs) the static and dynamic energy consumed by the circuit of FIG. 2A approaches that of the circuit of FIG. 1A. However, for randomly distributed input voltages between ground and the largest input voltage, the circuit of FIG. 2A is more energy efficient. Nevertheless, it still has the drawback that dynamic energy is drawn from the supply even if there is no change in Vin from sample to sample.
SUMMARY OF THE INVENTION
An energy efficient source follower circuit is presented which enables faster settling on both high-to-low and low-to-high transitions, and is particularly well-suited for driving sampled capacitive loads.
The present source follower circuit is suitable for receiving and buffering an input voltage (Vin) and providing the buffered input voltage to a sampling capacitor via a sampling switch; the voltage stored on the sampling capacitor is referred to herein as Vs. The source follower circuit comprises:

    
    
        an output node at which an output Vout of the source follower circuit is provided;
        a slew FET having its drain connected to the output node and its source connected to a fixed potential such that, when on, the FET accelerates the slew rate of Vout for one of a high-to-low or low-to-high transition;
        a slew capacitor Cslew connected between the output node and the slew FET's gate; and
        a SET switch connected between the slew FET's gate and a voltage Vset.
    
    


The source follower circuit is arranged such that:

    
    
        when the SET switch is closed and the sampling switch is open, the voltage (Vg) at the slew FET's gate is equal to Vset, the slew FET is substantially turned off, and Vout settles to a new value Vout_new which varies with Vin. When the SET switch opens and said sampling switch closes, Vout transitions to the voltage (Vs_prev) previously stored on the sampling capacitor, and Vg changes by a value ΔVg which is proportional to (Vs_prev−Vout_new).
    
    


When so arranged, if the slew FET is an NMOS FET and ΔVg>0, the slew FET turns on and pulls Vs down to Vout_new, and if the slew FET is a PMOS FET and ΔVg<0, the slew FET turns on and pulls Vs up to Vout_new.
The present source follower circuit preferably includes an input FET having its gate connected to input voltage Vin and its source connected to output node Vout. A bias FET is preferably connected in series with the input FET, with the output node being at the junction of the input and bias FETs. This arrangement enables fast settling on both high-to-low and low-to-high transitions.
Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a schematic diagram of a known source follower circuit.
FIG. 1B is a timing diagram which illustrates the operation of the source follower circuit in FIG. 1A.
FIG. 2A is a schematic diagram of another known source follower circuit.
FIG. 2B is a timing diagram which illustrates the operation of the source follower circuit in FIG. 2A.
FIG. 3A is a schematic diagram of an NMOS embodiment of a source follower circuit in accordance with the present invention.
FIG. 3B is a timing diagram which illustrates the operation of the source follower circuit in FIG. 3A.
FIG. 4A is a schematic diagram of a PMOS embodiment of a source follower circuit in accordance with the present invention.
FIG. 4B is a timing diagram which illustrates the operation of the source follower circuit in FIG. 4A.
FIG. 5A is a schematic diagram of one possible embodiment of a Vset generation circuit for use with an NMOS source follower circuit per the present invention.
FIG. 5B is a schematic diagram of one possible embodiment of a Vset generation circuit for use with a PMOS source follower circuit per the present invention.
FIG. 6 is a table comparing the simulated power consumption for a source follower circuit in accordance with the present invention with those of prior art source follower circuits.



DETAILED DESCRIPTION OF THE INVENTION
The present source follower circuit has a general applicability, but is particularly well-suited for receiving and buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch. One possible embodiment is shown in FIG. 3A. The source follower circuit preferably includes an NMOS input FET (M1) having its gate connected to input voltage Vin, its drain connected to a supply voltage Vdd, and its source connected to output node 100, and an NMOS bias FET (M2) having its gate connected to a bias voltage Vbias, its drain connected to output node 100, and its source connected to a circuit common point. M1 and M2 are thus connected in series, with output node 100 being the junction of M1 and M2. The circuit is arranged to receive and buffer an input voltage Vin, and provide the buffered voltage Vout at an output node 100. In this exemplary embodiment, voltage Vout is provided to a sampling capacitor Cs via a sampling switch SAMPLE, with the voltage stored on the sampling capacitor being referred to herein as Vs.
Both NMOS and PMOS source follower circuits are described herein. The source follower circuit includes a “slew enhancement circuit” 102, which operates to enhance the slew rate of low-to-high transitions (for a PMOS source follower) or high-to-low transitions (for an NMOS source follower) of buffered voltage Vout. Circuit 102 comprises a slew FET Mslew-n having its drain connected to output node 100 and its source connected to a fixed potential (such as ground) such that, when on, the slew FET accelerates the slew rate of Vout for a high-to-low transition. A slew capacitor Cslew is connected between output node 100 and the gate of Mslew-n, and a SET switch is connected between the gate of Mslew-n and a voltage Vset.
A timing diagram illustrating the operation of the circuit shown in FIG. 3A is shown in FIG. 3B. Switches SAMPLE and SET are operated with corresponding control signals SAMPLE and SET, respectively. In this example, the switches are closed when their corresponding control signal goes high; it is understood that the switches might also be arranged to operate with control signals having the opposite polarity to those shown in FIG. 3B. Signals SAMPLE and SET both have the same period Δt. Signal SAMPLE is high for a sampling time Δtsample, which typically takes most of the period Δt. Signal SET is high while signal SAMPLE is low, i.e. the two signals are non-overlapping. It is also assumed that for every sampling period the input voltage Vin transitions to the new value at the onset of the SET pulse. Let us first consider the circuit operation when switch SET is closed and switch SAMPLE is open. Under these conditions, the voltage Vg at the gate of FET equal Mslew-n is to Vset. Vset is selected to be slightly below Vt, where Vt is the FET turn-on threshold voltage, such that when Vg=Vset, Mslew-g is substantially turned off. Meanwhile, the input voltage Vin transitions to a new value Vin_new. Since switch SAMPLE is open and the source follower is not loaded by the sampling capacitor Cs, the output voltage Vout quickly settles to a new value Vout_new corresponding to Vin,new while switch SET is still closed.
Next, switch SET opens and switch SAMPLE closes. This connects node 100 to Cs, forcing Vout to jump from Vout_new to the voltage Vs_prev previously stored on C5. The slew capacitor Cslew couples this voltage transition to the gate of FET Mslew-n so that the voltage Vg at the gate of Mslew-n changes by a value ΔVg which is proportional to (Vs_prev−Vout_new). Specifically,




  
    
      
        
          
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              g
            
          
          =
          
            
              
                C
                slew
              
              
                
                  C
                  slew
                
                +
                
                  C
                  g
                
              
            
            ⁢
            
              
                C
                s
              
              
                
                  C
                  s
                
                +
                
                  C
                  eq
                
              
            
            ⁢
            
              (
              
                
                  V
                  
                    s
                    ⁢
                    _
                    ⁢
                    prev
                  
                
                +
                
                  V
                  
                    out
                    ⁢
                    _
                    ⁢
                    new
                  
                
              
              )
            
          
        
        ,
      
    
    
      
        (
        
          4
          ⁢
          a
        
        )
      
    
  




where





  
    
      
        
          C
          eq
        
        =
        
          
            C
            
              p
              ,
              out
            
          
          +
          
            
              
                
                  C
                  slew
                
                ⁢
                
                  C
                  g
                
              
              
                
                  C
                  slew
                
                +
                
                  C
                  g
                
              
            
            .
          
        
      
    
    
      
        
          (
          
            4
            ⁢
            b
          
          )
        
        .
      
    
  




Capacitor Cg is optional. Cg may be an actual capacitor connected between the gate of Mslew-n and a fixed potential such as ground (as illustrated in FIG. 3A), or may be the gate-to-source capacitance of Mslew-n. Cp,out is the parasitic capacitance at Vout (output node 100). Typically Ceq<<Cs and equation (4a) can be approximated by:





  
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          
            V
            g
          
        
        ≅
        
          
            
              C
              slew
            
            
              
                C
                slew
              
              +
              
                C
                g
              
            
          
          ⁢
          
            
              (
              
                
                  V
                  
                    s
                    ⁢
                    _
                    ⁢
                    prev
                  
                
                +
                
                  V
                  
                    out
                    ⁢
                    _
                    ⁢
                    new
                  
                
              
              )
            
            .
          
        
      
    
    
      
        (
        5
        )
      
    
  




If Vin has transitioned from high to low, then Vs_prev>Vout_new and ΔVg>0. Consequently, Mslew-n turns on and provides the current needed to pull the sampling capacitor Cs from Vs_prev down to Vout_new. This serves to increase the slew rate and speed up the settling for a high-to-low transition of Vout, as well as Vs.

On the other hand, if Vin has transitioned from low to high, then Vs_prev<Vout_new and ΔVg<0. In this case Mslew-n remains off and plays no role. However, the gate-to-source voltage of the input FET M1 increases, it turns on harder and provides the current needed to pull the sampling capacitor Cs from Vs_prev up to Vout_new. Thus, the slew-enhanced NMOS source follower circuit exhibits fast settling on both high-to-low and low-to-high transitions. This is to be contrasted with the conventional source follower which, for the same bias current, exhibits equally fast settling only in one direction.
The circuit shown in FIG. 3A illustrates the application of slew enhancement to an NMOS source follower according to the present invention. It is also possible to apply slew enhancement to a PMOS source follower; one possible embodiment is shown in FIG. 4A, with a corresponding timing diagram shown in FIG. 4B. The source follower circuit preferably includes a PMOS input FET (M4) having its gate connected to input voltage Vin, its drain connected to a circuit common point, and its source connected to output node 110, and a PMOS bias FET (M3) having its gate connected to a bias voltage Vbias, its drain connected to output node 110, and its source connected to supply voltage Vdd. M3 and M4 are thus connected in series, with output node 110 being the junction of M3 and M4. As before, voltage Vout is provided to a sampling capacitor Cs via a sampling switch SAMPLE, with the voltage stored on the sampling capacitor being referred to as Vs. A slew enhancement circuit 112 may be realized as shown, with a slew FET Mslew-p, switch SET and slew capacitor Cslew, preferably coupled to an output node 110.
Signals SAMPLE, SET and Vin in FIG. 4B are defined identically as in FIG. 3B. Let us first consider the circuit operation when switch SET is closed and switch SAMPLE is open. Under these conditions, the voltage Vg at the gate of FET Mslew-p is equal to Vset. Vset is selected to be slightly above (Vdd−Vt), where Vt is the FET turn-on threshold voltage, such that when Vg=Vset, Mslew-p is substantially turned off. Meanwhile, the input voltage Vin transitions to a new value Vin_new. Since switch SAMPLE is open and the source follower is not loaded by the sampling capacitor Cs, the output voltage Vout quickly settles to a new value Vout_new corresponding to Vin,new while switch SET is still closed.
When switch SET opens and switch SAMPLE closes, output node 110 is connected to Cs, such that Vout transitions to the voltage Vs_prev previously stored on Cs. The voltage Vg at the gate of Mslew-p, changes by a value ΔVg which is given by equation (4a) or approximately by equation (5). If Vin has transitioned from low to high, then Vs_prev<Vout_new and ΔVg<0. Consequently, Mslew-p turns on and provides the current needed to pull the sampling capacitor Cs from Vs_prev up to Vout_new. This serves to increase the slew rate and speed up the settling for a low-to-high transition of Vout, as well as Vs. On the other hand, if Vin has transitioned from high to low, then Vs_prev>Vout_new and ΔVg>0. In this case Mslew-p remains off and plays no role. However, the gate-to-source voltage of the input FET M4 increases, it turns on harder and provides the current needed to pull the sampling capacitor Cs from Vs_prev down to Vout_new. Thus, the slew-enhanced PMOS source follower circuit exhibits fast settling on both high-to-low and low-to-high transitions.
As noted above, Vset is selected to be slightly below Vt when the slew FET is NMOS, and selected to be slightly above (Vdd−Vt) when the slew FET is PMOS. Possible embodiments of circuits capable of generating Vset for NMOS and PMOS source follower circuits are shown in FIGS. 5A and 5B, respectively. In FIG. 5A, the generation circuit preferably comprises a diode-connected NMOS FET M5, driven with a bias current Ibias. If Ibias is small and M5's width-to-length (W/L) ratio is large, Vset<Vt. After the SET switch (preferably implemented with an NMOS FET) opens, clock feedthrough and switch charge injection may cause a small voltage error −ΔV, so that Vg=Vset−ΔV.
In FIG. 5B, the generation circuit preferably comprises a diode-connected PMOS FET M6, driven with a bias current Ibias. If Ibias is small and M6's width-to-length (W/L) ratio is large, Vset>(Vdd−Vt), where Vdd is the circuit supply voltage. After the SET switch (preferably implemented with a PMOS FET) opens, switch clock feedthrough and charge injection may cause a small voltage error +ΔV, so that Vg=Vset+ΔV.
Preferred embodiments of the SET switches shown in FIGS. 3A and 4A are also shown in the Vset generation circuits, with the SET switch in FIG. 5A implemented with an NMOS FET M7, and the SET switch in FIG. 5B implemented with an PMOS FET M8.
Below are some additional notes on the operation of the slew-enhanced source follower.
Capacitance Cslew can be much smaller than Cs. Typical values could be, for example, Cslew=20 fF and Cs=1 to 10 pF. As noted above, capacitor Cg may be optional; if used, it provides attenuation to ΔVg.
Vset+ΔVg when ΔVg<0 should not fall below −Vt for an NMOS embodiment of the present source follower circuit. Similarly, VsetΔVg when ΔVg>0 should not rise above Vdd+Vt for a PMOS embodiment. Capacitances Cslew and Cg can be ratioed to ensure that this is true for the largest signal swing. For example, assuming that Vset≈Vt for the NMOS implementation and Vset≈Vdd−Vt for the PMOS implementation, using equation (5) we can write:




  
    
      
        
          
            
            
              Δ
              ⁢
              
                
              
              ⁢
              
                V
                g
              
            
            
          
          ≅
          
            
              
                C
                slew
              
              
                
                  C
                  slew
                
                +
                
                  C
                  g
                
              
            
            ⁢
            
              (
              
                
                  V
                  
                    s
                    ⁢
                    _
                    ⁢
                    max
                  
                
                -
                
                  V
                  
                    s
                    ⁢
                    _
                    ⁢
                    min
                  
                
              
              )
            
          
          ≤
          
            2
            ⁢
            
              
            
            ⁢
            
              V
              t
            
          
        
        ,
      
    
    
      
        (
        6
        )
      
    
  




where Vs,min and Vs,max are respectively the minimum and maximum sampled voltages on capacitor Cs. Solving for Cg/Cslew we obtain:





  
    
      
        
          
            C
            g
          
          
            C
            slew
          
        
        ≥
        
          
            
              
                V
                
                  s
                  ,
                  max
                
              
              -
              
                V
                
                  s
                  ,
                  min
                
              
            
            
              2
              ⁢
              
                V
                t
              
            
          
          -
          1.
        
      
    
    
      
        (
        7
        )
      
    
  




Referring to FIG. 3A, FETs M1 and M2 are preferably in close proximity to slew enhancement circuit 102, to minimize the parasitic capacitance Cp,out at Vout (output node 100). This is because as Cp,out increases, Ceq increases (equation (4b)) and ΔVg decreases (equation (4a)), thus reducing the effectiveness of the slew enhancement. Similarly, for the PMOS embodiment in FIG. 4A, FETs M3 and M4 are preferably in close proximity to slew enhancement circuit 112.
A source follower circuit as described herein provides numerous advantages in comparison to prior art circuits. While the conventional NMOS source follower of FIG. 1A has fast settling only on low-to-high transitions, the slew-enhanced NMOS source follower of FIG. 3A operated at a similar bias current achieves fast settling on both low-to-high and high-to-low transitions. If the source follower of FIG. 1A is to have similarly fast high-to-low settling then its bias current needs to be increased significantly to provide the needed slew current but it will then be much less energy efficient than the slew-enhanced source follower. The same conclusions are valid if a conventional PMOS source follower is compared with the slew-enhanced source follower of FIG. 4A. When compared to the source follower with precharge of FIG. 2A, the slew-enhanced source follower circuit shows better energy efficiency since the charge on the sampling capacitor is not reset every sampling period. In fact, dynamic current is drawn from the supply only when needed and as much as needed for the sampling capacitor to settle to the new voltage. Consequently, the slew-enhanced source follower operates with a lower average dynamic current than the source follower with precharge of FIG. 2A. This leads to reduced power dissipation, as well as less substrate, ground or supply noise. The power savings provided by the present source follower circuit can be significant, particularly when used with, for example, multiple parallel circuits (for example, pixel or column source followers in image sensors), or when driving relatively large capacitive loads (for example, on-chip or output drivers). The improvement in energy efficiency will be discussed in more detail next.
FIG. 6 is a table comparing simulated typical power consumption values for the present slew-enhanced source follower circuit (rightmost column) and the source follower circuits depicted in prior art FIGS. 1A (leftmost column) and 2A (center column). Though bias current is slightly higher for the present circuit in comparison with the circuit of FIG. 2A, the values for average Vdd current and, consequently, average power, are considerably lower for the present circuit. The last row shows that the total power savings are significant when each of the three circuits is used in a 4096×4096 pixel array. The following assumptions were made when creating FIG. 6:

    
    
        Spectre simulation over 1000 sampling periods;
        the input Vin for each sample is random and uniformly distributed over the range from 0 to 2.0 V;
        the supply voltage Vdd=3.3 V;
        the sampling capacitor Cs=1 pF;
        the sampling time Δtsample=11 μs and the sampling period Δt=11.5 μs;
        a PMOS source follower is used.
        when reporting the average power in a 4096×4096 array, it is assumed that the source follower is powered up for the sampling period Δt=11.5 is and is powered down for the rest of the frame time of 1 ms.
    
    


The present source follower circuit can be used in numerous applications. In addition to those referenced above, examples include in-pixel source follower buffer circuits (for global shutter pixels, for example), source follower signal buffering (on-chip or off-chip load), and reference voltage buffering.
While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.

## Claims

1. A source follower circuit suitable for receiving and buffering an input voltage (Vin) and providing said buffered input voltage to a sampling capacitor via a sampling switch, the voltage stored on said sampling capacitor being Vs, comprising:
an output node at which an output Vout of said source follower circuit is provided;
a slew FET having its drain connected to said output node and its source connected to a fixed potential such that, when on, said FET accelerates the slew rate of Vout for one of a high-to-low or low-to-high transition;
a slew capacitor Cslew connected between said output node and said slew FET's gate; and
a SET switch connected between said slew FET's gate and a voltage Vset;
said source follower circuit arranged such that:
when said SET switch is closed and said sampling switch is open,
the voltage (Vg) at said slew FET's gate is equal to Vset and the slew FET is substantially turned off; and
Vout settles to a new value Vout_new which varies with Vin;

and when said SET switch opens and said sampling switch closes,
Vout transitions to the voltage (Vs_prev) previously stored on said sampling capacitor; and
Vg changes by a value ΔVg which is proportional to (Vs_prev−Vout_new); and
if said slew FET is an NMOS FET and ΔVg>0, said slew FET turns on and pulls Vs down to Vout_new, and
if said slew FET is a PMOS FET and ΔVg<0, said slew FET turns on and pulls Vs up to Vout_new.

2. The source follower circuit of claim 1, wherein said circuit further comprises an input FET having its gate connected to input voltage Vin and its source connected to said output node Vout.

3. The source follower circuit of claim 2, further comprising a bias FET connected in series with said input FET, said output node being at the junction of said input and bias FETs.

4. The source follower circuit of claim 3, wherein said input and bias FETs and said slew FET are NMOS FETs and the source of said bias FET is connected to said fixed potential, the fixed potential to which said slew FET and said bias FET are connected being a circuit common point.

5. The source follower circuit of claim 3, wherein said input and bias FETs and said slew FET are PMOS FETs and the source of said bias FET is connected to said fixed potential, the fixed potential to which said slew FET and said bias FET are connected being a circuit supply voltage Vdd.

6. The source follower circuit of claim 3, wherein the gate of said bias FET is connected to a fixed bias voltage Vbias.

7. The source follower circuit of claim 1, further comprising a gate capacitance Cg between the gate of said slew FET and a second fixed potential, such that




  
    
      Δ
      ⁢
      
        
      
      ⁢
      
        V
        g
      
    
    =
    
      
        
          C
          s
        
        
          
            C
            s
          
          +
          
            C
            eq
          
        
      
      ⁢
      
        
          C
          slew
        
        
          
            C
            slew
          
          +
          
            C
            g
          
        
      
      ⁢
      
        (
        
          
            V
            
              s
              ⁢
              _
              ⁢
              prev
            
          
          -
          
            V
            
              out
              ⁢
              _
              ⁢
              new
            
          
        
        )
      
    
  
  ,




where




  
    C
    eq
  
  =
  
    
      C
      
        p
        ,
        out
      
    
    +
    
      
        
          C
          slew
        
        ⁢
        
          C
          g
        
      
      
        
          C
          slew
        
        +
        
          C
          g
        
      
    
  




and Cp,out is the capacitance on said output node.

8. The source follower circuit of claim 7, wherein said second fixed potential is a circuit common point if said slew FET is an NMOS FET, and said second fixed potential is a circuit supply voltage Vdd if said slew FET is a PMOS FET.

9. The source follower circuit of claim 7, wherein said gate capacitance Cg is the gate-to-source capacitance of said slew FET.

10. The source follower circuit of claim 1, further comprising a Vset generation circuit, said Vset generation circuit comprising a diode-connected NMOS FET biased such that 0<Vset<Vt when said slew FET is an NMOS FET, or comprising a diode-connected PMOS FET biased such that (Vdd−Vt)<Vset<Vdd when said slew FET is a PMOS FET, where Vt is the FET turn-on threshold voltage and Vdd is a circuit supply voltage.

11. A source follower circuit suitable for receiving and buffering an input voltage (Vin) and providing said buffered input voltage to a sampling capacitor via a sampling switch, the voltage stored on said sampling capacitor being Vs comprising:
an input stage, comprising:
an input NMOS FET connected to receive said input voltage (Vin); and
a bias NMOS FET connected in series with said input NMOS FET, the gate of said bias FET connected to a fixed bias voltage Vbias;

an output node at the junction of said input and bias NMOS FETs at which an output Vout of said source follower circuit is provided;
a slew NMOS FET having its drain connected to said output node and its source connected to a circuit common point such that, when on, said slew NMOS FET accelerates the slew rate of Vout for a high-to-low transition;
a slew capacitor Cslew connected between said output node and said slew NMOS FET's gate; and
a SET switch connected between said slew NMOS FET's gate and a voltage Vset;
said source follower circuit arranged such that:
when said SET switch is closed and said sampling switch is open,
the voltage (Vg) at said slew NMOS FET's gate is equal to Vset and the slew NMOS FET is substantially turned off; and
Vout settles to a new value Vout_new which varies with Vin;

and when said SET switch opens and said sampling switch closes,
Vout transitions to the voltage (Vs_prev) previously stored on said sampling capacitor; and
Vg changes by a value ΔVg which is proportional to (Vs_prev−Vout_new); and
when ΔVg>0, said slew NMOS FET turns on and pulls Vs down to Vout_new.

12. The source follower circuit of claim 11, further comprising a Vset generation circuit, said Vset generation circuit comprising a diode-connected NMOS FET biased such that 0<Vset<Vt where Vt is the NMOS FET turn-on threshold voltage.

13. A source follower circuit suitable for receiving and buffering an input voltage (Vin) and providing said buffered input voltage to a sampling capacitor via a sampling switch, the voltage stored on said sampling capacitor being Vs, comprising:
an input stage, comprising:
an input PMOS FET connected to receive said input voltage (Vin); and
a bias PMOS FET connected in series with said input PMOS FET, the gate of said bias FET connected to a fixed bias voltage Vbias;

an output node at the junction of said input and bias PMOS FETs at which an output Vout of said source follower circuit is provided;
a slew PMOS FET having its drain connected to said output node and its source connected to a circuit supply voltage Vdd such that, when on, said slew PMOS FET accelerates the slew rate of Vout for a low-to-high transition;
a slew capacitor Cslew connected between said output node and said slew PMOS FET's gate; and
a SET switch connected between said slew PMOS FET's gate and a voltage Vset;
said source follower circuit arranged such that:
when said SET switch is closed and said sampling switch is open,
the voltage (Vg) at said slew PMOS FET's gate is equal to Vset and the slew PMOS FET is substantially turned off; and
Vout settles to a new value Vout_new which varies with Vin;

and when said SET switch opens and said sampling switch closes,
Vout transitions to the voltage (Vs_prev) previously stored on said sampling capacitor; and
Vg changes by a value ΔVg which is proportional to (Vs_prev−Vout_new), and
when ΔVg<0, said slew PMOS FET turns on and pulls Vs up to Vout_new.

14. The source follower circuit of claim 13, further comprising a Vset generation circuit, said Vset generation circuit comprising a diode-connected PMOS FET biased such that (Vdd−Vt)<Vset<Vdd, where Vt is the PMOS FET turn-on threshold voltage and Vdd is a circuit supply voltage.