Exhibit 4.17

 

ANNEX 1

 

RDA TECHNOLOGIES LIMITED

 

CORESIGHT DK-A5

 

	
TLA Number
    	
 
    	
TLA-00547
    
	
Legal Counsel
    	
 
    	
AF
    
	
Annex Effective Date
    	
 
    	
9 February 2012
    


 

This Annex, when signed by both parties, shall form part of and be incorporated into the Technology Licence Agreement (“TLA”) between the parties (document reference as identified in the table above). Solely for the purposes of interpretation of the TLA with respect to this Annex, to the extent that the provisions contained in this Annex conflict with any of the provisions of the TLA the provisions contained in this Annex shall prevail over and shall supersede the conflicting provisions in the TLA.

 

1











 

SECTION 1 - ARM TECHNOLOGY

 

Key to Disclosure Rights

 

	
D
    	
 
    	
CONFIDENTIAL except disclosure   permitted to “Designers” in   accordance with Clause 3 of the TLA
    
	
M
    	
 
    	
CONFIDENTIAL except disclosure   permitted to “Manufacturers” in   accordance with Clause 3 of the TLA
    
	
T
    	
 
    	
CONFIDENTIAL except disclosure   permitted to “Test Houses” in accordance   with Clause 3 of the TLA
    
	
CS
    	
 
    	
CONFIDENTIAL except disclosure   permitted to “Customers” in   accordance with Clause 3 of the TLA
    
	
N
    	
 
    	
NON-CONFIDENTIAL but disclosure may be   subject to license restrictions
    


 

CoreSight Design Kit -Cortex-A5- Per Use

 

PART A TECHNICAL REFERENCE MANUAL

 

TRM means: Technical Reference Manual

 

Section 1 Technical Reference Manuals

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
CoreSight   DK-A5 Errata List
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   Design Kit TRM - PDF
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   Design Kit TRM - FrameMaker
    	
 
    	
D
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   Design Kit Errata List
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ETM-A5 TRM - FrameMaker
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ETM-A5 TRM - PDF
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ETM-A5 Errata List - PDF
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
AHB   Trace Macrocell TRM - FrameMaker
    	
 
    	
D
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
AHB   Trace Macrocell TRM - PDF
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
AHB   Trace Macrocell Errata List
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   TPIU Lite TRM - FrameMaker
    	
 
    	
D
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   TPIU Lite TRM - PDF
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   TPIU Lite Errata List - PDF
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge TRM - PDF
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge Errata List
    	
 
    	
D,CS
    	
 
    	
 
    


 

Section 2 Architecture Documentation

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
CoreSight   Architecture Specification
    	
 
    	
N
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
ETM   Architecture Specification
    	
 
    	
N
    	
 
    	
 
    


 

2











 

PART B IMPLEMENTATION & INTEGRATION MANUALS

 

IG means: Implementation Guide

 

IM means: Integration Manual

 

CSG means: Configuration Sign-off Guide

 

TPIU means: Trace Port Interface Unit

 

SWD means: Serial Wire Debug

 

SWV means: Serial Wire Viewer

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
CoreSight   System Design Guide
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   Generic Components IG - PDF
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ETM-A5 CSG - PDF
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Integration   Manual - PDF
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Integration   Manual - FrameMaker
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ETM-A5 Release Note - PDF
    	
 
    	
D,CS
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
CoreSight   DK-A5 IM
    	
 
    	
D
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   DK-A5 Release Note
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   TPIU Lite Release Note - PDF
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge IM
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge Release Note
    	
 
    	
D,CS
    	
 
    	
 
    


 

PART C ARM CORE SYNTHESIZABLE SOURCE

 

Section 1 CoreSight ETM Synthesisable RTL

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
CoreSight   ETM-A5 Synth Verilog RTL
    	
 
    	
D
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
CoreSight   TPIU Lite Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    


 

Section 2 CoreSight Debug Synthesisable RTL

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
Debug   Access Port Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
AHB   Access Port Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
JTAG   Access Port Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Serial   Wire JTAG dualmode Debug Port RTL
    	
 
    	
D
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
APB   Access Port Verilog RTL
    	
 
    	
D
    	
 
    	
 
    
	
***
    	
 
    	
APBMUX   for DAP Verilog RTL
    	
 
    	
D
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Cross Trigger Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    


 

Section 3 CoreSight Multi Source Trace Synthesisable RTL

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
Trace   Funnel Verilog RTL
    	
 
    	
D,CS
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
Embedded   Trace Buffer Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    


 

3











 

	
***
    	
 
    	
Trace   Port Interface Unit Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Replicator Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Synchronous   Trace Bridge Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
AHB   Trace Macrocell Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    


 

Section 4 CoreSight Serial Wire Viewer Synthesisable RTL

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
Instrumentation   Trace Macro Verilog RTL
    	
 
    	
D,CS
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
Serial   Wire Output Verilog RTL
    	
 
    	
D,CS
    	
 
    	
 
    


 

Section 5 Synthesis Scripts

 

LEC means:RTL to Netlist Logical

 

Equivalence Check Scripts

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
Debug   Access Port Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Debug   Access Port Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Debug   Access Port Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Cross Trigger Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Cross Trigger Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Cross Trigger Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Trace Buffer Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Trace Buffer Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Trace Buffer Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Funnel Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Funnel Formality LEC
    	
 
    	
D,CS
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
Trace   Funnel Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Replicator Port Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Replicator Port Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Replicator Port Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Synch   Trace Bridge Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Synchronous   Trace Bridge Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Synchronous   Trace Bridge Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Port Interface Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Port Interface Unit Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Port Interface Unit Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
AHB   Trace Macrocell Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
AHB   Trace Macrocell Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    


 

4











 

	
***
    	
 
    	
AHB   Trace Macrocell Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   TPIU Lite Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   TPIU Lite LEC Formality
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   TPIU Lite LEC Conformal
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
ITM   Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
ITM   Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
ITM   Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Serial   Wire Output Synthesis Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Serial   Wire Output Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
Serial   Wire Output Verplex LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge Synth Scripts
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge Formality LEC
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge Cadence LEC
    	
 
    	
D,CS
    	
 
    	
 
    


 

PART D FUNCTIONAL TEST VECTORS

 

CRF means: Test Vectors - CRF

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
Debug   Access Port Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Cross Trigger CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
Embedded   Trace Buffer Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Funnel Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Replicator Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
Synchronous   Trace Bridge Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
Trace   Port Interface Unit CRF
    	
 
    	
D,M,T,CS
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
AHB   Trace Macrocell Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ETM-A5 Vector Replay
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ETM-A5 Port. Power Indic. CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   TPIU Lite Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
ITM   Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
Serial   Wire Output Functional CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ATB Async Bridge Func CRF
    	
 
    	
D,M,T,CS
    	
 
    	
 
    


 

PART E TEST

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
CoreSight   DK-A5 Integration Kit
    	
 
    	
D,CS
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
CoreSight   ETM-A5 Integration Kit
    	
 
    	
D,CS
    	
 
    	
 
    


 

5











 

	
***
    	
 
    	
CoreSight   ETM-A5 Port. Funct. Test Src
    	
 
    	
D,CS
    	
 
    	
 
    
	
***
    	
 
    	
CoreSight   ETM-A5 Port. Power Test Src
    	
 
    	
D,CS
    	
 
    	
 
    


 

PART F MODELS

 

	
Part Number
    	
 
    	
Description
    	
 
    	
Disclosure   Rights
    	
 
    	
Delivery   Date
    
	
***
    	
 
    	
DSM   Synopsys VCS Verilog Solaris
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   Synopsys VCS Verilog Linux
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   Synopsys VCS Verilog Solaris 64bit
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   Synopsys VCS Verilog Linux AMD 64bit
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   ModelSim Verilog Solaris
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   ModelSim Verilog Linux
    	
 
    	
N
    	
 
    	
Within   ten working days of Annex Effective Date
    
	
***
    	
 
    	
DSM   ModelSim Verilog Solaris 64bit
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   ModelSim Verilog Linux AMD 64bit
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   NC Verilog Solaris
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   NC Verilog Linux
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   NC Verilog Solaris 64bit
    	
 
    	
N
    	
 
    	
 
    
	
***
    	
 
    	
DSM   NC Verilog Linux AMD 64bit
    	
 
    	
N
    	
 
    	
 
    


 

6












 

SECTION 2 - LICENCE AND SPECIAL CONDITIONS

 

A.            Definitions

 

A.1         “Architecture Documentation” means the architecture documentation identified in Section 1 Part A Section 2.

 

A.2         “ARM Compliant Product” means any product designed by of for LICENSEE which has at a minimum; (i) an ARM Core; and (ii) CoreSight DK-A5.

 

A.3         “ARM Core” means either or both the Cortex-A5 Core MP Core or the Cortex-A5 UP Core licensed by LICENSEE from ARM and which is marketed as being compatible with the CoreSight DK-A5.

 

A.4         “CoreSight DK-A5” means subject to the compliance restrictions set out in Clause C of Section 2 of this Annex 1; any or all of; (i) the CoreSight ETM; (ii) the CoreSight Debug; (iii) the CoreSight Multi Source Trace and (iv) the Serial Wire Viewer.

 

A.5         “CoreSight Debug” means together the debug access port and the embedded cross trigger both as described in the Technical Reference Manual ***.

 

A.6         “CoreSight Debug Synthsisable RTL” means the synthesisable RTL identified in Section 1 Part C Section 2.

 

A.7         “CoreSight ETM” means the embedded trace macrocell identified in the Technical Reference manual part number ***.

 

A.8         “CoreSight ETM Synthesisable RTL” means the synthesisable RTL identified in Section 1 Part C Section 1.

 

A.9         “CoreSight Multi Source Trace” means together; (i) the CoreSight Debug; (ii) the CoreSight ETM (excluding the trace port and JTAG port); (iii) the trace funnel described in the Technical Reference Manual part number ***; (iv) either or both the embedded trace buffer or the trace port interface unit described in the Technical Reference Manual ***; and (v) which may in addition include the other additional trace capability described in the Technical Reference Manual part number ***.

 

A.10       “CoreSight Multi Source Trace Synthesisable RTL” means the synthesisable RTL identified in Section 1 Part C Section 3.

 

A.11       “Design Simulation Models” means (i) the design simulation models for the CoreSight ETM and identified in Section 1 Part F; and (ii) any other design simulation model for the CoreSight ETM which is generally available from ARM subject to; (a) receipt by ARM of a purchase order from LICENSEE requesting such design simulation model expressly subject to the terms and conditions of this Agreement; and (b) the payment by LICENSEE to ARM of the then current fee for such design simulation model as quoted by ARM from time to time.

 

A.12       “Design Start” means the earlier of any of the following; (i) the date that LICENSEE first synthesises the Synthesisable RTL for an ARM Compliant Product; (ii) the date that LICENSEE enters into a contract with a third party for the design of an ARM Compliant Product; or (iii) the date that LICENSEE delivers any ARM Technology or derivatives thereof, to a Customer pursuant to the licenses granted in this Annex 1.

 

A.13       “Download” means the removal or copying of any or all of the relevant ARM Technology in respect of each ARM Compliant Product from the secure area on www.connect.arm.com.

 

A.14       “End User Licence” means a license agreement substantially in the form set out in Section 10.

 

A.15       “Functional Test Vectors” means the functional test vectors identified in Section 1 Part D.

 

A.16       “Implementation and Integration Manuals” means the documentation identified in Section 1 Part B.

 

A.17       “Serial Wire Viewer” means the serial wire viewer identified in the Technical Reference manual part number ***.

 

A.18       “Serial Wire Viewer Synthesisable RTL” means the deliverables identified in Section 1 Part C Section 4 of this Annex 1.

 

A.19       “Synthesisable RTL” means any or all of; (i) the CoreSight ETM Synthesisable RTL; (ii) the CoreSight Debug Synthesisable RTL; (iii) the CoreSight Multi Source Trace Synthesisable RTL; and (iv) the Serial Wire Viewer Synthesisable RTL.

 

7











 

A.20       “Synthesis Scripts” means the deliverables identified in Section 1 Part C Section 5.

 

A.21       “Technical Reference Manuals” means the relevant technical reference manuals identified in Section 1 Part A. Section 1.

 

A.22       “Test” means the programs identified in Section 1 Part E.

 

A.23          “Unique ARM Compliant Product” means:

 

(i)         an unlimited number of units of a single design for an ARM Compliant Product which has been taped out and given a unique part number; and

 

(ii)        an unlimited number of units of any derivatives of the ARM Compliant Products referred to in Clause A.23(i), provided that:

 

(a)           such derivatives result only from any or all of the following modifications; (1) the implementation by LICENSEE of an Update delivered by ARM to some or all of the ARM Technology; (2) the correction of errors in such ARM Compliant Products to achieve conformance with the original specification for such design; and (3) a version of such ARM Compliant Product that has been ported to a different set of process design rules but is otherwise functionally unmodified (except to the extent accommodated by this definition); and

 

(b)           except as provided below, no more than one such derivative for the ARM Compliant Product referred to in Clause A.23(i) is being manufactured for LICENSEE at any time. LICENSEE shall be permitted to concurrently manufacture the derivative and the design from which such derivative was derived; (i) indefinitely if the derivative is a result of Clause A.23(ii)(a)(1) or Clause A.23(ii)(a)(2); and (ii) if the derivative is a result of Clause A.23(ii)(a)(3), then for a period of six (6) months from the date of first manufacture of the new derivative

 

A.24       “Use” means in respect of the object code of the Design Simulation Models, the use of (including copying the object code of the Design Simulation Models to the extent that such copying is incidental to such use, including installation, backup and execution) the object code of the Design Simulation Models, or any part thereof. Use shall specifically exclude: (i) the translation, adaptation, arrangement or other alteration of the object code of the Design Simulation Models except as allowed by local legislation implementing Article 6 of the EC Directive on the legal protection of computer programs (91/250/EEC) and then only to the extent necessary to achieve interoperability of an independently created program with other programs; and (ii) the adapting or reverse compiling of the object code of the Design Simulation Models for the purpose of error correction.

 

B.            Licence

 

B.1         Subject to the provisions of Clause 3 of the TLA, and the restrictions set out in Clause C below, ARM hereby grants, to LICENSEE, a non-transferable (subject to Clause 16.3 of the TLA), non-exclusive, world-wide licence for the Term to;

 

Technical Reference Documentation

 

(i)      use, copy, modify (solely to the extent necessary to reflect any permitted modifications in accordance with the provisions of this Clause B.1 or for incorporation into LICENSEE’s documentation), distribute and have distributed the Technical Reference Manuals;

 

(ii)     use and copy the Architecture Documentation for the purposes of designing ARM Compliant Products;

 

CoreSight DK-A5

 

(iii)    use and copy  the Implementation and Integration Manuals only for the purposes of designing, having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA) ARM Compliant Products;

 

(iv)    use, copy and modify; (solely for the purposes of scan insertion, buffer insertion, timing closure, targeting standard cell libraries, direct instantiations of cells and speed, power optimisation, use of licensee specified BIST, changing any “Verilog Defines” which are stated as being modifiable in the Implementation and Integration Manuals and changing any configuration settings permitted in the relevant Implementation and Integration Manuals) the Synthesisable RTL, only for the purposes of designing, and having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA) ARM Compliant Products;

 

8











 

(v)     use, copy and modify (a) the Synthesis Scripts; and (b) the Test, only for the purposes of designing, and having designed (subject to the provisions of Clause 2.2 and 2.3 of the TLA), ARM Compliant Products;

 

(vi)    use, copy and modify (solely for the purpose of and to the extent necessary run the vectors on a simulator or tester) the Functional Test Vectors, only for the purposes of designing and having designed (subject to the provisions of Clauses 2.2 and 2.3 of the TLA, manufacturing and having manufactured (subject to the provisions of Clause 2.4 of the TLA and testing and having tested (subject to the provisions of Clause 2.5 of the TLA) ARM Compliant Products;

 

(vii)   manufacture and have manufactured (subject to the provisions of Clause 2.4 of the TLA) the Unique ARM Compliant Products created under the licences granted in Clauses B.1(i) to B.1(vi) inclusive;

 

(viii)  sell, supply and distribute the Unique ARM Compliant Products manufactured under the licences granted in Clause B.1(vii);

 

Design Simulation Models

 

(ix)    reproduce and use, internally and for third party support purposes, the Design Simulation Models and related documentation;

 

(x)     use, reproduce and distribute, and sub-license (subject to the terms of an End User Licence) the Use of the object code of the Design Simulation Models, solely for the purpose of developing ARM Compliant Products; and

 

(xi)    modify, reproduce, use and distribute, in connection with the Design Simulation Models, the documentation related thereto.

 

C.            Compliance Restrictions

 

C.1         To ensure tools interoperability with the CoreSight DK-A5  LICENSEE shall comply with following topology constraints:

 

(i)             no nested debug access ports i.e. one debug access port must not drive another debug access port;

 

(ii)            in respect of the CoreSight Multi Source Trace, multiple inputs to the trace funnel must originate from unique trace sources;

 

(iii)           no feedback paths are permitted on the AMBA trace bus;

 

(iv)          Only one cross trigger interface is permitted per ARM Core being debugged using the CoreSight DK-A5;

 

(v)           In respect of the cross trigger interface trigger I/O, when ASICCTL = 0x00, the Cross trigger interface trigger I/O must be connected to the pins specified by the cross trigger interface connectivity rules in the Integration Manual identified in Section 1 Part B Section 1; and

 

(vi)          The CoreSight DK-A5 must be programmable by a single debug access port where present.

 

D.            Special Conditions

 

D.1      Notwithstanding the provisions of Clause 12.1 of the TLA, ARM shall not be obligated to indemnify LICENSEE in respect of any suit brought by a third party against LICENSEE based upon a claim that any of the ARM Technology delivered by ARM to LICENSEE under this Annex 1 infringes a patent owned by such third party where such claim is based on the implementation of a Standard other than a Standard licensed from ARM.

 

Where:

 

“Standard” means: (i) any specification which: (a) contains engineering or technical criteria, methods, processes or practices; (b) has been approved by a formal committee; and (c) is made available, whether publicly or to members, by a broadly recognised organisation whose primary business objective is the development, approval and dissemination of specifications for the purpose of achieving standardisation; and (ii) any version of either or both the 

 

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1149.1 IEEE Standard for Standard Test Access Port and Boundary-Scan Architecture and 1149.7 IEEE Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary Scan Architecture licensed or controlled by IEEE Standards Association.

 

E.            IP access model Provisions

 

Number of Unique ARM Compliant Products

 

E.1          Under this Annex 1, LICENSEE shall have the right to exercise the licenses granted under Clause B.1 of this Annex 1 for an unlimited number of Unique ARM Compliant Products, provided that for each such Unique ARM Compliant Product LICENSEE pays to ARM the respective Use Fee as set out in, and in accordance with the provisions of Section 8 of this Annex 1.

 

Audit

 

E.2          In addition to the audit requirements in Clause 6.6 of the TLA, the Auditors shall be entitled to review; (i) the ARM Technology which has been Downloaded by LICENSEE; (ii) Design Starts for any Unique ARM Compliant Products; and (iii) any information necessary to substantiate and verify the data submitted to ARM by LICENSEE in any Usage Report provided in accordance with Section 8. LICENSEE’s books and records relevant to verification of the information which LICENSEE is obliged to report pursuant to this Clause, shall be retained by LICENSEE for at least six (6) years after the end of the period to which the Download, Design Start or Usage Report relates.

 

F.            Limitation of Liability

 

F.1         For the purposes of this Annex 1, delete Clause 13.2 of the TLA and replace with the following:

 

“13.2     NOTWITHSTANDING ANYTHING TO THE CONTRARY CONTAINED IN THIS TLA, THE MAXIMUM LIABILITY OF ARM TO LICENSEE IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT TORT OR OTHERWISE UNDER OR IN CONNECTION WITH EACH ARM DELIVERABLE (AS DEFINED BELOW) LICENSED UNDER AN ANNEX 1 SHALL NOT EXCEED THE USE FEES PAID TO ARM IN RESPECT OF THAT ARM DELIVERABLE. THE EXISTENCE OF MORE THAN ONE CLAIM OR SUIT WILL NOT ENLARGE OR EXTEND THE LIMIT. LICENSEE RELEASES ARM FROM ALL OBLIGATIONS, LIABILITY, CLAIMS OR DEMANDS IN EXCESS OF THIS LIMITATION”

 

“ARM Deliverable” means an individual product being part of the ARM Technology delivered under an Annex 1 where such product has an associated Use Fee in Section 8 of the relevant Annex 1.

 

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SECTION 3 — VERIFICATION

 

Not applicable.

 

SECTION 4 - SUPPORT LIMITATION

 

4.1          Except as provided below, the maximum number of man hours that ARM shall be obligated to expend on any individual support case submitted to ARM by LICENSEE shall be capped at sixteen (16).

 

4.2          If ARM reasonably believes that any individual support case will exceed the support cap referred to above, ARM and LICENSEE will mutually agree a plan of action for resolution of the support case.

 

4.3          If a support case results in a defect being identified, any time associated with correcting such defect will not be logged against such support case.

 

4.4          If ARM, at ARM’s discretion, determines that LICENSEE has entered multiple cases which relate to the same support problem, ARM shall be entitled to compile these into a single case which in aggregate will be subject to the cap referred to above.

 

4.5          If ARM agrees to provide support at LICENSEE’s premises in accordance with the provisions of Clause 7.3 of the TLA, any time spent at LICENSEE’s premises including travel shall not be included as part of the support cap.

 

SECTION 5 - TRAINING REQUIREMENT

 

Not applicable.

 

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SECTION 6 - TRADEMARKS

 

	
Trademark
    	
 
    	
Registered/ Unregistered
    	
 
    
	
 
    	
 
    	
 
    	
 
    
	
Part A
    	
 
    	
 
    	
 
    
	
 
    	
 
    	
 
    	
 
    
	
ARM w/bar [logo]   Exhibit A
    	
 
    	
Registered
    	
 
    
	
 
    	
 
    	
 
    	
 
    
	
Part B
    	
 
    	
 
    	
 
    
	
 
    	
 
    	
 
    	
 
    
	
ARM Powered [logo]   Exhibit B
    	
 
    	
Registered
    	
 
    
	
 
    	
 
    	
 
    	
 
    
	
Part C
    	
 
    	
 
    	
 
    
	
 
    	
 
    	
 
    	
 
    
	
ARM [logo]   Exhibit C
    	
 
    	
Registered
    	
 
    


 

SECTION 7 — TERM

 

Unless terminated earlier in accordance with the provisions of Clause 14 of the TLA, this Annex 1 shall continue in force for a period of three (3) years.

 

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SECTION 8 - FEES AND ROYALTIES

 

Fees

 

“Product Annexes”, “Pre-Paid Licence Fees” and “Access Fees” shall have the meanings as defined in the MP Core annex (document number LES-ANX-20356)

 

Use Fees

 

Subject to the provisions of this Section 8, for each Unique ARM Compliant Product developed under this Annex 1, LICENSEE shall pay to ARM the relevant Use Fees set out below:

 

	
ARM Technology
    	
 
    	
Use Fee (US$)
    
	
Each   Unique ARM Compliant Product containing CoreSight DK-A5
    	
 
    	
See Use Fee Table as set out in   Section 8 of the MP Core annex document LES-ANX-20356
    


 

The Use Fee payable to ARM by LICENSEE shall be due to ARM as follows:-

 

(i)            Upon first Download of the ARM Technology; and

(ii)           Upon Design Start of the second and each subsequent Unique ARM Compliant Product incorporating such ARM Technology.

 

All Use Fees shall be due at the end of the Quarter in which the Download or Design Start has occurred as applicable. Notwithstanding the foregoing, LICENSEE shall not be obligated to pay the whole or any part of any Use Fees, to ARM under the Product Annexes, until such time as the aggregate Use Fees  which LICENSEE is obligated to pay to ARM under the Product Annexes has exceeded the amount of the Pre-Paid License Fee that has become due to ARM.

 

Where any Pre-Paid Licence Fees have not become due, invoices raised by ARM for amounts that exceed the amount of the Pre-Paid Licence Fee that has become due to ARM will be set off against any subsequent milestone payments for the Pre-Paid Licence Fee that have not yet become due to ARM.

 

Access to ARM Technology in the Product Annexes

 

For the avoidance of doubt, LICENSEE will not be able to Download any ARM technology licensed under the Product Annexes during any year of Term unless LICENSEE has paid the Access Fees for the relevant period.

 

Entitlement to Support and Maintenance Services.

 

In respect of each of the ARM Technology licenced under the Product Annexes, in addition to paying the Access Fee for the relevant period, LICENSEE must pay the Support and Maintenance Fees for the relevant period to be entitled to request Support and Maintenance Services in respect of such ARM Technology licensed under the Product Annexes.

 

USAGE REPORTS

 

8.1          For the purposes of this Annex 1 the provisions of Clause 6.3 of the TLA shall be replaced with the following:

 

“Usage Report

 

6.3          LICENSEE shall submit to ARM a report (each a “Usage Report”) within thirty (30) days after the end of every Quarter. Each Usage Report shall contain the following information relating to each ARM Compliant Product and which shall be substantially in the form set out below;

 

	
Part Number
    	
 
    	
Internal 
   Project
   Name
    	
 
    	
Foundry and
   Process
    	
 
    	
ARM Technology
    	
 
    	
Project
   Status
    	
 
    	
Production
   Status
    	
 
    	
Tape Out
   Type
    	
 
    	
Last Tape
   Out Date
    	
 
    	
Wafer
   Quantity
    
	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    
	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    
	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    	
 
    


 

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Each Usage report shall be submitted online at http://designstart.arm.com under the “My Account” link listed under the ARM Products and Services heading.

 

8.2          For the purposes of this Annex 1 the provisions of Clause 6.6 of the TLA shall be replaced with the following:

 

“Audit Rights

 

6.6          Subject to the provision of at least (30) days prior written notice, ARM or its agent shall have the right to conduct up to one (1) audit in any twelve (12) month period of LICENSEE’s relevant books and records to verify the information which LICENSEE is obliged to report pursuant to Clause 6.3 of the TLA.  Audits performed under this Clause 6.6 shall be conducted; (i) during normal business hours; and (ii) at ARM’s sole expense.  LICENSEE’s books and records relevant to verification of the information which LICENSEE is obliged to report pursuant to Clause 6.3 of the TLA, shall be retained by LICENSEE for at least six (6) years after the end of the period to which the Usage Report relates.”

 

Invoice address: 6/F, Building 4, 690 Bibo Road, Pudong, Shanghai 201203, PRC

 

Royalties

 

Not Applicable

 

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SECTION 9 - MARKETING

 

Notwithstanding anything to the contrary contained in the TLA either party may disclose to third parties that LICENSEE is a licensee of the ARM Technology licensed under this Annex 1. Except as expressly provided in the TLA, no right is granted to either party to disclose the terms and conditions of the TLA or this Annex 1.

 

Within sixty days (60) days of the Annex Effective Date the parties shall mutually agree the terms and method of issuance of a written announcement, which may be a press release, relating to the technology licensed under this Annex 1 and the relationship of the parties.

 

All communications for the above marketing activities shall be sent to the following contacts:

 

	
ARM Marketing Contact
    	
 
    	
LICENSEE Marketing Contact
    
	
 
    	
 
    	
 
    
	
Director of   Corporate Communications
    	
 
    	
 
    
	
CommsDirector@arm.com
    	
 
    	
 
    
	
110 Fulbourn Road
    	
 
    	
 
    
	
Cambridge
    	
 
    	
 
    
	
CB1 9NJ
    	
 
    	
 
    


 

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SECTION 10 — END USER LICENCE

 

[Respective LICENSEE entity]  (“LICENSOR”) hereby grants and the LICENSEE hereby accepts a non transferable and non-exclusive licence to use the Model solely for the purpose of developing a product which incorporates a CPU manufactured under LICENSOR’s licence from ARM (“Purpose”), under the following terms and conditions:

 

1.         Ownership.  The Model is the property of ARM LIMITED and/or its licensors. The LICENSEE acquires no title, right or interest in the Model other than the licence rights granted herein.

 

2.         Use.  The LICENSEE may use the Model on any one computer at one time except that the  Model may be executed from a common disc shared by multiple CPUs provided that one authorised copy of the  Model has been licensed from LICENSOR for each CPU concurrently executing the Model.

 

LICENSEE shall not reverse engineer, decompile or disassemble the Model, in whole or in part.

 

LICENSEE shall only be permitted to use the Model for the Purpose.

 

LICESENSOR hereby authorises  LICENSEE to concurrently use up to a maximum number of [       ] copies of the Model

 

3.         Copies.  Except as provided in Clause 2,  LICENSEE may make copies of the Model for back-up and archival purposes only. All copies of the Model must bear the same notice(s) contained on the original copies supplied by LICENSOR.

 

4.         Model Limited Warranty. LICENSOR warrants that the disks containing the Model shall be free from defects and workmanship under normal use and the programs will perform in accordance with the accompanying documentation for a period of ninety (90) days from the date of delivery.  Any written or oral information or advice given by LICENSOR distributors, agents or employees will in no way increase the scope of this warranty. LICENSOR’s entire liability and the LICENSEE’s exclusive remedy will be, at LICENSOR’s sole option, to replace the disk or to use LICENSOR’s reasonable efforts to make the Model meet the warranty set forth above.  Any replacement  Model will be warranted for the remainder of the original warranty period or thirty (30) days, whichever is the longer. The LICENSEE agrees that the supply of the Model does not include updates and upgrades, which may be available from LICENSOR under a separate support agreement.

 

THE ABOVE WARRANTIES ARE EXCLUSIVE AND IN LIEU OF ALL OTHER WARRANTIES, WHETHER EXPRESS OR IMPLIED INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

 

IN NO EVENT SHALL LICENSOR BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROM ITS PERFORMANCE OR FAILURE TO PERFORM UNDER THIS AGREEMENT OR THE FURNISHING, PERFORMANCE, OR USE OF ANY MODEL LICENSED HERETO, WHETHER DUE TO BREACH OF CONTRACT, BREACH OF WARRANTY, OR NEGLIGENCE EVEN IF LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

 

THE MAXIMUM LIABILITY OF LICENSOR SHALL BE LIMITED TO REFUND OF THE FEES PAID BY LICENSEE (IF ANY) FOR THE MODEL.

 

5.         Assignment of the Agreement.  This Agreement and any license granted hereunder to the LICENSEE may not be assigned, sub-licensed or otherwise transferred by the LICENSEE to any third party

 

6.         Term and Termination.  Unless terminated in accordance with the provisions of this Clause 6, this Agreement and licenses granted hereunder shall continue in force until completion of the Purpose.  LICENSOR may  terminated this Agreement by written notice to the LICENSEE in the event  of a breach by  LICENSEE of any provisions of this Agreement.

 

Upon expiration or termination of this Agreement, the LICENSEE shall refrain from any further use of the Model, and LICENSEE shall either return or destroy and copies of the Model in it’s possession at the date of expiration of termination as applicable.

 

7.         Applicability.  The limitations and exclusions above may not apply in certain countries or states where they conflict with local law. In cases where such a conflict exists the local law shall prevail and the remaining provisions of the Agreement shall remain in full force and effect.

 

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IN WITNESS WHEREOF the parties have caused this Annex 1 to be signed by their duly authorised representatives:

 

 

	
ARM   LIMITED
    	
RDA TECHNOLOGIES LIMITED
    
	
 
    	
 
    
	
 
    	
 
    
	
BY:
    	
/s/ Mike Inglis
    	
 
    	
BY:
    	
/s/ Vincent Tai
    
	
 
    	
 
    	
 
    	
 
    	
 
    
	
NAME:
    	
Mike Inglis
    	
 
    	
NAME:
    	
Vincent Tai
    
	
 
    	
 
    	
 
    	
 
    	
 
    
	
TITLE:
    	
Chief Commercial Officer
    	
 
    	
TITLE:
    	
CEO
    
	
 
    	
 
    	
 
    	
 
    	
 
    
	
DATE:
    	
8-1-13
    	
 
    	
DATE:
    	
2012.12.19
    


 

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