# Patent

## Title
Low noise analog electronic circuit design for recording peripheral nerve activity

## Abstract

Circuits and circuit systems to record activity (e.g., peripheral nerve activity) are provided. The circuits advantageously have good noise characteristics (e.g., low noise), as well as low power consumption and low area. A circuit can be implantable (e.g., in a human subject). Methods of designing, manufacturing, and using such circuits and circuit systems are also provided.

## Background
This invention was made with government support under a grant awarded from the National Institute of Health (NIH) under grant number NIH-R01EB008578. The government has certain rights in this invention.


BACKGROUND OF INVENTION
Though there have been many advances in prosthetic technology, existing systems are significantly limited in their ability to fully restore function after limb loss. Such limitations are manifested in the types of activities that can be achieved, the ease with which the tasks can be performed, and the richness of the experience. Improvements in state-of-the-art prosthetic technology can be achieved through fundamental advances in mechatronic systems, actuators, sensors, and control algorithms. However, truly advanced prosthetic systems require seamless integration of the intact sensory-motor living system with advanced, highly-capable artificial limbs, making it necessary to record neural activity to capture the motor-intent of the amputee.
It has been shown that despite partial atrophy and degeneration, both central and peripheral motor and somatosensory pathways retain significant function for many years following amputation—potentially allowing the use of neuroprosthetic technologies to establish efferent neural control of a prosthetic limb with direct afferent neural sensory feedback (Dhillon, Lawrence et al. 2004; Dhillon and Horch 2005; Dhillon, Kruger et al. 2005). Multiple electrode technologies currently exist to establish a neural interface. Choice of the electrode depends on many factors, including biocompatibility, long-term stability, ease of implantation, mechanical characteristics, electrochemical characteristics, and economics. Stimulation and recording can both be performed by electrodes placed either on the surface (surface electrodes) or beneath the skin (subcutaneous electrodes). Furthermore, subcutaneous electrodes can be placed on or in the muscle (epimysial or intramuscular electrodes), and on, in, or adjacent to peripheral nerves (extraneural or intraneural electrodes) (Keith 2001; Venkatasubramanian, Jung et al. 2006).
The current, most advanced hand and/or upper limb prostheses offer limited volitional motor control (Ohnishi, Weir et al., 2007). The primary pathway for the transmission of motor control information between the brain and muscle is through the peripheral nerves. Across numerous technologies, volitional motor control can be provided to a user at any level of the motor control pathway, but all of them require the recording of physiological signals. One approach is to record activity from peripheral nerves in the residual limb using longitudinal intrafascicular electrodes (LIFEs) and decode the signals to infer motor intent for the control of prostheses (Dhillon, Lawrence et al., 2004).
The few studies in which extracellular neural recordings from motor fascicles have been done in amputees using LIFEs indicate that the intrafascicular signal in the severed nerves has an ultra-low amplitude and broad shape. For example, when an amputee is attempting to generate activity of the missing limb, temporal 20 μV peak-to-peak signals can be obtained using intrafascicular recording (Dhillon, Lawrence et al., 2004). The signal-to-noise ratio is low, even with use of commercial recording systems (Dhillon, Lawrence et al., 2004; Lefurge, Goodall et al., 1991). Integrated circuits can be used for recording peripheral nerve activity (Uranga et al. 2004; Limunson et al. 2009; Rieger 2011). Often these use external components and are not always power/area efficient (200 μW/channel—order power and area above 0.06 mm2 per channel). FIG. 7 presents a typical recording circuit where the first active circuit is an amplifier.
BRIEF SUMMARY
Embodiments of the subject invention provide implantable circuits and circuit systems to record activity (e.g., peripheral nerve activity). The circuits of the subject invention advantageously have good noise characteristics (e.g., low noise). Such circuits can have low power consumption and/or low area. In an embodiment, such an implantable circuit can be powered wirelessly.
Embodiments of the subject invention also provide methods of designing, manufacturing, and using an analog amplifier with low noise and low area consumption.
Embodiments of the subject invention also provide electronic circuits (e.g., implantable electronic circuits) and circuit systems for recording low amplitude neural signals. These circuits are fully implantable. In an embodiment, an electronic circuit records low amplitude neural signals and also rejects signals with frequency components outside a tunable bandwidth. In a further embodiment, an electronic circuit records low amplitude neural signals, rejects signals with frequency components outside a tunable bandwidth, and maintains a low area consumption.
Embodiments of the subject invention also provide electronic circuits (e.g., implantable electronic circuits) and circuit systems that allow processing of neural activity to extract features while maintaining good noise characteristics (e.g., low noise), with relatively low power consumption and low area consumption.
In one embodiment, a circuit includes a low noise amplifier, wherein the low noise amplifier comprises an operational transconductance amplifier (OTA) having at least two differential input series-connected transistors (SCT). The circuit can be fully implantable (e.g., in a human subject). The low noise amplifier can be configured such that: the area per channel of the low noise amplifier is no more than 0.05 mm2; the power consumption per channel of the low noise amplifier is no more than 150 μW; and the input-referred noise density of the low noise amplifier is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth. In a further embodiment, the power consumption per channel of the low noise amplifier is no more than 20 μW.
In another embodiment, a system for recording peripheral nerve activity includes: a circuit; and at least one electrode in operable communication with the circuit. The circuit includes a low noise amplifier, wherein the low noise amplifier comprises an OTA having at least two differential input SCTs. The circuit can be fully implantable (e.g., in a human subject), and the low noise amplifier can be configured such that: the area per channel of the low noise amplifier is no more than 0.05 mm2; the power consumption per channel of the low noise amplifier is no more than 150 μW; and the input-referred noise density of the low noise amplifier is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth. In a further embodiment, the power consumption per channel of the low noise amplifier is no more than 20 μW.
In yet another embodiment, a method of recording peripheral nerve activity includes: implanting at least one electrode in or on at least one peripheral nerve; providing a circuit in operable communication with the at least one electrode; and recording activity of the at least one peripheral nerve using the circuit. The circuit includes a low noise amplifier, wherein the low noise amplifier comprises an OTA having at least two differential input SCTs. The circuit can be implantable (e.g., in a human subject), and the low noise amplifier can be configured such that: the area per channel of the low noise amplifier is no more than 0.05 mm2; the power consumption per channel of the low noise amplifier is no more than 150 μW; and the input-referred noise density of the low noise amplifier is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth. In a further embodiment, the power consumption per channel of the low noise amplifier is no more than 20 μW.
In yet another embodiment, an electronic circuit is configured to process neural activity to extract features. The circuit is configured such that: the area per channel of the circuit is no more than 0.05 mm2; the power consumption per channel of the circuit is no more than 150 μW; and the input-referred noise density of the circuit is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth. In a further embodiment, the power consumption per channel of the circuit is no more than 20 μW.



BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 shows a schematic of an analog circuit system according to an embodiment of the subject invention.
FIG. 2a shows a schematic of a shared operational transconductance amplifier (OTA) architecture.
FIG. 2b shows a schematic of a partial OTA sharing structure.
FIG. 3 shows a schematic of two series connected transistors (SCTs).
FIG. 4a shows a schematic of a circuit according to an embodiment of the subject invention, including a low noise amplifier.
FIG. 4b shows a schematic of a shared OTA recording system architecture according to an embodiment of the subject invention.
FIG. 4c shows a schematic of a shared OTA-SCT according to an embodiment of the subject invention.
FIG. 5 shows a plot of input-referred voltage noise density versus frequency.
FIG. 6 shows a schematic of a circuit according to an embodiment of the subject invention.
FIG. 7 shows a schematic of a conventional recording circuit.
FIG. 8 shows a layout view of a circuit according to an embodiment of the subject invention.



DETAILED DISCLOSURE
Embodiments of the subject invention provide implantable circuits and circuit systems to record activity (e.g., peripheral nerve activity). The circuits of the subject invention advantageously have good noise characteristics (e.g., low noise). Such circuits can have low power consumption and/or low area. In an embodiment, such an implantable circuit can be powered wirelessly.
Embodiments of the subject invention also provide methods of designing, manufacturing, and using an analog amplifier with low noise and low area consumption.
Embodiments of the subject invention also provide electronic circuits (e.g., implantable electronic circuits) and circuit systems for recording low amplitude neural signals. In an embodiment, an electronic circuit records low amplitude neural signals and also rejects signals with frequency components outside a tunable bandwidth. In a further embodiment, an electronic circuit records low amplitude neural signals, rejects signals with frequency components outside a tunable bandwidth, and maintains a low area consumption.
Embodiments of the subject invention also provide electronic circuits (e.g., implantable electronic circuits) and circuit systems that allow processing of neural activity to extract features while maintaining good noise characteristics (e.g., low noise), with relatively low power consumption and low area consumption.
Implantable circuits and circuit systems of the subject invention can be used to record activity from peripheral nerves in order to decode motor intent for seamless volitional control of prostheses. Such circuitry can be particularly applicable to recording intrafascicular signals from upper or lower extremities of amputees. Circuitry of the subject invention can be used for many purposes, including recording any peripheral nerve activity or brain activity.
In many embodiments, an analog circuit system is capable of recording activity from peripheral nerves and is implemented in a standalone integrated circuit (IC). The system includes the following cascaded analog sub-circuits: a low noise amplifier; a highpass filter with tunable corner frequency; and a programmable discrete gain amplifier. The output of this system can be accessible either directly or after processing through additional circuitry to provide information about the neural activity feature. Such a system advantageously associates two techniques, which may be used separately for different applications, for the design of the low noise amplifier. The system is a low power, low noise, low area amplifier.
FIG. 1 shows a schematic of an analog circuit system according to an embodiment of the subject invention. The circuit system can record activity (e.g., using an internal or external electrode) from peripheral nerves and can be implemented in a standalone integrated circuit. Electrodes that can be used with systems of the subject invention are discussed in more detail below. The system can include an implantable IC 102 including recording analog circuits 104 and, optionally, one or more processing circuits. The recording analog circuits 104 can include one or more of a low noise amplifier 202, a highpass filter 204, and a discrete gain amplifier 206. The low noise amplifier 202 can be a first stage of the recording analog circuits 104, highpass filter 204 can be a second stage, and the discrete gain amplifier 206 can be a third stage. The highpass filter 204 can have a tunable corner frequency, and the discrete gain amplifier 206 can be programmable. The output of the system can be accessed either directly or after additional processing circuitry that yields specific information about features of the recorded neural activity (e.g., spiking rate). In a particular embodiment, the processing circuits can include a comparator 208. The recording analog circuits 104 utilize an advantageous method for designing the first stage amplifier to achieve low noise, low power, and low area.
A circuit or circuit system can have an area per channel of, for example, any of the following values, about any of the following values, no more than any of the following values, or less than any of the following values (all numerical values are in square millimeters): 1, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.19, 0.18, 0.17, 0.16, 0.15, 0.14, 0.13, 0.12, 0.11, 0.10, 0.09, 0.08, 0.07, 0.06, 0.05, 0.04, 0.03, 0.02, 0.01, 0.009, 0.008, 0.007, 0.006, 0.005, 0.004, 0.003, 0.002, 0.001, 0.0009, 0.0008, 0.0007, 0.0006, 0.0005, 0.0004, 0.0003, 0.0002, or 0.0001. This can be the area per channel of the low noise amplifier 202, the area of the recording analog circuits 104, or the area of the recording analog circuits 104 together with any processing circuits (102). For example, the area per channel can be no more than 0.1 mm2 or 0.05 mm2. In a particular embodiment, the area per channel is in a range of from 0.0001 mm2 (100 μm2) to 0.05 mm2.
A circuit or circuit system can have a power consumption (e.g., a power consumption per channel) of, for example, any of the following values, about any of the following values, no more than any of the following values, or less than any of the following values (all numerical values are in micro-Watts): 500, 400, 300, 200, 197, 150, 100, 50, 45, 40, 35, 34, 33, 32.5, 32, 31, 30, 25, 20, 15, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0.9, 0.8, 0.7, 0.6, 0.5, 0.4, 0.3, 0.2, 0.10, 0.09, 0.08, 0.07, 0.06, 0.05, 0.04, 0.03, 0.02, 0.01, 0.009, 0.008, 0.007, 0.006, 0.005, 0.004, 0.003, 0.002, or 0.001. This can be the power consumption of the low noise amplifier 202, the power consumption of the recording analog circuits 104, or the power consumption of the recording analog circuits 104 together with any processing circuits (102). This can also be power consumption per channel or of the whole circuit. For example, the power consumption per channel can be no more than 150 μW or no more than 20 μW. In a particular embodiment, the power consumption per channel is in a range of from 0.005 μW (5 nW) to 20 μW.
A circuit or circuit system can have an input-referred voltage noise density of, for example, any of the following values, about any of the following values, no more than any of the following values, or less than any of the following values (all numerical values are in nano-Volts per square root of Hertz (nV/(Hz1/2))): 100, 90, 80, 70, 60, 50, 40, 30, 25, 24, 23, 22.8, 22, 21, 20, 19, 18, 17.7, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1. This can be, e.g., the input-referred voltage noise density of the low noise amplifier 202. These values can refer to the input-referred voltage noise density over a bandwidth (e.g., 100 Hz-4 kHz) or to the main white Gaussian noise contribution over the full bandwidth. For example, the input-referred noise density of the circuit can be no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.
Circuits and circuit systems according to embodiments of the subject invention provide the capability of recording neural signals from peripheral nerves that often have low amplitude (e.g., approximately 15 μV to 60 μV peak-to-peak or less than 60 μV peak-to-peak) on a bandwidth spanning hundreds of Hertz to a few kilo-Hertz (typically from 100-500 Hz to 5-10 kHz, or any range therebetween). Requirements for peripheral nerve recording are discussed in more detail below. Analog recording circuits of the subject invention can be provided on a chip designed to be fully implanted into a subject (e.g., a human subject such as an amputee).
The design of the first stage low noise amplifier combines a shared operational transconductance amplifier (OTA) recording system architecture with differential input series-connected transistors (SCT) (e.g., two such differential input SCTs). The OTA architecture can be that as described in Majidzadeh, Schmid et al., 2011. It is designed to reduce power and size consumption. FIG. 2a shows a schematic of a shared OTA architecture with a conventional structure of an array of n neural amplifiers (Majidzadeh, Schmid et al., 2011). FIG. 2b shows a partial OTA sharing structure for an array of n neural amplifiers, where the shaded box identifies the circuit shared among all low noise amplifiers.
In many embodiments, the shared OTA architecture is altered by adding SCT circuitry to permit further reduction of the noise and area consumption. An SCT has been used for a different purpose previously—to achieve low transconductance in integrated low frequency filters (Arnaud, Fiorelli et al. 2006). FIG. 3 shows an SCT that can be used as part of a circuit according to many embodiments of the subject invention. The additional SCT circuitry decreases the Cgd parasitic capacitance, as a function of the transistor width (Razavi 2003). A new parameter F helps to decrease the noise and area consumption, and increase the gain performance. The new parameter F is the width ratio of the differential input SCT, defined as follows:




  
    F
    =
    
      
        W
        ⁢
        
          
        
        ⁢
        
          (
          Mia
          )
        
      
      
        W
        ⁢
        
          
        
        ⁢
        
          (
          Mib
          )
        
      
    
  
  ,




where W(M) is the width W of the transistor M, and Mia and Mib are the differential input SCT of each branch of the OTA.
FIG. 4 shows a shared SCT-OTA recording system architecture according to an embodiment of the subject invention. The use of the SCT circuit along with the shared OTA architecture advantageously and surprisingly results in a low power, low noise, low area amplifier. Shaded boxes in FIG. 4 identify the shared circuit among all low noise amplifiers. FIG. 4a shows the full amputee peripheral nerve recording, including the low noise amplifiers. One low noise amplifier is required for each recording circuit (one per recording electrode). The dashed box identifies the enhanced OTA with SCT. FIG. 4b shows a schematic of a shared OTA recording system architecture according to an embodiment of the subject invention. Msct transistors are the SCTs. FIG. 4c shows a detailed schematic of a shared OTA-SCT according to an embodiment of the subject invention. Referring to FIG. 4c, instead of using one single transistor on the OTA differential pair, two SCTs are used—Mia, and Mib, sized with (W1/L1)Mia and (F. W1/L1)Mib, where W1 and L1 are the common width and length parameters of the input transistors, and F is a multiplicative factor for area/noise efficient sizing. F is a new parameter that allows tuning of the characteristics of the amplifier. This new design paradigm advantageously and surprisingly results in a low power, low noise, low area amplifier.
In an embodiment, an implantable circuit includes an OTA enhanced with at least two SCTs. The SCT-OTA can be in operable communication with at least one electrode.
In an embodiment, a circuit system can include an SCT-OTA as described herein, a highpass filter as described herein in operable communication with the SCT-OTA, and a discrete gain amplifier in operable communication with the highpass filter. In a further embodiment, the circuit system includes at least one electrode in operable communication with the SCT-OTA. In yet a further embodiment, the circuit system includes at least one processing circuit in operable communication with the discrete gain amplifier. The at least one processing circuit can be, for example, a comparator (e.g., a Schmitt trigger), though embodiments are not limited thereto. The SCT-OTA can be a first stage of the circuit system, the highpass filter can be a second stage of the circuit system, and the discrete gain amplifier can be a third stage of the circuit system.
As used herein, and unless otherwise specifically stated, the terms “operable communication” and “operably connected” mean that the particular elements are connected in such a way that they cooperate to achieve their intended function or functions. The “connection” may be direct or indirect, physical (e.g., by wires or other physical connections) or remote (e.g., wireless).
In an embodiment, the highpass filter can be a filter such as a passive resistor-capacitor filter circuit. This filter provides the ability to tune the bandwidth. For example, the filter can be capable of tuning the bandwidth in a range of about 100 Hz and 500 Hz. The filter does not degrade the gain characteristics provided by the low noise amplifier (first stage). Hence, the input impedances must be properly tuned.
The discrete gain amplifier (e.g., third stage programmable discrete gain amplifier) can further amplify the signal so that it can be efficiently utilized. The discrete gain amplifier can provide the capability for adapting the output of the second stage high pass filter to the dynamic input voltage/current range of the additional processing circuitry (if present).
In an embodiment, additional processing circuitry can be provided. Such processing circuitry can, for example, provide control signals to control the motors of a prosthesis. In a particular embodiment, additional processing circuitry can include a comparator, such as a Schmitt trigger.
FIG. 6 shows a schematic of a circuit according to an embodiment of the subject invention. Referring to FIG. 6, the shared low noise amplifier suitable for peripheral nerve recording includes m amplifiers represented on the schematic. One low noise amplifier is required for each recording circuit (one per recording electrode), which includes: the reference shared negative branch (shaded area); and a positive input branch (Vin p+, pεm). The two branches define the OTA for each low noise amplifier. The shaded box identifies the shared branch circuit among all low noise amplifiers. The dashed box identifies the two SCTs as the input transistor of one branch of the OTA. Instead of using one single transistor on the OTA differential pair, two SCTs (Mia and Mib) are used, sized with (W1/L1)Mia and (F. W1/L1)Mib, where W1 and L1 are the common width and length parameters of the input transistors, and F a multiplicative factor for area/noise efficient sizing. F is a new parameter that allows tuning of the characteristics of the amplifier.
In an embodiment, a method of recording peripheral nerve activity includes using an implantable circuit or circuit system as described herein to record the nerve activity. Circuits and circuit systems as described herein can also be used with any neural recording system that requires amplification of low amplitude signals with low noise and broad bandwidth.
Embodiments of the subject invention also provide methods of fabricating circuits or circuit systems as described herein.
The input-referred voltage noise density of a low noise amplifier according to embodiments of the subject invention can be characterized by the main noise contribution over a bandwidth (e.g., from a minimum frequency, f_min, to a maximum frequency, f_max). The main noise contribution at low frequency is the Flicker noise (1/f noise) and at high frequency is the white Gaussian noise. The subject invention minimizes the Flicker noise and in general the noise contribution in the low frequencies due to the architecture.
In conventional amplifies, the Flicker noise is not considered and only white noise of the components of the low noise amplifier architecture is considered (Harrison and Charles 2003, e.g., FIG. 7). If the Flicker noise is also considered, as in the subject invention, then the noise contribution on low frequencies can be very important and not negligible. Hence, the corner frequency is the characteristic frequency to describe at which frequency the low frequency noise switches, from being the main contributor to the overall noise of the low noise amplifier, to being a secondary contributor.
Circuits and circuit systems of the subject Mention meet the required noise performance, power consumption, and area consumption of an integrated circuit required for recording from multiple electrodes. Circuits and circuit systems of the subject Mention can be used with any number of electrodes implanted in peripheral nerves. While existing integrated circuits have power and size consumptions that forbid any future high density integration, embodiments of the subject invention overcome these disadvantages.
Low noise amplifiers of the subject invention can use a single additional parameter (F) to design the circuit for low noise and low area consumption, thereby providing a new design paradigm. A set of small transistors can be used in place of a single large transistor in part of the circuit. It is not expected that a combination of smaller transistors will yield the same noise performance as a bigger transistor, but they surprisingly did. This use of smaller transistors provides the benefit of reduced size to the overall architecture. Thus, the overall amplifier has both low noise and low area consumption. The low power consumption derives, at least in part, from the shared architecture.
Embodiments of the subject invention achieve good gain characteristics for the low noise amplifier while also achieving good noise performance (i.e., low noise). The parastic capacitance of the input OTA component of the low noise amplifier circuit can be modified. A two-SCT architecture can be used for the design of the parasitic capacitance to decrease the parasitic capacitance. A single additional parameter (F) can be utilized to achieve this reduced capacitance and provide a new design paradigm. It was not expected that a combination of smaller transistors would yield the same noise performance as a bigger transistor, but such noise performance was achieved. This use of smaller transistors provides the benefit of reduced size to the overall architecture. Thus, the overall amplifier has both low noise and low area consumption.
Electrodes
Extraneural electrodes are often of the “cuff” type. Examples are: (Stein, Charles et al. 1975; Naples, Mortimer et al. 1988; Figoni, Glaser et al. 1991; Sweeney, Crawford et al. 1995; Grill 2000; Navarro, Valderrama et al. 2001; Jensen, Sinkjaer et al. 2002). Cuff dimensions, mechanical properties and materials, and the configuration of the active and indifferent sites are important. The main limitation of “cuff electrodes”, however, is that their sensitivity level for both stimulation and recording lies at the level of the whole nerve. This can be problematic, as each peripheral nerve is made up of many heterogeneous motor and sensory axons, and true integration of neuroprosthetics will likely require sensitivity at the fascicular or axonal level (Zheng, Zhang et al. 2003). To access the fascicles, an intraneural electrode approach is required. Three main types of intraneural electrodes exist: regeneration electrodes (or sieve chips), multielectrode arrays, and single needle (Yoshida and Riso 2004).
Regeneration electrodes (or sieve chips) have been in development for nearly two decades with limited success (Edell 1986; Kovacs, Storment et al., 1992). Even in what may be the best result to date (in a fish vestibular nerve; (Mensinger, Anderson et al. 2000) only a limited number of channels with nerve fibers growing through them were able to produce definitive recordings. The most probable issues lie in the distance of the recording site to a node or blockage of nerve conduction as fibers pass through the small holes in the array. Modifications to the pore size and thickness of the chips may produce better results; however, extensive proof of principle studies would be required before these electrodes could be integrated into a prosthesis.
Anatomical and physiological constraints dictate that an effective peripheral nerve interface for providing discrete, distally referred sensations and for obtaining movement specific command signals from peripheral nerve stumps, must place electrode sites within the perineurium of individual nerve fascicles. This could be accomplished using punctate penetrating arrays such as the Utah multielectrode array (Branner and Normann 2000) or the slowly penetrating electrode (Malmstrom, McNaughton et al. 1998) or individual intrafascicular electrodes such as the longitudinal intrafascicular electrodes (LIFEs) developed in the Horch lab (Malagodi, Horch et al. 1989).
The Utah electrode array, originally designed to record and stimulate cortical tissue, with 100 electrodes in a 10×10 array measures as small as 2 mm2 with each 1 mm-long electrode spaced 400 μm apart (Campbell, Jones et al. 1991). It has been implanted in cat sciatic nerves chronically (Branner and Normann 2000; Branner, Stein et al. 2004). The development of the high density multi-micro electrode arrays, such as Utah Electrode Arrays, allows access to a larger population of fibers in the nerve and could allow recording from multiple electrodes of an array (Branner and Normann 2000; McDonnall, Clark et al. 2004). The lead wires for multiple electrodes can produce tethering forces on the array, resulting in damage to the nerve (Branner, Stein et al. 2004). Their implantation procedure also does not allow for the specific alignment of electrodes with specific fascicles. In addition, the implanted array has to be securely fixed to the nerve. These multiple challenges remain to be addressed for practical application in human subjects currently.
Another approach is to use LIFEs. These electrodes are a proven technology that has been shown to provide largely stable recordings and localized stimulation in chronic animal studies, and is the only technology proven to do the same in human amputee nerve stumps on a semi-chronic basis (Goodall, Lefurge et al. 1991; Lefurge, Goodall et al. 1991; Dhillon and Horch 2005; Dhillon, Kruger et al. 2005; Rossini, Rigosa et al. 2011). These electrodes allow access to individual fascicles and recording site exposure of 1 mm or more thereby providing improved recording capability (Malagodi, Horch et al. 1989). The somatotopic organization of peripheral nerves at both the fascicular and sub-fascicular levels (Hallin 1990; Watchmaker, Gumucio et al. 1991; Hallin and Wu 2001) allows directed access using LIFEs and is an asset for the circuits and circuit systems of the subject invention. Thus, in an embodiment of the subject invention, a circuit or circuit system as discussed herein is configured to interface with one or more LIFEs. In a further embodiment, a circuit or circuit system as discussed herein includes one or more LIFEs.
Peripheral Nerve Recording Requirements
FIG. 4a shows a recording system for peripheral nerve application. The intrafascicular activity, i.e., the signal-of-interest, has an ultra-low amplitude (in the range of micro-volts). One of the primary aims of the recording system, if not the primary aim, is to amplify this ultra-low amplitude signal to be efficiently processed by the following signal processing circuits.
Every electronic circuit has an intrinsic noise. This parasitic noise signal should not have a higher amplitude than the signal-of-interest. As illustrated by the Friis formula (Ziel 1970), the overall recording system noise is primarily established by the noise of the first amplifier, called the low noise amplifier. Hence, the noise of the low noise amplifier should be as low as possible. To provide an efficient amplification, the following requirements need to be quantitatively defined: the signal-of-interest amplitude, the recording system amplification gain, and the noise specification of the low noise amplifier.
Electronic noise can be diminished by increasing the transistor area and/or increasing the power consumption. At the transistor level, such a feature is sometime represented by the transconductance-to-current ratio (Gm/ID), where the transconductance is proportional to the transistor size (Razavi 2003). Therefore, a challenge for integrated recording systems is to find the best trade-off between the noise performance and the area/power consumption.
According to amputee peripheral nerve recording, implanted electrode in nerves on every level (cuff-recording, intra-nerve recording, intrafascicular recording with LIFE) record both nerve activity and nearby muscle activity (electromyograms, or EMG). In recording nerve activity, the only signal-of-interest is the intrafascicular activity; the EMG signal is then labeled as a parasitic signal. A second aim of the recording system is to reject parasitic signals, such as an EMG signal, from nearby muscles or other external parasitic sources.
The EMG signal should be characterized in order to select the appropriate parasitic rejection method. On one hand, the EMG spectrum is defined from 1 Hz to 3 kHz with a peak at about 250 Hz (Nikolic, Popovic et al. 1994). On the other hand, the amputee intrafascicular activity is described as a broad-shape spike (unlike the sharp-shape spike from microelectrode brain recording). The intrafascicular spike can be as broad as 4 to 6 milliseconds (the fundamental frequency would be about 150 to 250 Hz, with additional harmonic frequencies). Therefore, the EMG spectrum is large enough to overlap with the intrafascicular spectrum. Such overlap could lead to false intrafascicular activity signal processing. Because the intrafascicular and EMG signals share the same spectrum, their amplitude characteristics should be defined. Based on a cuff-recording study, EMG amplitude was described to be several orders of magnitude larger than nerve activity (Nikolic, Popovic et al. 1994). As for intrafascicular recording, the perineurium could potentially be insulated (Yoshida and Stein 1999).
To provide an efficient parasitic rejection, several methods can be used: shielding, differential recording; filtering; and common-mode rejection. Therefore, the additional following requirements need to be quantitatively defined: filtering bandwidth; and the recording system amplification common-mode rejection gain. To characterize the parasitic rejection in electronics, the common-mode gain rejection ratio (CMRR) is typically used. The CMRR is defined as the ratio between the differential and common mode gains.
The signal-of-interest is the intrafascicular activity by LIFEs differential recording. It has been shown that when an amputee attempts to generate activity of the missing limb, temporal 20 μV peak-to-peak (pp) signals can be obtained using intrafascicular recordings (Dhillon, Lawrence et al. 2004). Intrafascicular nerve recordings in animal models have been elicited by tactile or electrical stimulation delivered to the limb or nerve. The elicited activity peak-to-peak amplitude ranges between 10 to 20 μVpp (Goodall, Lefurge et al. 1991; McNaughton and Horch 1994) and 40 to 60 μVpp (Malagodi, Horch et al. 1989), respectively, for cat's radial and rat's sciatic nerve. On one hand, it has been reported that spontaneous sensory activity has larger average amplitude than evoked single units (Yoshida and Stein 1999). On the other hand, recorded activity could represent single action potentials or overlapped action potentials that derive from multiple neurons within a motor pool, which could explain the broad shape and low amplitude of the intrafascicular signal recorded from amputees.
In an embodiment of the subject invention, the range of recordable activity can be from about 10 μVpp to about 60 μVpp.
The recording system primary aim is to amplify the signal-of-interest. The overall gain for peripheral nerve recording is consistent in the literature, in the order of 10 kV/V (Malagodi, Horch et al. 1989; Yoshida and Horch 1996; Dhillon, Lawrence et al. 2004). With such amplification, the output of the recorded signal is expected to be in the hundreds of millivolt range for a 10 μVpp input amplitude. Integrated recording systems could target a lower amplitude for the recording signal to be processed on chip using low voltage bias. Published nerve recording systems offered an overall gain in the range of 1-5 kV/V (Uranga, Navarro et al. 2004; Limnuson, Tyler et al. 2009).
In an embodiment of the subject invention, the gain of the low noise amplifier is from 5 kV/V to 30 kV/V. In a preferred embodiment, the gain is at least 10 kV/V or at least about 10 kV/V. In a particular embodiment, the gain is 10 kV/V or about 10 kV/V. Since differential recording is applied to improve the parasitic rejection, the overall gain can also be defined as the differential gain. The device noise contribution should be low enough to allow the detection of intrafascicular activity. The noise specification is characterized by two performances.
The first noise specification is quantified by the input referred noise of the recording system, especially the low noise amplifier. The input referred noise could be represented by a noise density or a root mean square (RMS) value. The input referred noise density allows noise performance comparison between amplifiers with different gain and filter bandwidth. Indeed, electronic amplifiers don't have a constant gain over the full spectrum; because of parasitic electronic components, the amplifier may be better represented by a bandpass filter. The RMS noise is an average noise value over a defined bandwidth of integration, which includes the signal-of-interest spectrum.
The second noise specification is quantified by the signal-to-noise ratio (SNR). The SNR specification includes the input referred noise specification. The SNR is defined in the literature by different amplitude units, such as peak-to-peak, root-mean-square or standard deviation, with or without nulling the DC signal average (Kyung Hwan and Sung June 2000; Obeid 2007; Nabar and Rajgopal 2009). For the sake of clarity, SNR unit and/or definition is provided for each review.
The input referred noise of the recording system can be quantified by taking into account several features: the intrinsic noise of LIFE; the SNR of the intrafascicular activity measured by a commercial recording system; and the typical SNR to ease future signal processing (e.g. threshold detection).
In many cases, a LIFE is metal. Because the LIFE is metal, it has intrinsic thermal noise. For power/area reduction, there may not be a need to design a low noise amplifier with a lower noise than the LIFE-intrinsic thermal noise. Therefore, the LIFE-intrinsic thermal noise can define the minimal noise of the low noise amplifier. The LIFE equivalent impedance at 1 kHz range is between 8 and 12 kΩ according to the maxima of the standard deviation of LIFE impedance measurement from 2- to 6-month implantation in cats (Lefurge, Goodall et al. 1991). The LIFE-intrinsic thermal noise is expected to be in a range of 0.7-0.9 μVrms over 4 kHz. The noise bandwidth of integration is chosen to include the activity spectrum while not being too large to be compared with most of published recording studies (Malagodi, Horch et al. 1989; Yoshida and Horch 1996; Yoshida and Stein 1999; Dhillon, Lawrence et al. 2004). The LIFE-intrinsic RMS noise is equivalent to the usual thermal noise from cuff-electrodes, which is about 0.7μ VRMS (Stein, Nichols et al. 1977).
In sensory nerve recording studies using cuff-electrode or LIFE using bandpass filter amplification, SNRs measured with commercial instruments within 0-3 dB range have been reported (Malagodi, Horch et al. 1989; Lefurge, Goodall et al. 1991; Goodall and Horch 1992; Upshaw and Sinkjaer 1998). Such 0-3 dB SNR was qualified as a low SNR by authors. With regard to motor control activity, a recorded signal can be used with a Schmitt trigger-based process to control motion (Dhillon, Lawrence et al. 2004). The minimum threshold level for detecting neural activity was set manually, no SNR values are reported but it could be defined as approximately 3-6 dB according to the peak-to-peak maximal signal-to-noise ratio that was calculated from the presented data.
A qualitative SNR description is usually given to describe the ease of extracting information. The detection application of the studies is the brain spike detection. Even if brain spike has a different signal characteristic than amputee peripheral nerve signals, these comparative studies provide realistic quantification of SNR vs. detection efficiency, which can be used as a starting point applications of the subject invention. In a computational comparative study, a spike detector method can have performance scored as small (SNR≦1.8), medium (2.6≦SNR≦3.0), and large (SNR≧3.4) (Obeid and Wolf 2004). Other computational comparative spike sorting methods (which include a spike detection feature) use the following SNR ranges: 5-20 as the ratio of the mean peak signal level to the standard deviation of the background noise measured using segments of data that do not contain spikes (Zumsteg, Kemere et al. 2005); −10 dB-20 dB as the peak-to-peak amplitude of the average spike shape over six standard deviations of the noise (Gibson, Judy et al. 2010); and 1-2.5 as the average of the absolute peak amplitude of a spike over 3 RMS pure noise (Shalchyan, Jensen et al. 2012).
Based on the two previous reviews (SNR of the intrafascicular activity measured by a commercial recording system and the typical SNR to ease future signal processing), the maximum acceptable SNR can be defined, and therefore the maximal noise of the low noise amplifier can be defined for the minimal recordable signal-of-interest amplitude (e.g., 10 μVpp). The SNR can be defined as the ratio of the intrafascicular signal peak-to-peak amplitude to two standard deviations of background noise. This definition is based on the expectation that the maximal peak-to-peak noise amplitude will be close to 6 standard deviations. Based on the statistical definition, there is a 66% chance that the maximum noise amplitude is three times the RMS noise average to peak amplitude voltage.
First, the maximal SNR needs to be defined. If the minimal amplitude (10 μVpp) and the LIFE intrinsic noise (0.7 μVRMS) are considered, then the best recording system SNR is 7.14 V/V (17 dB). This SNR represent the best SNR that could be recorded if the electronic system was noiseless. The usual “high” SNR is defined as 5 or 6 dB, which leads to a resultant RMS noise of 0.8-1 μVRMS. According to a published SNR vs. detection efficiency study (Obeid and Wolf 2004), an SNR higher than 3.4 would be enough for sharp-shape brain spike detection. This 3.4 dB SNR is close to the minimum acceptable SNR (3 dB) for intrafascicular recording studies. The resultant RMS noise would be 1.6 μVRMS.
The input referred noise over 4 kHz can be defined as excellent if it is in the range of 0.7-1 μVRMS, and acceptable if it is in the range of 1-1.6 μVRMS. This definition is a rough estimation; extensive study takes into account the different noise nature impact (Flicker vs. thermal noise).
Bandpass filtering is one method used for parasitic rejection. The bandpass filter bandwidth is defined by two corner frequencies: the highpass and lowpass filter cut-off frequencies can be defined as, respectively, the low and high corner frequency of the bandpass filter. The highpass feature can also be used to attenuate the average DC and its drift in order to protect the electronic DC biasing.
Peripheral nerve recordings from LIFEs can be filtered from 300-600 Hz to 2.5-15 kHz (Malagodi, Horch et al. 1989; Goodall and Horch 1992; Yoshida and Horch 1996; Yoshida and Stein 1999; Dhillon, Lawrence et al. 2004). Usually, high-order highpass filters are used to attenuate the EMG signal while low-order lowpass filters are used to remove high-frequency noise. The EMG peak energy (about 250 Hz) explains the highpass filter cut-off frequency range, and high-order highpass filters can be used (respectively 5th and 8th order in (Yoshida and Horch 1996; Yoshida and Stein 1999) at 300 Hz and 600 Hz).
In an embodiment, the highpass and lowpass filter cut-off frequencies are defined between, respectively, 100-500 Hz and 5-10 kHz.
Providing a high common-mode gain is another method used for parasitic rejection. The CMRR is a result of the differential and common-mode gains.
An existing integrated recording circuit that uses an 85 dB-CMRR at 25 kHz for 74 dB amplification lead to approximately −10 dB of common mode amplification (Uranga, Navarro et al. 2004). Commercial recording systems usually provide a CMRR between 85 and 125 dB (CED 1902, CWE BMA-200, Grass Tech 15A12 DC/AC amplifier, as reviewed in (Uranga, Navarro et al. 2004)).
The final behavior of the common-mode rejection can be described as the system ability to attenuate the parasitic signal (e.g., EMG) while amplifying the signal-of-interest. The system could be then described as the attenuation of the output parasitic signal vs. the amplification of the signal-of-interest by an output attenuation factor (labeled N). The resultant CMRR is then defined as the ratio between the input parasitic signal amplitude by N and the input signal-of-interest. The CMRR is independent of the differential and common gains, which is represented by the N factor instead. Table 1 illustrates the different cases of couple input signal-of-interest/parasitic signal amplitude for N sets at 10 and 100. The CMRR range is 100V/V to 1 MV/V (40-120 dB).
In an embodiment, the CMRR can be defined to be between 30 kV/V and 1 MV/V (90 to 130 dB). Referring to Table 1, this can lead to a common-mode gain of 0.01-0.3 V/V (−40 dB to −10 dB) for a differential gain of 10 kV/V (80 dB).







TABLE 1







CMRR vs. output attenuation factor N
















Input signal-
Input parasitic

Output signal-
output
Output parasitic






of-interest
signal (EMG)
Differential
of-interest
attenuation
signal (EMG)
Common-mode
Common-mode
CMRR =


amplitude
amplitude
Gain Ad
amplitude
factor N
amplitude
Gain Ac
Gain Ac
Ad/Ac
CMRR


(μVpp)
(mVpp)
(kV/V)
(mVpp)
(V/V)
(mVpp)
(V/V)
(dB)
(V/V)
(dB)



















10
0.1
10
100
10
10
100
40
100
40



1




10
20
 1k
60



10




1
0
 10k
80



100




0.1
−20
100k
100



0.1


100
1
10
20
 1k
60



1




1
0
 10k
80



10




0.1
−20
100k
100



100




0.01
−40
1 Mega
120









Digital Chopper-Modulated Recording Amplifiers

The input-referred noise of chopper systems is often reported in terms of “average equivalent input white noise” since the Flicker noise has been suppressed by the chopper technique. For example, (Uranga, Navarro et al. 2004) reported an average equivalent input white noise of 6.6 nV/(Hz1/2), which is equivalent to 361 nVrms if integrated on a 3 kHz-bandwidth, or 466 nVrms if integrated on a 5 kHz-bandwidth.
In an embodiment, the input-referred noise of a circuit or circuit system as described herein is no more than 1.25 μVrms on 5 kHz-bandwidth, which is equivalent to an average equivalent input white noise of 173 nV/(Hz1/2). In a further embodiment, the input-referred noise of a circuit or circuit system as described herein is 1.25 μVrms on 5 kHz-bandwidth or about 1.25 μVrms on 5 kHz-bandwidth. In an alternative embodiment, the input-referred noise of a circuit or circuit system as described herein is no more than 1.25 μVrms on 3 kHz-bandwidth, which is equivalent to 22.8 nV/(Hz1/2). In a further embodiment, the input-referred noise of a circuit or circuit system as described herein is 1.25 μVrms on 3 kEz-bandwidth or about 1.25 μVrms on 3 kHz-bandwidth.
The invention includes, but is not limited to, the following embodiments:
Embodiment 1
A circuit, comprising a low noise amplifier, wherein the low noise amplifier comprises an operational transconductance amplifier (OTA) having at least two differential input series-connected transistors (SCT).
Embodiment 2
The circuit according to embodiment 1, wherein the low noise amplifier is configured such that: the area per channel of the low noise amplifier is no more than 0.10 mm2; the power consumption per channel of the low noise amplifier is no more than 200 μW; and the input-referred voltage noise density of the low noise amplifier is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.
Embodiment 3
The circuit according to embodiment 1, wherein the low noise amplifier is configured such that: the area per channel of the low noise amplifier is no more than 0.05 mm2; the power consumption per channel of the low noise amplifier is no more than 20 μW; and the input-referred voltage noise density of the low noise amplifier is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.
Embodiment 4
The circuit according to any of embodiments 1-3, further comprising a highpass filter in operable communication with the low noise amplifier.
Embodiment 5
The circuit according to embodiment 4, wherein the highpass filter is configured to tune the bandwidth in a range of about 100 Hz and 500 Hz.
Embodiment 6
The circuit according to any of embodiments 4-5, wherein the highpass filter is a passive resistor-capacitor filter circuit.
Embodiment 7
The circuit according to any of embodiments 4-6, further comprising a discrete gain amplifier in operable communication with the highpass filter.
Embodiment 8
The circuit according to embodiment 7, wherein the discrete gain amplifier is a programmable discrete gain amplifier.
Embodiment 9
The circuit according to any of embodiments 1 or 4-8, wherein the low noise amplifier is configured such that: the area per channel of the low noise amplifier is no more than 0.10 mm2; the power consumption per channel of the low noise amplifier is no more than 200 μW; and the input-referred voltage noise density of the low noise amplifier is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.
Embodiment 10
The circuit according to any of embodiments 1 or 4-8, wherein the implantable circuit is configured such that: the area per channel of the circuit is no more than 0.05 mm2; the power consumption per channel of the circuit is no more than 20 μW; and the input-referred voltage noise density of the circuit is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.
Embodiment 11
The circuit according to any of embodiments 7-10, further comprising at least one processing circuit in operable communication with the discrete gain amplifier.
Embodiment 12
The circuit according to embodiment 11, wherein the at least one processing circuit comprises a comparator.
Embodiment 13
The circuit according to any of embodiments 11-12, wherein the discrete gain amplifier is configured to adapt a signal from the highpass filter to the dynamic input voltage/current range of the at least one processing circuit.
Embodiment 14
The circuit according to any of embodiments 1-13, wherein the circuit is configured to record low amplitude neural signals having an amplitude of less than 60 μV peak-to-peak.
Embodiment 15
The circuit according to any of embodiments 1-14, wherein the circuit is configured to reject signals with frequency components outside a tunable bandwidth.
Embodiment 16
The circuit according to embodiment 14, wherein a minimum frequency of the tunable bandwidth is 100 Hz, and wherein a maximum frequency of the tunable bandwidth is 10 kHz.
Embodiment 17
The circuit according to any of embodiments 1, 2, or 4-16, wherein the area per channel of the low noise amplifier is no more than 0.05 mm2.
Embodiment 18
The circuit according to any of embodiments 1, 2, or 4-17, wherein the power consumption per channel of the low noise amplifier is no more than 20 μW.
Embodiment 19
The circuit according to any of embodiments 1-18, wherein the circuit is implantable (e.g., into a human subject).
Embodiment 20
A system for recording peripheral nerve activity, comprising:
the implantable circuit according to any of embodiments 1-19; and
at least one electrode in operable communication with the implantable circuit.
Embodiment 21
The system according to embodiment 20, wherein the at least one electrode is a longitudinal intrafascicular electrode.
Embodiment 22
A method of recording peripheral nerve activity, comprising:
implanting at least one electrode in or on at least one peripheral nerve;
providing the implantable circuit according to any of embodiments 1-19 (or the system according to any of embodiments (20-21) in operable communication with the at least one electrode; and
recording activity of the at least one peripheral nerve using the implantable circuit.
Embodiment 23
The method according to embodiment 22, wherein the low noise amplifier of the implantable circuit is configured such that: the area per channel of the low noise amplifier is no more than 0.05 mm2; the power consumption per channel of the low noise amplifier is no more than 20 μW; and the input-referred voltage noise density of the low noise amplifier is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.
Embodiment 24
An electronic circuit, wherein the circuit is configured to process neural activity to extract features,
wherein the circuit is configured such that: the area per channel of the circuit is no more than 0.10 mm2; the power consumption per channel of the circuit is no more than 200 μW; and the input-referred voltage noise density of the circuit is no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.
Embodiment 25
The electronic circuit according to embodiment 24, wherein the circuit is configured such that the area per channel of the circuit is no more than 0.05 mm2.
Embodiment 26
The electronic circuit according to any of embodiments 24-25, wherein the circuit is configured such that the power consumption per channel of the circuit is no more than 20 μW.
Embodiment 27
The electronic circuit according to any of embodiments 24-25, wherein the circuit is configured such that the power consumption per channel of the circuit is no more than 150 μW.
Embodiment 28
The circuit according to any of embodiments 1, 2, 4-9, 10-17, or 19, wherein the power consumption per channel of the low noise amplifier is no more than 150 μW.
Embodiment 29
The circuit according to any of embodiments 1, 2, 4-9, 10-17, or 19, wherein the power consumption per channel of the circuit is no more than 150 μW.
Embodiment 30
The system according to any of embodiments 20-21, wherein the power consumption per channel of the low noise amplifier is no more than 150 μW.
Embodiment 31
The method according to embodiment 22, wherein the power consumption per channel of the low noise amplifier is no more than 150 μW.
Following are examples that illustrate procedures for practicing the invention. These examples should not be construed as limiting.
Example 1
There are two main types of hardware architectures for neural amplifiers that have been published: digital design based chopper-modulation amplifiers; and analog amplifiers. Published specifications of low noise amplifiers for peripheral nerve recording indicate that these specifications are not conducive to design of an implantable chip with acceptable power/area characteristics.
A circuit as shown in FIG. 4 was prepared using 0.18 μm complementary metal oxide semiconductor (CMOS) process. Characteristics of the circuit, including input-referred noise density, were measured and compared with characteristics of low noise amplifier systems used for recording. Table 2 shows the results, with the circuit of the subject invention shown on the first row of data.
Originally designed for brain recording, the best low noise amplifiers that could potentially be used for peripheral nerve recording are also presented in Table 2 (rows 2-8). They present acceptable power, noise, and/or size consumption considerations. However, an amplifier according to the subject invention allows equivalent noise performance for lower power and area consumption.
FIG. 5 shows a plot of the input-referred noise density comparison between the amplifier of the subject and the three best low noise amplifiers used for brain recording. Referring to FIG. 5, the y-axis is input-referred noise density (V/Hz1/2), and the x-axis is frequency (Hz). The squares represent the circuit of the subject invention, the x's represent (Zhang, Hollerman et al. 2012), the triangles represent (Rezaee-Dehsorkh, Ravanshad et al. 2011), the diamonds represent (Harrison and Charles 2003), and the stars represent (Azin, Guggenmos et al. 2011). The bandwidth lowpass cut-off frequency of the overall recording system can be controlled with the additional amplifier (FIG. 2).
The circuit of the subject invention can also reach better noise performance by increasing the power consumption, with equivalent area consumption. Such a design is equivalent to the noise performance offered by (Uranga, Navarro et al. 2004) and (Rieger 2011) but has the advantage that it could be incorporated into an implantable chip and wirelessly powered (low power/area consumption).







TABLE 2







Latest low noise amplifier designs with the best noise performance




















Input
Integration

Power








referred
bandwidth for
Amplification
consumption
Area




Design

Process
noise
Noise
gain
per channel
consumption
Amplifier filter


Application
type
Circuit
(μm CMOS)
(μVrms)
calculation
(dB)
(μW)
(mm2)
bandwidth



















Peripheral
Analog
Embodiment of
0.18
1.1
0.1-4 kHz
40
32.5
0.05*
80-100 kHz


Nerve

the subject











invention (3











shared channels)











(Limnuson, Tyler
1.5
1.95
0.3-6 kHz
60
1000
4.84*
(3 mHz)300 Hz-




et al. 2009)



(full)
(full system)

6 kHz




(Rieger 2011)
0.35
1.84
0.1-10 kHz
56
280
0.064
10-few kHz



Digital
(Uranga, Navarro
0.7
0.45
3 kHz
74
965
2.7*
N/A




et al. 2004)



(full)
for 1 LNA




Brain
Analog
(Zhang, Holleman
0.13
2.2
0.01 Hz-105
40
12
0.072
0.05 Hz-10.5 kHz




et al. 2012)


kHz








(Rezaee-Dehsorkh,
0.18
2.38
0.5 Hz-50 kHz
52-57
20.8
0.061
300 Hz-10 kHz




Ravanshad et al.











2011)











(Harrison and
1.5
2.2
0.5 Hz-50
40
80
0.8
0.025 Hz-7.2 kHz




Charles 2003)


kHz








(Azin, Guggenmos
0.35
2.3
1.1-12k
51.9-65.6
19.9-26.9
0.342
(1.1-525)-




et al. 2011)

3.12
0.5-50 kHz



(5.1k-12k)




(Lee, Lee et al.
0.5
4.08
1-10k
67.8-78  
75
N/A
N/A




2010)











(Wattanapanitch,
0.5
3.06
45-5.3k
40.8
7.56
0.16
N/A




Fee et al. 2007)











(Yin and
1.5
3.6
20-10 kHz
39.3, 45.6
27.2
0.201
(0.015-700)-




Ghovanloo 2007)






(40, 400, 3k, 4k)




(Majidzadeh,
0.18
3.5
10-100k
39.4
7.92
0.0625
10-7.2k




Schmid et al.











2011)











(Lopez, Prodanov
0.35
2.3-
1 Hz-6 kHz
40-75
231
0.97*
572 Hz-6.2 kHz




et al. 2012)

2.9



approx




Digital
(Chen, Yang et al.
0.18
0.9
10 kHz
60.8
18
0.33
0.8 Hz-200/10 kHz




2011)









Example 2
An implantable neural recording amplifier for use with longitudinal intrafascicular electrodes (LIFEs) was manufactured. It met the low noise and low power/area consumption specifications for low amplitude recordings.
The low noise architecture was similar to the design shown in FIG. 6 (Limunson, Tyler et al., 2009; Harrison and Charles, 2003) but the amplifier included an OTA and two SCTs as discussed herein. The C1 input capacitor provides an equivalent input impedance to the low noise amplifier several orders higher than the LIFE impedance (8 MΩ vs. ̃2-10 kΩ at 1 kHz). The low noise amplifier provides a tunable low corner frequency to allow rejection of EMG signals. The low noise amplifier area was 0.15 mm2, designed with a 0.18 μm CMOS process. This design offers lower power/area consumption for equivalent noise performance of the integrated circuits for cuff recordings. The low noise amplifier meets low noise performance for ultra-low amplitude recording ability and low power/area consumption for a 16-channel recording system.
The integrated circuit was designed using a TSMC 0.18 μm 1P2M CMOS process with a 1.0 femto-Farad (fF) metal-insulator-metal capacitor option. FIG. 8 shows a layout view for fabrication of the circuit for one channel.
The tuning sensitivity of the low corner frequency allows a wide range configuration (from a few Hertz to few kiloHertz) with a 650-850 mV range voltage control.
Monte Carlo simulations (mismatch and process) were performed for three design cases: the pre-layout schematic and post-layout designs at room (27° C.) and body temperature (37° C.). A unique tunable voltage for low corner frequency flow was set for all simulations (single post-layout simulation gives flow=90.8 Hz). Selected Monte Carlo simulation runs in which the resultant flow was between 60 and 140 Hz are presented. This resultant flow range was chosen in order to remove the filter bandwidth variation impact on the input-referred noise performance; only the overall noise of the integrated components was evaluated. This selection will meet future noise measurement requirements and allow flow tuning capability. Table 3 shows a comparison of the amplifier of the subject invention with low noise amplifiers used with cuff electrodes for peripheral nerve recording. The input-referred noise was determined for the post-layout case (37° C.). The comparison amplifiers are those disclosed in (Limnuson, Tyler et al. 2009), abbreviated in Table 3 as “Limnuson 2009”, and (Uranga, Navarro et al. 2004), abbreviated in Table 3 as “Uranga 2004”.
Referring to Table 4, Monte Carlo simulations show that the low noise amplifier mid-gain, noise, and power performances are consistent between the pre-layout and post-layout designs based on the standard deviation of each parameter over the 155 iterations.
An additional gain amplifier may be required to relax input range performance of the analog signal processing circuits. There is no advantage in increasing the low noise amplifier mid-gain because it mainly relies on the C1 input capacitance (Harrison and Charles, 2003). Increasing the input capacitance will drastically increase the chip silicon area. Moreover, the increase in C1 leads to a decrease in the equivalent input impedance, which will divide the input signal circuit between the electrode equivalent capacitor and the low noise input impedance.
The low noise amplifier of the subject invention showed equivalent or better noise performance than those reported in the cuff-recording literature, and also had a power low enough ( ̃200 μW/channel vs. ̃1 mW in the literature) to implement 16 recording channels in the integrated circuit (0.05 mm2/channel). This low noise amplifier for ultra-low amplitude recording is also suitable for intrafascicular recordings from sensory fascicles since these have an equivalent signal amplitude range (Lefurge, Goodall et al., 1991; Malagodi, Horch et al., 1989).
Referring again to Table 4, the implantable amplifier achieved a mid-gain of 36.7±0.9% dB, input-referred noise of 2.3±7% μVrms on 10 Hz to 10 kHz at 37° C., and a power of 194±3%μW.







TABLE 3







Performance comparison with other Low noise


amplifier designs for nerve recording










Parameters
Subject Invention
Uranga 2004
Limnuson 2009





Amplifier Architecture
Analog
Chopper
Analog


Input-referred noise
0.7 ± 2.3%
0.45
—


(μVrms), (top) 0.3-3
0.6 ± 2.3%
—
1.95


kHz (bottom) 0.3-6





kHz





Power (W)
194μ
  1 m*
965μ


Area (mm2)
0.15
2.7*
4.8*


Process
0.18 μm
0.7 μm
1.5 μm





*Performance reported for the full recording system, including additional filter and amplification circuits, and/or analog signal processing circuits.













TABLE 4







Monte Carlo simulated performances*











Pre-Layout
Post-Layout
Post-Layout


Parameters
(27° C.)
(27° C.)
(37° C.)





Mid-Gain (dB)
37.3 ± 0.9%
 36.7 ± 0.9%
36.7 ± 0.9%


Low corner frequency (Hz)
91.1 ± 24% 
75.1 ± 12%
116 ± 12%


Input referred noise on
 2.0 ± 11%
1.9 ± 6%
2.3 ± 7% 


10 Hz-10 kHz (μVrms)





Power (μW)
203 ± 3% 
203 ± 3% 
194 ± 3% 





*Selected Monte Carlo simulation (155 iterations) with the low corner frequency in 60-140 Hz. Mean and standard deviation are reported






All patents, patent applications, provisional applications, and publications referred to or cited herein (including those listed in the References section) are incorporated by reference in their entirety, including all figures and tables, to the extent they are not inconsistent with the explicit teachings of this specification.
It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application.
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## Claims

1. An implantable circuit, comprising a low noise amplifier, the low noise amplifier comprising an operational transconductance amplifier (OTA) having at least two differential input series-connected transistors (SCT), each differential input SCT including an input terminal that is directly connected to the input terminal of each other differential input SCT, the input terminal of each differential input SCT being connected to the same differential input of the OTA, and the at least two differential input SCTs being connected to each other such that the entire current flowing through each differential input SCT flows into every other differential input SCT.

2. The implantable circuit according to claim 1, wherein the low noise amplifier is configured such that: the area per channel of the low noise amplifier is no more than 0.05 mm2; the power consumption per channel of the low noise amplifier is more than 0 μW and no more than 150 μW; and the input-referred voltage noise density of the circuit is more than 0 nV/(Hz1/2) and no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and more than 0 nV/(Hz1/2) and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.

3. The implantable circuit according to claim 1, further comprising a highpass filter in operable communication with the low noise amplifier.

4. The implantable circuit according to claim 3, wherein the highpass filter is configured to tune the bandwidth in a range of about 100 Hz and 500 Hz.

5. The implantable circuit according to claim 3, wherein the highpass filter is a passive resistor-capacitor filter circuit.

6. The implantable circuit according to claim 3, further comprising a discrete gain amplifier in operable communication with the highpass filter.

7. The implantable circuit according to claim 6, wherein the discrete gain amplifier is a programmable discrete gain amplifier.

8. The implantable circuit according to claim 6, wherein the implantable circuit is configured such that: the area per channel of the circuit is no more than 0.05 mm2; the power consumption per channel of the circuit is more than 0 μW and no more than 150 μW; and the input-referred voltage noise density of the circuit is more than 0 nV/(Hz1/2) and no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and more than 0 nV/(Hz1/2) and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.

9. The implantable circuit according to claim 6, further comprising at least one processing circuit in operable communication with the discrete gain amplifier.

10. The implantable circuit according to claim 9, wherein the at least one processing circuit comprises a comparator.

11. The implantable circuit according to claim 9, wherein the discrete gain amplifier is configured to adapt a signal from the highpass filter to the dynamic input voltage/current range of the at least one processing circuit.

12. The implantable circuit according to claim 1, wherein the circuit is configured to record low amplitude neural signals having an amplitude of less than 60 μV peak-to-peak.

13. The implantable circuit according to claim 12, wherein the circuit is configured to reject signals with frequency components outside a tunable bandwidth.

14. The implantable circuit according to claim 13, wherein a minimum frequency of the tunable bandwidth is 100 Hz, and wherein a maximum frequency of the tunable bandwidth is 10 kHz.

15. The implantable circuit according to claim 14, wherein the area per channel of the low noise amplifier is no more than 0.05 mm2.

16. A system for recording peripheral nerve activity, comprising:
the implantable circuit according to claim 1; and
at least one electrode in operable communication with the implantable circuit.

17. The system according to claim 16, wherein the at least one electrode is a longitudinal intrafascicular electrode.

18. An implantable circuit, comprising:
a low noise amplifier;
a highpass filter in operable communication with the low noise amplifier;
a discrete gain amplifier in operable communication with the highpass filter; and
at least one processing circuit in operable communication with the discrete gain amplifier,
the low noise amplifier comprising an operational transconductance amplifier (OTA) having at least two differential input series-connected transistors (SCT), each input differential SCT including an input terminal that is directly connected to the input terminal of each other differential input SCT, each differential input SCT being connected to the same differential input of the OTA, and the at least two differential input SCI's being connected to each other such that the entire current flowing through each differential input SCT flows into every other differential input SCT, and
the implantable circuit being configured such that: the area per channel of the circuit is no more than 0.05 mm2; the power consumption per channel of the circuit is more than 0 μW and no more than 150 μW; and the input-referred voltage noise density of the circuit is more than 0 nV/(Hz1/2) and no more than 50 nV/(Hz1/2) on 100 Hz-4 kHz bandwidth and more than 0 nV/(Hz1/2) and no more than 30 nV/(Hz1/2) on the main white Gaussian noise contribution over the full bandwidth.

19. The implantable circuit according to claim 18, wherein the highpass filter is configured to tune the bandwidth in a range of about 100 Hz and 500 Hz,
wherein the highpass filter is a passive resistor-capacitor filter circuit,
wherein the discrete gain amplifier is a programmable discrete gain amplifier,
wherein the at least one processing circuit comprises a comparator,
wherein the discrete gain amplifier is configured to adapt a signal from the highpass filter to the dynamic input voltage/current range of the at least one processing circuit,
wherein the circuit is configured to record low amplitude neural signals having an amplitude of less than 60 μV peak-to-peak,
wherein the circuit is configured to reject signals with frequency components outside a tunable bandwidth,
wherein a minimum frequency of the tunable bandwidth is 100 Hz, and wherein a maximum frequency of the tunable bandwidth is 10 kHz, and
wherein the area per channel of the low noise amplifier is no more than 0.05 mm2.

20. A system for recording peripheral nerve activity, comprising:
the implantable circuit according to claim 18; and
at least one electrode in operable communication with the implantable circuit.

21. An implantable circuit, comprising a low noise amplifier, the low noise amplifier comprising:
an operational transconductance amplifier (OTA) having a first reference input, a first reference output, a first input, and a first output;
a first resistor and a first capacitor connected between the first reference input of the OTA and the first reference output of the OTA; and
a second resistor and a second capacitor connected between the first input of the OTA and the first output of the OTA,
the OTA comprising:
a first branch series-connected transistor (SCT) connected to the first reference input of the OTA; and
a second branch SCT connected to the first input of the OTA,

the first branch SCT having at least two first branch transistors, and
the second branch SCT having at least two second branch transistors.

22. The implantable circuit according to claim 21, wherein each first branch transistor comprises an input terminal that is directly connected to the input terminal of each other first branch transistor and directly connected to the first reference input of the OTA, and wherein each second branch transistor comprises an input terminal that is directly connected to the input terminal of each other second branch transistor and directly connected to the first input of the OTA.

23. The implantable circuit according to claim 22, wherein the first branch transistors include a first PMOS first branch transistor and a second PMOS first branch transistor,
wherein a drain of the first PMOS first branch transistor is connected to a source of the second PMOS first branch transistor,
wherein a gate of the first PMOS first branch transistor and a gate of the second PMOS first branch transistor are directly connected to each other,
wherein the second branch transistors include a first PMOS second branch transistor and a second PMOS second branch transistor,
wherein a drain of the first PMOS second branch transistor is connected to a source of the second PMOS second branch transistor, and
wherein a gate of the first PMOS second branch transistor and a gate of the second PMOS second branch transistor are directly connected to each other.