# Patent

## Title
Low power multi-phase driving method for liquid crystal display

## Abstract

A method for driving a display panel is disclosed. At the transitions of scan periods, common and pixel electrode are coupled together to receive one of the power supply voltage and the ground in one phase of a transition, and the common and pixel electrode are further coupled together to receive one of the power supply voltage and the ground in another phase of a consecutive transition, during which the common driver and the source driver of the display panel induce no power consumption.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driving method for liquid crystal display (LCD), and more particularly to a driving method for liquid crystal display wherein a low power consumption is achieved by multi-phase charging sharing.
2. Description of the Prior Art
FIG. 1 shows a typical active matrix LCD. The LCD 100 includes a matrix of rows and columns of display cells. Each display cell includes a TFT (thin film transistor) 104 on an upper substrate 102, wherein the voltage on a source line 108 is coupled to a pixel electrode 105 and charges a storage capacitor (not shown) connected thereto when the TFT 104 being turned on by the voltage on a gate line 107 during a scan period. Each storage capacitor helps to hold the voltage on the pixel electrode 105 when the TFT 104 is turned off beyond the scan period. The voltages on the gate lines 107 and source lines 108 are respectively generated by a gate driver 110 and source driver 106. Besides, a common electrode 112 is disposed on a lower substrate 116 facing the upper substrate 102. A common voltage driver 114 provides a common voltage to the common electrode 112. Thus, molecules of a liquid crystal layer (not shown) sealed between the upper and lower substrates are rotated in response to voltage differences between the source and common electrodes, which determines the brightness or/and color of each display cell.
FIG. 2 shows an equivalent circuit of the matrix of the display cells in the LCD shown in FIG. 1. The same elements in FIGS. 1 and 2 refer to the same symbols for clarity. In each of the display cells, a switch 208 is coupled between the source line 108 and one end of a capacitor 202, and controlled by the voltage signal on the gate line (not shown). The other end of the capacitor 202 is coupled to the common electrode 112. The switch 208 is formed by the TFT 104 shown in FIG. 1 while the capacitor 202 results from the parallel connection of the storage capacitor with a capacitor formed by the pixel electrode 105, liquid crystal (LC) layer and the common electrode 112. In each column of the display cells, a parasitic capacitor 302 is formed between the common electrode 112 and the source line 108.
FIG. 3 shows waveforms of a common and source voltage respectively on the common electrode 112 and source line 108 of one of the display cells shown in FIG. 2 during three consecutive scan periods in a traditional line inversion driving method. The common voltage Vcom is alternately pulled up and down to the high common voltage level VCOMH and the low common voltage level VCOML at each transition of scan periods. The transition period D1 starts from the middle of the first scan period and ends at the middle of the second scan period while the transition period D2 starts from the middle of the second scan period and ends at the middle of the third scan period. The voltages VCOMH and VCOML are provided by directly pumping a power supply voltage VCI up to 2VCI or down to −VCI through a DC/DC pumping circuit, wherein the power supply voltage is derived from a current source driver. The source voltage Vs is pulled by the (data) signal on the source line 108 to corresponding levels for generation of desired voltage differences +Vb, −Va and +Vc between the source and common electrodes of the display cell respectively during the three scan periods.
The power consumption P, resulting from each scan period transition of one display cell, of the source or common voltage driver is VDD×I, where VDD is the voltage supplied by the source or common voltage driver, and IAVG is the average current drawn from the source or common voltage driver during the transition period D1 or D2 (having the same length of the scan period). Since the equivalent load of each display cell is dominated by the parasitic capacitor Cload, the average current IAVG is approximately equal to the current flowing through the parasitic capacitor Cload and is derived by the equation:

IAVG=Cload×Vw×F  (1)

where Vw is the difference between the voltages across the parasitic capacitor Cload before and after the transition, and F is the scan rate (reciprocal of one scan period). Further, the voltage difference Vw is derived by the equation:

Vw=VPOS+|VNEG|  (2)

where VPOS is the positive one of the voltages across the parasitic capacitor Cload before and after the transition, and the VNEG is the negative one. Therefore, the power consumption P is derived by the following equation:

P=VDD×Cload×(VPOS+|VNEG|)×F  (3)

Accordingly, during the transition period D1, the power consumption is 2VCI×Cload×(Va+Vb)×F. During the transition period D2, the power consumption is 3VCI×Cload×(Va+Vc)×F. Thus, for the scan period starting from the middle of the transition period D1 and ending at the middle of the transition period D2, the average power consumption Ptotal is derived by the equation:

Ptotal=1⁄2×2VCI×Cload×(Va+Vb)×F+1⁄2×3VC1×Cload×(Va+Vc)×F  (4)

However, such a power consumption is relatively large. A power-saving driving method is necessary for improvement of the display device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved line inversion driving method for liquid crystal display to save more power by multi-phase charging sharing.
It is another object of the present invention to provide a method for driving a display panel wherein no power consumption of the common driver and the source driver of the display panel is induced during portions of the scan periods.
In accordance with the present invention, a low power multi-phase driving method for display panel is disclosed. In one embodiment, the common electrode is pulled to one of a first and second voltage level both provided by pumping a power supply voltage, and the pixel electrode is pulled to corresponding voltage levels for generation of the desired voltage differences for each display cell of the display panel. At the transitions of the scan periods, the common and pixel electrode are coupled together to receive the power supply voltage in one of several phases of the transition. Further, the common and pixel electrode are further coupled together to ground in another phase of the transition. In another embodiment, the common electrode is further coupled to the first voltage level while the voltage difference between the pixel electrode and the common electrode remains identical due to the charge holding across the corresponding parasitic capacitor of the display panel.



BRIEF DESCRIPTION OF THE DRAWINGS
The objectives, features of the present invention as well as the advantages thereof can be best understood through the following preferred embodiments and the accompanying drawings, wherein:
FIG. 1 shows a conventional active matrix LCD;
FIG. 2 shows an equivalent circuit of the matrix of the display cells in the LCD shown in FIG. 1;
FIG. 3 shows waveforms of a common and source voltage respectively on the common electrode and source line of one of the display cells shown in FIG. 2;
FIG. 4 shows a display device according to one embodiment of the invention;
FIG. 5 shows waveforms of a common and source voltage respectively on the common electrode and source line of one of the display cells shown in FIG. 4 according to one embodiment of the invention;
FIG. 6 shows waveforms of a common and source voltage respectively on the common electrode and source line of one of the display cells shown in FIG. 4 according to another embodiment of the invention;
FIG. 7 shows a first special case of the second embodiment in FIG. 6; and
FIG. 8 shows a second special case of the second embodiment in FIG. 6.



DESCRIPTION OF THE PREFERRED EMBODIMENT
The invention will be explained in detail in accordance with the accompanying drawings. It is necessary to illustrate that the drawings below could be in simplified forms and not drawn in proportion to the real cases. Further, the dimensions of the drawings are enlarged for explaining and understanding more clearly.
FIG. 4 shows a display device according to one embodiment of the invention. The same elements in FIGS. 2 and 4 refer to the same symbols for clarity. The switches controlled by the signals SC1, SC2, SC3 and SC4 are coupled between the common electrode 112 and nodes receiving the voltages VCOMH, VCOML, VCI and a ground voltage GND, respectively. Each of the switches controlled by the signal SS1 is coupled between the source line 108 and a node receiving one of the voltages (data signals) DA_1, DA_2, . . . and DA_n. Each of the switches controlled by the signal SS2 is coupled between the source line 108 and a node receiving the voltage VCI. Each of the switches controlled by the signal SS3 is coupled between the source line 108 and ground.
FIG. 5 shows waveforms of the common and source voltage respectively on the common electrode 112 and source line 108 of one of the display cells in the display device shown in FIG. 4 during three consecutive scan periods in a line inversion driving method according to one preferred embodiment of the invention. Similarly to FIG. 3, the common voltage Vcom is pulled up and down to VCOMH and VCOML during the two consecutive transition periods D1 and D2, respectively. The source voltage Vs is pulled by the signal DA_1, DA_2, . . . or DA_n on the source line 108 to corresponding levels for generation of desired voltage differences +Vb, −Va and +Vc between the source and common electrodes of the display cell respectively during the three scan periods. It is noted that the transition period D1 is composed of 3 phases D11, D12 and D13, and the transition period D2 is composed of 3 phases D21, D22 and D23.
Initially, during the phase D11, only the two switches controlled by the signals SC2 and SS1 are closed, whereby the voltages Vcom and Vs are VCOML and VCOML+Vb. During the phase D12, the two switches controlled by the signals SC2 and SS1 are opened while those controlled by the signals SC3 and SS2 are closed so that the source line 108 and common electrode 112 are coupled together to receive the voltage VCI, whereby the voltages Vcom and Vs are pulled up to VCI. During the phase D13, the two switches controlled by the signals SC3 and SS2 are opened while those controlled by the signals SC1 and SS1 are closed so that the source line 108 and common electrode 112 are respectively coupled to receive the voltages VCOMH and the corresponding signal DA_1, DA_2, . . . or DA_n, whereby the voltages Vcom and Vs are pulled to VCOMH and VCOMHL−Va.
During the phase D21, the switches controlled by the signals SC1 and SS1 stay closed and the voltages Vcom and Vs remain at VCOMH and VCOMH−Va. During the phase D22, the two switches controlled by the signals SC1 and SS1 are opened while those controlled by the signals SC4 and SS3 are closed so that the common electrode 112 and the source line 108 are coupled together to the ground, whereby the voltages Vcom and Vs are pulled down to GND. During the phase D23, the two switches controlled by the signals SC4 and SS3 are opened while those controlled by the signals SC2 and SS1 are closed so that the common electrode 112 and the source line 108 are coupled to receive the voltages VCOML and the corresponding data signal DA_1, DA_2, . . . or DA_n, whereby the voltages Vcom and Vs are pulled to VCOML and VCOML+VC.
It is noted that no power consumption of the common voltage or source driver is induced during the phases D12 and D22 although the voltages Vcom and Vs are varied. This is because, during the phases D12 and D22, the source and common electrodes are coupled together, which results in a voltage difference of zero therebetween. Thus, the average power consumption Ptotal during the scan period starting from the middle of the transition period D1 and ending at the middle of the transition period D2 is derived by the equation:

Ptotal=1⁄2×PD13+1⁄2×PD23  (5)

where PD13 and PD23 are the power consumptions during the phases D13 and D23 respectively. Further, according to the equation (3), the average power consumption Ptotal is derived by:

Ptotal=1⁄2×2VCI×Cload×Va×F+1⁄2×3VCI×Cload×Vc×F  (6)

By comparison of the equations (4) and (6), it is noted that the average power consumption in the previously described embodiment is less than that in the prior art. For example, when VCOMH=4.5V, VCOML=1V, VCI=2.8V, Va=2.3V, Vb=3.2V and Vc=2.3V, the average power consumption caused by the traditional line inversion driving method is 13.75 Cload×F while that caused by the previously described line inversion driving method is 7.1Cload×F.
FIG. 6 shows waveforms of the common and source voltage respectively on the common electrode 112 and source line 108 of one of the display cells in the display device shown in FIG. 4 during three consecutive scan periods in a line inversion driving method according to another embodiment of the invention. Similarly to FIG. 5, the common voltage Vcom is pulled up and down to VCOMH and VCOML during the two consecutive transition periods D1 and D2, respectively. The source voltage Vs is pulled by the signal DA_1, DA_2, . . . or DA_n on the source line 108 to corresponding levels for generation of desired voltage difference +Vb, −Va and +Vc between the source and common electrodes of the display cell respectively during the three scan periods. It is noted that the transition period D1 is composed of 4 phases D11, D12, D13 and D14, and the transition period D2 is composed of 5 phases D21, D22, D23, D24 and D25.
Initially, during the phase D11, only the two switches controlled by the signals SC2 and SS1 are closed, whereby the voltage Vcom and Vs are VCOML and VCOML+Vb. During the phase D12, the two switches controlled by the signal SC2 and SS1 are opened while those controlled by the signals SC3 and SS2 are closed so that the source line 108 and common electrode 112 are coupled together to receive the voltage VCI, whereby the voltages Vcom and Vs are pulled up to VCI. During the phase D13, the switch controlled by the signal SC3 is opened and the switches controlled by the signal SS2 stay closed while the switch controlled by the signal SC1 is closed, whereby the voltage Vcom is pulled to VCOMH and the voltage Vs remains at VCI. During the phase D14, the switch controlled by the SC1 stays closed and the switches controlled by the signal SS2 are open while the switches controlled by the signal SS1 are closed and the source lines 108 are coupled to receive the corresponding signal DA_1, DA_2, . . . or DA_n, whereby the voltage Vcom remains at VCOMH and Vs are pulled to VCOML−Va.
During the phase D21, the switches controlled by the signals SC1 and SS1 stay closed and the voltages Vcom and Vs remain at VCOMH and VCOML−Va. During the phase D22, the two switches controlled by the signals SC1 and SS1 are opened while those controlled by the signals SC3 and SS2 are closed so that the common electrode 112 and the source line 108 are coupled together to receive the voltage VCI, whereby the voltages Vcom and Vs are pulled down to VCI. During the phase D23, the switches controlled by the signal SS2 stay closed and the switch controlled by the signal SC3 is opened while the switch controlled by the signal SC4 is closed so that the common electrode 112 is coupled to the ground, whereby the voltage Vcom is pulled down to GND and the voltage Vs remains at VCI. During the phase D24, the switches controlled by the signal SS2 and SC4 are opened while the switch controlled by the SC2 is closed so that the common electrode 112 is coupled to receive the voltage VCOML, whereby the voltage Vcom is pulled to VCOML and the voltage Vs is accordingly pulled down to VCOML+VCI since the voltage across the parasitic capacitor still holds at VCI. During the phase D25, the switch controlled by the SC2 stays closed while the switches controlled by the signal SS1 are closed so that the voltage Vcom remains at VCOML and the source lines 108 are coupled to received the corresponding signal DA_1, DA_2, . . . or DA_n, whereby the voltage Vcom and Vs are pulled to VCOML and VCOML+VC, wherein the sum of the Vc1 and Vc2 is equal to VC as shown in FIG. 6.
It is noted that no power consumption of the common driver or source driver is induced during the phases D12, D22 as well as D24 although the voltage Vcom and Vs are varied. This is because, during the phases D12 and D22, the source and common electrodes are coupled together, which results in a voltage difference of zero therebetween, while during the phase D24, the common voltage Vcom is pulled to VCOML as well as the source line is decoupled from any charging operation, thereby the source voltage Vs would accordingly change from VCI to VCOML+VC1 along with the variation of the common voltage Vcom from GND to VCOML, which does not consume any extra power. Thus, the average power consumption Ptotal during the scan period starting from the middle of the transition period D1 and ending at the middle of the transition period D2 is derived by the equation:

Ptotal=1⁄2×(PD13+PD14)+1⁄2×(PD23+PD25)  (7)

where PD13, PD14, PD23 and PD25 are the power consumptions during the phases D13, D14, D23 and D25 respectively. It is noted that, during the phase D13, for the reason that the source voltage Vs is at VCI and the common voltage is pulled to 2VCI (i.e., VCOMH), the charging current within the Cload would flow from the common electrode to the pixel electrode, in other words, a power energy PRE={1⁄2×(2VCI−VCI)×Cload×Va1×F} would be charged back to the power supply coupled to the pixel electrode. So, as the whole concerned, the actual total power consumption during the phase D13 is equal to PD13−PRE=1⁄2×VCI×Cload×Va1×F, where Va1 is equal to VCI. Besides, it is also noted that, during the phase D23, since the common voltage Vcom finally reaches GND and the source voltage is at VCI, which is just equal to the power supply voltage, the charging operation to make the voltage across the capacitor Cload from 0 to +Vc1 is mainly driven by the source voltage (VCI) and that is like the power supply directly charges the capacitor Cload through the source electrode without any pumping operation. Thus, the equivalent power consumption during the phase D23 is equal to PD23=1⁄2×VCI×Cload×Vc1×F, where Vc1 is equal to VCI. Further, according to equation (6), the average power consumption Ptotal in this embodiment is derived by:

Ptotal=1⁄2×2VCI×Cload×Va×F+1⁄2×VCI×Cload×Va1×F+1⁄2×VCI×Cload×Vc1×F+1⁄2×3VCI×Cload×Vc×F  (8)

Similarly, by comparison of the equations (4), (6) and (8), it is noted that the average power consumption in the second embodiment described above is less than that in the prior art and even less than that in the first embodiment earlier described. For example, when VCOMH=4.5V, VCOML=1V, VCI=2.8V, Va=2.3V, Vb=3.2V and Vc=2.3V, the average power consumption caused by the previously described line inversion driving method in FIG. 6 is 3.85 Cload×F while that caused by the first embodiment is 7.1Cload×F and that caused by the traditional line inversion driving method is 13.75 Cload×F.
FIG. 7 shows a first special case of the second embodiment in FIG. 6. The first special case is applicable when the value of the desired voltage difference −Va is equal to the voltage difference between the common voltage VCOMH and the power supply voltage VCI. The line inversion driving method of the first special case in FIG. 7 is the same as that in FIG. 6 except that no phase D14 exists in the first special case. As the phase D14 is no longer required, and therefore the average power consumption could be further conserved.
FIG. 8 shows a second special case of the second embodiment in FIG. 6. The second special case is applicable when the value of the desired voltage difference Vc1 is equal to the voltage difference between the power supply voltage VCI and the ground level GND (that is, VCI) as shown in FIG. 8. The line inversion driving method of the second special case in FIG. 8 is the same as that in FIG. 6 except that no phase D25 exists in the second special case. As the phase D25 is no longer required, and therefore the average power consumption could be further conserved. Specifically, in FIG. 8, during the phase D24, after the source voltage Vs is naturally pulled down to the VCOML+VCI and the common voltage Vcom is pulled to VCOML, the source voltage Vs would be maintained at VCOML+VCI (as the dotted line shown) without any charging operation due to the fact that the voltage across the capacitor still hold at Vc1 (or VCI) at this time. Thus, the average power consumption caused by the phase D25 of the second embodiment would be conserved in the second special case.
For the discussion described above, the present invention provides a low power multi-phase driving method for liquid crystal display, wherein the transition of the scan periods is divided into several phases through temporarily coupling the pixel electrode and the common electrode together to receive the power supply voltage or to the ground level as well as pulling the source voltage and the common voltage to different voltage levels. Accordingly, the present invention conserves a great deal of power compared to the traditional method.
Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from the spirit which is intended to be limited solely by the appended claims.

## Claims

1. A method for driving a display panel having an array of display cells wherein brightness of each display cell is determined by desired voltage differences between a pixel and common electrode during a plurality of scan periods, the method comprising the steps of:
at transitions of the scan periods, pulling a voltage on the common electrode to one of a first and second voltage level both provided by pumping a power supply voltage, and pulling a voltage on the pixel electrode to corresponding voltage levels for generation of the desired voltage differences for each display cell; and
wherein the common and pixel electrode are coupled together to receive the power supply voltage in one of a plurality phases of the transition.

2. The method according to claim 1, wherein said common and pixel electrode are further coupled together to ground in another of the plurality phases of a consecutive transition.

3. The method according to claim 1, wherein said first voltage level is provided by pumping the power supply voltage down to minus the power supply voltage, and said second voltage level is provided by pumping the power supply voltage up to two times the power supply voltage.

4. The method according to claim 1, wherein said plurality of phases of the transition comprise three phases during which the common electrode is pulled from the first voltage level to the second voltage level higher than the first voltage level:
a first phase wherein the common electrode is coupled to receive the first voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell;
a second phase wherein the common and pixel electrode are coupled together to receive the power supply voltage; and
a third phase wherein the common electrode is coupled to receive the second voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell.

5. The method according to claim 4, wherein said plurality of phases of a consecutive transition comprises three phases during which the common electrode is pulled from the second voltage level to the first voltage level lower than the second voltage level:
a first phase wherein the common electrode is coupled to receive the second voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell;
a second phase wherein the common and pixel electrode are coupled together to ground; and
a third phase wherein the common electrode is coupled to receive the first voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell.

6. The method according to claim 1, wherein said common and pixel electrode are further coupled together to the power supply voltage in another of the plurality phases of a consecutive transition.

7. The method according to claim 6, wherein said common electrode is further coupled to ground and the pixel electrode is coupled to the power supply voltage in another of the plurality phases of the consecutive transition.

8. The method according to claim 7, wherein said common electrode is further coupled to the first voltage level while the voltage difference between the pixel electrode and the common electrode remains identical due to charge holding across a corresponding parasitic capacitor.

9. The method according to claim 1, wherein said plurality of phases of the transition comprise four phases during which the common electrode is pulled from the first voltage level to the second voltage level higher than the first voltage level:
a first phase wherein the common electrode is coupled to receive the first voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell;
a second phase wherein the common and pixel electrode are coupled together to receive the power supply voltage;
a third phase wherein the common electrode is coupled to receive the second voltage level, and the pixel electrode is coupled to the power supply voltage; and
a fourth phase wherein the common electrode is coupled to the second voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell.

10. The method according to claim 9, wherein said plurality of phases of a consecutive transition comprise five phases during which the common electrode is pulled from the second voltage level to the first voltage level lower than the second voltage level:
a first phase wherein the common electrode is coupled to the second voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell;
a second phase wherein the common and pixel electrode are coupled together to the power supply voltage;
a third phase wherein the common electrode is coupled to the ground and the pixel electrode is coupled to the power supply voltage;
a fourth phase wherein the common electrode is coupled to the first voltage level while the voltage difference between the pixel electrode and the common electrode remains identical due to charge holding across a corresponding parasitic capacitor; and
a fifth phase wherein the common electrode is coupled to the first voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell.

11. The method according to claim 1, wherein said plurality of phases of the transition comprise three phases during which the common electrode is pulled from the first voltage level to the second voltage level higher than the first voltage level:
a first phase wherein the common electrode is coupled to receive the first voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell;
a second phase wherein the common and pixel electrode are coupled together to receive the power supply voltage; and
a third phase wherein the common electrode is coupled to receive the second voltage level, and the pixel electrode is coupled to the power supply voltage.

12. The method according to claim 11, wherein said plurality of phases of a consecutive transition comprise five phases during which the common electrode is pulled from the second voltage level to the first voltage level lower than the second voltage level:
a first phase wherein the common electrode is coupled to the second voltage level, and the pixel electrode is coupled to the poser supply voltage;
a second phase wherein the common and pixel electrode are coupled together to the power supply voltage;
a third phase wherein the common electrode is coupled to the ground and the pixel electrode is coupled to the power supply voltage;
a fourth phase wherein the common electrode is coupled to the first voltage level while the voltage difference between the pixel electrode and the common electrode remains identical due to charge holding across a corresponding parasitic capacitor; and
a fifth phase wherein the common electrode is coupled to the first voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell.

13. The method according to claim 1, wherein said plurality of phases of the transition comprise four phases during which the common electrode is pulled from the first voltage level to the second voltage level higher than the first voltage level:
a first phase wherein the common electrode is coupled to receive the first voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell;
a second phase wherein the common and pixel electrode are coupled together to receive the power supply voltage;
a third phase wherein the common electrode is coupled to receive the second voltage level, and the pixel electrode is coupled to the power supply voltage; and
a fourth phase wherein the common electrode is coupled to the second voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell.

14. The method according to claim 13, wherein said plurality of phases of a consecutive transition comprise four phases during which the common electrode is pulled from the second voltage level to the first voltage level lower than the second voltage level:
a first phase wherein the common electrode is coupled to the second voltage level, and the pixel electrode is coupled to receive corresponding voltage levels for generation of the desired voltage differences for each display cell;
a second phase wherein the common and pixel electrode are coupled together to the power supply voltage;
a third phase wherein the common electrode is coupled to the ground and the pixel electrode is coupled to the power supply voltage; and
a fourth phase wherein the common electrode is coupled to the first voltage level while the voltage difference between the pixel electrode and the common electrode remains identical due to charge holding across a corresponding parasitic capacitor.

15. A method for driving a display panel having an array of display cells wherein brightness of each display cell is determined by desired voltage differences between a pixel and common electrode during, a plurality of scan periods, the method comprising the steps of:
at transitions of the scan periods, pulling a voltage on the common electrode to one of a first and second voltage level, and pulling a voltage on the pixel electrode to corresponding voltage levels for generation of the desired voltage differences for each display cell; and
wherein the common and pixel electrode are coupled together to receive one of the power supply voltage and ground in one transition of the scan periods, and the common and pixel electrode are further coupled together to receive one of the power supply voltage and the ground in a consecutive transition of the scan periods, during which a common driver and a source driver induce no power consumption.

16. The method according to claim 15, wherein said common electrode is further coupled to the first voltage level while the voltage difference between the pixel electrode and the common electrode remains identical due to charge holding across a corresponding parasitic capacitor.

17. The method according to claim 15, wherein said first voltage level is provided by pumping the power supply voltage down to minus the power supply voltage, and said second voltage level is provided by pumping the power supply voltage up to two times the power supply voltage.