# Patent

## Title
MOSFET temperature compensation current source

## Abstract

A current source generates a constant current using metal oxide semiconductor (MOS) transistors. A biasing circuit generates a biasing current based on the transconductance of the MOS transistors. A load circuit, comprising a resistor coupled in parallel with a MOS transistor, generates a constant load current from the biasing current. The load current comprises the sum of a resistor current, which flows through the resistor, and a MOS current that flows through the transistor. The load current is constant because variations of the resistor current offset variations of the MOS current across temperature or process variations. A current mirror circuit generates an output current for the current source equal to a sum of the resistor current and the MOS current, the output current being approximately constant in value across temperature or process variations.

## Background
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Patent Application No. 60/660,728, filed Mar. 11, 2005, entitled “A MOSFET Temperature Compensation Current Source.”


FIELD OF THE INVENTION
The present invention is directed towards the field of temperature compensation current sources.
BACKGROUND OF THE INVENTION
Current sources are components commonly used in metal oxide semiconductor field effect transistors (MOSFETs). These current sources can be sensitive to temperature or process variations and produce an unstable and variable output current across a range of temperatures and process variations. Typically, current sources are designed to provide a constant current across temperature or process variations using junction diodes. FIG. 1 shows a conventional current source 100 implementing a junction diode 105 to achieve band gap voltage under full complementary metal oxide semiconductor (CMOS) processes. Under CMOS processes, however, junction diodes require large areas on a circuit.
Therefore, there is a need for a constant current source that does not vary significantly with temperature or process variations that requires less area on a circuit.
SUMMARY OF THE INVENTION
Some embodiments provide a current source that generates a constant current using metal oxide semiconductor (MOS) transistors. A biasing circuit generates a biasing current based on the transconductance of the MOS transistors. A load circuit generates a load current from the biasing current. In one embodiment, the load circuit comprises a resistor coupled in parallel with a MOS device (e.g., MOS transistor) having a resistance (RMOS). The load current comprises the sum of a resistor current, which flows through the resistor, and a MOS current that flows through the MOS device.
The biasing current generated by the biasing circuit is constant except under temperature or process variations which may cause the biasing current to increase or decrease (due to the effect of temperature or process variations upon the transconductance of the MOS transistors). An increase or decrease in the biasing current (caused by temperature or process variations) produces an increase or decrease, respectively, in the resistor current that flows through the resistor of the load circuit. Temperature or process variations, however, also have an effect on the resistance value (RMOS) of the MOS device of the load circuit and cause the resistance value RMOS to increase or decrease. The changes in the resistance value RMOS also causes a change in the MOS current that flows through the MOS device, whereby the change in MOS current offsets the change in the resistor current to produce a relatively constant load current.
For example, if temperature or process variations cause the biasing current to increase, the resistor current through the resistor of the load circuit increases. These temperature or process variations, however, also cause the resistance RMOS of the MOS device of the load circuit to increase, thereby causing the MOS current through the MOS device to decrease. Therefore, the decrease in the MOS current approximately offsets the increase in the resistor current to produce a relatively constant load current of the load circuit. Likewise, if temperature or process variations cause the biasing current to decrease, the resistor current through the resistor of the load circuit decreases. These temperature or process variations, however, also cause the resistance RMOS of the MOS device of the load circuit to decrease, thereby causing the MOS current through the MOS device to increase. Therefore, the increase in the MOS current approximately offsets the decrease in the resistor current to produce a relatively constant load current of the load circuit. As such, the changes in the biasing current due to temperature or process variations is, in effect, approximately offset by a change in the MOS current (of the MOS device of the load circuit) due to the same temperature or process variations.
Thus, the load current is relatively constant because variations of the biasing current and the resistor current are offset by variations of the MOS current across temperature or process variations. An output current of the current source is also equal to a sum of the resistor current and the MOS current. In one embodiment, the output current is output from a current mirror circuit that mirrors the load current as the output current. In some embodiments, the current source produces a stable output current (Iout) that does not vary significantly across temperatures and process variations, the current source being implemented without use of a junction diode.
In one embodiment, the biasing circuit comprises first and second transistor pairs. The first transistor pair generates a first transconductance between a reference voltage and the load circuit, and the second transistor pair generates a second transconductance between the reference voltage and ground. For this embodiment, the first transistor pair comprises a size greater than the second transistor pair (e.g., four times the size)



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a conventional current source implementing a junction diode.
FIG. 2 is a block diagram illustrating a constant current source of some embodiments.
FIG. 3 is a block diagram illustrating detail of a constant current source of some embodiments.
FIG. 4 is a flowchart showing a method for generating a constant current using metal oxide semiconductor (MOS) transistors.
FIG. 5 is a circuit analysis diagram of a non-constant current source.
FIG. 6 is a circuit analysis diagram of the constant current source of FIG. 3.
FIG. 7 is a graph that shows the output currents of a constant current source and a non-constant current source as a function of the transconductance parameter KP.



DETAILED DESCRIPTION
The disclosure of U.S. Provisional Patent Application No. 60/660,728, filed Mar. 11, 2005, entitled “A MOSFET Temperature Compensation Current Source,” is hereby expressly incorporated herein by reference.
Although the present invention is described below in terms of specific exemplary embodiments, one skilled in the art will realize that various modifications and alterations may be made to the below embodiments without departing from the spirit and scope of the invention.
In the discussion below, Section I describes a constant current source and a method for generating a constant current. Section II describes characteristics of a non-constant current source and a constant current source. And Section III discusses output currents of current sources as a function of the transconductance parameter.
I. Constant Current Source
FIG. 2 is a block diagram illustrating a constant current source 200 of some embodiments. The constant current source 200 comprises a biasing circuit 205, a load circuit 210, and a current mirror circuit 215. The biasing circuit 205 comprises a plurality of metal oxide semiconductor (MOS) transistors for generating a biasing current based on transconductance of the MOS transistors.
The load circuit 210 is coupled to the biasing circuit 205 and comprises at least one resistor and at least one MOS device coupled in parallel with the at least one resistor. As described below, the MOS device of the load circuit 210 is a MOS transistor. In other embodiments, however, the MOS device is any other type of metal oxide semiconductor device. The load circuit 210 receives the biasing current from the biasing circuit 205 and generates a constant load current from the biasing current. In particular, the load circuit 210 generates a resistor current (Ir) that flows through the resistor and a MOS current (It) that flows through the MOS transistor, the load current being the sum of a resistor current and the MOS current. The load current is relatively constant because variations of the resistor current are offset by variations of the MOS current across temperature or process variations (i.e., the resistor and MOS currents balance each other to produce a constant load current).
The current mirror circuit 215 is coupled to the biasing circuit 205 and generates an output current (Iout) equal to a sum of the resistor current (Ir) and the MOS current (It). The current mirror circuit 215 mirrors the load current of the load circuit 210 as the output current (Iout). In some embodiments, the current source 200 produces a stable output current (Iout) that does not vary significantly across temperatures and process variations, the current source being implemented without use of a junction diode.
If the current source 200 is to produce a constant output current of value A, the first current has a value of B, and the second current has a value of C, then A=B+C. If the first current changes in value, the second current balances the first current so that the output current is still approximately equal to A. For example, if temperature or processing variations cause the first current to increase in value to equal (B+delta), the value of the second current would thereby decrease in value to approximately equal (C−delta) so that the sum of the first and second currents is still approximately equal to A. Conversely, if temperature or processing variations cause the first current to decrease in value to equal (B−delta), the value of the second current would thereby increase in value to approximately equal (C+delta) so that the sum of the first and second currents is still approximately equal to A.
FIG. 3 is a block diagram illustrating detail of a constant current source 300 of some embodiments. The constant current source 200 comprises a biasing circuit 205, a load circuit 210, and a current mirror circuit 215.
The biasing circuit 205 comprises a plurality of metal oxide semiconductor (MOS) transistors Q1 (305), Q2 (310), Q3 (315), and Q4 (320). As shown in FIG. 3, a gate of the transistor Q3 is coupled to a drain of transistor Q3, a source of transistor Q3 is coupled to a gate of transistor Q1, and a source of transistor Q1 is coupled to the load circuit, a drain of transistor Q2 is coupled to the source of transistor Q3, a source of transistor Q2 is coupled to ground, a gate of the transistor Q2 is coupled to a source of transistor Q4 and to the drain of transistor Q1, and the gate of the transistor Q3 is coupled to the gate of transistor Q4.
The biasing circuit 205 receives a starting current (Ista) and generates a regulated biasing current based on transconductance of the MOS transistors Q1 (305), Q2 (310), Q3 (315), and Q4 (320). In particular, the biasing circuit 205 comprises a first transistor pair Q1 (305) and Q3 (315) and a second transistor pair Q2 (310) and Q4 (320). The first transistor pair Q1 (305) and Q3 (315) generates a first transconductance between a reference voltage and the load circuit 210. The second transistor pair Q2 (310) and Q4 (320) generates a second transconductance between the reference voltage and ground.
The load circuit 210 is coupled to the biasing circuit 205 and comprises a resistor 325 coupled in parallel with a MOS transistor Q8 (330). The load circuit 210 receives the biasing current from the biasing circuit 205 and generates a constant load current from the biasing current. The load circuit 210 generates a resistor current (Ir) through the resistor 325 and a MOS current (It) through the MOS transistor 330, whereby load current equals resistor current (Ir)+MOS current (It).
The biasing current generated by the biasing circuit 205 is constant except under temperature or process variations which may cause the biasing current to increase or decrease (due to the effect of temperature or process variations upon the transconductance of the MOS transistors Q1 to Q4 of the biasing circuit 205). An increase or decrease in the biasing current (caused by temperature or process variations) produces an increase or decrease, respectively, in the resistor current (Ir) through the resistor 325 of the load circuit 210. Temperature or process variations, however, also have an effect on the resistance value (RMOS) of the MOS device 330 of the load circuit 210 and cause the resistance value RMOS to increase or decrease. The changes in the resistance value RMOS also causes a change in the MOS current (It) that flows through the MOS device 330, whereby the change in MOS current (It) offsets the change in the resistor current (Ir) to produce a relatively constant load current.
For example, if temperature or process variations cause the biasing current to increase, the resistor current (Ir) through the resistor 325 of the load circuit 210 increases. These temperature or process variations, however, also cause the resistance RMOS of the MOS device 330 of the load circuit 210 to increase, thereby causing the MOS current (It) through the MOS device 330 to decrease. Therefore, the decrease in the MOS current (It) offsets the increase in the resistor current (Ir) to produce a relatively constant load current of the load circuit 210. Likewise, if temperature or process variations cause the biasing current to decrease, the resistor current (Ir) through the resistor 325 of the load circuit decreases. These temperature or process variations, however, also cause the resistance RMOS of the MOS device 330 of the load circuit to decrease, thereby causing the MOS current (It) through the MOS device to increase. Therefore, the increase in the MOS current (It) offsets the decrease in the resistor current (Ir) to produce a relatively constant load current of the load circuit. As such, the changes in the biasing current due to temperature or process variations is, in effect, approximately offset by a change in the MOS current (of the MOS device of the load circuit) due to the same temperature or process variations. Thus, the load current is relatively constant because variations of the biasing current and resistor current (Ir) are offset by variations of the MOS current (It) across temperature or process variations.
As shown in FIG. 3, the voltage drop through transistors Q1 and Q3 and the resistor 325 is equal to the voltage drop through transistors Q2 and Q4. This can be shown by the following observations:

    
    
        the voltage at the gate of transistor Q3 is equal to the voltage at the gate of transistor Q4 (indicated by point V in FIG. 3);
        the gate to source voltage of Q3 (VGS3) plus the gate to source voltage of Q1 (VGS1) plus the voltage across the resistor 325 (Ir*R) is equal to the gate to source voltage of Q4 (VGS4) plus the gate to source voltage of Q2 (VGS2) so that:

V=VGS3+VGS1+Ir*R=VGS4+VGS2

        the drain to source voltage of Q8 (VDS8) is equal to the voltage across the resistor 325 (Ir*R) so that:

VDS8=Ir*R

    
    


As such, in some embodiments, the first transistor pair Q1 (305) and Q3 (315) comprises transistors that are larger in size than the transistors of the second transistor pair Q2 (310) and Q4 (320) to accommodate the additional voltage drop (Ir*R) across the resistor 325 (which lies in the voltage drop path of transistors Q1 and Q3). In one embodiment, the size of transistors Q1 and Q3 are four times the size of transistors Q2 and Q4.
The current mirror circuit 215 is coupled to the biasing circuit 205 and comprises a plurality of MOS transistors Q5 (335), Q6 (340), and Q7 (345). As shown in FIG. 3, transistor Q5 is coupled to transistor Q3 and mirrors current flowing through transistors Q3 and Q2; transistor Q6 is coupled to transistors Q5 and Q4 and mirrors current flowing through transistors Q4 and Q1; and transistor Q7 is coupled to transistor Q6 and mirrors current flowing through transistor Q6 and sources the output current. The current mirror circuit 215 further comprises a resistor that couples the source of transistor Q7 to ground. The current mirror circuit 215 mirrors the load current of the load circuit 210 to generate an output current (Iout). The generated output current (Iout) is equal to a sum of the resistor current (Ir) across the resistor 325 and the MOS current (It) across transistor Q8 (330) of the load circuit 210 so that:

Iout=Ir+It

FIG. 4 is a flowchart showing a method 400 for generating a constant current using metal oxide semiconductor (MOS) transistors. The method 400 begins by generating (at 405) a biasing current (e.g., using a biasing circuit comprising a plurality of MOS transistors), the biasing current being generated based on a transconductance of at least one MOS transistor. For example, the method may generate the biasing current by generating a first transconductance between a reference voltage and a load circuit and generating a second transconductance between the reference voltage and ground.
The method then generates (at 410) a constant load current from the biasing current (e.g., using a load circuit comprising a resistor and a MOS transistor in parallel), the load current comprising a resistor current and a MOS current, wherein variations of the resistor current are offset by variations of the MOS current across temperature or process variations. The method then generates (at 415) an output current equal to a sum of the resistor current and the MOS current, the output current being approximately constant in value across temperature or process variations.
II. Current Source Characteristics
Characteristics of the constant current source can be better understood by first examining the characteristics of a non-constant current source that produces an output current that varies significantly across temperature or processing variations. As known in the art, a transconductance parameter (KP) of a current source has a high correlation to temperature or processing variations and varies significantly along with temperature or processing variations. As such, the transconductance parameter of a current source is typically used to correlate variations in the output current of the current source to variations in temperature or processing. Thus, a current source that produces significant variations in its output current as the transconductance parameter of the current source varies is also considered to produce significant variations in its output current with temperature or processing variations (as discussed further below in relation to FIG. 7). Such a current source is sometimes referred to as a KP dependent current source.
FIG. 5 is a circuit analysis diagram of a KP dependent current source 500 that does not produce a constant current across temperature or processing variations. Note that in comparison with the constant current source 300 of FIG. 3, the KP dependent current source 500 does not have a MOS device connected in parallel with resistor R so that there is no offsetting MOS current. Thus the output current (Iout) of the KP dependent current source 500 is equal to the current (I) across the resistor R. As discussed below in relation to FIG. 7, the current (I) across the resistor R varies significantly across temperature or processing variations.
To determine temperature compensation (TC) as a function of output current (ID) for the KP dependent current source 500 of FIG. 5:
Given:
k=gain of current source circuit;
W=width of gate channel;
L=length of gate channel;
N=transistor size multiplication factor between Q1 and Q2 and between Q4 and Q3 (e.g., if Q1 and Q4 are four times larger than Q2 and Q3, N=4);
KP=transconductance parameter (A/V2);
ID=drain current;
VTH=threshold voltage;
VGS=gate-source voltage;
VDS=drain-source voltage; and
T=temperature,
then:



  
    
      
        V
        
          GS
          ⁢
          
            
          
          ⁢
          1
        
      
      +
      
        V
        
          GS
          ⁢
          
            
          
          ⁢
          4
        
      
      +
      RI
    
    =
    
      
        V
        
          GS
          ⁢
          
            
          
          ⁢
          3
        
      
      +
      
        V
        
          GS
          ⁢
          
            
          
          ⁢
          2
        
      
    
  




  
    RI
    =
    
      
        (
        
          
            V
            
              GS
              ⁢
              
                
              
              ⁢
              3
            
          
          -
          
            V
            
              GS
              ⁢
              
                
              
              ⁢
              1
            
          
        
        )
      
      +
      
        (
        
          
            V
            
              GS
              ⁢
              
                
              
              ⁢
              2
            
          
          -
          
            V
            
              GS
              ⁢
              
                
              
              ⁢
              4
            
          
        
        )
      
    
  




  
    RI
    =
    
      2
      ⁢
      Δ
      ⁢
      
        
      
      ⁢
      
        
          V
          GS
        
        ⁢
        
          

        
        (
        
          
            if
            ⁢
            
              
            
            ⁢
            
              I
              STA
            
            ⁢
            
              <<
              
                I
                OUT
              
            
          
          ,
          
            
              I
              OUT
            
            =
            
              I
              D
            
          
        
        )
      
    
  




  
    
      I
      D
    
    =
    
      I
      =
      
        
          I
          OUT
        
        =
        
          
            2
            ⁢
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              GS
            
          
          R
        
      
    
  




  
    
      Δ
      ⁢
      
        
      
      ⁢
      
        V
        GS
      
    
    =
    
      k
      *
      
        
          
            I
            D
          
          KP
        
      
    
  




  
    k
    =
    
      
        
          2
          
            (
            
              W
              L
            
            )
          
        
      
      *
      
        (
        
          1
          -
          
            1
            
              N
            
          
        
        )
      
    
  




  
    
      I
      D
    
    =
    
      I
      =
      
        
          2
          *
          
            1
            R
          
          ⁢
          k
          *
          
            
              
                I
                D
              
              KP
            
          
        
        =
        
          
            
              2
              ⁢
              k
            
            R
          
          *
          
            
              
                I
                D
              
              KP
            
          
        
      
    
  




  
    
      
        R
        
          2
          ⁢
          k
        
      
      ⁢
      
        I
        D
      
    
    =
    
      
        
          
            
              I
              D
            
            KP
          
        
        ⇒
        
          
            
              (
              
                R
                
                  2
                  ⁢
                  k
                
              
              )
            
            2
          
          *
          
            I
            D
            2
          
        
      
      =
      
        
          
            
              I
              D
            
            KP
          
          ⁢
          
            

          
          ∴
          
            I
            D
          
        
        =
        
          
            
              
                (
                
                  
                    2
                    ⁢
                    k
                  
                  R
                
                )
              
              2
            
            *
            
              1
              KP
            
          
          =
          
            I
            OUT
          
        
      
    
  



As such, temperature compensation (TC) as a function of output current (ID) can be represented by the equation:



  
    
      TC
      ⁡
      
        (
        
          I
          D
        
        )
      
    
    =
    
      
        
          -
          
            TC
            ⁡
            
              (
              KP
              )
            
          
        
        -
        
          2
          ⁢
          
            TC
            ⁡
            
              (
              R
              )
            
          
        
      
      =
      
        
          
            -
            
              (
              
                
                  -
                  1.5
                
                T
              
              )
            
          
          -
          
            2
            ⁢
            a
          
        
        =
        
          
            (
            
              1.5
              T
            
            )
          
          -
          
            2
            ⁢
            a
          
        
      
    
  




  
    
      where
      ⁢
      
        :
      
    
    ⁢
    
      

    
    ⁢
    a
    =
    
      the
      ⁢
      
        
      
      ⁢
      temperature
      ⁢
      
        
      
      ⁢
      compensation
      ⁢
      
        
      
      ⁢
      value
      ⁢
      
        
      
      ⁢
      at
      ⁢
      
        
      
      ⁢
      resistor
      ⁢
      
        
      
      ⁢
      
        R
        .
      
    
  



To determine the value of the output current (ID):



  
    where
    ⁢
    
      :
    
  




  
    
      I
      D
    
    =
    
      
        
          (
          
            
              2
              ⁢
              k
            
            R
          
          )
        
        2
      
      *
      
        1
        KP
      
    
  




  
    k
    =
    
      
        
          2
          
            (
            
              W
              L
            
            )
          
        
      
      *
      
        (
        
          1
          -
          
            1
            
              N
            
          
        
        )
      
    
  




  
    then
    ⁢
    
      :
    
  




  
    
      I
      D
    
    =
    
      4
      ⁢
      
        k
        2
      
      *
      
        1
        
          
            R
            2
          
          *
          KP
        
      
    
  




  
    
      I
      D
    
    =
    
      4
      *
      
        2
        
          W
          L
        
      
      ⁢
      
        
          (
          
            1
            -
            
              1
              
                N
              
            
          
          )
        
        2
      
      ⁢
      
        1
        
          R
          2
        
      
      *
      
        1
        KP
      
    
  




  
    
      V
      ON
    
    =
    
      
        
          2
          ⁢
          
            I
            D
          
        
        
          KP
          ⁡
          
            (
            
              W
              L
            
            )
          
        
      
    
  




  
    
      V
      ON
      2
    
    =
    
      
        2
        ⁢
        
          I
          D
        
      
      
        KP
        ⁡
        
          (
          
            W
            L
          
          )
        
      
    
  




  
    
      
        V
        ON
        2
      
      
        2
        ⁢
        
          I
          D
        
      
    
    =
    
      1
      
        KP
        ⁡
        
          (
          
            W
            L
          
          )
        
      
    
  




  
    
      I
      D
    
    =
    
      
        
          V
          ON
          2
        
        
          2
          ⁢
          
            I
            D
          
        
      
      *
      8
      ⁢
      
        
          (
          
            1
            -
            
              1
              
                N
              
            
          
          )
        
        2
      
      ⁢
      
        1
        
          R
          2
        
      
    
  




  
    
      I
      D
      2
    
    =
    
      
        V
        ON
        2
      
      *
      4
      ⁢
      
        
          (
          
            1
            -
            
              1
              
                N
              
            
          
          )
        
        2
      
      ⁢
      
        1
        
          R
          2
        
      
    
  




  
    
      I
      D
    
    =
    
      2
      ⁢
      
        V
        ON
      
      *
      
        (
        
          1
          -
          
            1
            
              N
            
          
        
        )
      
      ⁢
      
        1
        R
      
    
  



For example:




  
    N
    =
    4
  




  
    
      (
      
        1
        -
        
          1
          
            N
          
        
      
      )
    
    =
    0.5
  




  
    
      I
      D
    
    =
    
      
        V
        ON
      
      *
      
        1
        R
      
    
  




  
    
      V
      ON
    
    =
    
      0.5
      ⁢
      V
    
  




  
    
      I
      D
    
    =
    
      
        
          100
          ⁢
          mA
        
        ⇒
        R
      
      =
      
        
          
            V
            ON
          
          
            I
            D
          
        
        =
        
          
            0.5
            
              100
              ⁢
              m
            
          
          =
          
            5
            ⁢
            kOhm
          
        
      
    
  



Other characteristics of the MOSFET KP dependent current source 500 of FIG. 5 are shown by the following equations:




  
    
      
        g
        m
      
      ⁡
      
        (
        
          
            V
            GS
          
          -
          
            V
            TH
          
        
        )
      
    
    =
    
      2
      ⁢
      
        I
        D
      
    
  




  
    
      V
      GS
    
    =
    
      
        V
        TH
      
      +
      
        
          2
          ⁢
          
            I
            D
          
        
        
          g
          m
        
      
    
  




  
    
      g
      m
    
    =
    
      
        2
        *
        
          I
          D
        
        *
        KP
        *
        
          (
          
            W
            L
          
          )
        
      
    
  




  
    
      V
      GS
    
    =
    
      
        
          V
          TH
        
        +
        
          
            2
            ⁢
            
              I
              D
            
          
          
            
              2
              *
              
                I
                D
              
              *
              KP
              *
              
                (
                
                  W
                  L
                
                )
              
            
          
        
      
      =
      
        V
        
          GS
          ⁢
          
            
          
          ⁢
          1
        
      
    
  




  
    
      V
      
        GS
        ⁢
        
          
        
        ⁢
        2
      
    
    =
    
      
        
          V
          TH
        
        +
        
          
            
              2
              ⁢
              
                I
                D
              
            
            
              KP
              *
              
                (
                
                  W
                  L
                
                )
              
              *
              N
            
          
        
      
      =
      
        V
        
          GS
          ⁢
          
            
          
          ⁢
          2
        
      
    
  




  
    
      V
      
        GS
        ⁢
        
          
        
        ⁢
        1
      
    
    ⇒
    
      W
      L
    
  




  
    
      V
      
        GS
        ⁢
        
          
        
        ⁢
        2
      
    
    ⇒
    
      n
      *
      
        W
        L
      
    
  




  
    (
    
      if
      ⁢
      
        
      
      ⁢
      both
      ⁢
      
        
      
      ⁢
      
        I
        D
      
      ⁢
      
        
      
      ⁢
      are
      ⁢
      
        
      
      ⁢
      same
    
    )
  




  
    
      V
      GS
    
    =
    
      
      
        
          V
          
            GS
            ⁢
            
              
            
            ⁢
            1
          
        
        -
        
          V
          
            GS
            ⁢
            
              
            
            ⁢
            2
          
        
      
      
    
  




  
    
      V
      GS
    
    =
    
      
        
          V
          TH
        
        +
        
          
            
              2
              ⁢
              
                I
                D
              
            
            
              KP
              *
              
                (
                
                  W
                  L
                
                )
              
            
          
        
        -
        
          V
          TH
        
        -
        
          
            
              
                2
                ⁢
                
                  I
                  D
                
              
              
                KP
                *
                
                  (
                  
                    W
                    L
                  
                  )
                
              
            
          
          *
          
            1
            
              N
            
          
          ⁢
          
            

          
          ⁢
          
            V
            GS
          
        
      
      =
      
        
          
            
              
                2
                ⁢
                
                  I
                  D
                
              
              
                KP
                *
                
                  (
                  
                    W
                    L
                  
                  )
                
              
            
          
          *
          
            (
            
              1
              -
              
                1
                
                  N
                
              
            
            )
          
        
        =
        
          
            k
            *
            
              
                
                  I
                  D
                
                KP
              
            
            ⁢
            
              

            
            ⁢
            
              I
              D
            
          
          =
          
            
              
                Δ
                ⁢
                
                  
                
                ⁢
                
                  V
                  GS
                
              
              R
            
            =
            
              
                k
                *
                
                  1
                  R
                
                *
                
                  
                    
                      I
                      D
                    
                    KP
                  
                
                ⁢
                
                  

                
                ⁢
                k
              
              =
              
                
                  
                    
                      2
                      
                        (
                        
                          W
                          L
                        
                        )
                      
                    
                  
                  *
                  
                    (
                    
                      1
                      -
                      
                        1
                        
                          N
                        
                      
                    
                    )
                  
                  ⁢
                  
                    

                  
                  ⁢
                  
                    
                      R
                      *
                      
                        I
                        D
                      
                    
                    k
                  
                
                =
                
                  
                    
                      
                        
                          I
                          D
                        
                        KP
                      
                    
                    ⁢
                    
                      

                    
                    ⁢
                    
                      
                        
                          R
                          2
                        
                        *
                        
                          I
                          D
                          2
                        
                      
                      
                        k
                        2
                      
                    
                  
                  =
                  
                    
                      
                        
                          I
                          D
                        
                        KP
                      
                      ⁢
                      
                        

                      
                      ⁢
                      thus
                      ⁢
                      
                        :
                      
                      ⁢
                      
                        

                      
                      ⁢
                      
                        I
                        D
                      
                    
                    =
                    
                      
                        
                          k
                          2
                        
                        
                          R
                          2
                        
                      
                      =
                      
                        
                          1
                          KP
                        
                        .
                      
                    
                  
                
              
            
          
        
      
    
  



FIG. 6 is a circuit analysis diagram of the constant current source 300 of FIG. 3. Characteristics of the constant current source 300 are shown by the following equations:
Given:



  
    
      I
      t
    
    =
    
      
        
          (
          
            
              2
              ⁢
              k
            
            R
          
          )
        
        2
      
      *
      
        1
        KP
      
    
  




  
    k
    =
    
      
        
          2
          
            (
            
              W
              L
            
            )
          
        
      
      *
      
        (
        
          1
          -
          
            1
            
              N
            
          
        
        )
      
    
  




  
    
      R
      MOS
    
    =
    
      (
      
        1
        
          
            W
            L
          
          *
          KP
          *
          
            (
            
              
                V
                GS
              
              -
              
                V
                TH
              
            
            )
          
        
      
      )
    
  




  
    
      V
      ON
    
    =
    
      
        
          2
          ⁢
          
            I
            D
          
        
        
          KP
          ⁡
          
            (
            
              W
              L
            
            )
          
        
      
    
  




  
    
      V
      ON
    
    ∝
    
      
        (
        KP
        )
      
      
        -
        0.5
      
    
  




  
    then
    ⁢
    
      :
    
  




  
    
      I
      t
    
    =
    
      
        
          [
          
            2
            ⁢
            k
            *
            
              (
              
                W
                L
              
              )
            
            *
            KP
            *
            
              (
              
                
                  V
                  GS
                
                -
                
                  V
                  TH
                
              
              )
            
          
          ]
        
        2
      
      *
      
        (
        
          1
          KP
        
        )
      
    
  




  
    
      I
      t
    
    =
    
      
        
          [
          
            2
            ⁢
            k
            *
            
              (
              
                W
                L
              
              )
            
            *
            
              (
              
                
                  V
                  GS
                
                -
                
                  V
                  TH
                
              
              )
            
          
          ]
        
        2
      
      *
      KP
    
  




  
    
      I
      r
    
    ∝
    
      
        1
        KP
      
      *
      
        1
        R
      
    
  




  
    
      I
      t
    
    ∝
    
      
        
          (
          
            
              V
              GS
            
            -
            
              V
              TH
            
          
          )
        
        2
      
      *
      
        KP
        2
      
    
  




  
    when
    ⁢
    
      
    
    ⁢
    
      (
      
        
          I
          r
        
        =
        
          I
          t
        
      
      )
    
    ⁢
    
      :
    
  




  
    
      
        (
        
          
            2
            ⁢
            k
          
          R
        
        )
      
      2
    
    =
    
      
        [
        
          2
          ⁢
          k
          *
          
            (
            
              W
              L
            
            )
          
          *
          
            (
            
              
                V
                GS
              
              -
              
                V
                TH
              
            
            )
          
        
        ]
      
      2
    
  




  
    
      1
      R
    
    =
    
      
        (
        
          W
          L
        
        )
      
      *
      
        (
        
          
            V
            GS
          
          -
          
            V
            TH
          
        
        )
      
    
  




  
    
      V
      GS
    
    =
    
      N
      *
      
        (
        
          
            V
            ON
          
          +
          
            V
            TH
          
        
        )
      
    
  




  
    
      
        N
        *
        
          (
          
            
              V
              ON
            
            +
            
              V
              TH
            
          
          )
        
      
      -
      
        V
        TH
      
    
    =
    
      
        (
        
          N
          *
          
            V
            ON
          
        
        )
      
      +
      
        (
        
          
            (
            
              N
              -
              1
            
            )
          
          *
          
            V
            TH
          
        
        )
      
    
  



III. Output Current as a Function of the Transconductance Parameter KP

As discussed above, the transconductance parameter KP of a current source varies significantly with temperature or processing variations and can be used to correlate the output current of the current source to variations in temperature or processing. A current source that produces significant variations in its output current as the transconductance parameter KP of the current source varies is also considered to produce significant variations in its output current with temperature or processing variations.
FIG. 7 is a graph that shows the output currents of a constant current source and a non-constant current source as a function of the transconductance parameter KP of the current sources across a range of KP values from a lower boundary to an upper boundary (assuming that temperature or process variations of KP are +30%). A first graph line 705 shows the output current of a non-constant current source as a function of the transconductance parameter KP of the current source. In particular, the first graph line 705 shows the output current of the KP dependent current source 500 of FIG. 5 where the output current is equal to the current (Ir) across the resistor R. As shown in FIG. 7, the output current of the KP dependent current source 500 varies significantly across the various values of KP. This indicates that the output current of the KP dependent current source 500 would also vary significantly across temperature or process variations.
A second graph line 710 shows the output current of the constant current source 300 of FIG. 3 as a function of the transconductance parameter KP of the current source, whereby the output current is equal to a resistor current (Ir) across a resistor R and a MOS current (It) across a transistor. As shown in FIG. 7, the output current of the constant current source 300 is relatively constant within various values of KP that reflect typical operating conditions (indicated by the dashed lines). This indicates that the output current of the constant current source 300 would also be relatively constant across temperature or process variations. This is due to the fact that as the value of the resistor current (Ir) varies over various values of KP, the values of the MOS current (It) varies to offset the variations of the resistor current (Ir) to maintain a relatively constant output current (Iout).
One of ordinary skill will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention, even though the invention has been described with reference to numerous specific details. In view of the foregoing, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.

## Claims

1. A current source circuit comprising:
biasing circuit comprising a plurality of metal oxide semiconductor (MOS) transistors for generating a biasing current;
load circuit comprising:
at least one MOS device for receiving the biasing current and generating a MOS current through the MOS device; and
resistor the load circuit receiving the biasing current and generating a resistor current through the resistor; and

current mirror circuit, coupled to the biasing circuit, for generating an output current equal to the sum of the resistor current and the MOS current,
wherein a change in the biasing current due to temperature or process variations is approximately offset by a change in MOS current due to the temperature or process variations, and a change in the resistor current due to the temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations to produce the output current that is approximately constant across temperature and process variations.

2. The current source circuit of claim 1, wherein:
temperature or process variations cause an increase in the biasing current and an increase in the resistance of the MOS device, whereby the increase in the resistance of the MOS device causes a decrease in the MOS current which approximately offset the increase in the biasing current.

3. The current source circuit of claim 1, wherein:
temperature or process variations cause decrease in the biasing current and a decrease in the resistance of the MOS device, whereby the decrease in the resistance of the MOS device causes an increase in the MOS current which approximately offsets the decrease in the biasing current.

4. The current source circuit claim 1, wherein the biasing circuit generates the biasing current based on transconductance of the MOS transistors of the biasing circuit.

5. The current source circuit of claim 4, wherein the biasing circuit comprises:
first transistor pair for generating a first transconductance between a reference voltage and the load circuit; and
second transistor pair for generating a second transconductance between the reference voltage and ground.

6. The current source circuit of claim 5, wherein the first transistor pair comprises a size four times as large as the second transistor pair.

7. The current source circuit of claim 1, wherein the biasing circuit comprises:
first and third transistors, wherein a gate of the third transistor is coupled to a drain of the third transistor, a source of the third transistor is coupled to a gate of the first transistor, and a source of the first transistor is coupled to the load circuit; and
second and fourth transistors, wherein a drain of the second transistor is coupled to the source of the third transistor, a source of the second transistor is coupled to ground, a gate the second transistor is coupled to a source of the fourth transistor and to the drain of the first transistor, and the gate of the third transistor is coupled to the gate of the fourth transistor
wherein the gate to source voltage of the third transistor (VGS3) plus the gate to source voltage of the first transistor (VGS1) plus the voltage across the resistor (If*R) of the load circuit is equal to the gate to source voltage of the fourth transistor (VGS4) plus the gate to source voltage of the second transistor (VGS2), as represented by the equation:


VGS3+VGS1+IrR=VGS4+VGS2.

8. A current source circuit comprising:
means for generating a biasing current;
means for receiving the biasing current and generating a current through a metal oxide semiconductor (MOS) device (MOS current), the means for receiving the biasing current further comprising means generating a resistor current through a resistor; and
means for generating an output current equal to the sum of the resistor current and the MOS current,
wherein a change in the biasing current due to temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations, and a change in the resistor current due to the temperature or process variations is approximately offset by a change in the MOS current due to the temperature process variations to produce the output current that is approximately constant across temperature and process variations.

9. The current source circuit of claim 8, wherein:
temperature or process variations cause an increase in the biasing current and an increase in the resistance of the device, whereby the increase in the resistance of the MOS device causes a decrease in the MOS current which approximately offsets the increase in the biasing current.

10. The current source circuit of claim 8, wherein:
temperature or process variations cause a decrease the biasing current and a decrease in the resistance in the MOS device, whereby the decrease in the resistance of the MOS device causes an increase in the MOS current which approximately offset the decrease in the biasing current.

11. The current source circuit of claim 8, wherein the means for generating the biasing current comprises a means for generating the biasing current based on transconductance of one or more MOS transistors.

12. A method for generating current, the method comprising:
generating a biasing current;
receiving the biasing current and generating a current through a metal oxide semiconductor (MOS) device (MOS current);
generating a resistor current through a resistor; and
generating an output equal to the sum of the resistor current and the MOS current,
wherein a change in the biasing current due to temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations, and a change in the resistor current due to the temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations to produce the output current that is approximately constant across temperature and process variations.

13. The method of claim 12, wherein:
temperature or process variations cause an increase to the biasing current and an increase in the resistance of the MOS device, whereby the increase in the resistance of the MOS device causes a decrease in the MOS current which approximately offsets the increase in the biasing current.

14. The method of claim 12, wherein:
temperature or process variations cause a decrease in the biasing current and a decrease or the resistance of MOS device, whereby the decrease in the resistance of the MOS device causes an increase in the MOS current which approximately offsets the decrease in the biasing current.

15. The method of claim 12, wherein generating the biasing current comprises generating the biasing current based on transconductance of one or more MOS transistors.

16. A current source circuit comprising:
biasing circuit comprising a plurality of metal oxide semiconductor (MOS) transistors for generating a biasing current based on transconductance of the MOS transistors of the biasing circuit,
wherein the biasing circuit comprises:
first transistor pair for generating a first transconductance between a reference voltage and a load circuit; and
second transistor pair for generating a second transconductance between the reference voltage and ground, wherein the first transistor pair comprises a size approximately four times as large as the second transistor pair; and

the load circuit comprising at least one MOS device for receiving the biasing current and generating a MOS current through the MOS device,
wherein a change in the biasing current due to temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations.

17. A current source circuit comprising:
biasing circuit comprising a plurality of metal oxide semiconductor (MOS) transistors for generating a biasing current, wherein the biasing circuit comprises:
first and third transistors, wherein a gate of the third transistor is coupled to a drain of the third transistor, a source of the third transistor is coupled to a gate of the first transistor, and a source of the first transistor is coupled to a load circuit; and
second and fourth transistors, wherein a drain of the second transistor is coupled to the source of the third transistor, a source of the second transistor is coupled to ground, a gate of the second transistor is coupled to a source of the fourth transistor and to the drain of the first transistor, and the gate of the third transistor is coupled to the gate of the fourth transistor,
wherein the gate to source voltage of the third transistor (VGS3) plus the gate to source voltage of the first transistor (VGS1) plus the voltage across the resistor (Ir*R) of the load circuit is equal to the gate to source voltage of the fourth transistor (VGS4) plus the gate to source voltage of the second transistor (VGS2), as represented by the equation:


VGS3 +VGS1+Ir*R =VGS4 +VGS2; and



the load circuit comprising at least one MOS device for receiving the biasing current and generating a MOS current through the MOS device,
wherein a change in the biasing current due to temperature or process variations is approximately offset by a change in the MOS current due to the temperature or process variations.