# Patent

## Title
Voltage output digital-to-analog converter circuit

## Abstract

According to this invention, there is provided a voltage output digital-to-analog converter circuit, including other ones of the second resistive elements and third resistive elements having a desired resistance value are series-connected between the other ends of the second resistive elements, which are connected to switching elements of the plurality of switching elements to which a most significant bit and a least significant bit are supplied, and the ground.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority under 35 USC 119 from the Japanese Patent Application No. 2005-357713, filed on Dec. 12, 2005, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a voltage output digital-to-analog converter circuit.
A voltage output digital-to-analog converter circuit has a plurality of switching elements which switch their connection states according to respective bits of an input digital signal and a resistor network formed by connecting, in a so-called “ladder-type” manner, resistors of two types which are selected such that the ratio between their resistance values is 1:2.
The voltage output digital-to-analog converter circuit switches the connection state of each switching element to the reference voltage terminal or the ground terminal according to a digital signal input as a corresponding bit and divides the reference voltage using the resistor network, thereby generating an output voltage corresponding to the input digital signal, i.e., an output analog signal (see, e.g., Toshikazu Yoneyama, “Introduction to A/D Converters”, Ohmsha, Ltd., pp. 139-140).
Each switching element is formed by, e.g., connecting a source of PMOS transistor and a source of NMOS transistor to the reference voltage terminal and the ground terminal respectively. Each of the PMOS transistor and NMOS transistor generates an on-resistance having a certain resistance value using a MOS transistor when it is on.
For this reason, if the PMOS transistor connected to the reference voltage terminal is turned on, the NMOS transistor connected to the ground terminal is turned off, and the reference voltage is selected, a problem arises. More specifically, since the PMOS transistor has the on-resistance, the on-resistance is series-connected to the resistor connected to the switching element, and an error occurs in the output voltage, i.e., analog signal.
SUMMARY OF THE INVENTION
A voltage output digital-to-analog converter circuit according to one aspect of the present invention includes
a plurality of switching elements provided corresponding to respective bits of an input digital signal to switch connection states of the plurality of switching elements to either the reference voltage terminal or the ground terminal according to the bits of the digital signal; and
a resistor network which includes first resistive elements and second resistive elements having a resistance value twice a resistance value of the first resistive elements and in which one ends of the second resistive elements are connected to the plurality of switching elements respectively, the first resistive elements are connected between neighboring pairs of the other ends of the second resistive elements respectively, and other ones of the second resistive elements and third resistive elements having a desired resistance value are series-connected between the other ends of the second resistive elements, which are connected to switching elements of the plurality of switching elements to which a most significant bit and a least significant bit are supplied, and the ground.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing the basic configuration of a voltage output digital-to-analog converter circuit;
FIG. 2 are circuit diagrams each showing the circuit configuration of a switching element;
FIG. 3 is an explanatory graph showing a relationship between an input code of a digital signal and an error;
FIG. 4 is a block diagram showing the configuration of a voltage output digital-to-analog converter circuit according to a first embodiment of the present invention;
FIG. 5 is an explanatory graph showing relationships before and after correction between an input code of a digital signal and an error; and
FIG. 6 is a block diagram showing the configuration of a voltage output digital-to-analog converter circuit according to a second embodiment of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
Hereafter, embodiments of the present invention will be described more specifically with reference to the drawings.
First Embodiment
FIG. 1 shows the basic configuration of a voltage output digital-to-analog converter circuit 10. The voltage output digital-to-analog converter circuit 10 has a plurality of switching elements S1 to SN provided corresponding to respective bits of an input digital signal. The switching elements S1 to SN switch their connection states according to the bits of the digital signal.
More specifically, if a corresponding one of the bits of the input digital signal which is supplied to each of the switching elements S1 to SN is data “1”, the switching element switches its connection state to the reference voltage terminal “Vref”, thereby selecting the reference voltage “Vref”. On the other hand, if the corresponding bit is data “0”, the switching element switches its connection state to the ground terminal (GND), thereby selecting 0 V.
Note that in this embodiment, a digital signal input as bits b1 (LSB) to bN (MSB) is inverted by inverters (not shown), and inverted data/b1 is input to the switching element S1, and data/b2 is input to the switching element S2. Similarly, data/bN−1 is input to the switching element SN−1, and data/bN is input to the switching element SN.
FIG. 2(a) shows the specific circuit configuration of a switching element S. The switching element S is formed by connecting a source of PMOS transistor Tr10 and a source of NMOS transistor Tr20 to the reference voltage terminal “Vref” and the ground terminal (GND) respectively.
With this configuration, if data “0” obtained by inverting input data “1” is supplied, the switching element S turns on the PMOS transistor Tr10 and turns off the NMOS transistor Tr20, thereby selecting the reference voltage “Vref”.
On the other hand, if data “1” obtained by inverting input data “0” is supplied, the switching element S turns off the PMOS transistor Tr10 and turns on the NMOS transistor Tr20, thereby selecting 0 V.
The voltage output digital-to-analog converter circuit 10 also has a resistor network formed by connecting, in a so-called “ladder-type” manner, resistors R101 to R10N−1 and resistors R201 to R20N+2 of two types which are selected such that the ratio between their resistance values is 1:2.
More specifically, one ends of the resistors R201 to R20N having a resistance value of “2R” are respectively connected to the switching elements S1 to SN The other end of the resistor R201 is connected to a junction point of the resistor R20N+1 connected to the ground (GND) and having a resistance value of “2R” and the resistor R101 having a resistance value of “R”. The other end of the resistor R202 is connected to a junction point of the resistor R101 and the resistor R102 (not shown) having a resistance value of “R”.
The other ends of the succeeding resistors are similarly connected in order. The other end of the resistor R20N−1 is connected to a junction point of the resistor R10N−2 (not shown) having a resistance value of “R” and the resistor R10N−1 having a resistance value of “R”. The other end of the resistor R20N is connected to a junction point of the resistor R10N−1 and the resistor R20N+2 connected to the ground (GND) and having a resistance value of “2R”.
An amplifier 20 for driving a load by keeping output impedance low is connected to a junction point P of the resistors R20N, R10N−1, and R20N+2.
The voltage output digital-to-analog converter circuit 10 switches the connection state of each of the switching elements S1 to SN to the reference voltage terminal “Vref” or the ground terminal (GND) according to a corresponding one of the bits b1 to bN of an input digital signal and divides the reference voltage “Vref” using the resistor network (the resistors R101 to R10N−1 and R201 to R20N+2), thereby generating an output voltage “VOUT” corresponding to the input digital signal, i.e., an output analog signal.
In this case, assuming that only a desired one of the bits of the input digital signal is data “1” and that the ones other than the bit are data “0”, a potential “Vai” of the junction point P is calculated by:




  
    
      
        
          V
          ai
        
        =
        
          
            
              V
              ref
            
            3
          
          ×
          
            1
            
              2
              
                N
                -
                i
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




As described above, the potential “Vai” is calculated for each of ones of the bits which are data “1” using Formula (1). An output voltage “Va”, i.e., “Vout” is calculated by adding the calculated potentials “Vai” by:




  
    
      
        
          V
          out
        
        =
        
          
            V
            a
          
          =
          
            
              
                V
                ref
              
              3
            
            ⁢
            
              
                ∑
                
                  i
                  =
                  1
                
                N
              
              ⁢
              
                
                  b
                  i
                
                
                  2
                  
                    N
                    -
                    i
                  
                
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




As shown in FIG. 2(b), when each of the PMOS transistor Tr10 and NMOS transistor Tr20 forming the switching element S is turned on, a MOS transistor therein constitutes an on-resistance R20on having a certain resistance value of “ron”. Note that the on-resistance R20on of the PMOS transistor Tr10 and NMOS transistor Tr20 are designed here to have resistance values equal to each other.
For this reason, the voltage output digital-to-analog converter circuit 10 has the same circuit configuration as one in which the on-resistance R20on is series-connected to a resistor R20 connected to the switching element S. In this case, an error occurs in the output voltage.
FIG. 3 shows a relationship between an input code of a digital signal and an error (Vout−Vout(ron)) when, e.g., a 4-bit digital signal is input. Note that “Vout” represents a ideal value of the output voltage and that “Vout (ron)” represents a value of the output voltage calculated in consideration of the on-resistance R20on of the switching element S.
As shown in FIG. 3, if a 4-bit digital signal is input, the absolute value of the error becomes the maximum when an input code of the digital signal is “1100”. The absolute value of the error becomes the maximum when data “1” is supplied as each of the two higher-order bits of the input code, and data “0” is supplied as each of the bits other than the two higher-order bits, regardless of the number of bits, N.
An absolute value |Vout−Vout(ron)| of the maximum error is represented by:




  
    
      
        
          
            
            
              
                V
                out
              
              -
              
                V
                
                  out
                  ⁡
                  
                    (
                    
                      r
                      on
                    
                    )
                  
                
              
            
            
          
          ≈
          
            
              
              
                
                  
                    
                      r
                      on
                    
                    -
                    
                      
                        
                          a
                          
                            N
                            -
                            2
                          
                        
                        +
                        
                          a
                          1
                        
                      
                      2
                    
                  
                  
                    18
                    ⁢
                    R
                  
                
                -
                
                  
                    a
                    1
                  
                  
                    12
                    ⁢
                    R
                  
                
                +
                
                  
                    
                      r
                      on
                    
                    -
                    
                      
                        a
                        
                          N
                          -
                          1
                        
                      
                      2
                    
                  
                  
                    9
                    ⁢
                    R
                  
                
              
              
            
            ⁢
            
              V
              ref
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            a
            1
          
          =
          
            
              r
              on
            
            4
          
        
        ⁢
        
          

        
        ⁢
        
          
            a
            n
          
          =
          
            
              
                
                  r
                  on
                
                ⁡
                
                  (
                  
                    
                      4
                      n
                    
                    -
                    1
                  
                  )
                
              
              
                3
                ×
                
                  4
                  n
                
              
            
            ≈
            
              
                
                  r
                  on
                
                3
              
              ⁢
              
                (
                
                  n
                  ≧
                  2
                
                )
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




In order for the voltage output digital-to-analog converter circuit 10 to achieve N-bit accuracy, it is desirable to make the absolute value of the maximum error smaller than 1/2×LSB (i.e., 1/2 times the ideal value “Vout” of the output voltage when only the bit b1(LSB) is data “1”).

In other words, to achieve desired accuracy, it is necessary to satisfy:




  
    
      
        
          
            
              
              
                
                  
                    
                      r
                      on
                    
                    -
                    
                      
                        
                          a
                          
                            N
                            -
                            2
                          
                        
                        +
                        
                          a
                          1
                        
                      
                      2
                    
                  
                  
                    18
                    ⁢
                    R
                  
                
                -
                
                  
                    a
                    1
                  
                  
                    12
                    ⁢
                    R
                  
                
                +
                
                  
                    
                      r
                      on
                    
                    -
                    
                      
                        a
                        
                          N
                          -
                          1
                        
                      
                      2
                    
                  
                  
                    9
                    ⁢
                    R
                  
                
              
              
            
            ⁢
            
              V
              ref
            
          
          <
          
            
              1
              2
            
            ⁢
            LSB
          
        
        =
        
          
            1
            2
          
          ×
          
            
              V
              ref
            
            3
          
          ×
          
            1
            
              2
              
                N
                -
                1
              
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




Formula (4) is simplified as follows:





  
    
      
        
          r
          on
        
        <
        
          
            3
            
              2
              N
            
          
          ⁢
          R
        
      
    
    
      
        (
        5
        )
      
    
  




This means that an increase of the accuracy by one bit requires reducing the on-resistance R20on of the switching element S by 1/2 times or increasing the resistance value of “R” by twice. That is, if the switching elements S of the same size are used, the size of each resistor increases by twice, and thus, the area of each chip increases by about twice.
In the voltage output digital-to-analog converter circuit 10, the output voltage is determined by the ratio between the resistance value of the resistors R101 to R10N−1 and that of the resistors R201 to R20N+2. Accordingly, an error which occurs in the output voltage results from series connection of the on-resistance R20on to the resistors R201 to R20N connected to the switching elements S1 to SN and a change in the ratio between the resistance value of the resistors R201 to R20N, to which the on-resistance R20on are series-connected, and that of the other resistors R20N+1 and R20N+2 and resistors R101 to R10N−1.
It is possible to keep the ratio between the resistance value of the resistors R101 to R10N−1 and that of the resistors R201 and R20N+2 at 1:2 by series-connecting resistors having a resistance value of (1/2)ron to the resistors R101 to R10N−1 and series-connecting resistors having a resistance value of “ron” to the resistors R20N+1 and R20N+2. In this case, however, the circuit configuration becomes complicated. More specifically, the number of resistors increases or other reference voltage generating circuits are required if each resistor is formed from a MOS transistor.
Accordingly, as shown in FIG. 4, in a voltage output digital-to-analog converter circuit 30 according to this embodiment, correction-resistance R301 and R302 having a desired resistance value are connected to the resistors R20N+1 and R20N+2, which are not connected to the switching elements S1 to SN, in order to reduce the absolute value of a maximum error with a simpler circuit configuration. The optimal value of the resistance value of “r0” of correction-resistance R301 and R302 will be calculated below.
The sum of the first and second terms in the right-hand side of Formula (3) described above indicates an error which occurs when only the bitN−1, which is the second most significant bit, is data “1”. The third term indicates an error which occurs when only the bit bN, which is the MSB (Most Significant Bit), is data “1”.
For example, as shown in FIG. 3, where the number of bits of the input code is 4, an error which occurs when the input code is “0100” and one which occurs when the input code is “1000” have the same sign (+). If the input code is “1100”, the two errors are added.
Similarly, if the number of bits of the input code is N, an error which occurs when only the bit bN−1 is data “1” and one which occurs when only the bit bN is data “1” have the same sign. If each of the two higher-order bits is data “1”, and each of the bits other than the two higher-order bits is data “0”, the two errors are added.
Accordingly, for example, assume that when the number of bits of the input code is 4, the correction-resistance R301 and R302 having the resistance value of “r0”, which is adjusted such that an error which occurs when the input code is “0100” becomes “0”, are connected to the resistors R20N+1 and R20N+2. In this case, a plot of the maximum error is wholly shifted upward, as shown in FIG. 5.
For this reason, the absolute value of the maximum error when the input code is “1100” becomes smaller in a case where the correction-resistance R301 and R302 are connected to the resistors R20N+1 and R20N+2 than in a case where the correction-resistance R301 and R302 are not connected.
Similarly, if the number of bits of the input code is N, the absolute value of the maximum error can be reduced by adjusting the resistance value of “r0” of the correction-resistance R301 and R302 such that an error which occurs when only the bit bN−1, which is the second most significant bit, is data “1” becomes “0”.
An absolute value |Vout−V′out(ron)| of the maximum error in the voltage output digital-to-analog converter circuit 30 according to this embodiment is represented by:




  
    
      
        
          
            
            
              
                V
                out
              
              -
              
                V
                
                  out
                  ⁡
                  
                    (
                    
                      r
                      on
                    
                    )
                  
                
                ′
              
            
            
          
          ≈
          
            
              
              
                
                  
                    
                      r
                      on
                    
                    -
                    
                      
                        
                          a
                          
                            N
                            -
                            2
                          
                          ′
                        
                        +
                        
                          a
                          1
                          ′
                        
                      
                      2
                    
                  
                  
                    18
                    ⁢
                    R
                  
                
                -
                
                  
                    a
                    1
                    ′
                  
                  
                    12
                    ⁢
                    R
                  
                
                +
                
                  
                    
                      r
                      on
                    
                    -
                    
                      
                        a
                        
                          N
                          -
                          1
                        
                        ′
                      
                      2
                    
                  
                  
                    9
                    ⁢
                    R
                  
                
              
              
            
            ⁢
            
              V
              ref
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            a
            1
            ′
          
          =
          
            
              
                r
                on
              
              +
              
                r
                0
              
            
            4
          
        
        ⁢
        
          

        
        ⁢
        
          
            a
            n
            ′
          
          =
          
            
              
                
                  
                    r
                    on
                  
                  ⁡
                  
                    (
                    
                      
                        4
                        n
                      
                      -
                      1
                    
                    )
                  
                
                
                  3
                  ×
                  
                    4
                    n
                  
                
              
              +
              
                
                  r
                  0
                
                
                  4
                  n
                
              
            
            ≈
            
              
                
                  r
                  on
                
                3
              
              ⁢
              
                (
                
                  n
                  ≧
                  2
                
                )
              
            
          
        
      
    
    
      
        (
        6
        )
      
    
  




Note that “V′out(ron)” represents a value of the output voltage calculated in consideration of the on-resistance R20on of the switching element S when the correction-resistance R301 and R302 are connected.

The sum of the first and second terms in the right-hand side of Formula (6) indicates an error which occurs when only the bit bN−1, which is the second most significant bit, is data “1”. The resistance value of “r0” of the correction-resistance R301 and R302 needs to satisfy:




  
    
      
        
          
            
              
                r
                on
              
              -
              
                
                  
                    a
                    
                      N
                      -
                      2
                    
                    ′
                  
                  +
                  
                    a
                    1
                    ′
                  
                
                2
              
            
            
              18
              ⁢
              R
            
          
          -
          
            
              a
              1
              ′
            
            
              12
              ⁢
              R
            
          
        
        =
        0
      
    
    
      
        (
        7
        )
      
    
  




If Formula (7) is simplified, the resistance value of “r0” of the correction-resistance R301 and R302 is represented by:





  
    
      
        
          r
          0
        
        =
        
          
            2
            3
          
          ⁢
          
            r
            on
          
        
      
    
    
      
        (
        8
        )
      
    
  




If the correction-resistance R301 and R302 having the resistance value of “r0” represented by Formula (8) are connected to the resistors R20N+1 and R20N+2, the absolute value of the maximum error can be reduced.

As described above, in order for the voltage output digital-to-analog converter circuit 30 to achieve N-bit accuracy, it is desirable to make the absolute value |Vout−V′out(ron)| of the maximum value according to this embodiment smaller than 1/2×LSB (i.e., 1/2 times the ideal value “Vout” of the output voltage when only the bit b1(LSB) is data “1”).
In other words, it is necessary to satisfy:




  
    
      
        
          
            
              
              
                
                  
                    r
                    on
                  
                  -
                  
                    
                      a
                      
                        N
                        -
                        1
                      
                      ′
                    
                    2
                  
                
                
                  9
                  ⁢
                  R
                
              
              
            
            ⁢
            
              V
              ref
            
          
          <
          
            
              1
              2
            
            ⁢
            LSB
          
        
        =
        
          
            1
            2
          
          ×
          
            
              V
              ref
            
            3
          
          ×
          
            1
            
              2
              
                N
                -
                1
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




Formula (9) is simplified as follows:





  
    
      
        
          r
          on
        
        <
        
          
            3
            
              2
              
                N
                -
                1
              
            
          
          ⁢
          R
        
      
    
    
      
        (
        10
        )
      
    
  




According to Formula (10) after correction, if the resistance value of “ron” of the on-resistance R20on and the resistance value of “R” of the resistors R101 to R10N−1 are equal to those in Formula (5) before correction, the number N of bits of the input code can be increased by one bit, and thus, the accuracy of the output voltage can be increased.
According to Formula (10) after correction, the number N of bits is equal to that in Formula (5) before correction. If the resistance value of “R” equal to that in Formula (5) is used, the resistance value of “ron” of the on-resistance R20on can be increased by twice. Since the resistance value of “ron” of the on-resistance R20on is inversely proportional to an aspect ratio (W/L) (“W”: a channel width, “L”: a channel length) of the PMOS transistor Tr10 and the NMOS transistor Tr20, the channel width W can be reduced by, e.g., 1/2 times, and the area of each chip can be reduced.
According to Formula (10) after correction, the number N of bits is equal to that in Formula (5) before correction. If the switching elements S of the same size are used, the resistance value of “R” of the resistors R101 to R10N−1 can be reduced by 1/2 times, and thus, the area of each chip can be reduced.
Second Embodiment
FIG. 6 shows the configuration of a voltage output digital-to-analog converter circuit 40 according to a second embodiment. The voltage output digital-to-analog converter circuit 40 is formed by connecting NMOS transistors Tr30 and Tr40 to resistors R20N+1 and R20N+2 which are not connected to switching elements S1 to SN.
Sources of the NMOS transistors Tr30 and Tr40 are connected to a ground (GND), like the NMOS transistor Tr20 forming the switching element S. The same voltage as that in a case where data “1” is supplied to the gate of NMOS transistor Tr20 to turn on the NMOS transistor Tr20 is always applied to gates of the NMOS transistors Tr30 and Tr40. This causes the NMOS transistors Tr30 and Tr40 to be always on. Accordingly, another circuit for generating a reference voltage is not required to turn on the NMOS transistors Tr30 and Tr40.
Note that like the NMOS transistor Tr20 forming the switching element S, a resistance value of “ron” of an on-resistance in each of the NMOS transistors Tr30 and Tr40 is represented by:




  
    
      
        
          
            r
            on
          
          =
          
            1
            
              k
              ×
              
                W
                L
              
              ×
              
                (
                
                  
                    V
                    gs
                  
                  -
                  
                    V
                    t
                  
                
                )
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          k
          ⁢
          
            :
          
          ⁢
          
            
          
          ⁢
          constant
        
      
    
    
      
        (
        11
        )
      
    
  




In this embodiment, (Vgs−Vt) (“Vgs”: a gate-to-source voltage of an NMOS transistor, “Vt”: a gate threshold voltage) in Formula (11) has the same value in any of the NMOS transistors Tr30 and Tr40 and NMOS transistor Tr20 forming the switching element S.
Accordingly, the resistance value of “ron” of the NMOS transistors Tr30 and Tr40 can be made 2/3 times that of the on-resistance R20on of the NMOS transistor Tr20 forming the switching element S by making an aspect ratio (W/L) (“W”: a channel width, “L”: a channel length) of the NMOS transistors Tr30 and Tr40 3/2 times that of the NMOS transistor Tr20 forming the switching element S.
Note that the element area of an MOS transistor is generally smaller than that of a resistor. Accordingly, if the NMOS transistors Tr30 and Tr40 are connected to the resistors R20N+1 and R20N+2, which are not connected to the switching elements S1 to SN, as in this embodiment, the area of each chip can be made smaller than that of the first embodiment, in which the correction-resistance R301 and R302 are connected.
Note that the above-described embodiments are merely examples and not intended to limit the present invention. In the embodiments, the switching element S is formed by, e.g., connecting the source of PMOS transistor Tr10 and source of NMOS transistor Tr20 to the reference voltage terminal “Vref” and the ground terminal (GND) respectively. Various other switching elements may be used instead.

## Claims

1. A voltage output digital-to-analog converter circuit, comprising:
a plurality of switching elements provided corresponding to respective bits of an input digital signal to switch connection states of the plurality of switching elements to either the reference voltage terminal or the ground terminal according to the bits of the input digital signal; and
a resistor network which includes first resistive elements and second resistive elements having a resistance value twice a resistance value of the first resistive elements and in which one ends of the second resistive elements are connected to the plurality of switching elements respectively, the first resistive elements are connected between neighboring pairs of the other ends of the second resistive elements respectively, and other ones of the second resistive elements and third resistive elements having a desired resistance value are series-connected between the other ends of the second resistive elements, which are connected to switching elements of the plurality of switching elements to which a most significant bit and a least significant bit are supplied, and the ground.

2. The voltage output digital-to-analog converter circuit according to claim 1, wherein
each of the switching element is formed by connecting a source of first transistor and a source of second transistor to the reference voltage terminal and the ground terminal respectively and connecting the one end of the second resistive element to a junction point of the drain of first and second transistors.

3. The voltage output digital-to-analog converter circuit according to claim 2, wherein
the first and second transistors are formed such that resistance values of on-resistance are equal to each other.

4. The voltage output digital-to-analog converter circuit according to claim 2, wherein
the first transistor is composed of a PMOS transistor, and the second transistor is composed of an NMOS transistor.

5. The voltage output digital-to-analog converter circuit according to claim 1, wherein
each of the third resistive element has a resistance value which is 2/3 times a resistance value of on-resistance of the plurality of switching elements.

6. The voltage output digital-to-analog converter circuit according to claim 1, wherein
each of the third resistive element is a third transistor which has an on-resistance having a resistance value 2/3 times a resistance value of on-resistance of the plurality of switching elements.

7. The voltage output digital-to-analog converter circuit according to claim 6, wherein
the third transistor is composed of an NMOS transistor.

8. The voltage output digital-to-analog converter circuit according to claim 6, wherein
a voltage equal to a voltage applied to the gate of second transistor is always applied to a gate of the third transistor, and thereby the third transistor is set to be on.

9. The voltage output digital-to-analog converter circuit according to claim 6, wherein
each of the switching element is formed by connecting a first transistor and a second transistor to the reference voltage terminal and the ground terminal respectively and connecting the one end of the second resistive element to a junction point of the drain of first and second transistors.

10. The voltage output digital-to-analog converter circuit according to claim 9, wherein
the third transistor is formed to have an aspect ratio which is 3/2 times an aspect ratio of the second transistor.

11. The voltage output digital-to-analog converter circuit according to claim 1, further comprising
an amplifier connected to a junction point of the second resistive element connected to the switching element, to which the most significant bit is supplied, and the first resistive element.

12. A voltage output digital-to-analog converter circuit, comprising:
a plurality of switching elements provided corresponding to respective bits of an input digital signal to switch connection states of the plurality of switching elements to either the reference voltage terminal or the ground terminal according to the bits of the input digital signal; and
a resistor network which includes first resistive elements and second resistive elements having a resistance value twice a resistance value of the first resistive elements and in which one ends of the second resistive elements are connected to the plurality of switching elements respectively, the first resistive elements are connected between neighboring pairs of the other ends of the second resistive elements respectively, and other ones of the second resistive elements and correction transistors each having an on resistance with a desired resistance value are series-connected between the other ends of the second resistive elements, which are connected to switching elements of the plurality of switching elements to which a most significant bit and a least significant bit are supplied, and the ground.

13. The voltage output digital-to-analog converter circuit according to claim 12, wherein
each of the switching element is formed by connecting a source of first transistor and a source of second transistor to the reference voltage terminal and the ground terminal respectively and connecting the one end of the second resistive element to a junction point of the drain of first and second transistors.

14. The voltage output digital-to-analog converter circuit according to claim 13, wherein
the first and second transistors are formed such that resistance values of on-resistance are equal to each other.

15. The voltage output digital-to-analog converter circuit according to claim 13, wherein
the first transistor is composed of a PMOS transistor, and the second transistor is composed of an NMOS transistor.

16. The voltage output digital-to-analog converter circuit according to claim 12, wherein
each of the correction transistor has an on-resistance having a resistance value which is 2/3 times a resistance value of on-resistance of the plurality of switching elements.

17. The voltage output digital-to-analog converter circuit according to claim 12, wherein
the correction transistor is composed of an NMOS transistor.

18. The voltage output digital-to-analog converter circuit according to claim 13, wherein
a voltage equal to a voltage applied to the gate of second transistor is always applied to a gate of the correction transistor, and thereby the correction transistor is set to be on.

19. The voltage output digital-to-analog converter circuit according to claim 13, wherein
the correction transistor is formed to have an aspect ratio which is 3/2 times an aspect ratio of the second transistor.

20. The voltage output digital-to-analog converter circuit according to claim 12, further comprising
an amplifier connected to a junction point of the corresponding second resistive element connected to the switching element, to which the most significant bit is supplied, and the corresponding first resistive element.