# Patent

## Title
Power conversion device

## Abstract

A power conversion device including sub-inverters, each connected in series with respective phase of a three-phase main inverter including a smoothing capacitor, which is fed from a power supply via a converter, as a DC input thereof, and feeds power to a load using the sum of outputs of the inverters. A manipulative quantity is determined so that the DC voltage at each of smoothing capacitors which is an input of each of the sub-inverters will follow a command value. The manipulative quantity is added to an output voltage command for the three-phase main inverter, and is subtracted from an output voltage command for the sub-inverters. Thus, power is shifted from the three-phase main inverter to the smoothing capacitors of the sub-inverters.

## Background
TECHNICAL FIELD
The present invention relates to a power conversion device, or more particularly, to a power conversion device having multiple inverters connected in series with one another.
BACKGROUND ART
A driving device used as a conventional power conversion device adopts multiple power cells connected in series with each of phase output lines led to a three-phase load, for example, a three-phase AC motor. A three-phase AC input power is fed to a primary winding circuit of a power transformer. The primary winding circuit energizes multiple secondary winding circuits, and a three-phase power related to the secondary winding circuits is fed to the power cells respectively. The multiple power cells are connected to the respective phase output lines, and each of the power cells includes a three-phase input converter, a smoothing filter, and a single-phase output converter (refer to, for example, a patent document 1).
Patent document 1: JP-A-2001-103766
DISCLOSURE OF THE INVENTION
Problems to be Solved by the Invention
In the conventional power conversion device, multiple inverters are connected in series with one another for the purposes of minimization of harmonics in an output voltage or current and an increase in an output voltage. A converter is needed as a power source for each of the inverters. Further, by constructional reason that numerous converters whose potentials are different from one another are connected to one AC power supply, the number of parts such as switching elements increases, and a large and heavy multi-winding transformer is needed for insulation.
The present invention is intended to solve the above problems. An object of the present invention is to provide, in a power conversion device that has multiple inverters connected in series with one another in relation to phases, a structure suitable for a power conversion device that includes an inverter, from which a converter for feeding power to a DC power supply serving as a DC input is excluded, as one of the multiple inverters, and that has compactness and simplicity facilitated.
Means for Solving the Problems
A first power conversion device in accordance with the present invention has a first single-phase inverter, which converts direct-current (DC) power of a first DC power supply fed from a power supply into alternating-current (AC) power, and a second single-phase inverter, which converts DC power of a second DC power supply into AC power, connected in series at AC side thereof so as to feed power to a load. The first power conversion device includes a means that detects a voltage at the second DC power supply, and a DC voltage control means that adjusts an output voltage command for each of the first and the second single-phase inverters so that the detected voltage at the second DC power supply will follow a command value.
A second power conversion device in accordance with the present invention has a first single-phase inverter, which converts DC power of a first DC power supply fed from a power supply into AC power, and a second single-phase inverter, which converts DC power of a second DC power supply into AC power, connected in series at AC side thereof so as to feed power to a load. The second power conversion device includes a means that detects a voltage at the second DC power supply, and an initial charging control device that controls the outputs of each of the first and the second single-phase inverters so as to initially charge the second DC power supply. While applying a voltage, which does not permit the load to operate, to the load, the initial charging control device controls the outputs of each of the first and the second single-phase inverters so that the second DC power supply will be charged via the first and the second single-phase inverters.
ADVANTAGE OF THE INVENTION
In the first power conversion device according to the present invention, since the output voltage command for each of the first and the second single-phase inverters is adjusted so that the voltage at the second DC power supply which is an input of the second single-phase inverter will follow the command value, a converter to be used to externally feed power to the second DC power supply can be excluded or simplified, and the compactness and simplicity of the power conversion device can be facilitated.
In the second power conversion device according to the present invention, the initial charging control device is included so that the second DC power supply that is an input of the second single-phase inverter will be charged via the first and the second single-phase inverters. Consequently, the second single-phase inverter obviates the necessity of initial charging of the second DC power supply from an external power supply via a converter, and the compactness and simplicity of the power conversion device can be facilitated by excluding the converter.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a configuration diagram of a power conversion device in accordance with an embodiment 1 of the present invention;
FIG. 2 is a circuit diagram of a three-phase main inverter in accordance with the embodiment 1 of the present invention;
FIG. 3 is a circuit diagram of a converter in accordance with the embodiment 1 of the present invention;
FIG. 4 is a circuit diagram of a single-phase sub-inverter in accordance with the embodiment 1 of the present invention;
FIG. 5 is a block diagram of a DC voltage control circuit employed in the embodiment 1 of the present invention;
FIG. 6 is a block diagram of a driving signal generation circuit employed in the embodiment 1 of the present invention;
FIG. 7 is a block diagram of a driving signal generation circuit employed in an embodiment 2 of the present invention;
FIG. 8 is a configuration diagram of a power conversion device in accordance with an embodiment 3 of the present invention;
FIG. 9 is a block diagram of a DC voltage control circuit employed in the embodiment 3 of the present invention;
FIG. 10 is a block diagram of a driving signal generation circuit employed in the embodiment 3 of the present invention;
FIG. 11 is a block diagram of a driving signal generation circuit employed in an embodiment 4 of the present invention;
FIG. 12 is a configuration diagram of a power conversion device in accordance with an embodiment 5 of the present invention;
FIG. 13 is a block diagram of a DC voltage control circuit employed in the embodiment 5 of the present invention;
FIG. 14 is a block diagram of a driving signal generation circuit employed in the embodiment 5 of the present invention;
FIG. 15 is a configuration diagram of a power conversion device in accordance with an embodiment 6 of the present invention;
FIG. 16 is a block diagram of a DC voltage control circuit employed in the embodiment 6 of the present invention;
FIG. 17 is a block diagram of a driving signal generation circuit employed in the embodiment 6 of the present invention;
FIG. 18 is a configuration diagram of a power conversion device in accordance with an embodiment 7 of the present invention;
FIG. 19 is a block diagram of a DC voltage control circuit employed in the embodiment 7 of the present invention;
FIG. 20 is a block diagram of a driving signal generation circuit employed in the embodiment 7 of the present invention;
FIG. 21 is a block diagram of a driving signal generation circuit employed in an embodiment 8 of the present invention;
FIG. 22 is a configuration diagram of a power conversion device in accordance with an embodiment 9 of the present invention;
FIG. 23 is a block diagram of a DC voltage control circuit employed in the embodiment 9 of the present invention;
FIG. 24 is a block diagram of a driving signal generation circuit employed in the embodiment 9 of the present invention;
FIG. 25 is a block diagram of a driving signal generation circuit employed in an embodiment 10 of the present invention;
FIG. 26 is a configuration diagram of a power conversion device in accordance with an embodiment 11 of the present invention;
FIG. 27 is a block diagram of a DC voltage control circuit employed in the embodiment 11 of the present invention;
FIG. 28 is a configuration diagram of a power conversion device in accordance with an embodiment 12 of the present invention;
FIG. 29 is a configuration diagram of a power conversion device in accordance with an embodiment 13 of the present invention; and
FIG. 30 is a block diagram of a DC voltage control circuit employed in the embodiment 13 of the present invention.



BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1
A power conversion device in accordance with an embodiment 1 of the present invention will be described below in conjunction with drawings.
FIG. 1 is a diagram showing the configuration of a power conversion device in accordance with the embodiment 1 of the present invention. As shown in FIG. 1, the power conversion device has single-phase sub-inverters 2a to 2c of which AC sides of respective phases are connected in series with respective phase output lines on an AC side of a three-phase main inverter 1.
The three-phase main inverter 1 has a smoothing capacitor 6 serving as a first DC power supply on the DC side thereof, and has a converter 5 connected in parallel therewith. On the AC side of the converter 5, an AC power supply 11 is connected via a reactor 10. The single-phase sub-inverter 2a for u phase has a smoothing capacitor 3a serving as a second DC power supply on the DC side thereof, and has one terminal on the AC side thereof connected to the three-phase main inverter 1 and the other terminal thereon connected to a load 12. The single-phase sub-inverters 2b and 2c for v and w phases respectively have smoothing capacitors 3b and 3c respectively serving as second DC power supplies and have the same configuration as the single-phase sub-inverter 2a. 
The three-phase main inverter 1 is, as shown in FIG. 2 showing the circuitry, a three-phase inverter including multiple self-turn-off switching elements 21a to 21f and diodes 22a to 22f each of which is connected with the respective switching elements 21a to 21f in reverse parallel direction. Herein, the three-phase main inverter 1 is regarded as having first single-phase inverters star-connected as three phase parts. For each of the phases, the AC side of the first single-phase inverter (each phase part of the three-phase main inverter 1) and the AC side of each of the single-phase sub-inverters 2a to 2c serving as second single-phase inverters are connected in series with each other.
The converter 5 includes, for example, as shown in FIG. 3, multiple self-turn-off switching elements 23a to 23f and diodes 24a to 24f each of which is connected with the respective switching elements 23a to 23f in reverse parallel direction. Moreover, each of the single-phase sub-inverters 2a to 2c is, as shown in FIG. 4, a single-phase full-bridge inverter including multiple self-turn-off switching elements 25a to 25d and diodes 26a to 26d each of which is connected with the respective switching elements 25a to 25d in reverse parallel direction.
Moreover, the power conversion device has an overall command generation circuit 13, a DC voltage control circuit 14, and a driving signal production circuit 15 for the purpose of controlling the three-phase main inverter 1 and each of single-phase sub-inverters 2a to 2c and controlling the voltages of the smoothing capacitors 3a to 3c that are the DC inputs of each the single-phase sub-inverters 2a to 2c respectively.
The overall command generation circuit 13 is a circuit that generates an output voltage command for the load 12, and is a control circuit that outputs a desired voltage, which is outputted in total by all of the three-phase main inverter 1 and single-phase sub-inverters 2a to 2c, as a dq axial voltage command vd* and vq*.
The DC voltage control circuit 14 performs control computation on the basis of the outputs of voltage sensors 4a to 4c, which measure the voltages of the smoothing capacitors 3a to 3c that are the DC inputs of the respective single-phase sub-inverters 2a to 2c, and outputs a voltage command representing a manipulative quantity. The DC voltage control circuit 14 is constructed as shown in, for example, FIG. 5, wherein subtractors 31a to 31c each obtain the deviation between each of the DC voltages vdcsu, vdcsv, and vdcsw of the smoothing capacitors 3a to 3c of the respective single-phase sub-inverters 2a to 2c, which are measured by the voltage sensors 4a to 4c respectively, and a command value vdcs*, and controllers 32a to 32c obtain manipulative quantities. The manipulative quantities are used to adjust the output voltage command for each of the inverters 1 and 2a to 2c so that each of the DC voltages vdcsu, vdcsv, and vdcsw will follow the command value vdcs*, and d-axis manipulative quantities and q-axis manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* that are d-axis components and q-axis components distributed by dq axis distribution circuits 33a to 33c are outputted.
The controllers 32a to 32c may be formed with general proportional/integral (PI) controls or the like. Moreover, as a method according to which the dq axis distribution circuits 33a to 33c distribute the manipulative quantities, which are outputted from the controllers 32a to 32c respectively, into d-axis components and q-axis components, a method matching the type of load or the use purpose of the power conversion device may be selected. An arbitrary method such as a method of equalizing d-axis components and q-axis components or a method employing only the d axis or q axis may be adopted.
Based on the outputs of the overall command generation circuit 13 and DC voltage control circuit 14, the driving signal production circuit 15 computes voltages, each voltage is outputted by each of the three-phase main inverter 1 and the single-phase sub-inverters 2a to 2c, and produces pulses, with which the switching elements are driven, through pulse-width modulation (PWM). The driving signal production circuit 15 is constructed as shown in, for example, FIG. 6, wherein based on the dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13, an individual inverter voltage command production circuit 41 produces the dq-axis voltage command vdm* and vqm* for the three-phase main inverter 1 and the dq-axis voltage command vds* and vqs* for the single-phase sub-inverters 2a to 2c. At this time, the respective dq-axis voltage commands have relationships expressed by equations (1a) and (1b) below.

vd*=vdm*+vds*  (1a)

vq*=vqm*+vqs*  (1b)

The production of the dq-axis voltage command vdm* and vqm* for the three-phase main inverter 1 and the dq-axis voltage command vds* and vqs* for each of the single-phase sub-inverters 2a to 2c is not limited to that based on the above equations (1a) and (1b). An arbitrary means such as a method of determining voltages, which are assigned to the three-phase main inverter 1 and the single-phase sub-inverters 2a to 2c, according to the withstand voltage of the switching elements forming each of the inverters 1 and 2a to 2c or a method of keeping a voltage, which is outputted by the three-phase main inverter 1 or each of the single-phase sub-inverters 2a to 2c, constant may be adopted.
A sub-inverter instantaneous voltage command production circuit 42 inputs the sub-inverter dq-axis voltage command vdS* and vqs*, which is outputted by the individual inverter voltage command production circuit 41, and the d-axis manipulative quantities and the q-axis manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* which are outputted by the DC voltage control circuit 14, and computes a sub-inverter final voltage command 44a that is a command for the voltage instantaneous value outputted by the single-phase sub-inverters 2a to 2c. 
Incidentally, for conversion of a dq axial voltage into a three-phase voltage, an equation (2) below is generally employed.




  
    
      
        
          [
          
            
              
                
                  v
                  u
                
              
            
            
              
                
                  v
                  v
                
              
            
            
              
                
                  v
                  w
                
              
            
          
          ]
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  
                    
                      cos
                      ⁢
                      
                        
                      
                      ⁢
                      θ
                    
                  
                  
                    
                      
                        -
                        sin
                      
                      ⁢
                      
                        
                      
                      ⁢
                      θ
                    
                  
                
                
                  
                    
                      cos
                      ⁡
                      
                        (
                        
                          θ
                          -
                          
                            
                              2
                              ⁢
                              π
                            
                            3
                          
                        
                        )
                      
                    
                  
                  
                    
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            -
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
                
                  
                    
                      cos
                      ⁡
                      
                        (
                        
                          θ
                          +
                          
                            
                              2
                              ⁢
                              
                                
                              
                              ⁢
                              π
                            
                            3
                          
                        
                        )
                      
                    
                  
                  
                    
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            +
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    v
                    d
                  
                
              
              
                
                  
                    v
                    q
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        2
        )
      
    
  




In the above equation (2), vu, vv, and vw denote voltages of u, v, and w phases, and vd and vq denote voltages on the d and q axis respectively.
In the present embodiment, as expressed by equations (3a), (3b), and (3c) below, the dq axial manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* for the respective phases, which are outputted from the DC voltage control circuit 14, are subtracted from the sub-inverter dq-axis voltage command vdS* and vqs* which is outputted from the individual inverter voltage command production circuit 41, and the result is converted into a three-phase voltage in order to compute the sub-inverter final voltage command 44a (vus*, vvs*, and vws*)




  
    
      
        
          v
          us
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁢
                  
                    
                  
                  ⁢
                  θ
                
                -
                
                  sin
                  ⁢
                  
                    
                  
                  ⁢
                  θ
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      ds
                      *
                    
                    -
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        du
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      qs
                      *
                    
                    -
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qu
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          3
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          v
          vs
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁡
                  
                    (
                    
                      θ
                      -
                      
                        
                          2
                          ⁢
                          
                            
                          
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
                -
                
                  sin
                  ⁡
                  
                    (
                    
                      θ
                      -
                      
                        
                          2
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      ds
                      *
                    
                    -
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        dv
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      qs
                      *
                    
                    -
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qv
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          3
          ⁢
          b
        
        )
      
    
  
  
    
      
        
          v
          ws
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁡
                  
                    (
                    
                      θ
                      +
                      
                        
                          2
                          ⁢
                          
                            
                          
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
                -
                
                  sin
                  ⁡
                  
                    (
                    
                      θ
                      +
                      
                        
                          2
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      ds
                      *
                    
                    -
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        dw
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      qs
                      *
                    
                    -
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qw
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          3
          ⁢
          c
        
        )
      
    
  




The thus computed sub-inverter final voltage command 44a is inputted to a PWM circuit 44, and the PWM circuit 44 outputs voltage pulse signals, each signal has the pulse width thereof modulated, so as to drive each of the single-phase sub-inverters 2a to 2c. 
Moreover, a main inverter instantaneous voltage command production circuit 43 inputs the main inverter dq-axis voltage command vdm* and vqm* which is outputted by the individual inverter voltage command production circuit 41, and the d-axis manipulative quantities and q-axis manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* which are outputted by the DC voltage control circuit 14, and computes a main inverter final voltage command 45a that is a command for a voltage instantaneous value outputted by the three-phase main inverter 1.
In this case, as expressed by equations (4a), (4b), and (4c) below, the dq axial manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* for the respective phases, which are outputted by the DC voltage control circuit 14, are added to the main inverter dq-axis voltage command vdm* and vqm* which is outputted by the individual inverter voltage command production circuit 41, and the result is converted into a three-phase voltage in order to compute the main inverter final voltage command 45a (vum*, vvm*, and vwm*)




  
    
      
        
          v
          um
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁢
                  
                    
                  
                  ⁢
                  θ
                
                -
                
                  sin
                  ⁢
                  
                    
                  
                  ⁢
                  θ
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      
                        d
                        ⁢
                        
                          
                        
                        ⁢
                        m
                      
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        du
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      qm
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qu
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          4
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          v
          vm
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁡
                  
                    (
                    
                      θ
                      -
                      
                        
                          2
                          ⁢
                          
                            
                          
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
                -
                
                  sin
                  ⁡
                  
                    (
                    
                      θ
                      -
                      
                        
                          2
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      
                        d
                        ⁢
                        
                          
                        
                        ⁢
                        m
                      
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        dv
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      qm
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qv
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          4
          ⁢
          b
        
        )
      
    
  
  
    
      
        
          v
          wm
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁡
                  
                    (
                    
                      θ
                      +
                      
                        
                          2
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
                -
                
                  sin
                  ⁡
                  
                    (
                    
                      θ
                      +
                      
                        
                          2
                          ⁢
                          
                            
                          
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      
                        d
                        ⁢
                        
                          
                        
                        ⁢
                        m
                      
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        dw
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      qm
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qw
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          4
          ⁢
          c
        
        )
      
    
  




The thus computed main inverter final voltage command 45a is inputted to a PWM circuit 45, and the PWM circuit 45 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
As mentioned above, the dq axial manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* for the respective phases, which are outputted by the DC voltage control circuit 14, are added to the main inverter dq-axis voltage command vdm* and vqm*, and subtracted from the sub-inverter dq-axis voltage command vds* and vqs*. Since the AC sides of the single-phase sub-inverters 2a to 2c for the respective phases are connected in series with the respective phase output lines on the AC side of the three-phase main inverter 1, the voltage to be applied to the load 12 comes to the sum total of the output of the three-phase main inverter and the outputs of the single-phase sub inverters 2a to 2c. Consequently, the added manipulative quantities and the subtracted manipulative quantities are canceled out, and the voltage to be applied to the load 12 is determined with the dq-axis voltage command vd* and vq* outputted by the overall command generation circuit 13.
Assume that a voltage expressed on the d and q axis and applied to the load 12 is vd and vq, a current flowing into the load 12 is id and iq, and an active power to be fed to the load 12 is p. Moreover, assuming that out of the voltage outputted by each of the three-phase main inverter 1 and the single-phase sub-inverters 2a to 2c, voltage components caused by the dq-axis voltage command vdm*, vqm*, vds*, and vqs* outputted by the individual inverter voltage command production circuit 41 are vdm, vqm, vds, and vqs, the active power p is expressed by an equation (5) below.

p=vd·id+vq·iq=(vdm+vds)·id+(vqm+vqs)·iq  (5)

Since the active power p is three-phase power, for example, an active power pu of the u phase is expressed by an equation (6) below.




  
    
      
        
          p
          u
        
        =
        
          
            p
            /
            3
          
          =
          
            
              {
              
                
                  
                    (
                    
                      
                        v
                        
                          d
                          ⁢
                          
                            
                          
                          ⁢
                          m
                        
                      
                      +
                      
                        v
                        ds
                      
                    
                    )
                  
                  ·
                  
                    i
                    d
                  
                
                +
                
                  
                    (
                    
                      
                        v
                        qm
                      
                      +
                      
                        v
                        qs
                      
                    
                    )
                  
                  ·
                  
                    i
                    q
                  
                
              
              }
            
            /
            3
          
        
      
    
    
      
        (
        6
        )
      
    
  




On the other hand, assuming that the u-phase active power of the three-phase main inverter 1 is pmu, the active power of the single-phase sub-inverter 2a is ps2a, and voltage components caused by the dq axial manipulative quantities Δvdu* and Δvqu* outputted by the DC voltage control circuit 14 out of a voltage outputted by each of the inverters 1 and 2a are Δvdu and Δvqu*, pmu and Ps2a are expressed by equations (7) and (8) below in the same manner as that by the equation (6).

Pmu={(vdm+Δvdu)·id+(vqm+Δvqu)·iq}/3  (7)

Ps2a={(vds−Δvdu)·id+(vqs−Δvqu)·iq}/3  (8)

Moreover, pu, pmu, and ps2a have a relationship expressed by an equation (9) below.

Pu=pmu+ps2a  (9)

From the equations (7) to (9), it is understood that {(ΔVdu·id+ΔVqu·iq)/3} out of the active power outputted by the three-phase main inverter 1 is a component which is fed to the single-phase sub-inverter 2a but is not fed to the load 12. When power consumption caused by a loss occurring in the single-phase sub-inverter 2a is ignored, {(ΔVdu·id+ΔVqu·iq)/3} is fed to the smoothing capacitor 3a of the single-phase sub-inverter 2a, and the voltage of the smoothing capacitor 3a increases. Moreover, if {(ΔVdu·id+ΔVqu·iq)/3} takes on a negative value, the voltage of the smoothing capacitor 3a is lowered.
The voltage of the smoothing capacitor 3a is controlled as mentioned above. Since the d- and q-axis manipulative quantities ΔVdu* and ΔVqu* for the u phase are determined so that the DC voltage Vdcsu of the smoothing capacitor 3a will follow the command value Vdcs*, and can be sustained high reliably in a desired voltage.
The control of the DC voltage for the single-phase sub-inverter 2a has been described above. The same as that to the u phase applies to the v phase and w phase.
In the present embodiment, as mentioned above, since the manipulative quantities are determined so that each of the DC voltages Vdcsu, Vdcsv, and Vdcsw of the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c will follow the command value Vdcs*, and the output voltage command for each of the inverters 1 and 2a to 2c is adjusted, each of the DC voltages Vdcsu, Vdcsv, and Vdcsw of the smoothing capacitors 3a to 3c is controlled to be retained at a desired voltage. Consequently, the desired DC voltage can be sustained in each of the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c without feed of power from another power supply. Simplification of a device configuration and cost reduction such as exclusion of converters for the single-phase sub-inverters 2a to 2c or replacement of a multi-winding transformer with a reactor can be achieved.
Incidentally, due to an error of each of the control circuits, when the output voltage command for each of the inverters 1 and 2a to 2c is merely adjusted, if DC voltage control for each of the smoothing capacitors 3a to 3c cannot be precisely achieved, a converter is provided in order to feed power from the AC power supply 11. However, the capacity of the converter may be much smaller than the conventional one, and the device configuration can be fully simplified.
Moreover, in the embodiment 1, the three-phase main inverter 1 is a three-phase full-bridge inverter. Even when three single-phase full-bridge inverters like the single-phase sub-inverters 2a to 2c are adopted, the same control can be achieved. Moreover, even when the three-phase main inverter 1 and the single-phase sub-inverters 2a to 2c are three-level inverters, the same control can be achieved. Moreover, if power need not be restored to the AC power supply 11, the converter 5 may be a diode converter.
Embodiment 2
In the foregoing embodiment 1, in the driving signal production circuit 15, based on the dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13, a dq-axis voltage command is produced for not only the three-phase main inverter 1 but also the single-phase sub-inverters 2a to 2c. In the present embodiment, the single-phase sub-inverters 2a to 2c are operated as inverters to be used to output a voltage which cancel voltage harmonics outputted by the three-phase main inverter 1.
In this case, instead of the driving signal production circuit 15 in the embodiment 1, a driving signal production circuit 15a shown in FIG. 7 is employed. The other circuit components are identical to those of the embodiment 1.
The driving signal production circuit 15a computes a voltage outputted by each of the three-phase main inverter 1 and the single-phase sub-inverters 2a to 2c on the basis of the outputs of the overall command generation circuit 13 and DC voltage control circuit 14, and produces pulses, with which the respective switching elements are driven, through PWM. As shown in FIG. 7, the main inverter instantaneous voltage command production circuit 48 inputs a dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13 and the d-axis manipulative quantities and q-axis manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* outputted by the DC voltage control circuit 14, and computes a main inverter final voltage command 45a that is a command for a voltage instantaneous value outputted by the three-phase main inverter 1.
In this case, as expressed by equations (10a), (10b), and (10c) below, the dq axial manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* for the respective phases outputted by the DC voltage control circuit 14 are added to the dq-axis voltage command vd* and vq*, and the result is converted into a three-phase voltage in order to compute the main inverter final voltage command 45a (vum*, vvm*, and vwm*)




  
    
      
        
          v
          um
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁢
                  
                    
                  
                  ⁢
                  θ
                
                -
                
                  sin
                  ⁢
                  
                    
                  
                  ⁢
                  θ
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      
                        d
                        ⁢
                        
                          
                        
                      
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        du
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      q
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qu
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          10
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          v
          vm
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁡
                  
                    (
                    
                      θ
                      -
                      
                        
                          2
                          ⁢
                          
                            
                          
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
                -
                
                  sin
                  ⁡
                  
                    (
                    
                      θ
                      -
                      
                        
                          2
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      
                        d
                        ⁢
                        
                          
                        
                      
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        dv
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      q
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qv
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          10
          ⁢
          b
        
        )
      
    
  
  
    
      
        
          v
          wm
          *
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  cos
                  ⁡
                  
                    (
                    
                      θ
                      +
                      
                        
                          2
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
                -
                
                  sin
                  ⁡
                  
                    (
                    
                      θ
                      +
                      
                        
                          2
                          ⁢
                          
                            
                          
                          ⁢
                          π
                        
                        3
                      
                    
                    )
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      
                        d
                        ⁢
                        
                          
                        
                      
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        dw
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      q
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        qw
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        
          10
          ⁢
          c
        
        )
      
    
  




The thus computed main inverter final voltage command 45a is inputted to the PWM circuit 45, and the PWM circuit 45 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
A sub-inverter instantaneous voltage command production circuit 49 inputs the dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13, and the d-axis manipulative quantities and q-axis manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw* outputted by the DC voltage control circuit 14, and further inputs a voltage pulse signal Vumpwm, Vvmpwm, and Vwmpwm for the three-phase main inverter 1 outputted by the PWM circuit 45. Based on the input signals, the instantaneous voltage command production circuit 49 computes, as expressed by equations (11a), (11b), and (11c) below, a sub-inverter final voltage command 44a (vus*, vvs*, and vws*) that is a command for a voltage instantaneous value outputted by the single-phase sub-inverters 2a to 2c.




  
    
      
        
          v
          us
          *
        
        =
        
          
            
              
                
                  2
                  3
                
              
              ⁡
              
                [
                
                  
                    cos
                    ⁢
                    
                      
                    
                    ⁢
                    θ
                  
                  -
                  
                    sin
                    ⁢
                    
                      
                    
                    ⁢
                    θ
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    
                      
                        v
                        d
                        *
                      
                      -
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          du
                          *
                        
                      
                    
                  
                
                
                  
                    
                      
                        v
                        q
                        *
                      
                      -
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          qu
                          *
                        
                      
                    
                  
                
              
              ]
            
          
          -
          
            v
            umpwm
          
        
      
    
    
      
        (
        
          11
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          v
          vs
          *
        
        =
        
          
            
              
                
                  2
                  3
                
              
              ⁡
              
                [
                
                  
                    cos
                    ⁡
                    
                      (
                      
                        θ
                        -
                        
                          
                            2
                            ⁢
                            
                              
                            
                            ⁢
                            π
                          
                          3
                        
                      
                      )
                    
                  
                  -
                  
                    sin
                    ⁡
                    
                      (
                      
                        θ
                        -
                        
                          
                            2
                            ⁢
                            π
                          
                          3
                        
                      
                      )
                    
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    
                      
                        v
                        d
                        *
                      
                      -
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          dv
                        
                      
                    
                  
                
                
                  
                    
                      
                        v
                        q
                        *
                      
                      -
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          qv
                        
                      
                    
                  
                
              
              ]
            
          
          -
          
            v
            vmpwm
          
        
      
    
    
      
        (
        
          11
          ⁢
          b
        
        )
      
    
  
  
    
      
        
          v
          ws
          *
        
        =
        
          
            
              
                
                  2
                  3
                
              
              ⁡
              
                [
                
                  
                    
                      
                        
                          cos
                          ⁢
                          
                            (
                            
                              θ
                              +
                              
                                
                                  2
                                  ⁢
                                  
                                    
                                  
                                  ⁢
                                  π
                                
                                3
                              
                            
                            )
                          
                        
                        -
                      
                    
                  
                  
                    
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            +
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    
                      
                        v
                        d
                        *
                      
                      -
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          dw
                        
                      
                    
                  
                
                
                  
                    
                      
                        v
                        q
                        *
                      
                      -
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          qw
                        
                      
                    
                  
                
              
              ]
            
          
          -
          
            v
            wmpwm
          
        
      
    
    
      
        (
        
          11
          ⁢
          c
        
        )
      
    
  




The thus computed sub-inverter final voltage command 44a is inputted to the PWM circuit 44, and the PWM circuit 44 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive each of the single-phase sub-inverters 2a to 2c. 
Under the foregoing control, the three-phase main inverter 1 outputs a voltage caused by an output voltage command having the d-axis manipulative quantities and q-axis manipulative quantities Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw*, which are outputted by the DC voltage control circuit 14, added to the dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13.
The single-phase sub-inverters 2a to 2c each output a voltage caused by an output voltage command having the d-axis manipulative quantities and q-axis manipulative quantities Δvdu* and Δvqu*, Δvdv* and Δvqv*, or Δvdw* and Δvqw*, which are outputted by the DC voltage control circuit 14, and the voltage pulse signal of the three-phase main inverter 1 Vumpwm, Vvmpwm, and Vwmpwm, subtracted from the dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13. Since the voltage pulse signal Vumpwm, Vvmpwm, and Vwmpwm is subtracted from the signal of each phase having the dq-axis voltage command Vd* and Vq* converted into a three-phase instantaneous voltage, the fundamental wave component of the instantaneous voltage into which the dq-axis voltage command vd* and vq* is converted is canceled. The sub-inverter final voltage command 44a is a command causing output of a voltage that is in opposite phase with harmonics outputted from the three-phase main inverter 1, and the single-phase sub-inverters 2a to 2c operate to cancel the voltage harmonics outputted from the three-phase main inverter 1.
Further, similarly to the embodiment 1, the d and q axial manipulative quantities for the respective phases Δvdu*, Δvqu*, Δvdv*, Δvqv*, Δvdw*, and Δvqw*, which are outputted by the DC voltage control circuit 14, are added for computation of the voltage command for the three-phase main inverter 1, and are subtracted for computation of the voltage command for each of the single-phase sub-inverters 2a to 2c. Consequently, similarly to the embodiment 1, for example, for the u phase, {(Δdu·id+Δqu·iq)/3} out of an active power outputted by the three-phase main inverter 1 is fed to the single-phase sub-inverter 2a in order to charge the smoothing capacitor 3a of the single-phase sub-inverter 2a. When {(Δvdu·id+Δvqu·iq)/3} takes on a positive value, the voltage of the smoothing capacitor 3a increases. When {(Δvdu·id+Δvqu·iq)/3} takes on a negative value, the voltage of the smoothing capacitor 3a is lowered. The voltage of the smoothing capacitor 3a is thus controlled. Since the d- and q-axis manipulative quantities Δdu* and Δvqu* for the u phase are determined so that the DC voltage Vdcsu of the smoothing capacitor 3a will follow a command value Vdcs*, a desired voltage can be highly reliably sustained. The same as that to the u phase applies to the v and w phases.
The voltage outputted by the three-phase main inverter 1 contains harmonics due to PWM control. In the present embodiment, since the single-phase sub-inverters 2a to 2c are operated to cancel the voltage harmonics outputted by the three-phase main inverter 1, the voltage to be fed to the load 12 has the harmonics thereof suppressed.
Moreover, since the manipulative quantities are determined so that each of the DC voltages Vdcsu, Vdcsv, and Vdcsw of the respective smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c will follow the command value Vdcs*, and the output voltage command for each of the inverters 1 and 2a to 2c is adjusted, each of the DC voltages Vdcsu, Vdcsv, and Vdcsw of the respective smoothing capacitors 3a to 3c is controlled to be retained at a desired voltage. Consequently, the same advantage as the advantage of the embodiment 1 can be exerted, and the desired DC voltage can be sustained in each of the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c without feed of power from another power supply. Eventually, simplification of a device configuration and cost reduction such as exclusion/simplification of converters for the single-phase sub-inverters 2a to 2c or replacement of a multi-winding transformer with a reactor can be achieved.
Embodiment 3
FIG. 8 is a diagram showing the configuration of a power conversion device in accordance with an embodiment 3 of the present invention. A main circuit is identical to that shown in FIG. 1 of the embodiment 1. In the present embodiment, a dq axial voltage command is not employed, but a three-phase instantaneous voltage command is outputted from the overall command generation circuit 16.
As shown in the drawing, the power conversion device includes an overall command generation circuit 16, a DC voltage control circuit 17, and a driving signal production circuit 18, controls the three-phase main inverter 1 and respective single-phase sub-inverters 2a to 2c, and controls the voltages of the smoothing capacitors 3a to 3c that are the DC inputs of the respective single-phase sub-inverters 2a to 2c. 
The foregoing overall command generation circuit 16 is a circuit that generates an output voltage command for the load 12, and outputs a desired voltage, which is outputted in total by all of the three-phase main inverter 1 and the single-phase sub-inverters 2a to 2c, as a three-phase instantaneous voltage command vu*, vv*, and vw*.
The DC voltage control circuit 17 performs control computation on the basis of the outputs of voltage sensors 4a to 4c that measure the voltages of the respective smoothing capacitors 3a to 3c that are the DC inputs of the single-phase sub-inverters 2a to 2c, and outputs a voltage command representing manipulative quantities. The DC voltage control circuit 17 is constructed as shown in, for example, FIG. 9, wherein subtractors 31a to 31c obtain the deviations between the respective DC voltages Vdcsu, Vdcsv, and Vdcsw of the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c, which are measured by the voltage sensors 4a to 4c, and the command value Vdcs*, and controllers 34a to 34c obtain the manipulative quantities. The manipulative quantities are used to adjust the output voltage command for each of the inverters 1 and 2a to 2c so that each of the DC voltages Vdcsu, Vdcsv, and Vdcsw will follow the command value Vdcs*. The manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases are outputted. The controllers 34a to 34c may be formed with general PI controls or the like.
The driving signal production circuit 18 computes a voltage, which is outputted by each of the three-phase main inverter 1 and single-phase sub-inverters 2a to 2c, on the basis of the outputs of the overall command generation circuit 16 and DC voltage control circuit 17, and produces pulses, with which the respective switching elements are driven, through PWM. The driving signal production circuit 18 is constructed as shown in, for example, FIG. 10, wherein an individual inverter voltage command production circuit 50 produces a voltage command vumi*, vvmi*, and vwmi* for the three-phase main inverter 1 and a voltage command vusi*, vvsi*, and vwsi* for each of the single-phase sub-inverters 2a to 2c on the basis of an instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16. The respective voltage commands have relationships expressed by equations (12a), (12b), and (12c) below.

vu*=vumi*+vusi*  (12a)

vv*=vvmi*+vvsi*  (12b)

vw*=vwmi*+vwsi*  (12c)

The production of the voltage command vumi*, vvmi*, and vwmi* for the three-phase main inverter 1 and the voltage command vusi*, vvsi*, and vwsi* for each of the single-phase sub-inverters 2a to 2c is not limited to the one based on the equations (12a), (12b), and (12c). An arbitrary means such as a method of determining voltages, which are assigned to the three-phase main inverter 1 and single-phase sub-inverters 2a to 2c, according to the withstand voltage of the switching elements forming each of the inverters 1 and 2a to 2c or a method of keeping a voltage, which is outputted by the three-phase main inverter 1 or each of the single-phase sub-inverters 2a to 2c, constant may be adopted.
A sub-inverter instantaneous voltage command production circuit 46 inputs the sub-inverter voltage command vusi*, vvsi*l and vwsi* outputted by the individual inverter voltage command production circuit 50, and the manipulative quantities Δvu, Δvv*, and Δvw* for the respective phases outputted by the DC voltage control circuit 17, and computes a sub-inverter final voltage command 44a that is a command for a voltage instantaneous value outputted by the single-phase sub-inverters 2a to 2c. Herein, as expressed by equations (13a), (13b), and (13c) below, the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases outputted by the DC voltage control circuit 17 are subtracted from the sub-inverter voltage command vusi*, vvsi* and vwsi* outputted by the individual inverter voltage command production circuit 50 in order to compute the sub-inverter final voltage command 44a (vus*, Vvs* and vws*).

vus*=vusi*−Δvu*  (13a)

vvs*=vvsi*−Δvv*  (13b)

vws*=vwsi*−Δvw*  (13c)

The thus computed sub-inverter final voltage command 44a is inputted to the PWM circuit 44, and the PWM circuit 44 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive each of the single-phase sub-inverters 2a to 2c. 
Moreover, a main inverter instantaneous voltage command production circuit 47 inputs the main inverter voltage command vumi*, vvmi*, and vwmi* outputted by the individual inverter voltage command production circuit 50, and the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases outputted by the DC voltage control circuit 17, and computes a main inverter final voltage command 45a that is a command for a voltage instantaneous value outputted by the three-phase main inverter 1. Herein, as expressed by equations (14a), (14b), and (14c) below, the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases outputted by the DC voltage control circuit 17 are added to the main inverter voltage command vumi*, vvmi*, and vwmi* outputted by the individual inverter voltage command production circuit 50 in order to compute the main inverter final voltage command 45a (vum*, vvm*, and vwm*).

vum*=vumi*+Δvu*  (14a)

vvm*=vvmi*+Δvv*  (14b)

vwm*=vwmi*+Δvw*  (14c)

The thus computed main inverter final voltage command 45a is inputted to the PWM circuit 45, and the PWM circuit 45 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter
Under the foregoing control, the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases outputted by the DC voltage control circuit 17 are added for computation of the voltage command for the three-phase main inverter 1, and are subtracted for computation of the voltage command for each of the single-phase sub-inverters 2a to 2c. The voltage to be applied to the load 12 is the sum total of the output of the three-phase main inverter 1 and the outputs of the single-phase sub-inverters 2a to 2c. Therefore, the added manipulative quantities and the subtracted manipulative quantities are canceled out. The voltage to be applied to the load 12 is determined with the voltage command vu*, vv*, and vw* outputted by the overall command generation circuit 16.
Herein, the powers of the three-phase main inverter 1, single-phase sub-inverter 2a, and load 12 for the u phase will be discussed below. Assuming that the power factor of the load 12 is cos θ, the u-phase voltage of the three-phase inverter 1 is vum, the voltage of the single-phase sub-inverter 2a is vus, the voltage to be applied to the load 12 is vu, a current flowing into the u phase of the load 12 is iu, the active power to be fed to the load 12 by the u phase of the three-phase main inverter 1 and the sub-inverter 2a is pu, the active power pu is expressed by an equation (15) below.




  
    
      
        
          
            
              
                p
                u
              
              =
              
                
                  
                    v
                    u
                  
                  ·
                  
                    i
                    u
                  
                  ·
                  cos
                
                ⁢
                
                  
                
                ⁢
                θ
              
            
          
        
        
          
            
              =
              
                
                  
                    (
                    
                      
                        v
                        um
                      
                      +
                      
                        v
                        us
                      
                    
                    )
                  
                  ·
                  
                    i
                    u
                  
                  ·
                  cos
                
                ⁢
                
                  
                
                ⁢
                θ
              
            
          
        
      
    
    
      
        (
        15
        )
      
    
  




Among voltage components contained in each of the voltages vum, and vus outputted by the u phase of the three-phase main inverter 1 and the sub-inverter 2a, a component caused by the u-phase voltage command Vumi* or vusi* outputted by the individual inverter voltage command production circuit 50 shall be vumi or vusi, and a component caused by the u-phase manipulative quantity Δvu* outputted by the DC voltage control circuit 17 shall be Δvu. The active power outputted by the u phase of the three-phase main inverter 1 shall be pum, and the active power outputted by the single-phase sub inverter 2a shall be pus. Assuming that Δvu is a DC component, the relational equations (16a), (16b), and (17) below are established.

pum=(vum·cos θ+Δvu)·iu  (16a)

pus=(vus·cos θ−Δvu)·iu  (16b)

pu=pum+pus  (17)

From the equations (16a), (16b), and (17), it is understood that Δvu·iu out of the active power outputted from the u phase of the three-phase main inverter 1 is a component which is fed to the single-phase sub-inverter 2a but is not fed to the load 12. If power consumption caused by a loss occurring in the single-phase sub-inverter 2a is ignored, Δvu·iu charges the smoothing capacitor 3a of the single-phase sub-inverter 2a, and the voltage of the smoothing capacitor 3a increases. Moreover, if Δvu·iu takes on a negative value oppositely, the voltage of the smoothing capacitor 3a is lowered.
The voltage of the smoothing capacitor 3a of the single-phase sub-inverter 2a is controlled as mentioned above. Nevertheless, since the u-phase manipulative quantity Δvu* is determined so that the DC voltage vdcsu of the smoothing capacitor 3a will follow the command value vdcs*, a desired voltage can be sustained highly reliably. Incidentally, the same as that to the u phase can apply to the v and w phases.
As mentioned above, according to the present embodiment, in the power conversion device that controls an instantaneous value of a voltage or a current, since the manipulative quantities are determined so that each of the DC voltages vdcsu, vdcsv, and Vdcsw of the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c will follow the command value vdcs*, and an output voltage command for each of the inverters 1 and 2a to 2c is adjusted, each of the DC voltages vdcsu, vdcsv, and Vdcsw of the smoothing capacitors 3a to 3c is controlled to be sustained at a desired voltage. Consequently, the desired DC voltage can be sustained at each of the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c without feed of power from another power supply. Simplification of a device configuration and cost reduction such as exclusion of converters for the single-phase sub-inverters 2a to 2c or replacement of a multi-winding transformer with a reactor can be achieved.
Incidentally, due to an error of each of the control circuits, when the output voltage command for each of the inverters 1 and 2a to 2c is merely adjusted, if DC voltage control for each of the smoothing capacitors 3a to 3c cannot be highly precisely achieved, a converter is provided in order to feed power from the AC power supply 11. In this case, the capacity of the converter may be much smaller than the conventional one, and the device configuration can be fully simplified.
In the embodiment 3, the three-phase main inverter 1 is a three-phase full-bridge inverter. Even when three single-phase full-bridge inverters like the single-phase sub-inverters 2a to 2c or the like are employed, the same control can be achieved. Moreover, even when the three-phase main inverter 1 and single-phase sub-inverters 2a to 2c are three-level inverters, the same control can be achieved. Moreover, the converter 5 may be a diode converter if power need not be restored to the AC power supply 11.
Embodiment 4
In the foregoing embodiment 3, in the driving signal production circuit 18, a voltage command is produced for not only the three-phase main inverter 1 but also the single-phase sub-inverters 2a to 2c on the basis of the instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16. In the present embodiment, the single-phase sub-inverters 2a to 2c are operated as inverters to be used to output a voltage that cancels voltage harmonics outputted by the three-phase main inverter 1.
In this case, instead of the driving signal production circuit 18 in the embodiment 3, a driving signal production circuit 18a shown in FIG. 11 is employed. The other circuit components are identical to those of the embodiment 3.
The driving signal production circuit 18a computes a voltage, which is outputted by each of the three-phase main inverter 1 and single-phase sub-inverters 2a to 2c, on the basis of the outputs of the overall command generation circuit 16 and DC voltage control circuit 17, and produces pulses, with which the respective switching elements are driven, through PWM. As shown in FIG. 11, a main inverter instantaneous voltage command production circuit 71 inputs an instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16, and manipulative quantities Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 17, and computes a main inverter final voltage command 45a that is a command for a voltage instantaneous value outputted by the three-phase main inverter 1.
In this case, as expressed by equations (18a), (18b), and (18c) below, the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases outputted from the DC voltage control circuit 17 are added to the instantaneous voltage command vu*, vv*, and vw* in order to compute the main inverter final voltage command 45a (vum*, vvm*, and vwm*)

vum*=vu*+Δvu*  (18a)

vvm*=vv*+Δvv*  (18b)

vwm*=vw*+Δvw*  (18c)

The thus computed main inverter final voltage command 45a is inputted to the PWM circuit 45, and the PWM circuit 45 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
A sub-inverter instantaneous voltage command production circuit 72 inputs the voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16, and the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases outputted from the DC voltage control circuit 17, and further inputs a voltage pulse signal vumpwm, vvmpwm, and vwmpwm for the three-phase main inverter 1 outputted by the PWM circuit 45. Based on the input signals, the sub-inverter instantaneous voltage command production circuit 72 computes a sub-inverter final voltage command 44a (vus*, vvs*, and vws*), which is a command for a voltage instantaneous value outputted by the single-phase sub-inverters 2a to 2c, according to equations (19a), (19b), and (19c) below.

vus*=vu*−Δvu*−vumpwm  (19a)

vvs*=vv*−Δvv*−vvmpwm  (19b)

vws*=vv*−Δvv*−vwmpwm  (19c)

The thus computed sub-inverter final voltage command 44a is inputted to the PWM circuit 44, and the PWM circuit 44 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive each of the single-phase sub-inverters 2a to 2c. 
Under the foregoing control, the three-phase main inverter 1 outputs a voltage caused by an output voltage command having the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases, which are outputted by the DC voltage control circuit 17, added to the instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16.
The single-phase sub-inverters 2a to 2c each output a voltage caused by an output voltage command having the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases, which are outputted by the DC voltage control circuit 17, and the voltage pulse signal vumpwm, vvmpwm, and vwmpwm for the three-phase main inverter 1 subtracted from the instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16. Since the voltage pulse signal vumpwm, vvmpwm, and vwmpwm is subtracted from the signal of the instantaneous voltage command vu*, vv*, and vw*, the fundamental wave component of an instantaneous voltage is canceled. The sub-inverter final voltage command 44a becomes a command causing output of a voltage that is in opposite phase with harmonics outputted from the three-phase main inverter 1. The single-phase sub-inverters 2a to 2c operate to cancel the voltage harmonics outputted by the three-phase main inverter 1.
Further, similarly to the embodiment 3, the manipulative quantities Δvu*, Δvv*, and Δvw* for the respective phases, which are outputted by the DC voltage control circuit 17, are added for computation of the voltage command for the three-phase main inverter 1, and are subtracted for computation of the voltage command for each of the single-phase sub-inverters 2a to 2c. Consequently, similarly to the embodiment 3, for example, for the u phase, Δvu·iu out of an active power outputted by the three-phase main inverter 1 is fed to the single-phase sub-inverter 2a in order to charge the smoothing capacitor 3a of the single-phase sub-inverter 2a. When Δvu·iu takes on a positive value, the voltage of the smoothing capacitor 3a increases. When Δvu·iu takes on a negative value, oppositely, the voltage of the smoothing capacitor 3a is lowered. The voltage of the smoothing capacitor 3a of the single-phase sub-inverter 2a is thus controlled. Nevertheless, since the u-phase manipulative quantity Δvu* is determined so that the DC voltage vdcsu of the smoothing capacitor 3a will follow the command value vdcs*, a desired voltage can be sustained highly reliably. Incidentally, the same as that to the u phase can apply to the v and w phases.
A voltage outputted by the three-phase main inverter 1 contains harmonics due to PWM control. In the present embodiment, since the single-phase sub-inverters 2a to 2c are operated to cancel the voltage harmonics outputted by the three-phase main inverter 1, the voltage to be fed to the load 12 has the harmonics suppressed.
Moreover, since the manipulative quantities are determined so that each of the DC voltages vdcsu, Vdcsv, and Vdcsw of the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c will follow the command value Vdcs*, and the output voltage command for each of the inverters 1 and 2a to 2c is adjusted, each of the DC voltages vdcsu Vdcsv, and Vdcsw of the smoothing capacitors 3a to 3c is controlled to be sustained at a desired voltage. Consequently, the same advantage as that of the embodiment 3 can be exerted. The desired DC voltage can be sustained in each of the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c without feed of power from another power supply. Simplification of a device configuration and cost reduction such as exclusion/simplification of converters for the single-phase sub-inverters 2a to 2c and replacement of a multi-winding transformer with a reactor can be achieved.
Embodiment 5
FIG. 12 is a diagram showing the configuration of a power conversion device in accordance with an embodiment 5 of the present invention. In the embodiments 1 to 4, the power conversion device has the single-phase sub-inverters 2a to 2c of which the AC sides of the respective phases connected in series with the respective phase output lines on the AC side of the three-phase main inverter 1. In the present embodiment, the AC sides of two sub-inverters, that is, each of the single-phase sub-inverters 2a to 2c and each of single-phase sub-inverters 51a to 51c that are second single-phase inverters are connected in series with each of the phase output lines on the AC side of the three-phase main inverter 1 (first single-phase inverters for three phases). For convenience' sake hereinafter, the single-phase sub-inverters 2a to 2c shall be called a sub-inverter 1 group and the single-phase sub-inverters 51a to 51c shall be called a sub-inverter 2 group. Incidentally, the configuration of each of the single-phase sub-inverters 51a to 51c is identical to that of the single-phase sub-inverters 2a to 2c shown in FIG. 4.
The three-phase main inverter 1 has a smoothing capacitor 6 as a first DC power supply on the DC side thereof, and further has a converter 5 connected in parallel therewith. On the AC side of the converter 5, an AC power supply 11 is connected via a reactor 10. The single-phase sub-inverters 2a to 2c have smoothing capacitors 3a to 3c as second DC power supplies on the DC sides thereof. The single-phase sub-inverters 51a to 51c have smoothing capacitors 52a to 52c as second DC power supplies on the DC sides thereof.
Moreover, the power conversion device has an overall command generation circuit 13, a DC voltage control circuit 57, and a driving signal production circuit 58 for the purpose of controlling the three-phase main inverter 1 and respective single-phase sub-inverters 2a to 2c and 51a to 51c and controlling the voltages of the smoothing capacitors 3a to 3c and 52a to 52c that are the DC inputs of the respective single-phase sub-inverters 2a to 2c and 51a to 51c. 
The overall command generation circuit 13 is a circuit that generates an output voltage command for the load 12, and a control circuit that outputs a desired voltage, which is outputted in total by all of the three-phase main inverter 1 and single-phase sub-inverters 2a to 2c and 51a to 51c, as a dq-axis voltage command vd* and vq*.
The DC voltage control circuit 57 performs control computation on the basis of the outputs of voltage sensors 4a to 4c and 53a to 53c that measure the voltages of the smoothing capacitors 3a to 3c and 52a to 52c that are the DC inputs of the respective single-phase sub-inverters 2a to 2c and 51a to 51c, and outputs a voltage command as manipulative quantities. The DC voltage control circuit 57 is constructed as shown in, for example, FIG. 13, wherein a subtractor 61a obtains the deviations between the DC voltages vdcs1u, vdcs1v, and vdcs1w of the smoothing capacitors 3a to 3c of the sub-inverter 1 group, which are measured by the voltage sensors 4a to 4c, and a command value vdcs1*, and a controller 62a obtains manipulative quantities. The d-axis manipulative quantities and q-axis manipulative quantities, Δvd1u*, Δvq1u*, Δvd1v*, Δvq1v*, Δvd1w*, and Δvq1w*, which are d-axis components and q-axis components into which the manipulative quantities are divided by a dq-axis distribution circuit 63a, are outputted.
The controller 62a may be formed with a general PI control or the like. As for a method according to which the dq-axis distribution circuit 63a distributes the manipulative quantities, which are outputted from the controller 62a, into the d-axis components and q-axis components, a method that matches the type of load or the purpose of use of the power conversion device may be selected. An arbitrary method such as a method of equalizing the components on the d axis and the components on the q axis or a method employing only the d axis or q axis can be adopted.
The same applies to the sub-inverter 2 group. A subtractor 61b obtains the deviations between the DC voltages vdcs2u, vdcs2v, and vdcs2w of the smoothing capacitors 52a to 52c of the sub-inverter 2 group, which are measured by the voltage sensors 53a to 53c, and a command value vdcs2*, and a controller 62b obtains manipulative quantities. The d-axis manipulative quantities and q-axis manipulative quantities Δvd2u*, Δvq2u*, Δvd2v*, Δvq2v*, Δvd2w*, and Δvq2w* that are d-axis components and q-axis components into which the manipulative quantities are divided by a dq-axis distribution circuit 63b are outputted. Herein, each of the subtractors 61a and 61b, controllers 62a and 62b, and dq-axis distribution circuits 63a and 63b has three phases separately constructed.
The driving signal production circuit 58 computes a voltage, which is outputted by each of the three-phase main inverter 1 and single-phase sub-inverter 2a to 2c and 51a to 51c, on the basis of the outputs of the overall command generation circuit 13 and DC voltage control circuit 57, and produces pulses, with which the respective switching elements are driven, through PWM. The driving signal production circuit 58 is constructed as shown in, for example, FIG. 14, wherein an individual inverter voltage command production circuit 64 produces a dq-axis voltage command vdm* and vqm* for the three-phase main inverter 1, a dq-axis voltage command vds1* and vqs1* for the sub-inverter 1 group, and a dq-axis voltage command vds2* and vqs2* for the sub-inverter 2 group on the basis of a dq-axis voltage command Vd* and Vq*, which is outputted from the overall command generation circuit 13. At this time, the respective dq-axis voltage commands have relationships expressed by equations (20a) and (20b) below.

vd*=vdm*+Vds1*+vds2*  (20a)

vq*=vqm*+Vqs1*+Vqs2*  (20b)

As the production method, an arbitrary means such as a method of determining voltages, which are assigned to the three-phase main inverter 1, sub-inverter 1 group, and sub-inverter 2 group, according to the withstand voltage of the switching elements forming the respective inverters 1, 2a to 2c, and 51a to 51c, or a method of keeping the voltage, which is outputted by the three-phase main inverter 1, constant may be adopted.
A sub-inverter 1 group instantaneous voltage command production circuit 65 inputs the sub-inverter dq-axis voltage command vdS1* and vqs1* of the sub-inverter 1 group, which is outputted by the individual inverter voltage command production circuit 64, and the dq axial manipulative quantities Δvd1u*, Δvq1u*, Δvd1v*, Δvq1v*, Δvd1w*, and Δvq1w* for the sub-inverter 1 group which are outputted by the DC voltage control circuit 57, and computes a sub-inverter final voltage command 68a (vus1*, vvs1*, and vws1*), which is a command for a voltage instantaneous value to be outputted by the sub-inverter group, according to equations (21a), (21b), and (21c) below.




  
    
      
        
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            us
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        (
        
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The thus computed sub-inverter final voltage command 68a is inputted to a PWM circuit 68, and the PWM circuit 68 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive each of the single-phase sub-inverters 2a to 2c of the sub-inverter 1 group.
Likewise, as for the sub-inverter 2 group, a sub-inverter 2 group instantaneous voltage command production circuit 66 computes a sub-inverter final voltage command 69a (vus2*, vvs2*, and vws2*) according to equations (22a), (22b), and (22c) below.




  
    
      
        
          v
          
            us
            ⁢
            
              
            
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        =
        
          
            
              
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                  cos
                  ⁢
                  
                    
                  
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                -
                
                  sin
                  ⁢
                  
                    
                  
                  ⁢
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          ⁢
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                  ⁡
                  
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                    )
                  
                
              
              ]
            
          
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                      ⁢
                      
                        
                      
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                        v
                        
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                          ⁢
                          
                            
                          
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                      ⁢
                      
                        
                      
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                        v
                        
                          qw
                          ⁢
                          
                            
                          
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        (
        
          22
          ⁢
          c
        
        )
      
    
  




The thus computed sub-inverter final voltage command 69a is inputted to a PWM circuit 69, and the PWM circuit 69 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive each of the single-phase sub-inverters 51a to 51c of the sub-inverter 2 group.
A main inverter instantaneous voltage command production circuit 67 inputs the main inverter dq-axis voltage command vdm* and vqm*, which is outputted by the individual inverter voltage command production circuit 64, the d- and q-axis manipulative quantities Δvd1u*, Δvq1u*, Δvd1v*, Δvq1v*, Δvd1w*, Δvq1w*, Δvd2u*, Δvq2u*, Δvd2v*, Δvq2v*, Δvd2w*, and Δvq2w*, which are outputted by the DC voltage control circuit 57, and computes a main inverter final voltage command 70a (vum*, vvm*, and vwm*), which is a command for a voltage instantaneous value outputted by the three-phase main inverter 1, according to equations (23a), (23b), and (23c) below.




  
    
      
        
          
        
        ⁢
        
          
            v
            um
            *
          
          =
          
            
              
                
                  2
                  3
                
              
              ⁡
              
                [
                
                  
                    cos
                    ⁢
                    
                      
                    
                    ⁢
                    θ
                  
                  ⁢
                  
                    
                  
                  -
                  
                    sin
                    ⁢
                    
                      
                    
                    ⁢
                    θ
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    
                      
                        v
                        
                          d
                          ⁢
                          
                            
                          
                          ⁢
                          m
                        
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                      +
                      
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                        ⁢
                        
                          
                        
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                          v
                          
                            du
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                          *
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            du
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                          *
                        
                      
                    
                  
                
                
                  
                    
                      
                        v
                        
                          q
                          ⁢
                          
                            
                          
                          ⁢
                          m
                        
                        *
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            qu
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                          *
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            qu
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                          *
                        
                      
                    
                  
                
              
              ]
            
          
        
      
    
    
      
        (
        
          23
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          
            v
            vm
            *
          
          =
          
            
              
                
                  2
                  3
                
              
              ⁡
              
                [
                
                  
                    cos
                    ⁡
                    
                      (
                      
                        θ
                        -
                        
                          
                            2
                            ⁢
                            π
                          
                          3
                        
                      
                      )
                    
                  
                  ⁢
                  
                    
                  
                  -
                  
                    sin
                    ⁡
                    
                      (
                      
                        θ
                        -
                        
                          
                            2
                            ⁢
                            π
                          
                          3
                        
                      
                      )
                    
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    
                      
                        v
                        
                          d
                          ⁢
                          
                            
                          
                          ⁢
                          m
                        
                        *
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            dv
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                          *
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            dv
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                          *
                        
                      
                    
                  
                
                
                  
                    
                      
                        v
                        
                          q
                          ⁢
                          
                            
                          
                          ⁢
                          m
                        
                        *
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            qv
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                          *
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            qv
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                          *
                        
                      
                    
                  
                
              
              ]
            
          
        
      
    
    
      
        (
        
          23
          ⁢
          b
        
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          
            v
            wm
            *
          
          =
          
            
              
                
                  2
                  3
                
              
              ⁡
              
                [
                
                  
                    cos
                    ⁡
                    
                      (
                      
                        θ
                        +
                        
                          
                            2
                            ⁢
                            π
                          
                          3
                        
                      
                      )
                    
                  
                  ⁢
                  
                    
                  
                  -
                  
                    sin
                    ⁡
                    
                      (
                      
                        θ
                        +
                        
                          
                            2
                            ⁢
                            π
                          
                          3
                        
                      
                      )
                    
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    
                      
                        v
                        
                          d
                          ⁢
                          
                            
                          
                          ⁢
                          m
                        
                        *
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            dw
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                          *
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            dw
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                          *
                        
                      
                    
                  
                
                
                  
                    
                      
                        v
                        
                          q
                          ⁢
                          
                            
                          
                          ⁢
                          m
                        
                        *
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            qw
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                          *
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          
                            qw
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                          *
                        
                      
                    
                  
                
              
              ]
            
          
        
      
    
    
      
        (
        
          23
          ⁢
          c
        
        )
      
    
  




The thus computed main inverter final voltage command 70a is inputted to a PWM circuit 70, and the PWM circuit 70 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter.
As mentioned above, since the three-phase main inverter 1, sub-inverter 1 group, and sub-inverter 2 group are connected in series with one another, a voltage to be applied to the load 12 is the sum total of the voltages to be outputted by the three-phase main inverter 1, sub-inverter 1 group, and sub-inverter 2 group. The d- and q-axis manipulative quantities Δvd1u*, Δvq1u*, Δvd1v*, Δvq1v*, Δvd1w*, Δvq1w*, Δvd2u*, Δvq2u*, Δvd2v*, Δvq2v*, Δvd2w*, and Δvq2w*, which are outputted by the DC voltage control circuit 57, are added for computation of the voltage command for the three-phase main inverter 1, and are subtracted for computation of the voltage command for the sub-inverter 1 group or sub-inverter 2 group. Consequently, the added manipulative quantities and subtracted manipulative quantities are canceled out. The voltage to be applied to the load 12 is determined by the voltage command vd* and vq* which is outputted by the overall command generation circuit 13.
A voltage that is expressed on the d and q axes and is applied to the load 12 shall be vd and vq, and a current that is expressed on the d and q axes and flows into the load 12 shall be id and iq. Moreover, assuming that voltage components caused by the d- and q-axis voltage commands vdm*, vqm*, vds1*, vqs1*, vds2*, and vqs2* outputted by the individual inverter voltage command production circuit 64 are vdm, vqm, vds1, vqs1, vds2, and vqs2, and an active power to be fed to the load 12 is p, p is expressed by an equation (24) below.




  
    
      
        
          
            
              p
              =
              
                
                  
                    v
                    d
                  
                  ·
                  
                    i
                    d
                  
                
                +
                
                  
                    v
                    q
                  
                  ·
                  
                    i
                    q
                  
                
              
            
          
        
        
          
            
              =
              
                
                  
                    (
                    
                      
                        v
                        
                          d
                          ⁢
                          
                            
                          
                          ⁢
                          m
                        
                      
                      +
                      
                        v
                        
                          ds
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      +
                      
                        v
                        
                          ds
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                    )
                  
                  ·
                  
                    i
                    d
                  
                
                +
                
                  
                    (
                    
                      
                        v
                        qm
                      
                      +
                      
                        v
                        
                          qs
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      +
                      
                        v
                        
                          qs
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                    )
                  
                  ·
                  
                    i
                    q
                  
                
              
            
          
        
      
    
    
      
        (
        24
        )
      
    
  




Since the active power p is a three-phase power, an active power pu of, for example, the u phase is expressed by an equation (25) below.




  
    
      
        
          
            
              
                p
                u
              
              =
              
              ⁢
              
                p
                /
                3
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  (
                  
                    
                      
                        v
                        d
                      
                      ·
                      
                        i
                        d
                      
                    
                    +
                    
                      
                        v
                        q
                      
                      ·
                      
                        i
                        q
                      
                    
                  
                  )
                
                /
                3
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  {
                  
                    
                      
                        (
                        
                          
                            v
                            
                              d
                              ⁢
                              
                                
                              
                              ⁢
                              m
                            
                          
                          +
                          
                            v
                            
                              ds
                              ⁢
                              
                                
                              
                              ⁢
                              1
                            
                          
                          +
                          
                            v
                            
                              ds
                              ⁢
                              
                                
                              
                              ⁢
                              2
                            
                          
                        
                        )
                      
                      ·
                      
                        i
                        d
                      
                    
                    +
                    
                      
                        (
                        
                          
                            v
                            qm
                          
                          +
                          
                            v
                            
                              qs
                              ⁢
                              
                                
                              
                              ⁢
                              1
                            
                          
                          +
                          
                            v
                            
                              qs
                              ⁢
                              
                                
                              
                              ⁢
                              2
                            
                          
                        
                        )
                      
                      ·
                      
                        i
                        q
                      
                    
                  
                  }
                
                /
                3
              
            
          
        
      
    
    
      
        (
        25
        )
      
    
  




On the other hand, assuming that the active power of the u phase of the three-phase main inverter 1 is pmu, the active power of the single-phase sub-inverter 2a is ps1u, the active power of the single-phase sub-inverter 51a is ps2u, and voltage components caused by the d- and q-axis manipulative quantities Δvd1u*, Δvq1u*, Δvd2u*, and Δvq2u* for the u phase outputted by the DC voltage control circuit 57 are Δvd1u, Δvq1u, Δvd2u, and ΔVq2u, pmu, ps1u, and ps2u can be expressed in the same manner as that by the equation (25), and are expressed by equations (26) to (28) below.

pmu={(vdm+Δvd1u+Δvd2u)·id+(vqm+Δvq1u+vq2u)·iq}/3  (26)

ps1u={(vds−Δvd1u)·id+(vqs−Δvq1u)·iq}/3  (27)

ps2u={(vds−Δvq2u)·id+(vqs−Δvq2u)·iq}/3  (28)

Moreover, Pu, pmu, ps1u, and ps2u have a relationship expressed by an equation (29) below established.

pu=pmu+ps1u+ps2u  (29)

From the equations (26) to (29), it is understood that (Δvd1u·id+Δvq1u·iq)/3 out of the active power to be outputted by the three-phase main inverter 1 is a component to be fed to the single-phase sub-inverter 2a and that (Δvd2u·id+Δvq2u·iq)/3 is a component to be fed to the single-phase sub-inverter 51a. When power consumption caused by a loss occurring in the single-phase sub-inverter 2a or 51a is ignored, (Δvd1u·id+Δvq1u·iq)/3 or (Δvd2u·id+Δvq2u·iq)/3 charges the smoothing capacitor 3a or 52a of the single-phase sub-inverter 2a or 51a, and the voltage of the smoothing capacitor 3a or 52a increases. Moreover, if (Δvd1u·id+Δvq1u·iq)/3 or (Δvd2u·id+Δvq2u·iq)/3 takes on a negative value, oppositely, the voltage of the smoothing capacitor 3a or 52a is lowered.
The voltage of the smoothing capacitor 3a or 52a is thus controlled. Since the dq axial manipulative quantities for the u phase and the dq axial manipulative quantities for the u phase, Δvd1u*, Δvq1u*, Δvd2u*, and Δvq2u*, are determined so that the DC voltages vdcs1u and vdcs2u of the smoothing capacitors 3a and 52a will follow the command values vdcs1* and vdcs2*, desired voltages can be highly reliably sustained.
The DC voltage control for the single-phase sub-inverter 2a and 51a has been described so far. The same as that to the u phase applies to the v phase and w phase.
In the present embodiment, as mentioned above, since the manipulative quantities are determined so that each of the DC voltages of the smoothing capacitors 3a to 3c and 52a to 52c of the single-phase sub-inverters 2a to 2c and 51a to 51c will follow a command value, and the output voltage command for each of the inverters 1, 2a to 2c, and 51a to 51c is adjusted, each of the DC voltages of the smoothing capacitors 3a to 3c and 52a to 52c is controlled to be sustained at a desired voltage. Consequently, the desired DC voltage can be sustained in each of the smoothing capacitors 3a to 3c and 52a to 52c of the single-phase sub-inverters 2a to 2c and 51a to 51c without feed of power from another power supply. Consequently, simplification of a device configuration and cost reduction such as exclusion of converters for the single-phase sub-inverters 2a to 2c and 51a to 51c and replacement of a multi-winding transformer with a reactor can be achieved.
Incidentally, due to an error or the like of each of the control circuits, when the output voltage command for each of the inverters 1, 2a to 2c, and 51a to 51c is merely adjusted, if the DC voltage control for each of the smoothing capacitors 3a to 3c and 52a to 52c is not be precisely achieved, a converter is provided in order to feed power from the AC power supply 11. In this case, the capacity of the converters may be much smaller than the conventional one, and a device configuration can be fully simplified.
Moreover, the three-phase main inverter 1 is a three-phase full-bridge inverter. Even when three single-phase full-bridge inverters like the single-phase sub-inverters 2a to 2c are employed, the same control can be achieved. Moreover, even when the three-phase main inverter 1 and the single-phase sub-inverters 2a to 2c and 51a to 51c are three-level inverters, the same control can be achieved. Moreover, if power need not be restored to the AC power supply 11, the converter 5 may be a diode converter.
Embodiment 6
FIG. 15 is a diagram showing the configuration of a power conversion device in accordance with an embodiment 6 of the present invention. The main circuit is identical to that of the embodiment 5 shown in FIG. 12. However, in the present embodiment, a dq axial voltage command is not employed, but a three-phase instantaneous voltage command is outputted from an overall command generation circuit 16.
As shown in the drawing, the power conversion device includes an overall command generation circuit 16, a DC voltage control circuit 81, and a driving signal production circuit 82, controls a three-phase main inverter 1, each of single-phase sub-inverters 2a to 2c (sub-inverter 1 group), and single-phase sub-inverters 51a to 51c (sub-inverter 2 group), and controls the voltages of smoothing capacitors 3a to 3c and 52a to 52c that are the DC inputs of the respective single-phase sub-inverters 2a to 2c and 51a to 51c. 
The overall command generation circuit 16 described above is a circuit that generates an output voltage command for a load 12, and outputs a desired voltage, which is outputted in total by all of the three-phase main inverter 1 and single-phase sub-inverters 2a to 2c and 51a to 51c, as a three-phase instantaneous voltage command vu*, vv*, and vw*.
The DC voltage control circuit 81 performs control computation on the basis of the outputs of voltage sensors 4a to 4c and 53a to 53c that measure the voltages of the smoothing capacitors 3a to 3c and 52a to 52c that are the DC inputs of the respective single-phase sub-inverters 2a to 2c and 51a to 51c, and outputs a voltage command as manipulative quantities. The DC voltage control circuit 81 is constructed as shown in, for example, FIG. 16, wherein subtractors 83a and 83b obtain the deviations between the DC voltages vdcs1u, vdcs1v, vdcs1w, vdcs2u, vdcs2v and vdcs2w of the single-phase sub-inverters 2a to 2c and 51a to 51c, which are measured by the voltage sensors 4a to 4c and 53a to 53c, and command values vdcs1* and vdcs2*, and controllers 84a and 84b obtain manipulative quantities. The manipulative quantities are used to adjust an output voltage command for each of the inverters 1, 2a to 2c, and 51a to 51c so that each of the DC voltages vdcs1u, Vdcs1v, Vdcs1w, vdcs2u, vdcs2v, and vdcs2w will follow the command value vdcs1* or vdcs2*. The manipulative quantities for the respective phases, Δv1u*, Δv1v*, Δv1w*, Δv2u*, Δv2v*, and Δv2w*, are outputted from the DC voltage control circuit 81. The controllers 84a to 84c may be formed with general PI controls or the like.
The driving signal production circuit 82 computes a voltage, which is outputted by each of the three-phase main inverter 1 and single-phase sub-inverters 2a to 2c and 51a to 51c, on the basis of the outputs of the overall command generation circuit 16 and DC voltage control circuit 81, and produces pulses, with which the respective switching elements are driven, through PWM. The driving signal production circuit 82 is constructed as shown in, for example, FIG. 17, wherein an individual inverter voltage command production circuit 85 produces a voltage command vumi*, vvmi*, and vwmi* for the three-phase main inverter 1, and voltage commands vusi*, vvs1i*, vws1i*, vus2i*, vvs2i*, and vws2i* for the single-phase sub-inverters 2a to 2c and 51a to 51c. At this time, the respective voltage commands have relationships expressed by equations (30a), (30b), and (30c) below.

vu*=vumi*+vus1i*+vus2i*  (30a)

vv*=vvmi*+vvs1i*+vs2i*  (30b)

vw*=vwmi*+vws1i*+vws2i*  (30c)

The production of the respective voltage commands is not limited to that based on the above equations (30a), (30b), and (30c). An arbitrary means such as a method of determining voltages, which are assigned to the three-phase main inverter 1, single-phase sub-inverters 2a to 2c, and single-phase sub-inverters 51a to 51c, according to the withstand voltage of the switching elements forming the respective inverters 1, 2a to 2c, and 51a to 51c or a method of keeping the voltage, which is outputted by the three-phase main inverter 1 or each of the single-phase sub-inverters 2a to 2c and single-phase sub-inverters 51a to 51c, constant may be adopted.
A sub-inverter 1 group instantaneous voltage command production circuit 86 inputs a sub-inverter voltage command vus1i*, vvs1i*, and vws1i* for the sub-inverter 1 group, which is outputted by the individual inverter voltage command production circuit 85, and the manipulative quantities Δv1u*, Δv1v*, and Δv1w* for the sub-inverter 1 group, which are outputted by the DC voltage control circuit 81, and computes a sub-inverter final voltage command 68a that is a command for a voltage instantaneous value outputted by the single-phase sub-inverters 2a to 2c. As expressed by equations (31a), (31b), and (31c) below, the manipulative quantities Δv1u*, Δv1v*, and Δv1w* for the sub-inverter 1 group which are outputted by the DC voltage control circuit 81 are subtracted from the sub-inverter voltage command vus1i*, vvs1i*, and vws1i* for the sub-inverter 1 group which are outputted by the individual inverter voltage command production circuit 85 so as to compute a sub-inverter final voltage command 68a (vus1*, vvs1*, and vws1*)

vus1*=vus1i*−Δvu1*  (31a)

vvs1*=vvs1i*−Δvv1*  (31b)

vws1*=vws1i*−Δvw1*  (31c)

The thus computed sub-inverter final voltage command 68a is inputted to a PWM circuit 68, and the PWM circuit 68 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive each of the single-phase sub-inverters 2a to 2c. 
A sub-inverter 2 group instantaneous voltage command production circuit 87 inputs the sub-inverter voltage command vus2i*, vvs2i*, and vws2i* for the sub-inverter 2 group which is outputted by the individual inverter voltage command production circuit 85, and the manipulative quantities Δv2u*, Δv2v*, and Δv2w* for the sub-inverter 2 group, which are outputted by the DC voltage control circuit 81, so as to compute a sub-inverter final voltage command 69a that is a command for a voltage instantaneous value outputted by the single-phase sub-inverters 51a to 51c. Herein, as expressed by equations (32a), (32b), and (32c) below, the manipulative quantities Δv2u*, Δv2v*, and Δv2w* for the sub-inverter 2 group which are outputted by the DC voltage control circuit 81 are subtracted from the sub-inverter voltage command vus2i*, vvs2i*, and vws2i* for the sub-inverter 2 group, which are outputted by the individual inverter voltage command production circuit 85, in order to compute the sub-inverter final voltage command 69a (vus2*, vvs2*, and vws2*)

vus2*=vus2i−Δvu2*  (32a)

vvs2*=vvs2i−Δvv2*  (32b)

vws2*=vws2i−Δvw2*  (32c)

The thus computed sub-inverter final voltage command 69a is inputted to a PWM circuit 69, and the PWM circuit 69 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive each of the single-phase sub-inverters 51a to 51c. 
A main inverter instantaneous voltage command production circuit 88 inputs a main inverter voltage command vumi*, vvmi*, and vvwi* which is outputted by the individual inverter voltage command production circuit 85, and the manipulative quantities Δv1u*, Δv1v*, Δv1w*, Δv2u*, Δv2v*, and Δv2w*, which are outputted by the DC voltage control circuit 81, so as to compute a main inverter final voltage command 70a (vum*, vvm*, and vwm*), which is a command for a voltage instantaneous value outputted by the three-phase main inverter 1, according to equations (33a), (33b), and (33c) below.

vum*=vumi*+Δvu1*+Δvu2*  (33a)

vvm*=vvmi*+Δvv1*+Δvv2*  (33b)

vwm*=vwmi*+Δvw1*+Δvw2  (33c)

The thus computed main inverter final voltage command 70a is inputted to a PWM circuit 70, and the PWM circuit 70 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter.
As mentioned above, since the three-phase main inverter 1, sub-inverter 1 group, and sub-inverter 2 group are connected in series with one another, the voltage to be applied to the load 12 is the sum total of the voltages outputted by the three-phase main inverter 1, sub-inverter 1 group, and sub-inverter 2 group. The manipulative quantities Δv1u*, Δv1v*, Δv1w*, Δv2u*, Δv2v*, and Δv2w* outputted by the DC voltage control circuit 81 are added for computation of the voltage command for the three-phase main inverter 1, and are subtracted for computation of the voltage command for the sub-inverter 1 group or sub-inverter 2 group. Consequently, the added manipulative quantities and subtracted manipulative quantities are canceled out, and the voltage to be applied to the load 12 is determined with the instantaneous voltage command vu*, vv*, and vw* outputted by the overall command generation circuit 16.
Now, the powers of the three-phase main inverter 1, single-phase sub-inverters 2a and 51a, and load 12 for the u phase will be discussed. Assuming that the power factor of the load 12 is cos θ, the voltage of the u phase of the three-phase main inverter 1 is vum, the voltage of the single-phase sub-inverter 2a is vus1, the voltage of the single-phase sub-inverter 51a is vus2, the voltage to be applied to the load 12 is vu, the current flowing into the u phase of the load 12 is iu, and the active power to be fed to the load 12 by the u phase of the three-phase main inverter 1 and the single-phase sub-inverters 2a and 51a is pu, the active power pu is expressed by an equation (34) below.




  
    
      
        
          
            
              
                p
                u
              
              =
              
                
                  
                    v
                    u
                  
                  ·
                  
                    i
                    u
                  
                  ·
                  cos
                
                ⁢
                
                  
                
                ⁢
                θ
              
            
          
        
        
          
            
              =
              
                
                  
                    (
                    
                      
                        v
                        um
                      
                      +
                      
                        v
                        
                          us
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      +
                      
                        v
                        
                          us
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                    
                    )
                  
                  ·
                  
                    i
                    u
                  
                  ·
                  cos
                
                ⁢
                
                  
                
                ⁢
                θ
              
            
          
        
      
    
    
      
        (
        34
        )
      
    
  




Among the voltage components contained in vum, vus1, or vus2, a component caused by the u-phase voltage command vumi*, vus1i*, or vus2i* outputted by the individual inverter voltage command production circuit 51 shall be vumi, vus1i, or vus2i, and a component caused by the u-phase manipulative quantity vus1* or vu2* outputted by the DC voltage control circuit 81 shall be Δvu1 or Δvu2. The active power outputted by the u phase of the three-phase main inverter 1 shall be pum, the active power outputted by the single-phase sub-inverter 2a shall be pus1, and the active power outputted by the single-phase sub-inverter 51a shall be pus2. Assuming that Δvu1 and Δvu2 are DC components, relational equations (35a), (35b), (35c) and (36) below are established.

pum=(vum·cos θ+Δvu1+Δvu2)·iu  (35a)

pus1=(vus·cos θ−Δvu1)·iu  (35b)

pus2=(vus·cos θ−Δvu2)·iu  (35c)

pu=pum+pus1+pus2  (36)

From the equations (35a) to (35c) and (36), it is understood that Δvu1·iu out of the active power outputted from the u phase of the three-phase main inverter 1 is a component to be fed to the single-phase sub-inverter 2a and Δvu2·iu is a component to be fed to the single-phase sub-inverter 51a. If power consumption caused by losses in the single-phase sub-inverters 2a and 51a is ignored, Δvu1·iu and Δvu2·iu charge the smoothing capacitors 3a and 52a of the single-phase sub-inverters 2a and 51a, and the voltages of the smoothing capacitors 3a and 52a increase. If Δvu1·iu and Δvu2·iu take on negative values, oppositely, the voltages of the smoothing capacitors 3a and 52a are lowered.
The voltages of the smoothing capacitors 3a and 52a are thus controlled. Since the manipulative quantity Δvu1* or Δvu2* for the u phase is determined so that the DC voltage vdcs1u or vdcs2u of the smoothing capacitor 3a or 52a will follow the command value Δvdcs1* or Δvdcs2*, a desired voltage can be highly reliably sustained. The same as that to the u phase applies to the v and w phases.
As mentioned above, in the present embodiment, in the power conversion device that controls an instantaneous value of a voltage or current, since manipulative quantities are determined so that each of the DC voltages of the smoothing capacitors 3a to 3c and 52a to 52c of the single-phase sub-inverters 2a to 2c and 51a to 51c will follow a command value, and an output voltage command for each of the inverters 1, 2a to 2c, and 51a to 51c is adjusted, each of the DC voltages of the smoothing capacitors 3a to 3c and 52a to 52c is controlled to be sustained at a desired voltage. Consequently, the same advantage as that of the embodiment 5 can be exerted. The desired DC voltage can be sustained in each of the smoothing capacitors 3a to 3c and 52a to 52c of the single-phase sub-inverters 2a to 2c and 51a to 51c without feed of power from another power source. Simplification of a device configuration and cost reduction such as exclusion/simplification of converters for the single-phase sub-inverters 2a to 2c and 51a to 51c and replacement of a multi-winding transformer with a reactor can be achieved.
In the embodiments 5 and 6, as presented in the embodiments 2 and 4, the single-phase sub-inverters 2a to 2c and 51a to 51c may be operated as inverters for outputting voltages that cancel voltage harmonics outputted by the three-phase main inverter 1.
Embodiment 7
FIG. 18 is a diagram showing the configuration of a power conversion device in accordance with an embodiment 7 of the present invention.
As shown in FIG. 18, the power conversion device has a three-phase main inverter 1 and a three-phase sub-inverter 91, their respective phase output lines on AC sides are connected in series with each other via a load 90 having open windings. The three-phase main inverter 1 has a smoothing capacitor 6, which serves as a first DC power supply, on the DC side thereof, and further has a converter 5 connected in parallel therewith. On the AC side of the converter 5, an AC power supply 11 is connected via a reactor 10. The three-phase sub-inverter 91 has a smoothing capacitor 92, which serves as a second DC power supply, on the DC side thereof.
The three-phase main inverter 1 and converter 5 are identical to those of the embodiment 1.
Herein, the three-phase main inverter 1 and the three-phase sub-inverter 91 are regarded as having first single-phase inverters and second single-phase inverters star-connected respectively as three phase parts. For each of phases, the AC side of the first single-phase inverter (each phase part of the three-phase main inverter 1) and the AC side of the second single-phase inverter (each phase part of the three-phase sub-inverter 91) are connected in series with each other with the load 90 between them.
Moreover, for controlling the three-phase main inverter 1 and three-phase sub-inverter 91, and controlling the voltage of the smoothing capacitor 92 that is the DC input of the three-phase sub-inverter 91, the power conversion device has an overall command generation circuit 13, a DC voltage control circuit 94, and a driving signal production circuit 95.
The overall command generation circuit 13 is a circuit identical to that of the embodiment 1 which generates an output voltage command for the load 12, and a control circuit that outputs a desired voltage, which is outputted in total by all of the three-phase main inverter 1 and three-phase sub-inverter 91, as a dq-axis voltage command vd* and vq*.
The DC voltage control circuit 94 performs control computation on the basis of the output of a voltage sensor 93 that measures the DC voltage of the smoothing capacitor 92 which is the DC input of the three-phase sub-inverter 91, and outputs a voltage command as manipulative quantities. The DC voltage control circuit 94 is constructed as shown in, for example, FIG. 19, wherein a subtractor 96 obtains the deviation between the DC voltage vdcs of the smoothing capacitor 92 of the three-phase sub-inverter 91, which is measured by the voltage sensor 93, and a command value vdcs*, and a controller 97 obtains a manipulative quantity. The manipulative quantity is used to adjust an output voltage command for each of the inverters 1 and 91, which will be described later, so that the DC voltage vdcs will follow the command value vdcs*. A d-axis manipulative quantity Δvd* and a q-axis manipulative quantity Δvq* that are a d-axis component and a q-axis component into which the manipulative quantity is divided by a dq-axis distribution circuit 98 are outputted.
The controller 97 may be formed with a general PI control or the like. Moreover, as a method according to which the dq-axis distribution circuit 98 distributes the manipulative quantity, which is outputted from the controller 97, into the d-axis component and q-axis component, a method that matches the type of load or the purpose of use of the power conversion device may be selected. An arbitrary method such as a method of equalizing the d-axis and q-axis components or a method of employing only the d axis or q axis may be adopted.
The driving signal production circuit 95 computes a voltage, which is outputted by each of the three-phase main inverter 1 and three-phase sub-inverter 91 on the basis of the outputs of the overall command generation circuit 13 and DC voltage control circuit 94, and produces pulses, with which the respective switching elements are driven, through PWM. The driving signal production circuit 95 is constructed as shown in, for example, FIG. 20, wherein an individual inverter voltage command production circuit 108 produces a dq-axis voltage command vdm* and vqm* for the three-phase main inverter 1, and a dq-axis voltage command vdS* and vqs* for the three-phase sub-inverter 91 on the basis of the dq-axis voltage command Vd* and Vq* which is outputted from the overall command generation circuit 13. At this time, the respective dq-axis voltage commands have relationships expressed by equations (37a) and (37b) below.

vd*=vdm*−vds*  (37a)

vq*=vqm*−vqs*  (37b)

The production of the dq-axis voltage command vdm* and vqm* for the three-phase main inverter 1, and a dq-axis voltage command vds* and vqs* for the three-phase sub-inverter 91 is not limited to that based on the equations (37a) and (37b). An arbitrary means such as a method of determining voltages, which are assigned to the three-phase main inverter 1 and three-phase sub-inverter 91, according to the withstand voltage of the switching elements forming the respective inverters 1 and 91 or a method of keeping the voltage, which is outputted by the three-phase main inverter 1 or three-phase sub-inverter 91, constant may be adopted.
A sub-inverter instantaneous voltage command production circuit 99 inputs a sub-inverter dq-axis voltage command vds* and vqs* which is outputted by the individual inverter voltage command production circuit 108, and a d-axis manipulative quantity and a q-axis manipulative quantity Δvd* and Δvq* which are outputted by the DC voltage control circuit 94, and computes a sub-inverter final voltage command 44a that is a command for a voltage instantaneous value outputted by the three-phase sub-inverter 91.
In the present embodiment, as expressed by an equation (38) below, the d- and q-axis manipulative quantities Δvd* and Δvq* outputted from the DC voltage control circuit 94 are added to the sub-inverter dq-axis voltage command vds* and vqs* outputted by the individual inverter voltage command production circuit 108, and the result is converted into a three-phase voltage in order to compute the sub-inverter final voltage command 44a (vus*, vvs*, and vws*)




  
    
      
        
          [
          
            
              
                
                  v
                  us
                  *
                
              
            
            
              
                
                  v
                  vs
                  *
                
              
            
            
              
                
                  v
                  ws
                  *
                
              
            
          
          ]
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  
                    
                      cos
                      ⁢
                      
                        
                      
                      ⁢
                      θ
                    
                  
                  
                    
                      
                        -
                        sin
                      
                      ⁢
                      
                        
                      
                      ⁢
                      θ
                    
                  
                
                
                  
                    
                      cos
                      ⁡
                      
                        (
                        
                          θ
                          -
                          
                            
                              2
                              ⁢
                              π
                            
                            3
                          
                        
                        )
                      
                    
                  
                  
                    
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            -
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
                
                  
                    
                      cos
                      ⁡
                      
                        (
                        
                          θ
                          +
                          
                            
                              2
                              ⁢
                              π
                            
                            3
                          
                        
                        )
                      
                    
                  
                  
                    
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            +
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      ds
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        d
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      qs
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        q
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        38
        )
      
    
  




The thus computed sub-inverter final voltage command 44a is inputted to a PWM circuit 44, and the PWM circuit 44 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase sub-inverter 91.
Moreover, a main inverter instantaneous voltage command production circuit 100 inputs a main inverter dq-axis voltage command vdm* and vqm* outputted by the individual inverter voltage command production circuit 108, and the d- and q-axis manipulative quantities Δvd* and Δvq* outputted by the DC voltage control circuit 94, and computes a main inverter final voltage command 45a that is a command for a voltage instantaneous value outputted by the three-phase main inverter 1.
In this case, as expressed by an equation (39) below, the d- and q-axis manipulative quantities Δvd* and Δvq* outputted by the DC voltage control circuit 94 are added to the main inverter dq-axis voltage command vdm* and vqm* outputted by the individual inverter voltage command production circuit 108, and the result is converted into a three-phase voltage in order to compute the main inverter final voltage command 45a (vum*, vvm*, and vwm*)




  
    
      
        
          [
          
            
              
                
                  v
                  um
                  *
                
              
            
            
              
                
                  v
                  vm
                  *
                
              
            
            
              
                
                  v
                  wm
                  *
                
              
            
          
          ]
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  
                    
                      cos
                      ⁢
                      
                        
                      
                      ⁢
                      θ
                    
                  
                  
                    
                      
                        -
                        sin
                      
                      ⁢
                      
                        
                      
                      ⁢
                      θ
                    
                  
                
                
                  
                    
                      cos
                      ⁡
                      
                        (
                        
                          θ
                          -
                          
                            
                              2
                              ⁢
                              π
                            
                            3
                          
                        
                        )
                      
                    
                  
                  
                    
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            -
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
                
                  
                    
                      cos
                      ⁡
                      
                        (
                        
                          θ
                          +
                          
                            
                              2
                              ⁢
                              π
                            
                            3
                          
                        
                        )
                      
                    
                  
                  
                    
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            +
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      
                        d
                        ⁢
                        
                          
                        
                        ⁢
                        m
                      
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        d
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      qm
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        q
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        39
        )
      
    
  




The thus computed main inverter final voltage command 45a is inputted to a PWM circuit 45, and the PWM circuit 45 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
Since the three-phase main inverter 1 and three-phase sub-inverter 91 are connected in series with each other face to face with the load 90 between them, the voltage to be applied to the load 90 is the difference between the output voltage of the three-phase main inverter 1 and the output voltage of the three-phase sub-inverter 91. Since the d- and q-axis manipulative quantities Δvd* and Δvq* outputted by the DC voltage control circuit 94 are added to the output voltage command for each of the three-phase main inverter 1 and three-phase sub-inverter 91, the added manipulative quantities and added manipulative quantities are canceled out. The voltage to be applied to the load 90 is determined with the voltage command vd* and vq* outputted by the overall command generation circuit 13.
A voltage that is applied to the load 90 and is defined on the d and q axes shall be vd and vq, a current flowing into the load 90 shall be id and iq, and an active power to be fed to the load 90 shall be p. Moreover, assuming that voltage components, which are caused by the dq-axis voltage commands vdm* and vqm* and vds* and vqs* outputted by the individual inverter voltage command production circuit 108, out of the voltages outputted by the three-phase main inverter 1 and three-phase sub-inverter 91 are vdm, vqm, vds, and vqs, the active power p is expressed by an equation (40) below.

p=vd·id+Vq·iq=(vdm−vds)·id+(vqm−vqs)·iq  (40)

On the other hand, assuming that the active power of the three-phase main inverter 1 is pm, the active power of the three-phase sub-inverter 91 is ps, and voltage components caused by the d- and q-axis manipulative quantities Δvd* and Δvq* outputted by the DC voltage control circuit 94 are Δvd and Δvq, the active powers pm and ps are expressed by equations (41) and (42) below.




  
    
      
        
          p
          m
        
        =
        
          
            
              (
              
                
                  v
                  
                    d
                    ⁢
                    
                      
                    
                    ⁢
                    m
                  
                
                +
                
                  Δ
                  ⁢
                  
                    
                  
                  ⁢
                  
                    v
                    d
                  
                
              
              )
            
            ·
            
              i
              d
            
          
          +
          
            
              (
              
                
                  v
                  qm
                
                +
                
                  Δ
                  ⁢
                  
                    
                  
                  ⁢
                  
                    v
                    q
                  
                
              
              )
            
            ·
            
              i
              q
            
          
        
      
    
    
      
        (
        41
        )
      
    
  
  
    
      
        
          
            
              
                p
                s
              
              =
              
                
                  
                    (
                    
                      
                        v
                        ds
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          d
                        
                      
                    
                    )
                  
                  ·
                  
                    (
                    
                      -
                      
                        i
                        d
                      
                    
                    )
                  
                
                +
                
                  
                    (
                    
                      
                        v
                        qs
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          q
                        
                      
                    
                    )
                  
                  ·
                  
                    (
                    
                      -
                      
                        i
                        q
                      
                    
                    )
                  
                
              
            
          
        
        
          
            
              =
              
                
                  
                    -
                    
                      (
                      
                        
                          v
                          ds
                        
                        +
                        
                          Δ
                          ⁢
                          
                            
                          
                          ⁢
                          
                            v
                            d
                          
                        
                      
                      )
                    
                  
                  ·
                  
                    i
                    d
                  
                
                -
                
                  
                    (
                    
                      
                        v
                        qs
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          q
                        
                      
                    
                    )
                  
                  ·
                  
                    i
                    q
                  
                
              
            
          
        
      
    
    
      
        (
        42
        )
      
    
  




Moreover, p, pm, and ps have a relational equation (43) below established.

p=pm+ps  (43)

From the equations (41) to (43), it is understood that (Δvd·id+Δvq·iq) out of the active power outputted by the three-phase main inverter 1 is a component which is fed to the three-phase sub-inverter 91 but is not fed to the load 90. If power consumption caused by a loss in the three-phase sub-inverter 91 is ignored, (Δvd·id+Δvq·iq) charges the smoothing capacitor 92 of the three-phase sub-inverter 91, and the voltage of the smoothing capacitor 92 increases. Moreover, if (Δvd·id+Δvq·iq) takes on a negative value, oppositely the voltage of the smoothing capacitor 92 is lowered.
The voltage of the smoothing capacitor 92 is thus controlled. Since the d- and q-axis manipulative quantities Δvd* and Δvq* are determined so that the DC voltage vdcs of the smoothing capacitor 92 will follow the command value vdcs*, a desired voltage can be highly reliably sustained.
As mentioned above, in the present embodiment, in the power conversion device having the three-phase main inverter 1 and three-phase sub-inverter 91 connected in series with each other face to face with the load 90 between them, since manipulative quantities are determined so that the DC voltage of the smoothing capacitor 92 of the three-phase sub-inverter 91 will follow a command value, and the output voltage command for each of the inverters 1 and 91 is adjusted, the DC voltage of the smoothing capacitor 92 can be controlled to be sustained at a desired voltage. Consequently, the desired DC voltage is sustained in the smoothing capacitor 92 of the three-phase sub-inverter 91 without feed of power from another power supply. Eventually, simplification of a device configuration and cost reduction such as exclusion/simplification of a converter for the three-phase sub-inverter 91 and replacement of a multi-winding transformer with a reactor can be achieved.
Moreover, in the embodiment 7, the three-phase main inverter 1 and three-phase sub-inverter 91 are three-phase full-bridge inverters. Even when three single-phase full-bridge inverters are adopted as one or both of the inverters 1 and 91, the same control can be achieved. Moreover, even when the three-phase main inverter 1 and three-phase sub-inverter 91 are three-level inverters, the same control can be achieved. Moreover, if power need not be restored to the AC power supply 11, the converter 5 may be a diode converter.
Embodiment 8
In the embodiment 7, in the driving signal production circuit 95, a dq-axis voltage command is produced for not only the three-phase main inverter 1 but also the three-phase sub-inverter 91 on the basis of the dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13. In the present embodiment, the three-phase sub-inverter 91 is operated as an inverter for outputting a voltage that cancels voltage harmonics outputted by the three-phase main inverter 1.
In this case, instead of the driving signal production circuit 95 in the embodiment 7, a driving signal production circuit 95a shown in FIG. 21 is employed. The other circuit components are identical to those of the embodiment 7.
The driving signal production circuit 95a computes a voltage, which is outputted by each of the three-phase main inverter 1 and three-phase sub-inverter 91, on the basis of the outputs of the overall command generation circuit 13 and DC voltage control circuit 94, and produces pulses, with which the respective switching elements are driven, through PWM. As shown in FIG. 21, a main inverter instantaneous voltage command production circuit 102 inputs a dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13, and a d-axis manipulative quantity and a q-axis manipulative quantity Δvd* and Δvq* outputted by the DC voltage control circuit 94, and computes a main inverter final voltage command 45a that is a command for a voltage instantaneous value outputted by the three-phase main inverter 1.
In this case, as expressed by an equation (44) below, the dq axial manipulative quantities Δvd* and Δvq* outputted from the DC voltage control circuit 94 are added to the dq-axis voltage command vd* and vq*, and the result is converted into a three-phase voltage in order to compute the main inverter final voltage command 45a (vum*, vvm*, and vwm*)




  
    
      
        
          [
          
            
              
                
                  v
                  um
                  *
                
              
            
            
              
                
                  v
                  vm
                  *
                
              
            
            
              
                
                  v
                  wm
                  *
                
              
            
          
          ]
        
        =
        
          
            
              
                2
                3
              
            
            ⁡
            
              [
              
                
                  
                    
                      cos
                      ⁢
                      
                        
                      
                      ⁢
                      θ
                    
                  
                  
                    
                      
                        -
                        sin
                      
                      ⁢
                      
                        
                      
                      ⁢
                      θ
                    
                  
                
                
                  
                    
                      cos
                      ⁡
                      
                        (
                        
                          θ
                          -
                          
                            
                              2
                              ⁢
                              π
                            
                            3
                          
                        
                        )
                      
                    
                  
                  
                    
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            -
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
                
                  
                    
                      cos
                      ⁡
                      
                        (
                        
                          θ
                          +
                          
                            
                              2
                              ⁢
                              π
                            
                            3
                          
                        
                        )
                      
                    
                  
                  
                    
                      -
                      
                        sin
                        ⁡
                        
                          (
                          
                            θ
                            +
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                  
                
              
              ]
            
          
          ⁡
          
            [
            
              
                
                  
                    
                      v
                      d
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        d
                        *
                      
                    
                  
                
              
              
                
                  
                    
                      v
                      q
                      *
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        v
                        q
                        *
                      
                    
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        44
        )
      
    
  




The thus computed main inverter final voltage command 45a is inputted to a PWM circuit 45, and the PWM circuit 45 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
A sub-inverter instantaneous voltage command production circuit 101 inputs the dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13, and the d- and q-axis manipulative quantities Δvd* and Δvq* outputted by the DC voltage control circuit 94, and further inputs a voltage pulse signal vumpwm, vvmpwm, and vwmpwm for the three-phase main inverter 1 outputted by the PWM circuit 45. Based on the input signals, the sub-inverter instantaneous voltage command production circuit 101 computes a sub-inverter final voltage command 44a (vus*, vvs*, and vws*), which is a command for a voltage instantaneous value outputted by the three-phase sub-inverter 91, according to an equation (45) below.




  
    
      
        
          [
          
            
              
                
                  v
                  us
                  *
                
              
            
            
              
                
                  v
                  vs
                  *
                
              
            
            
              
                
                  v
                  ws
                  *
                
              
            
          
          ]
        
        =
        
          
            
              
                
                  2
                  3
                
              
              ⁡
              
                [
                
                  
                    
                      
                        cos
                        ⁢
                        
                          
                        
                        ⁢
                        θ
                      
                    
                    
                      
                        
                          -
                          sin
                        
                        ⁢
                        
                          
                        
                        ⁢
                        θ
                      
                    
                  
                  
                    
                      
                        cos
                        ⁡
                        
                          (
                          
                            θ
                            -
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                    
                      
                        -
                        
                          sin
                          ⁡
                          
                            (
                            
                              θ
                              -
                              
                                
                                  2
                                  ⁢
                                  π
                                
                                3
                              
                            
                            )
                          
                        
                      
                    
                  
                  
                    
                      
                        cos
                        ⁡
                        
                          (
                          
                            θ
                            +
                            
                              
                                2
                                ⁢
                                π
                              
                              3
                            
                          
                          )
                        
                      
                    
                    
                      
                        -
                        
                          sin
                          ⁡
                          
                            (
                            
                              θ
                              +
                              
                                
                                  2
                                  ⁢
                                  π
                                
                                3
                              
                            
                            )
                          
                        
                      
                    
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    
                      
                        -
                        
                          v
                          d
                          *
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          d
                          *
                        
                      
                    
                  
                
                
                  
                    
                      
                        -
                        
                          v
                          q
                          *
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          v
                          q
                          *
                        
                      
                    
                  
                
              
              ]
            
          
          +
          
            [
            
              
                
                  
                    v
                    umpwm
                  
                
              
              
                
                  
                    v
                    vmpwm
                  
                
              
              
                
                  
                    v
                    wmpwm
                  
                
              
            
            ]
          
        
      
    
    
      
        (
        45
        )
      
    
  




The thus computed sub-inverter final voltage command 44a is inputted to a PWM circuit 44, and the PWM circuit 44 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase sub-inverter 91.
Under the foregoing control, the three-phase main inverter 1 outputs a voltage caused by an output voltage command having the d- and q-axis manipulative quantities Δvd* and Δvq*, which are outputted by the DC voltage control circuit 94, added to the dq-axis voltage command vd* and vq* which is outputted from the overall command generation circuit 13.
The three-phase sub-inverter 91 outputs a voltage caused by an output voltage command having the d- and q-axis manipulative quantities Δvd* and Δvq*, which are outputted by the DC voltage control circuit 94, and the voltage pulse signal Vumpwm, vvmpwm, and vwmpwm for the three-phase main inverter 1, which is added after conversion to a three-phase signal, added to a command whose polarity is the reverse of the polarity of the dq-axis voltage command vd* and vq* outputted from the overall command generation circuit 13. Since the voltage pulse signal vumpwm, vvmpwm, and vwmpwm is added from the signal of respective phases that is a three-phase instantaneous voltage into which the command −vd* and −vq* is converted, the fundamental wave component of the instantaneous voltage of the command signal −vd* and −vq* produced by reversing the polarity of the dq-axis voltage command vd* and vq* is canceled. The sub-inverter final voltage command 44a becomes a command causing output of a voltage that is in phase with harmonics outputted from the three-phase main inverter 1.
Since the three-phase main inverter 1 and three-phase sub-inverter 91 are connected in series with each other face to face with the load 90 between them, the voltage to be applied to the load 90 comes to the difference between the output voltage of the three-phase main inverter 1 and the output voltage of the three-phase sub-inverter 91. Consequently, the three-phase sub-inverter 91 operates to cancel the voltage harmonics outputted by the three-phase main inverter 1.
Further, similarly to the embodiment 7, since the d- and q-axis manipulative quantities Δvd* and Δvq* outputted by the DC voltage control circuit 94 are added to each of the output voltage commands for the three-phase main inverter 1 and three-phase sub-inverter 91, the added manipulative quantities and added manipulative quantities are canceled out. The voltage to be applied to the load 90 is therefore determined with the voltage command vd* and vq* outputted by the inverter overall control circuit 13. Consequently, similarly to the embodiment 7, (Δvd·id+Δvq·iq) out of the active power outputted by the three-phase main inverter 1 is fed to the three-phase sub-inverter 91 in order to charge the smoothing capacitor 92. When (Δvd·id+Δvq·iq) takes on a positive value, the voltage of the smoothing capacitor 92 increases. When (Δvd·id+Δvq·iq) takes on a negative voltage, the voltage of the smoothing capacitor 92 is lowered. The voltage of the smoothing capacitor 92 is thus controlled. Nevertheless, since the d- and q-axis manipulative quantities Δvd* and Δvq* are determined so that the DC voltage Vdcs of the smoothing capacitor 92 will follow the command value Vdcs*, a desired voltage can be highly reliably sustained.
The voltage outputted by the three-phase main inverter 1 contains harmonics due to PWM control. In the present embodiment, in the power conversion device having the three-phase main inverter 1 and three-phase sub-inverter 91 connected in series with each other face to face with the load 90 between them, since the three-phase sub-inverter 91 is operated in order to cancel the voltage harmonics outputted by the three-phase main inverter 1, the voltage to be fed to the load 90 has the harmonics suppressed.
Moreover, since manipulative quantities are determined so that the DC voltage Vdcs of the smoothing capacitor 92 of the three-phase sub-inverter 91 will follow the command value Vdcs*, and the output voltage command for each of the inverters 1 and 91 is adjusted, the DC voltage Vdcs of the smoothing capacitor 92 is controlled to be sustained at the desired voltage. Consequently, the same advantage as that of the embodiment 7 can be exerted. In the smoothing capacitor 92 of the three-phase sub-inverter 91, the desired DC voltage can be sustained without feed of power from another power supply. Simplification of a device configuration and cost reduction such as exclusion/simplification of a converter for the three-phase sub-inverter 91 and replacement of a multi-winding transformer with a reactor can be achieved.
Embodiment 9
FIG. 22 is a diagram showing the configuration of a power conversion device in accordance with an embodiment 9 of the present invention. The main circuit is identical to that shown in FIG. 18 of the embodiment 7. In the present embodiment, a dq axial voltage command is not employed but a three-phase instantaneous voltage command is outputted from the overall command generation circuit 16.
As shown in the drawing, the power conversion device includes an overall command generation circuit 16, a DC voltage control circuit 103, and a driving signal production circuit 104, controls a three-phase main inverter 1 and a three-phase sub-inverter 91, and also controls the voltage of a smoothing capacitor 92 that is the DC input of the three-phase sub-inverter 91.
The overall command generation circuit 16 described above is a circuit that generates an output voltage command for the load 90, and outputs a desired voltage, which is outputted in total by all of the three-phase main inverter 1 and three-phase sub-inverter 91, as a three-phase instantaneous voltage command vu*, vv*, and vw*.
The DC voltage control circuit 103 performs control computation on the basis of the output of a voltage sensor 93 that measures the voltage of the smoothing capacitor 92 which is the DC input of the three-phase sub-inverter 91, and outputs a voltage command as manipulative quantities. The DC voltage control circuit 103 is constructed as shown in, for example, FIG. 23, wherein a subtractor 107 obtains the deviation between the DC voltage vdcs of the smoothing capacitor 92 of the three-phase sub-inverter 91, which is measured by the voltage sensor 93, and a command value vdcs*, and a controller 105 obtains a manipulative quantity. The manipulative quantity is used to adjust the output voltage command for each of the inverters 1 and 91 so that the DC voltage vdcs will follow the command value vdcs*. Manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* are outputted. The controller 105 may be formed with a general PI control or the like.
The driving signal production circuit 104 computes a voltage, which is outputted by each of the three-phase main inverter 1 and three-phase sub-inverter 91, on the basis of the outputs of the overall command generation circuit 16 and DC voltage control circuit 103, and produces pulses, with which the respective switching elements are driven, through PWM. The driving signal production circuit 104 is constructed as shown in, for example, FIG. 24, wherein an individual inverter voltage command production circuit 109 produces a voltage command vumi*, vvmi*, and vwmi* for the three-phase main inverter 1 and a voltage command vusi*, vvsi* and vwsi* for the three-phase sub-inverter 91 on the basis of an instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16. At this time, the respective voltage commands have relationships expressed by equations (46a), (46b), and (46c) below.

vu*=vumi*−vusi*  (46a)

vv*=vvmi*−vvsi*  (46b)

vw*=vwmi*−vwsi*  (46c)

The production of the voltage command vumi*, vvmi*, and vwmi* for the three-phase main inverter 1 and the voltage command vusi*, vvsi*, and vwsi* for the three-phase sub-inverter 91 is not limited to the one based on the equations (46a), (46b), and (46c). An arbitrary means such as a method of determining voltages, which are assigned to the three-phase main inverter 1 and three-phase sub-inverter 91, according to the withstand voltage of the switching elements forming the respective inverters 1 and 91, or a method of keeping the voltage, which is outputted by the three-phase main inverter 1 or three-phase sub-inverter 91, constant may be adopted.
A sub-inverter instantaneous voltage command production circuit 110 inputs a sub-inverter voltage command vusi*, vvsi*, and vwsi* outputted by the individual inverter voltage command production circuit 109, and manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 103, and computes a sub-inverter final voltage command 44a that is a command for a voltage instantaneous value outputted by the three-phase sub-inverter 91. Herein, as expressed by equations (47a), (47b), and (47c) below, the manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* outputted from the DC voltage control circuit 103 are added to the sub-inverter voltage command vusi*, vvsi*, and vwsi* outputted by the individual inverter voltage command production circuit 109 in order to compute the sub-inverter final voltage command 44a (vus*, vvs*, and vws*)

vus*=vusi*+Δvu*  (47a)

vvs*=vvsi*+Δvv*  (47b)

vws*=vwsi*+Δvw*  (47c)

The thus computed sub-inverter final voltage command 44a is inputted to a PWM circuit 44, and the PWM circuit 44 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase sub-inverter 91.
Moreover, a main inverter instantaneous voltage command production circuit 111 inputs a main inverter voltage command vumi*, vvmi*, and vwmi* outputted by the individual inverter voltage command production circuit 109, and the manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 103, and computes a main inverter final voltage command 45a that is a command for a voltage instantaneous value outputted by the three-phase main inverter 1. Herein, as expressed by equations (48a), (48b), and (48c) below, the manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 103 are added to the main inverter voltage command vumi*, vvmi*, and vwmi* outputted by the individual inverter voltage command production circuit 109 in order to compute the main inverter final voltage command 45a (vum*, vvm*, and vwm*)

vum*=vumi*+Δvu*  (48a)

vvm*=vvmi*+Δvv*  (48b)

vwm*=vwmi*+Δvw*  (48c)

The thus computed main inverter final voltage command 45a is inputted to a PWM circuit 45, and the PWM circuit 45 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
Since the three-phase main inverter 1 and three-phase sub-inverter 91 are connected in series with each other face to face with the load 90 between them, the voltage to be applied to the load 90 comes to the difference between the output voltage of the three-phase main inverter 1 and the output voltage of the three-phase sub-inverter 91. Since the manipulative quantities Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 103 are added to each of the output voltage commands for the three-phase main inverter 1 and three-phase sub-inverter 91, the added manipulative quantities and added manipulative quantities are canceled out. The voltage to be applied to the load 90 is therefore determined with the voltage command vu*, vv*, and vw* outputted by the overall command generation circuit 16.
Herein, the powers of the three-phase main inverter 1, three-phase sub-inverter 91, and load 90 for the u phase will be discussed below. Assuming that the power factor of the load 90 is cos θ, the voltage of the u phase of the three-phase main inverter 1 is vum, the voltage of the u phase of the three-phase sub-inverter 91 is vus, the voltage to be applied to the load 90 is vu, the current flowing into the u phase of the load 90 is iu, and the active power to be fed to the load 90 by the u phase of the three-phase main inverter and the u phase of the three-phase sub-inverter 91 is pu, the active power pu is expressed by an equation (49) below.




  
    
      
        
          
            
              
                p
                u
              
              =
              
                
                  
                    v
                    u
                  
                  ·
                  
                    i
                    u
                  
                  ·
                  cos
                
                ⁢
                
                  
                
                ⁢
                θ
              
            
          
        
        
          
            
              =
              
                
                  
                    (
                    
                      
                        v
                        um
                      
                      -
                      
                        v
                        us
                      
                    
                    )
                  
                  ·
                  
                    i
                    u
                  
                  ·
                  cos
                
                ⁢
                
                  
                
                ⁢
                θ
              
            
          
        
      
    
    
      
        (
        49
        )
      
    
  




Among voltage components contained in each of the voltages vum and vus outputted by the u phase of the three-phase main inverter 1 and the u phase of the three-phase sub-inverter 91, a component caused by the u-phase voltage command vumi* or vusi* outputted by the individual inverter voltage command production circuit 109 shall be vumi or vusi, a component caused by the u-phase manipulative quantity Δvu* outputted by the DC voltage control circuit 103 shall be Δvu, the active power outputted by the u phase of the three-phase main inverter 1 shall be pum, and the active power outputted by the u phase of the three-phase sub-inverter 91 shall be pus. Assuming that Δvu denotes a DC component, relational equations (50a), (50b), and (51) below are established.

pum=(vum·cos θ+Δvu)·iu  (50a)

pus=(vus·cos θ+Δvu)·(−iu)  (50b)

pu=pum+pus  (51)

From the equations (50a), (50b), and (51), it is understood that Δvu·iu out of the active power outputted from the u phase of the three-phase main inverter 1 is a component which is fed to the u phase of the three-phase sub-inverter 91 but is not fed to the load 90. The same as that to the u phase applies to the v and w phases.
If power consumption caused by a loss in the three-phase sub-inverter 91 is ignored, the active power fed from the respective phases, Δvu·iu+Δvv·iv+Δvw·iw, charges the smoothing capacitor 92 of the three-phase sub-inverter 91 and raises the voltage of the smoothing capacitor 92. Moreover, if Δvu·iu+Δvv·iv+Δvw·iw takes on a negative value, oppositely, the voltage of the smoothing capacitor 92 is lowered.
The voltage of the smoothing capacitor 92 of the three-phase sub-inverter 91 is thus controlled. Since the manipulative quantities for the respective phases Δvu*, Δvv*, and Δvw* are determined so that the DC voltage vdcs of the smoothing capacitor 92 will follow the command value vdcs*, a desired voltage can be highly reliably sustained.
As mentioned above, in the present embodiment, in the power conversion device that has the three-phase main inverter 1 and three-phase sub-inverter 91 connected in series with each other face to face with the load 90 between them, and that extends control relative to an instantaneous value of a voltage or a current, since the manipulative quantities for the respective phases are determined so that the DC voltage vdcs of the smoothing capacitor 92 of the three-phase sub-inverter 91 will follow the command value vdcs*, and the output voltage command for each of the inverters 1 and 91 is adjusted, the DC voltage vdcs of the smoothing capacitor 92 is controlled to be sustained at a desired voltage. Consequently, in the smoothing capacitor 92 of the three-phase sub-inverter 91, the desired DC voltage can be sustained without feed of power from another power supply. Simplification of a device configuration and cost reduction such as exclusion of a converter for the three-phase sub-inverter 92 and replacement of a multi-winding transformer with a reactor can be achieved.
Incidentally, due to an error or the like of each of the control circuits, when the output voltage command for each of the inverters 1 and 91 is merely adjusted, if the DC voltage control for the smoothing capacitor 92 cannot be precisely achieved, a converter is included in order to feed power from the AC power supply 11. In this case, the capacity of the converter may be much smaller than the conventional one, and the device configuration can be fully simplified.
Moreover, in the embodiment 9, the three-phase main inverter 1 and three-phase sub-inverter 91 are three-phase full-bridge inverters. Even when three single-phase full-bridge inverters are adopted as one or both of the inverters 1 and 91, the same control can be achieved. Moreover, even when the three-phase main inverter 1 and three-phase sub-inverter 91 are three-level inverters, the same control can be achieved. Moreover, if power need not be restored to the AC power supply 11, the converter 5 may be a diode converter.
Embodiment 10
In the embodiment 9, in the driving signal production circuit 104, based on the instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16, a voltage command is produced for not only the three-phase main inverter 1 but also the three-phase sub-inverter 91. In the present embodiment, the three-phase sub-inverter 91 is operated as an inverter for outputting a voltage that cancels voltage harmonics outputted by the three-phase main inverter 1.
In this case, instead of the driving signal production circuit 104 presented in the embodiment 9, a driving signal production circuit 104a shown in FIG. 25 is employed. The other circuit components are identical to those of the embodiment 9.
The driving signal production circuit 104a computes a voltage, which is outputted by each of the three-phase main inverter 1 and three-phase sub-inverter 91, on the basis of the outputs of the overall command generation circuit 16 and DC voltage control circuit 103, and produces pulses, with which the respective switching elements are driven, through PWM. As shown in FIG. 25, a main inverter instantaneous voltage command production circuit 112 inputs an instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16, and manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 103, and computes a main inverter final voltage command 45a that is a command for a voltage instantaneous value outputted by the three-phase main inverter 1.
In this case, as expressed by equations (52a), (52b), and (52c) below, the manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 103 are added to the instantaneous voltage command vu*, vv*, and vw* in order to compute the main inverter final voltage command 45a (vum*, vvm*, and vwm*)

vum*=vu*+Δvu*  (52a)

vvm*=vv*+Δvv*  (52a)

vwm*=vw*+Δvw*  (52a)

The thus computed main inverter final voltage command 45a is inputted to a PWM circuit 45, and the PWM circuit 45 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
A sub-inverter instantaneous voltage command production circuit 113 inputs a voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16, and the manipulative quantities of respective phases Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 103, and further inputs a voltage pulse signal vumpwm, vvmpwm, and vwmpwm for the three-phase main inverter 1 outputted by the PWM circuit 45. Based on the input signals, the sub-inverter instantaneous voltage command production circuit 113 computes a sub-inverter final voltage command 44a (vus*, vvs*, and vws*) which is a command for a voltage instantaneous value outputted by the three-phase sub-inverter 91, as expressed by equations (53a), (53b), and (53c) below.

vus*=−vu*+Δvu*+vumpwm  (53a)

vvs*=−vv*+Δvv*+vvmpwm  (53b)

vws*=−vw*+Δvw*+vwmpwm  (53c)

The thus computed sub-inverter final voltage command 44a is inputted to a PWM circuit 44, and the PWM circuit 44 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase sub-inverter 91.
Under the foregoing control, the three-phase main inverter 1 outputs a voltage caused by an output voltage command having the manipulative quantities of respective phases Δvu*, Δvv*, and Δvw*, which are outputted by the DC voltage control circuit 103, added to the instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16.
The three-phase sub-inverter 91 outputs a voltage caused by an output voltage command having the manipulative quantities of respective phases Δvu*, Δvv*, and Δvw*, which are outputted by the DC voltage control circuit 103, and the voltage pulse signal vumpwm, vvmpwm and vwmpwm for the three-phase main inverter 1 added to a command produced by reversing the polarity of the instantaneous voltage command vu*, vv*, and vw* outputted from the overall command generation circuit 16. Since the voltage pulse signal vumpwm, vvmpwm, and vwmpwm is added to a signal of respective phases that is a three-phase instantaneous voltage into which the command −vu*, −vv*, and −vw* is converted, the fundamental wave component of the instantaneous voltage is canceled by the voltage command of the reverse polarity −vu*, −vv*, and −vw*. The sub-inverter final voltage command 44a becomes a command causing output of a voltage that is in phase with the harmonics outputted from the three-phase main inverter 1.
Since the three-phase main inverter 1 and three-phase sub-inverter 91 are connected in series with each other face to face with the load 90 between them, the voltage to be applied to the load 90 comes to the difference between the output voltage of the three-phase main inverter 1 and the output voltage of the three-phase sub-inverter 91. Consequently, the three-phase sub-inverter 91 operates to cancel the voltage harmonics outputted by the three-phase main inverter 1.
Further, similarly to the embodiment 9, since the manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 103 are added to each of the output voltage commands for the three-phase main inverter 1 and three-phase sub-inverter 91, the added manipulative quantities and added manipulative quantities are canceled out. The voltage to be applied to the load 90 is therefore determined with the voltage command vu*, vv*, and vw* outputted by the overall command generation circuit 16. Consequently, similarly to the embodiment 9, the active power Δvu·iu+Δvv·iv+Δvw·iw fed from the respective phases out of the active power outputted by the three-phase main inverter 1 charges the smoothing capacitor 92 of the three-phase sub-inverter 91, and raises the voltage of the smoothing capacitor 92. Moreover, if Δvu·iu+Δvv·iv+Δvw·iw takes on a negative value, oppositely, the voltage of the smoothing capacitor 92 is lowered.
The voltage of the smoothing capacitor 92 of the three-phase sub-inverter 91 is thus controlled. Since the manipulative quantities for respective phases Δvu*, Δvv*, and Δvw* are determined so that the DC voltage vdcs of the smoothing capacitor 92 will follow the command value Vdcs*, a desired voltage can be highly reliably sustained.
A voltage outputted by the three-phase main inverter 1 contains harmonics due to PWM control. In the present embodiment, since the three-phase sub-inverter 91 is operated to cancel the voltage harmonics outputted by the three-phase main inverter 1, the voltage to be fed to the load 90 has the harmonics suppressed.
Moreover, since the manipulative quantities are determined so that the DC voltage Vdcs of the smoothing capacitor 92 of the three-phase sub-inverter 91 will follow the command value Vdcs*, and the output voltage command for each of the inverters 1 and 91 is adjusted, the DC voltage Vdcs of the smoothing capacitor 92 is controlled to be sustained at a desired voltage. Consequently, the same advantage as that of the embodiment 9 is exerted. In the smoothing capacitor 92 of the three-phase sub-inverter 91, the desired DC voltage can be sustained without feed of power from another power source. Simplification of a device configuration and cost reduction such as exclusion/simplification of a converter for the three-phase sub-inverter 91 and replacement of a multi-winding transformer with a reactor can be achieved.
Embodiment 11
A power conversion device in accordance with an embodiment 11 of the present invention will be described below, rebating to the drawings.
FIG. 26 is a diagram showing the configuration of the power conversion device in accordance with the embodiment 11 of the present invention. As shown in FIG. 26, the power conversion device has single-phase sub-inverters 2 of which AC sides of respective phases are connected in series with respective phase output lines on an AC side of a three-phase main inverter 1.
The three-phase main inverter 1 has a smoothing capacitor 6, which serves as a first DC power supply, on the DC side thereof, and further has a converter 5 connected in parallel therewith. On the AC side of the converter 5, an AC power supply 11 is connected via a reactor 10. Each of the single-phase sub-inverters 2 for the u phase, v phase, and w phase has a smoothing capacitor 3, which serves as a second DC power supply, on the DC side thereof, has one terminal thereof on the AC side thereof connected to the three-phase main inverter 1, and has the other terminal thereof connected to a motor 12 serving as a load. Thus, sub-inverter units 7a to 7c for the u phase, v phase, and w phase are constructed.
The foregoing main circuitry is identical to those of the embodiments 1 to 4. Herein, the load 12 is a motor.
Moreover, for convenience' sake, only the single-phase sub-inverter and smoothing capacitor for the u phase out of the respective single-phase sub-inverters 2a to 2c and respective smoothing capacitors 3a to 3c for the u phase, v phase, and w phase are shown as each of the single-phase sub-inverters 2 and each of the smoothing capacitors 3.
Moreover, the circuitries of the three-phase main inverter 1, converter 5, and single-phase sub-inverters 2 are identical to those shown in FIG. 2 to FIG. 4. Further, even in this case, the three-phase main inverter 1 is regarded as having first single-phase inverters star-connected as three phase parts. For each of phases, the AC side of the first single-phase inverter (each phase part of the three-phase main inverter 1) and the AC side of the single-phase sub-inverter 2 serving as a second single-phase inverter connected in series with each other.
The power conversion device in accordance with the embodiment 11 includes, as shown in FIG. 26, an initial charging control device for the purpose of initially charging the smoothing capacitor 3 of each of the single-phase sub-inverters 2. The initial charging control device includes a current control circuit 13a, a DC voltage control circuit 14a, an adder 115, a gain 116, PWM circuits 117 and 118, and a current sensor 19.
Initial charging of the smoothing capacitor 3 of the u-phase sub-inverter unit 7a by the initial charging control device for the u phase will be described below. For the v phase and w phase, the same initial charging control devices are included for controlling initial charging in the same manner. The initial charging control devices for the respective phases may be constructed as one device.
The current control circuit 13a is a control circuit that performs feedback control on a current which flows into the motor 12 and which is measured by a current sensor 19, and outputs a voltage command vu* for the three-phase main inverter 1 so that the measured current will follow a command value.
Herein, the current command value shall be a value equal to or smaller than the current capacity of the switching elements forming each of the inverters 1 and 2, and the voltage command vu* shall be a command of a DC voltage.
The DC voltage control circuit 14a performs control computation on the basis of the output of the voltage sensor 4 that measures the voltage of the smoothing capacitor 3 that is the DC input of the single-phase sub-inverter 2, and outputs a voltage command as a manipulative quantity. The DC voltage control circuit 14a is constructed as shown in, for example, FIG. 27, wherein a subtractor 119 obtains the deviation between the DC voltage vdcsu of the smoothing capacitor 3 of the single-phase sub-inverter 2, which is measured by the voltage sensor 4, and a command value Vdcs*, and a controller 120 obtains and outputs a manipulative quantity Δvu*. The manipulative quantity is used to adjust the output voltage command for each of the inverters 1 and 2 so that the DC voltage Vdcsu will follow the command value Vdcs*. Incidentally, the controller 120 may be formed with a general PI control or the like.
The voltage command vu* outputted by the current control circuit 13a and the manipulative quantity Δvu* outputted by the DC voltage control circuit 14a are added up, as expressed by an equation (54) below, by an adder 115 in order to compute a main inverter voltage command 117a (vum*) that is a u-phase output voltage command for the three-phase main inverter 1.

vum*=vu*+Δvu*  (54)

The thus computed main inverter voltage command 117a is inputted to a PWM circuit 117, and the PWM circuit 117 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
The manipulative quantity Δvu* outputted by the DC voltage control circuit 14a is multiplied by −1 by the gain 116 in order to reverse the polarity thereof, and a sub-inverter voltage command 118a (vus*=−Δvu*) that is an output voltage command for the single-phase sub-inverter 2 for the u phase is computed.
The thus computed sub-inverter voltage command 118a is inputted to a PWM circuit 118, and the PWM circuit 118 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the single-phase sub-inverter 2.
The three-phase main inverter 1 and single-phase sub-inverter 2 are connected in series with each other, and the total value of the voltages outputted by the three-phase main inverter 1 and single-phase sub-inverter 2 becomes the voltage of the motor 12. The single-phase sub-inverter 2 outputs a voltage caused by a voltage command produced by reversing the polarity of the manipulative quantity Δvu*. Consequently, out of the voltage outputted by the three-phase main inverter 1, a voltage component Δvu* caused by the manipulative quantity Δvu* is canceled by the voltage outputted by the single-phase sub-inverter 2. The voltage to be applied to the motor 12 is determined by the voltage command vu* outputted by the current control circuit 13a. 
Consequently, the current control circuit 13a and DC voltage control circuit 14a operate independently of each other. The manipulative quantity Δvu* outputted by the DC voltage control circuit 14a does not affect the motor 12.
As mentioned above, the current flowing through the three-phase main inverter 1 and single-phase sub-inverter 2 is controlled by the current control circuit 13a. When a current command value equal to or smaller than the current capacity of the switching elements is adopted as mentioned above, the switching elements can be protected from a breakdown caused by an overcurrent. Moreover, a protective circuit need not be operated. When the current command value is set to the largest possible value equal to or smaller than the current capacity, the current capacity of the switching elements can be utilized to the greatest extent, and initial charging can be achieved swiftly.
As mentioned above, the voltage to be applied to the motor 12 is determined with the voltage command vu* outputted by the current control circuit 13a, and a DC voltage that does not permit the motor 12 to rotate is applied.
Now, the powers of the three-phase main inverter 1, single-phase sub-inverter 2, and motor 12 for the u phase will be discussed. Assuming that the voltage of the three-phase main inverter 1 is vum, the voltage of the single-phase sub-inverter 2 is vus, the voltage to be applied to the motor 12 is vu, the current flowing into the motor 12 is iu, and the active power to be fed to the motor 12 by the three-phase main inverter 1 and sub-inverter 2 is pu, the active power pu is expressed by an equation (55) below.




  
    
      
        
          
            
              
                p
                u
              
              =
              
                
                  v
                  u
                
                ·
                
                  i
                  u
                
              
            
          
        
        
          
            
              =
              
                
                  (
                  
                    
                      v
                      um
                    
                    -
                    
                      v
                      us
                    
                  
                  )
                
                ·
                
                  i
                  u
                
              
            
          
        
      
    
    
      
        (
        55
        )
      
    
  




Assuming that a voltage component caused by the manipulative quantity Δvu* out of voltage components contained in each of the voltages vum and vus outputted by the three-phase main inverter 1 and single-phase sub-inverter 2 is Δvu, the power outputted by the three-phase main inverter 1 is pmu, and the power outputted by the single-phase sub-inverter 2 is psu, pmu and psu are expressed by equations (56) and (57) below.




  
    
      
        
          
            
              
                p
                mu
              
              =
              
                
                  v
                  um
                
                ·
                
                  i
                  u
                
              
            
          
        
        
          
            
              =
              
                
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Herein, pu, pmu, and psu have a relationship expressed by an equation (58).

pu=pmu+psu  (58)

From the equations (56) to (58), it is understood that Δvu·iu out of the power outputted from the three-phase main inverter 1 is a component which is fed to the single-phase sub-inverter 2 but is not fed to the motor 12. If power consumption caused by a loss in the single-phase sub-inverter 2 is ignored, Δvu·iu charges the smoothing capacitor 3 of the single-phase sub-inverter 2, and increases the voltage of the smoothing capacitor 3.
By performing the foregoing control, power can be fed from the three-phase main inverter 1 to the single-phase sub-inverter 2 without operation of the motor 12, and the smoothing capacitor 3 can be charged. Consequently, the necessity of a charging circuit that charges the smoothing capacitor 3 is obviated.
When the same circuitry is included for the v phase and w phase alike, the smoothing capacitors 3 of the single-phase sub-inverters 2 for the respective phases can be charged independently of one another. Moreover, even when the three-phase main inverter 1 is constructed using single-phase inverters for the respective phases, charging can be achieved according to the same method.
As mentioned above, in the present embodiment, since the smoothing capacitors 3 of the single-phase sub-inverters 2 can be initially charged without reception of power fed from an external power supply via converters, a structure suitable for a power conversion device that has converters, which are used to feed power to the smoothing capacitors 3, excluded for the purpose of facilitating compactness and simplicity ensues.
Incidentally, the foregoing initial charging control can be applied to the aforesaid embodiments 1 to 4. In this case, a current sensor 19 that detects a current flowing into the load 12 is included, and the overall command generation circuit 13 or 16, DC voltage control circuit 14 or 17, and driving signal production circuit 15 (15a) or 18 (18a) are used to initially charge the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c. The overall command generation circuit 13 or 16 outputs a command of a voltage that does not permit the load 12 to operate. The output voltage command is regarded as an output voltage command for the three-phase main inverter 1, and the output voltage command for the single-phase sub-inverters 2a to 2c is set to 0. Manipulative quantities obtained by the DC voltage control circuit 14 or 17 are used to adjust the output voltage command for each of the inverters 1 and 2a to 2c. Consequently, similarly to the embodiment 11, the smoothing capacitors 3a to 3c of the single-phase sub-inverters 2a to 2c can be initially charged, and the same advantage can be exerted.
EMBODIMENT 12
FIG. 28 is a diagram showing the configuration of a power conversion device in accordance with an embodiment 12 of the present invention. In the embodiment 11, the power conversion device has the single-phase sub-inverters 2 of which the AC sides of the respective phases are connected in series with the respective phase output lines on the AC side of the three-phase main inverter 1. In the present embodiment, each of sub-inverter units 54a to 54c for respective phases is constructed by connecting AC sides of two single-phase sub-inverters 2 and 51 in series with each other, and the two single-phase sub-inverters 2 and 51 serving as second single-phase inverters are connected in series with each of phase output lines on an AC side of a three-phase main inverter 1 (first single-phase inverters for three phases). Power is thus fed to a motor 12.
The second single-phase sub-inverters 51 have the same circuitry as the single-phase sub-inverters 2 (see FIG. 4). Specifications including an output voltage may be different from those for the single-phase sub-inverters 2.
The three-phase main inverter 1 has a smoothing capacitor 6, which serves as a first DC power supply, on the DC side thereof, and further has a converter 5 connected in parallel therewith. On the AC side of the converter 5, an AC power supply 11 is connected via a reactor 10. The respective single-phase sub-inverters 2 and 51 for the u phase, v phase, and w phase have smoothing capacitors 3 and 52, which serves as second DC power supplies, on the DC sides thereof.
The foregoing main circuitry is identical to those of the embodiments 5 and 6. Herein, the load 12 is a motor. For convenience' sake, among the single-phase sub-inverters 2a to 2c and 51a to 51c and smoothing capacitors 3a to 3c and 52a to 52c for the u phase, v phase, and w phase, the sub-inverters and smoothing capacitors for the u phase alone are shown as the single-phase sub-inverter 2, single-phase sub-inverter 51, smoothing capacitor 3, and smoothing capacitor 52.
The power conversion device in accordance with the embodiment 12 includes, as shown in FIG. 28, an initial charging control device for the purpose of initially charging the smoothing capacitors 3 and 52 of the respective single-phase sub-inverters 2 and 51. The initial charging control device includes a current control circuit 13a, DC voltage control circuits 14a and 14b, adders 115 and 123, gains 116 and 121, PWM circuits 117, 118, and 122, and a current sensor 19.
Initial charging of the smoothing capacitors 3 and 52 of the u-phase sub-inverter unit 54a by the initial charging control device for the u phase will be described below. For the v phase and w phase alike, the same initial charging control device is included in order to control initial charging in the same manner. The initial charging control devices for the respective phases may be constructed as one device.
The current control circuit 13a is a control circuit that performs feedback control on a current which flows into the motor 12 and which is measured by the current sensor 19, and outputs a voltage command vu* for the three-phase main inverter 1 so that the measured current will follow a command value.
Herein, the current command value shall be a value equal to or smaller than the current capacity of switching elements forming each of the inverters 1, 2, and 51, and the voltage command vu* shall be a command of a DC voltage.
The DC voltage control circuits 14a and 14b perform control computation on the basis of the outputs of the voltage sensors 4 and 53 that measure the voltages of the smoothing capacitors 3 and 52 which are the DC inputs of the respective single-phase sub-inverters 2 and 51 respectively, and outputs manipulative quantities Δvu1* and Δvu2* which are used to adjust the output voltage command for each of the inverters 1, 2, and 51. The DC voltage control circuits 14a and 14b obtain the deviations between the DC voltages of the smoothing capacitors 3 and 52, which are measured by the voltage sensors 4 and 53 respectively, and a command value, and obtain the manipulative quantities Δvu1* and Δvu2* so that the DC voltages will follow the command value.
To the voltage command vu* outputted by the current control circuit 13a, the manipulative quantity Δvu1* outputted by the DC voltage control circuit 14a is added by the adder 115, and the manipulative quantity Δvu2* outputted by the DC voltage control circuit 14b is added by the adder 123. Thus, a main inverter voltage command 117a (vum*=vu*+Δvu1*+Δvu2*) that is a u-phase output voltage command for the three-phase main inverter 1 is computed.
The thus computed main inverter voltage command 117a is inputted to the PWM circuit 117, and the PWM circuit 117 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
On the other hand, the manipulative quantity Δvu1* outputted by the DC voltage control circuit 14a is multiplied by −1 by the gain 116 in order to reverse the polarity thereof. A sub-inverter voltage command 118a (vus1*=−Δvu1*) that is an output voltage command for the single-phase sub-inverter 2 is thus computed.
The thus computed sub-inverter voltage command 118a is inputted to the PWM circuit 118, and the PWM circuit 118 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the single-phase sub-inverter 2.
Moreover, the manipulative quantity Δvu2* outputted by the DC voltage control circuit 14b is multiplied by −1 by the gain 121 in order to reverse the polarity thereof. A second sub-inverter voltage command 122a (vus2*=−Δvu2*) that is an output voltage command for the second single-phase sub-inverter 51 is thus computed.
The thus computed second sub-inverter voltage command 122a is inputted to the PWM circuit 122, and the PWM circuit 122 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the second single-phase sub-inverter 51.
As mentioned above, since the three-phase main inverter 1, single-phase sub-inverter 2, and second single-phase sub-inverter 51 are connected in series with one another, the voltage to be applied to the motor 12 is the sum total of the voltages to be outputted by the respective inverters 1, 2, and 51. The manipulative quantities Δvu1* and Δvu2* outputted by the DC voltage control circuits 14a and 14b are added for computation of the voltage command for the three-phase main inverter 1, and are subtracted for computation of the voltage command for the single-phase sub-inverter 2 or 51. Out of the voltage outputted by each of the inverters 1, 2, and 51, a voltage component caused by the added manipulative quantities and a voltage component caused by the subtracted manipulative quantities are canceled out. The voltage to be applied to the motor 12 is determined with the voltage command vu* outputted by the current control circuit 13a. 
Consequently, the current control circuit 13a and the DC voltage control circuits 14a and 14b operate independently of one another, and the manipulative quantities outputted by the DC voltage control circuits 14a and 14b do not affect the motor 12.
As mentioned above, a current flowing through the three-phase main inverter 1 and single-phase sub-inverters 2 and 52 is controlled by the current control circuit 13a. When a current command value equal to or smaller than the current capacity of the switching elements is adopted as mentioned above, the switching elements can be protected from a breakdown caused by an overcurrent. Moreover, a protective circuit need not be operated. When the current command value is set to the largest possible value equal to or smaller than the current capacity, while the current capacity of the switching elements is utilized to the greatest extent, initial charging can be swiftly achieved.
As mentioned above, the voltage to be applied to the motor 12 is determined with the voltage command vu* outputted by the current control circuit 13a, and a DC voltage that does not permit the motor 12 to rotate is applied.
Herein, assuming that a current flowing into the motor 12 is iu, and voltage components, which are caused by the manipulative quantities Δvu1* and Δvu2*, out of a voltage outputted by each of the inverters 1, 2, and 51 are Δvu1 and Δvu2, when the powers of the three-phase main inverter 1 and single-phase sub-inverters 2 and 51 for the u phase are discussed, it is understood that out of the power outputted from the three-phase main inverter 1, Δvu1·iu is a component which is fed to the single-phase sub-inverter 2 and Δvu2·iu is a component which is fed to the second single-phase sub-inverter 51. When power consumption caused by a loss in the single-phase sub-inverters 2 and 51 is ignored, Δvu1·iu and Δvu2·iu charge the smoothing capacitors 3 and 52 of the single-phase sub-inverters 2 and 51 and increase the voltages of the smoothing capacitors 3 and 52.
By performing the foregoing control, power can be fed from the three-phase main inverter 1 to the single-phase sub-inverters 2 and 51 without operation of the motor 12, and the smoothing capacitors 3 and 52 can be charged. Consequently, the necessity of a charging circuit for charging the smoothing capacitors 3 and 52 can be obviated.
Incidentally, when the same circuitry is included for the v phase and w phase alike, the smoothing capacitors of the sub-inverters for the phases can be charged independently among the phases. Moreover, even when the three-phase main inverter 1 is constructed using single-phase inverters for the respective phases, charging can be achieved according to the same method.
As mentioned above, the power conversion device in accordance with the present embodiment can initially charge the smoothing capacitors 3 and 52 of the single-phase sub-inverters 2 and 51 without reception of power fed from an external power supply via a converter. Consequently, a structure suitable for a power conversion device that has converters, which are used to feed power to the smoothing capacitors 3 and 52, excluded therefrom and that has compactness and simplicity facilitated ensues.
The aforesaid initial charging control can be applied to the embodiments 5 and 6. In this case, a current sensor 19 that detects a current flowing into the load 12 is included, and the overall command generation circuit 13 or 16, DC voltage control circuit 57 or 81, and driving signal production circuit 58 or 82 are used to initially charge the smoothing capacitors 3a to 3c and 52a to 52c of the single-phase sub-inverters 2a to 2c and 51a to 51c. The overall command generation circuit 13 or 16 outputs a command of a voltage that does not permit the load 12 to operate. The output voltage command is used as an output voltage command for the three-phase main inverter 1, and an output voltage command for the single-phase sub-inverters 2a to 2c or 51a to 51c is set to 0. Manipulative quantities obtained by the DC voltage control circuit 57 or 81 are used to adjust the output voltage command for each of the inverters 1, 2a to 2c, and 51a to 51c. Consequently, similarly to the embodiment 12, the smoothing capacitors 3a to 3c and 52a to 52c of the single-phase sub-inverters 2a to 2c and 51a to 51c can be initially charged. The same advantage can be exerted.
EMBODIMENT 13
FIG. 29 is a diagram showing the configuration of a power conversion device in accordance with an embodiment 13 of the present invention.
As shown in the drawing, the power conversion device has a three-phase main inverter 1 and a three-phase sub-inverter 91, their respective phase output lines on an AC side are connected in series with each other via an open-winding motor 90, which is a load including open windings. The three-phase main inverter 1 has a smoothing capacitor 6, which serves as a first DC power supply, on the DC side thereof, and further has a converter 5 connected in parallel therewith. On the AC side of the converter 5, an AC power supply 11 is connected via a reactor 10. The three-phase sub-inverter 91 has a smoothing capacitor 92, which serves as a second DC power supply, on the DC side thereof.
The three-phase main inverter 1 and converter 5 are identical to those of the aforesaid embodiments.
Herein, each of the three-phase main inverter 1 and three-phase sub-inverter 91 is regarded as having first single-phase inverters or second single-phase inverters star-connected as three phase parts. For each of the phases, the AC side of the first single-phase inverter (each phase part of the three-phase main inverter 1) and the AC side of the second single-phase inverter (each phase part of the three-phase sub-inverter 91) are connected in series with each other via the open-winding motor 90.
The foregoing main circuitry is identical to those of the embodiments 7 to 10. Herein, a description will be made with the load 90 regarded as an open-winding motor.
The power conversion device in accordance with the embodiment 13 includes, as shown in FIG. 29, an initial charging control device for the purpose of initially charging the smoothing capacitor 92 of the three-phase sub-inverter 91. The initial charging control device includes a current control circuit 13b, a DC voltage control circuit 14c, an adder 126, PWM circuits 124 and 125, and current sensors 55a to 55c. 
The current control circuit 13b is a control circuit that performs feedback control on currents of respective phases which flow into the open-winding motor 90 and are measured by the current sensors 55a to 55c, and outputs a voltage command of the phases, vu*, vv*, and vw*, for the three-phase main inverter 1 so that the respective measured phases currents will follow a command value.
Herein, the current command value shall be a value equal to or smaller than the current capacity of switching elements forming each of the inverters 1 and 91, and the voltage command of the respective phases, vu*, vv*, and vw*, shall be a command of a DC voltage.
The DC voltage control circuit 14c performs control computation on the basis of the output of a voltage sensor 93 that measures the voltage of the smoothing capacitor 92 which is the DC input of the three-phase sub-inverter 91, and outputs a voltage command as manipulative quantities. The DC voltage control circuit 14c is constructed as shown in, for example, FIG. 30, wherein a subtractor 127 obtains the deviation between the DC voltage vdcs of the smoothing capacitor 92 of the three-phase sub-inverter 91, which is measured by the voltage sensor 93, and a command value vdcs*, and a controller 128 obtains a manipulative quantity. The manipulative quantity is used to adjust the output voltage command for each of the inverters 1 and 91 so that the DC voltage vdcs will follow the command value vdcs*. The manipulative quantity is inputted to a three-phase distribution circuit 129 in order to output manipulative quantities Δvu*, Δvv*, and Δvw* obtained by distributing the manipulative quantity into three phases. The controller 128 may be formed with a general PI control or the like. Moreover, a method according to which the three-phase distribution circuit 129 distributes the manipulative quantity into the three phases may be any one. For example, the manipulative quantity may be distributed so that the resultant quantities for the three phases will have the same value.
Thereafter, the voltage command of the phases, vu*, vv*, and vw*, outputted by the current control circuit 13b and the manipulative quantities Δvu*, Δvv*, and Δvw* for the phases outputted by the DC voltage control circuit 14c are added up by an adder 126 according to equations (59a), (59b), and (59c) below in order to compute a main inverter voltage command 124a (vum*, vvm*, and vwm*) that is the output voltage command for the three-phase main inverter 1.

vum*=vu*+Δvu*  (59a)

vvm*=vv*+Δvv*  (59b)

vwm*=vw*+Δvw*  (59c)

The thus computed main inverter voltage command 124a is inputted to the PWM circuit 124, and the PWM circuit 124 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase main inverter 1.
On the other hand, the manipulative quantities Δvu*, Δvv*, and Δvw* for the phases outputted by the DC voltage control circuit 14c are adopted as they are as a sub-inverter voltage command 125a that is an output voltage command of phases for the three-phase sub-inverter 91. The sub-inverter voltage command 125a (Δvu*, Δvv*, and Δvw*) is inputted to the PWM circuit 125, and the PWM circuit 125 outputs a voltage pulse signal, which has the pulse width thereof modulated, so as to drive the three-phase sub-inverter 91.
Since the three-phase main inverter 1 and three-phase sub-inverter 91 are connected in series with each other face to face with the open-winding motor 90 between them, the voltage to be applied to the open-winding motor 90 is the difference between the output voltage of the three-phase main inverter 1 and the output voltage of the three-phase sub-inverter 91. Since the manipulative quantities Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 14c are contained in each of the output voltage commands for the three-phase main inverter 1 and three-phase sub-inverter 91 while taking on a positive polarity, the contained manipulative quantities and contained manipulative quantities are canceled out. The voltage to be applied to the open-winding motor 90 is determined with the voltage command vu*, vv*, and vw* outputted by the current control circuit 13b. 
Consequently, the current control circuit 13b and DC voltage control circuit 14c operate independently of each other, and the manipulative quantities Δvu*, Δvv*, and Δvw* outputted by the DC voltage control circuit 14c do not affect the open-winding motor 90.
As mentioned above, the current flowing through the three-phase main inverter 1 and three-phase sub-inverter 91 is controlled by the current control circuit 13b. When a current command value equal to or smaller than the current capacity of switching elements is adopted as mentioned above, the switching elements can be protected from a breakdown caused by an overcurrent. Moreover, a protective circuit need not be operated. When the current command value is set to the largest possible value equal to or smaller than the current capacity, the current capacity of the switching elements can be utilized to the greatest extent and initial charging can be swiftly achieved.
As mentioned above, the voltage to be applied to the open-winding motor 90 is determined with the voltage command vu*, vv*, and vw* outputted by the current control circuit 13b, and the DC voltage vu, vv, and vw that does not permit the open-winding motor 90 to rotate is applied.
Assuming that the respective phase currents flowing into the open-winding motor 90 are iu, iv, and iw and the power to be fed to the open-winding motor 90 is p, a relational equation (60) below is established.

p=vu·iu+vv·iv+vw·iw  (60)

Assuming that components caused by the manipulative quantities Δvu*, Δvv*, and Δvw* out of components contained in the voltage outputted by each of the three-phase main inverter 1 and three-phase sub-inverter 91 are Δvu, Δvv, and Δvw, the power outputted by the three-phase main inverter 1 is pm, and the power outputted by the three-phase sub-inverter 91 is ps, pm and ps are expressed by equations (61) and (62) below.

pm=(vu+Δvu)·iu+(vv+Δvv)·iv+(vw+Δvw)·iw  (61)

ps=Δvu·(−iu)+Δvv·(−iv)+Δvw·(−iw)  (62)

Moreover, p, pm, and ps have a relationship expressed by an equation (63) below.

p=pm+ps  (63)

From the equations (61) to (63), it is understood that Δvu·iu+Δvv·iv+Δvw·iw out of the power outputted from the three-phase main inverter 1 is a component which is fed to the three-phase sub-inverter 91 but is not fed to the open-winding motor 90.
When power consumption caused by a loss in the three-phase sub-inverter 91 is ignored, the power Δvu·iu+Δvv·iv+Δvw·iw charges the smoothing capacitor 92 of the three-phase sub-inverter 91 and raises the voltage of the smoothing capacitor 92.
By performing the foregoing control, while the open-winding motor 90 is controlled not to operate, power can be fed from the three-phase main inverter 1 to the three-phase sub-inverter 91 in order to charge the smoothing capacitor 92. The necessity of a charging circuit for charging the smoothing capacitor 92 can be obviated.
Incidentally, the three-phase main inverter 1 and three-phase sub-inverter 91 may be constructed not only as the aforesaid three-phase inverters but also using single-phase inverters for phases. Nevertheless, charging can be achieved according to the same method.
As mentioned above, the power conversion device in accordance with the present embodiment can initially charge the smoothing capacitor 92 of the three-phase sub-inverter 91 without reception of power fed from an external power supply via a converter. Consequently, a structure suitable for a power conversion device that has a converter, which is used to feed power to the smoothing capacitor 92, excluded therefrom and that has compactness and simplicity facilitated ensues.
The foregoing initial charging control may be applied to the embodiments 7 to 10. In this case, the current sensors 55a to 55c that detect currents flowing into the load 90 are included. The overall command generation circuit 13 or 16, DC voltage control circuit 94 or 103, and driving signal production circuit 95 (95a) or 104 (104a) are used to initially charge the smoothing capacitor 92 of the three-phase sub-inverter 91. The overall command generation circuit 13 or 16 outputs a command of a voltage that does not permit the load 90 to operate. The output voltage command is used as an output voltage command for the three-phase main inverter 1, and an output voltage command for the three-phase sub-inverter 91 is set to 0. Manipulative quantities obtained by the DC voltage control circuit 94 or 103 are used to adjust the output voltage command for each of the inverters 1 and 91. Consequently, similarly to the embodiment 13, the smoothing capacitor 92 of the three-phase sub-inverter 91 can be initially charged, and the same advantage can be exerted.
EMBODIMENT 14
In the aforesaid embodiments 11 to 13, a voltage to be applied to the motor 12 or open-winding motor 90 (hereinafter, simply, motor 12 or 90) is a DC voltage. An AC voltage will do as long as it is a voltage which does not permit the motor 12 or 90 to operate.
Assuming that respective phase voltages of u to w phases to be applied to the motor 12 or 50 are vu, vv, and vw, V denotes the amplitude of the u-phase voltage, ω denotes an angular frequency, and t denotes a time, an AC voltage expressed by equations (64a) to (64c) below is applied to the motor 12 or 90.

vu=V sin ωt  (64a)

vv=(V/2)·sin(ωt−180°)  (64b)

vw=(V/2)·sin(ωt−180°)  (64c)

With the AC voltage, since a rotating field is not generated, the motor 12 or 90 does not operate. Consequently, when a voltage command is outputted from the current control circuit 13a or 13b so that the AC voltage expressed by the above equations (64a) to (64c) will be applied to the motor 12 or 90, the smoothing capacitor 3, 52, or 92 can be initially charged in the same manner as that in the embodiments 11 to 13. The same advantage can be exerted.
Incidentally, when an AC load is the motor 12 or 90, an AC voltage that does not induce a rotating field is used. For loads other than the motor, any AC voltage that does not permit the load to operate will do.
Moreover, initial charging of the smoothing capacitor 3, 52, or 92 is terminated when the voltage of the smoothing capacitor 3, 52, or 92 reaches the command value. When an AC voltage whose frequency is low enough is applied to the AC load, the initial charging can be terminated while the phase of the AC voltage hardly changes. Specifically, a range of phase angles within which an adverse effect on the AC load can be ignored, for example, 0 to 180° is designated, and an AC voltage of a low frequency permitting termination of initial charging within the range is applied to the AC load. Consequently, similarly to the embodiments 11 to 13, the smoothing capacitor 3, 52, and 92 can be initially charged, and the same advantage can be exerted. In this case, an ordinary three-phase AC voltage whose components differ in phase by 120° will do.
INDUSTRIAL APPLICABILITY
The present invention can be widely applied to power conversion devices that have one single-phase sub-inverter or multiple single-phase sub-inverters connected in series with phase AC output lines of a main inverter so as to feed power to a load.

## Claims

1. A power conversion device having a first inverter which converts DC power of a first DC power supply fed from a power supply into AC power, and a second inverter, which converts DC power of a second DC power supply into AC power, connected in series at the AC side thereof so as to feed power to a load, the power conversion device comprising:
a means for detecting the voltage of the second DC power supply; and
a DC voltage control means that adjusts an output voltage command for each of the first and the second inverters so that the detected voltage of the second DC power supply will follow a command value.

2. The power conversion device according to claim 1, wherein:
the power conversion device feeds an output voltage to the load using the sum total of the generated voltages of the first and the second inverters; and
the DC voltage control means determines a manipulative quantity so that the detected voltage of the second DC power supply will follow the command value, adjusts the output voltage command for the first inverter by adding the manipulative quantity, and adjusts the output voltage
command for the second inverter by subtracting the manipulative quantity.

3. The power conversion device according to claim 1, wherein:
both of the first inverter and the second inverter are three-phase inverters;
the first inverter and the second inverter are connected in series at the AC side thereof via the load;
the power conversion device feeds the difference voltage between the generated voltages of the first and the second inverters to the load;
the DC voltage control means determines a manipulative quantity so that the detected voltage of the second DC power supply will follow the command value, and adjusts the output voltage command for each of the first and the second inverters by adding the manipulative quantity.

4. The power conversion device according to claim 3, wherein the DC voltage control means adjusts a dq axial output voltage command for each of the first and the second inverters.

5. The power conversion device according to claim 1, wherein the second inverter outputs a voltage that is used to cancel voltage harmonics outputted by the first inverter.

6. The power conversion device according to claim 1, wherein:
while a voltage that does not permit the load to operate is applied to the load, the DC voltage control means adjusts the output voltage command for each of the first and the second inverters and controls the output of each of the inverters, so that the second DC power supply will be initially charged via the first and the second inverters; and
in the initial charging of the second DC power supply, the unadjusted output voltage command for the first inverter produced by the DC voltage control means is the command value for the voltage to be applied to the load, and the unadjusted output voltage command for the second inverter is 0.

7. The power conversion device according to claim 1, wherein:
both of the first inverter and the second inverter are single-phase inverters.

8. The power conversion device according to claim 1, wherein:
the first inverter is a three-phase inverter; and
the second inverter is a single-phase inverter of which AC side connected in series with each phase of the AC side of the three-phase inverter.

9. The power conversion device according to claim 8, wherein the DC voltage control means adjusts a dq axial output voltage command for each of the first and the second inverters.

10. A power conversion device having a first inverter which converts DC power of a first DC power supply fed from a power supply into AC power, and a second inverter, which converts DC power of a second DC power supply into AC power, connected in series at the AC side thereof so as to feed power to a load, the power conversion device comprising:
a means for detecting the voltage of the second DC power supply; and
an initial charging control device that controls the output of each of the first and the second inverters so as to initially charge the second DC power supply, wherein;
while the initial charging control device applies a voltage, which does not permit the load to operate, to the load, the initial charging control device controls the output of each of the first and the second inverters so that the second DC power supply will be charged via the first and the second inverters.

11. The power conversion device according to claim 10, wherein:
the power conversion device feeds an output voltage to the load using the sum total of the generated voltages of the first and the second inverters;
the initial charging control device determines a manipulative quantity so that the detected voltage of the second DC power supply will reach a command value, adds the manipulative quantity to the command value for the voltage to the load so as to adopt the result as an output voltage command for the first inverter, and reverses the polarity of the manipulative quantity so as to adopt the result as an output voltage command for the second inverter.

12. The power conversion device according to claim 10, wherein:
both of the first inverter and the second inverter are three-phase inverters;
the first inverter and the second inverter are connected in series via the load;
the power conversion device feeds the difference voltage between the generated voltages of the first and the second inverters to the load;
the initial charging control device determines a manipulative quantity so that the detected voltage of the second DC power supply will reach a command value, adds the manipulative quantity to the command value for the voltage to the load so as to adopt the result as an output voltage command for the first inverter, and adopts the manipulative quantity as an output voltage command for the second inverter.

13. The power conversion device according to claim 10, wherein:
the initial charging control device includes a means that detects a current flowing to the load, and a current control means that produces the command value for the voltage to the load so that the detected current will follow the command value.

14. The power conversion device according to claim 10, wherein the voltage to be applied to the load by the initial charging control device is DC voltage.

15. The power conversion device according to claim 10, wherein the load is a motor, and the voltage to be applied to the load by the initial charging control device is an AC voltage which does not induce a rotating field in the motor.

16. The power conversion device according to claim 10, wherein:
the initial charging control device terminates the initial charging of the second DC power supply when the detected voltage of the second DC power supply reaches the command value; and
the voltage to be applied to the load by the initial charging control device is an AC voltage of a low frequency that undergoes a phase change, which falls within a predetermined range, by completion of the initial charging.

17. The power conversion device according to claim 10, wherein:
both of the first inverter and the second inverter are single-phase inverters.

18. The power conversion device according to claim 10, wherein:
the first inverter is a three-phase inverter; and
the second inverter is a single-phase inverter of which AC side connected in series with each phase of the AC side of the three-phase inverter.