# Patent

## Title
Digital broadcasting system and method of processing data

## Abstract

A digital broadcast system and method of processing digital data is disclosed, including a digital broadcast transmitter and digital broadcast receiver and methods thereof.

## Background
This application claims the benefit of the Korean Patent Application No. 10-2007-0031960, filed on Mar. 30, 2007, which is hereby incorporated by reference as if fully set forth herein. Also, this application claims the benefit of U.S. Provisional Application No. 60/909,575, filed on Apr. 2, 2007, which is hereby incorporated by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital broadcasting system and method of processing data.
2. Discussion of the Related Art
The Vestigial Sideband (VSB) transmission mode, which is adopted as the standard for digital broadcasting in North America and the Republic of Korea, is a system using a single carrier method. Therefore, the receiving performance of the digital broadcast receiving system may be deteriorated in a poor channel environment. Particularly, since resistance to changes in channels and noise is more highly required when using portable and/or mobile broadcast receivers, the receiving performance may be even more deteriorated when transmitting mobile service data by the VSB transmission mode.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a digital broadcasting system and a method of processing data that substantially obviate one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a digital broadcasting system and a method of processing data that are highly resistant to channel changes and noise.
Another object of the present invention is to provide a digital broadcasting system and a method of processing data that can enhance the receiving performance of a digital broadcast receiving system by performing additional encoding on mobile service data and by transmitting the processed data to the receiving system.
A further object of the present invention is to provide a digital broadcasting system and a method of processing data that can also enhance the receiving performance of a digital broadcast receiving system by inserting known data already known in accordance with a pre-agreement between the receiving system and the transmitting system in a predetermined area within a data area.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a digital broadcast transmitting system includes a service multiplexer and a transmitter. The service multiplexer multiplexes mobile service data and main service data at pre-determined data rates and, then, transmits the multiplexed service data to the transmitter. The transmitter performs additional encoding on the mobile service data transmitted from the service multiplexer and, also, groups a plurality of mobile service data packets having encoding performed thereon so as to configure a data group.
Herein, the transmitter may multiplex a mobile service data packet including the mobile service data and a main service data packet including the main service data in packet units and may transmit the multiplexed data packets to a digital broadcast receiving system. Herein, the transmitter may multiplex the data group and the main service data packet in a burst structure, wherein the burst section may be divided in a burst-on section including the data group, and a burst-off section that does not include the data group. The data group may be divided into a plurality of regions based upon a degree of interference of the main service data. A long known data sequence may be periodically inserted in the region having no interference with the main service data.
In another aspect of the present invention, a digital broadcast receiving system may use the known data sequence for demodulating and channel equalizing processes. When receiving only the mobile service data, the digital broadcast receiving system turns power on only during the burst-on section so as to process the mobile service data.
In another aspect of the present invention, a channel equalizer of a digital broadcast receiving system includes a frequency domain converter, a CIR estimator, a CIR calculator, a coefficient calculator, and a distortion compensator. Herein, the frequency domain converter receives a known data sequence, when the known data sequence is periodically inserted and transmitted in general data, and converts the received data to frequency domain data. The CIR estimator uses the data being received during a known data section and known data generated by a receiving system, so as to estimate a channel impulse response (CIR). The CIR calculator interpolates or extrapolates the CIR estimated by the CIR estimator in accordance with characteristics of the general data being received. The coefficient calculator converts the CIR being outputted from the CIR calculator to a frequency domain CIR and calculates and outputs an equalization coefficient. And, the distortion compensator multiplies the equalization coefficient calculated by the coefficient calculator with the data converted to frequency domain data by the frequency domain converter, thereby compensating channel distortion.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention. In the drawings:
FIG. 1 illustrates a block diagram showing a general structure of a digital broadcasting system according to an embodiment of the present invention;
FIG. 2 illustrates a block diagram showing an example of a service multiplexer of FIG. 1;
FIG. 3 illustrates a block diagram showing an example of a transmitter of FIG. 1;
FIG. 4 illustrates a block diagram showing an example of a pre-processor of FIG. 3;
FIG. 5(a) to FIG. 5(e) illustrate error correction encoding and error detection encoding processed according to an embodiment of the present invention;
FIG. 6A and FIG. 6B illustrate data configuration before and after a data deinterleaver in a digital broadcast transmitting system according to the present invention;
FIG. 7 illustrates a process of dividing a RS frame for configuring a data group according to the present invention;
FIG. 8 illustrates exemplary operations of a packet multiplexer for transmitting the data group according to the present invention;
FIG. 9 illustrates a block diagram showing a structure of a block processor according to the present invention;
FIG. 10 illustrates a detailed block diagram of a symbol encoder shown in FIG. 9;
FIG. 11(a) to FIG. 11(c) illustrate a variable length interleaving process of a symbol interleaver shown in FIG. 9;
FIG. 12A and FIG. 12B illustrate block diagrams showing structures of a block processor according to another embodiment of the present invention;
FIG. 13(a) to FIG. 13(c) illustrate block encoding and trellis encoding processes according to the present invention;
FIG. 14 illustrates a block diagram showing a trellis encoding module according to the present invention;
FIG. 15A and FIG. 15B a block processor and a trellis encoding module connected to one another according to the present invention;
FIG. 16 illustrates a block processor according to another embodiment of the present invention;
FIG. 17 illustrates a block processor according to yet another embodiment of the present invention;
FIG. 18 illustrates an example of a group formatter inserting and transmitting a transmission parameter;
FIG. 19 illustrates an example of a block processor inserting and transmitting a transmission parameter;
FIG. 20 illustrates an example of a packet formatter inserting and transmitting a transmission parameter;
FIG. 21 illustrates an example for inserting and transmitting the transmission parameter in a field synchronization segment area;
FIG. 22 illustrates a block diagram showing a structure of a digital broadcast receiving system according to the present invention;
FIG. 23 illustrates an example of known data sequence being periodically inserted and transmitted in-between actual data by a transmitting system;
FIG. 24(a) to FIG. 24(c) illustrate correlation between a main signal and a ghost signal when a post-ghost exists;
FIG. 25(a) to FIG. 25(c) illustrate correlation between a main signal and a ghost signal when a pre-ghost exists;
FIG. 26 illustrates a block diagram of an example of a channel equalizer according to the present invention;
FIG. 27 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 28 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 29 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 30 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 31 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 32 illustrates an example of an interpolation operation;
FIG. 33 illustrates an example of overlap & save processes according to an embodiment of the present invention;
FIG. 34 illustrates another example of overlap & save processes according to the present invention;
FIG. 35 illustrates an example of an extrapolation operation;
FIG. 36 illustrates a conceptual diagram of the extrapolation operation according to the present invention;
FIG. 37 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 38 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 39 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 40 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 41 illustrates a block diagram of an example of a CIR estimator according to the present invention;
FIG. 42 illustrates a block diagram of another example of a channel equalizer according to the present invention;
FIG. 43 illustrates a detailed block diagram of an example of a remaining carrier phase error estimator according to the present invention;
FIG. 44 illustrates a block diagram of a phase error detector obtaining a remaining carrier phase error and phase noise according to the present invention;
FIG. 45 illustrates a phase compensator according to an embodiment of the present invention; and
FIG. 46 illustrates an example of an error correction decoding process according to the present invention.



DETAILED DESCRIPTION OF THE INVENTION
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. In addition, although the terms used in the present invention are selected from generally known and used terms, some of the terms mentioned in the description of the present invention have been selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Furthermore, it is required that the present invention is understood, not simply by the actual terms used but by the meaning of each term lying within.
Among the terms used in the description of the present invention, main service data correspond to data that can be received by a fixed receiving system and may include audio/video (A/V) data. More specifically, the main service data may include A/V data of high definition (HD) or standard definition (SD) levels and may also include diverse data types required for data broadcasting. Also, the known data correspond to data pre-known in accordance with a pre-arranged agreement between the receiving system and the transmitting system. Additionally, in the present invention, mobile service data may include at least one of mobile service data, pedestrian service data, and handheld service data, and are collectively referred to as mobile service data for simplicity. Herein, the mobile service data not only correspond to mobile/pedestrian/handheld service data (M/P/H service data) but may also include any type of service data with mobile or portable characteristics. Therefore, the mobile service data according to the present invention are not limited only to the M/P/H service data.
The above-described mobile service data may correspond to data having information, such as program execution files, stock information, and so on, and may also correspond to A/V data. Most particularly, the mobile service data may correspond to A/V data having lower resolution and lower data rate as compared to the main service data. For example, if an A/V codec that is used for a conventional main service corresponds to a MPEG-2 codec, a MPEG-4 advanced video coding (AVC) or scalable video coding (SVC) having better image compression efficiency may be used as the A/V codec for the mobile service. Furthermore, any type of data may be transmitted as the mobile service data. For example, transport protocol expert group (TPEG) data for broadcasting real-time transportation information may be serviced as the main service data.
Also, a data service using the mobile service data may include weather forecast services, traffic information services, stock information services, viewer participation quiz programs, real-time polls & surveys, interactive education broadcast programs, gaming services, services providing information on synopsis, character, background music, and filming sites of soap operas or series, services providing information on past match scores and player profiles and achievements, and services providing information on product information and programs classified by service, medium, time, and theme enabling purchase orders to be processed. Herein, the present invention is not limited only to the services mentioned above. In the present invention, the transmitting system provides backward compatibility in the main service data so as to be received by the conventional receiving system. Herein, the main service data and the mobile service data are multiplexed to the same physical channel and then transmitted.
The transmitting system according to the present invention performs additional encoding on the mobile service data and inserts the data already known by the receiving system and transmitting system (i.e., known data), thereby transmitting the processed data. Therefore, when using the transmitting system according to the present invention, the receiving system may receive the mobile service data during a mobile state and may also receive the mobile service data with stability despite various distortion and noise occurring within the channel.
General Description of a Transmitting System
FIG. 1 illustrates a block diagram showing a general structure of a digital broadcast transmitting system according to an embodiment of the present invention. Herein, the digital broadcast transmitting includes a service multiplexer 100 and a transmitter 200. Herein, the service multiplexer 100 is located in the studio of each broadcast station, and the transmitter 200 is located in a site placed at a predetermined distance from the studio. The transmitter 200 may be located in a plurality of different locations. Also, for example, the plurality of transmitters may share the same frequency. And, in this case, the plurality of transmitters receives the same signal. Accordingly, in the receiving system, a channel equalizer may compensate signal distortion, which is caused by a reflected wave, so as to recover the original signal. In another example, the plurality of transmitters may have different frequencies with respect to the same channel.
A variety of methods may be used for data communication each of the transmitters, which are located in remote positions, and the service multiplexer. For example, an interface standard such as a synchronous serial interface for transport of MPEG-2 data (SMPTE-310M). In the SMPTE-310M interface standard, a constant data rate is decided as an output data rate of the service multiplexer. For example, in case of the 8VSB mode, the output data rate is 19.39 Mbps, and, in case of the 16VSB mode, the output data rate is 38.78 Mbps. Furthermore, in the conventional SVSB mode transmitting system, a transport stream (TS) packet having a data rate of approximately 19.39 Mbps may be transmitted through a single physical channel. Also, in the transmitting system according to the present invention provided with backward compatibility with the conventional transmitting system, additional encoding is performed on the mobile service data. Thereafter, the additionally encoded mobile service data are multiplexed with the main service data to a TS packet form, which is then transmitted. At this point, the data rate of the multiplexed TS packet is approximately 19.39 Mbps.
At this point, the service multiplexer 100 receives at least one type of mobile service data and program specific information (PSI)/program and system information protocol (PSIP) table data for each mobile service and encapsulates the received data to each transport stream (TS) packet. Also, the service multiplexer 100 receives at least one type of main service data and PSI/PSIP table data for each main service so as to encapsulate the received data to a TS packet. Subsequently, the TS packets are multiplexed according to a predetermined multiplexing rule and outputs the multiplexed packets to the transmitter 200.
Service Multiplexer
FIG. 2 illustrates a block diagram showing an example of the service multiplexer. The service multiplexer includes a controller 110 for controlling the overall operations of the service multiplexer, a PSI/PSIP generator 120 for the main service, a PSI/PSIP generator 130 for the mobile service, a null packet generator 140, a mobile service multiplexer 150, and a transport multiplexer 160. The transport multiplexer 160 may include a main service multiplexer 161 and a transport stream (TS) packet multiplexer 162. Referring to FIG. 2, at least one type of compression encoded main service data and the PSI/PSIP table data generated from the PSI/PSIP generator 120 for the main service are inputted to the main service multiplexer 161 of the transport multiplexer 160. The main service multiplexer 161 encapsulates each of the inputted main service data and PSI/PSIP table data to MPEG-2 TS packet forms. Then, the MPEG-2 TS packets are multiplexed and outputted to the TS packet multiplexer 162. Herein, the data packet being outputted from the main service multiplexer 161 will be referred to as a main service data packet for simplicity.
Thereafter, at least one type of the compression encoded mobile service data and the PSI/PSIP table data generated from the PSI/PSIP generator 130 for the mobile service are inputted to the mobile service multiplexer 150. The mobile service multiplexer 150 encapsulates each of the inputted mobile service data and PSI/PSIP table data to MPEG-2 TS packet forms. Then, the MPEG-2 TS packets are multiplexed and outputted to the TS packet multiplexer 162. Herein, the data packet being outputted from the mobile service multiplexer 150 will be referred to as a mobile service data packet for simplicity. At this point, the transmitter 200 requires identification information in order to identify and process the main service data packet and the mobile service data packet. Herein, the identification information may use values pre-decided in accordance with an agreement between the transmitting system and the receiving system, or may be configured of a separate set of data, or may modify predetermined location value with in the corresponding data packet. As an example of the present invention, a different packet identifier (PID) may be assigned to identify each of the main service data packet and the mobile service data packet.
In another example, by modifying a synchronization data byte within a header of the mobile service data, the service data packet may be identified by using the synchronization data byte value of the corresponding service data packet. For example, the synchronization byte of the main service data packet directly outputs the value decided by the ISO/IEC13818-1 standard (i.e., 0x47) without any modification. The synchronization byte of the mobile service data packet modifies and outputs the value, thereby identifying the main service data packet and the mobile service data packet. Conversely, the synchronization byte of the main service data packet is modified and outputted, whereas the synchronization byte of the mobile service data packet is directly outputted without being modified, thereby enabling the main service data packet and the mobile service data packet to be identified.
A plurality of methods may be applied in the method of modifying the synchronization byte. For example, each bit of the synchronization byte may be inversed, or only a portion of the synchronization byte may be inversed. As described above, any type of identification information may be used to identify the main service data packet and the mobile service data packet. Therefore, the scope of the present invention is not limited only to the example set forth in the description of the present invention.
Meanwhile, a transport multiplexer used in the conventional digital broadcasting system may be used as the transport multiplexer 160 according to the present invention. More specifically, in order to multiplex the mobile service data and the main service data and to transmit the multiplexed data, the data rate of the main service is limited to a data rate of (19.39-K) Mbps. Then, K Mbps, which corresponds to the remaining data rate, is assigned as the data rate of the mobile service. Thus, the transport multiplexer which is already being used may be used as it is without any modification. Herein, the transport multiplexer 160 multiplexes the main service data packet being outputted from the main service multiplexer 161 and the mobile service data packet being outputted from the mobile service multiplexer 150. Thereafter, the transport multiplexer 160 transmits the multiplexed data packets to the transmitter 200.
However, in some cases, the output data rate of the mobile service multiplexer 150 may not be equal to K Mbps. In this case, the mobile service multiplexer 150 multiplexes and outputs null data packets generated from the null packet generator 140 so that the output data rate can reach K Mbps. More specifically, in order to match the output data rate of the mobile service multiplexer 150 to a constant data rate, the null packet generator 140 generates null data packets, which are then outputted to the mobile service multiplexer 150. For example, when the service multiplexer 100 assigns K Mbps of the 19.39 Mbps to the mobile service data, and when the remaining (19.39-K) Mbps is, therefore, assigned to the main service data, the data rate of the mobile service data that are multiplexed by the service multiplexer 100 actually becomes lower than K Mbps. This is because, in case of the mobile service data, the pre-processor of the transmitting system performs additional encoding, thereby increasing the amount of data. Eventually, the data rate of the mobile service data, which may be transmitted from the service multiplexer 100, becomes smaller than K Mbps.
For example, since the pre-processor of the transmitter performs an encoding process on the mobile service data at a coding rate of at least 1⁄2, the amount of the data outputted from the pre-processor is increased to more than twice the amount of the data initially inputted to the pre-processor. Therefore, the sum of the data rate of the main service data and the data rate of the mobile service data, both being multiplexed by the service multiplexer 100, becomes either equal to or smaller than 19.39 Mbps. Therefore, in order to match the data rate of the data that are finally outputted from the service multiplexer 100 to a constant data rate (e.g., 19.39 Mbps), an amount of null data packets corresponding to the amount of lacking data rate is generated from the null packet generator 140 and outputted to the mobile service multiplexer 150.
Accordingly, the mobile service multiplexer 150 encapsulates each of the mobile service data and the PSI/PSIP table data that are being inputted to a MPEG-2 TS packet form. Then, the above-described TS packets are multiplexed with the null data packets and, then, outputted to the TS packet multiplexer 162. Thereafter, the TS packet multiplexer 162 multiplexes the main service data packet being outputted from the main service multiplexer 161 and the mobile service data packet being outputted from the mobile service multiplexer 150 and transmits the multiplexed data packets to the transmitter 200 at a data rate of 19.39 Mbps.
According to an embodiment of the present invention, the mobile service multiplexer 150 receives the null data packets. However, this is merely exemplary and does not limit the scope of the present invention. In other words, according to another embodiment of the present invention, the TS packet multiplexer 162 may receive the null data packets, so as to match the data rate of the finally outputted data to a constant data rate. Herein, the output path and multiplexing rule of the null data packet is controlled by the controller 110. The controller 110 controls the multiplexing processed performed by the mobile service multiplexer 150, the main service multiplexer 161 of the transport multiplexer 160, and the TS packet multiplexer 162, and also controls the null data packet generation of the null packet generator 140. At this point, the transmitter 200 discards the null data packets transmitted from the service multiplexer 100 instead of transmitting the null data packets.
Further, in order to allow the transmitter 200 to discard the null data packets transmitted from the service multiplexer 100 instead of transmitting them, identification information for identifying the null data packet is required. Herein, the identification information may use values pre-decided in accordance with an agreement between the transmitting system and the receiving system. For example, the value of the synchronization byte within the header of the null data packet may be modified so as to be used as the identification information. Alternatively, a transport_error_indicator flag may also be used as the identification information.
In the description of the present invention, an example of using the transport_error_indicator flag as the identification information will be given to describe an embodiment of the present invention. In this case, the transport_error_indicator flag of the null data packet is set to ‘1’, and the transport_error_indicator flag of the remaining data packets are reset to ‘0’, so as to identify the null data packet. More specifically, when the null packet generator 140 generates the null data packets, if the transport_error_indicator flag from the header field of the null data packet is set to ‘1’ and then transmitted, the null data packet may be identified and, therefore, be discarded. In the present invention, any type of identification information for identifying the null data packets may be used. Therefore, the scope of the present invention is not limited only to the examples set forth in the description of the present invention.
According to another embodiment of the present invention, a transmission parameter may be included in at least a portion of the null data packet, or at least one table or an operations and maintenance (OM) packet (or OMP) of the PSI/PSIP table for the mobile service. In this case, the transmitter 200 extracts the transmission parameter and outputs the extracted transmission parameter to the corresponding block and also transmits the extracted parameter to the receiving system if required. More specifically, a packet referred to as an OMP is defined for the purpose of operating and managing the transmitting system. For example, the OMP is configured in accordance with the MPEG-2 TS packet format, and the corresponding PID is given the value of 0x1FFA. The OMP is configured of a 4-byte header and a 184-byte payload. Herein, among the 184 bytes, the first byte corresponds to an OM_type field, which indicates the type of the OM packet.
In the present invention, the transmission parameter may be transmitted in the form of an OMP. And, in this case, among the values of the reserved fields within the OM_type field, a pre-arranged value is used, thereby indicating that the transmission parameter is being transmitted to the transmitter 200 in the form of an OMP. More specifically, the transmitter 200 may find (or identify) the OMP by referring to the PID. Also, by parsing the OM_type field within the OMP, the transmitter 200 can verify whether a transmission parameter is included after the OM_type field of the corresponding packet. The transmission parameter corresponds to supplemental data required for processing mobile service data from the transmitting system and the receiving system.
Herein, the transmission parameter may include data group information, region information within the data group, RS frame information, super frame information, burst information, turbo code information, and RS code information. The burst information may include burst size information, burst period information, and time information to next burst. The burst period signifies the period at which the burst transmitting the same mobile service is repeated. The data group includes a plurality of mobile service data packets, and a plurality of such data groups is gathered (or grouped) to form a burst. A burst section signifies the beginning of a current burst to the beginning of a next burst. Herein, the burst section is classified as a section that includes the data group (also referred to as a burst-on section), and a section that does not include the data group (also referred to as a burst-off section). A burst-on section is configured of a plurality of fields, wherein one field includes one data group.
The transmission parameter may also include information on how signals of a symbol domain are encoded in order to transmit the mobile service data, and multiplexing information on how the main service data and the mobile service data or various types of mobile service data are multiplexed. The information included in the transmission parameter is merely exemplary to facilitate the understanding of the present invention. And, the adding and deleting of the information included in the transmission parameter may be easily modified and changed by anyone skilled in the art. Therefore, the present invention is not limited to the examples proposed in the description set forth herein. Furthermore, the transmission parameters may be provided from the service multiplexer 100 to the transmitter 200. Alternatively, the transmission parameters may also be set up by an internal controller (not shown) within the transmitter 200 or received from an external source.
Transmitter
FIG. 3 illustrates a block diagram showing an example of the transmitter 200 according to an embodiment of the present invention. Herein, the transmitter 200 includes a demultiplexer 210, a packet jitter mitigator 220, a pre-processor 230, a packet multiplexer 240, a post-processor 250, a synchronization (sync) multiplexer 260, and a transmission unit 270. Herein, when a data packet is received from the service multiplexer 100, the demultiplexer 210 should identify whether the received data packet corresponds to a main service data packet, a mobile service data packet, or a null data packet. For example, the demultiplexer 210 uses the PID within the received data packet so as to identify the main service data packet and the mobile service data packet. Then, the demultiplexer 210 uses a transport_error_indicator field to identify the null data packet. The main service data packet identified by the demultiplexer 210 is outputted to the packet jitter mitigator 220, the mobile service data packet is outputted to the pre-processor 230, and the null data packet is discarded. If a transmission parameter is included in the null data packet, then the transmission parameter is first extracted and outputted to the corresponding block. Thereafter, the null data packet is discarded.
The pre-processor 230 performs an additional encoding process of the mobile service data included in the service data packet, which is demultiplexed and outputted from the demultiplexer 210. The pre-processor 230 also performs a process of configuring a data group so that the data group may be positioned at a specific place in accordance with the purpose of the data, which are to be transmitted on a transmission frame. This is to enable the mobile service data to respond swiftly and strongly against noise and channel changes. The pre-processor 230 may also refer to the transmission parameter when performing the additional encoding process. Also, the pre-processor 230 groups a plurality of mobile service data packets to configure a data group. Thereafter, known data, mobile service data, RS parity data, and MPEG header are allocated to pre-determined areas within the data group.
Pre-Processor within Transmitter
FIG. 4 illustrates a block diagram showing an example of the pre-processor 230 according to the present invention. The pre-processor 230 includes a data randomizer 301, a RS frame encoder 302, a block processor 303, a group formatter 304, a data deinterleaver 305, a packet formatter 306. The data randomizer 301 within the above-described pre-processor 230 randomizes the mobile service data packet including the mobile service data that is inputted through the demultiplexer 210. Then, the data randomizer 301 outputs the randomized mobile service data packet to the RS frame encoder 302. At this point, since the data randomizer 301 performs the randomizing process on the mobile service data, the randomizing process that is to be performed by the data randomizer 251 of the post-processor 250 on the mobile service data may be omitted. The data randomizer 301 may also discard the synchronization byte within the mobile service data packet and perform the randomizing process. This is an option that may be chosen by the system designer. In the example given in the present invention, the randomizing process is performed without discarding the synchronization byte within the mobile service data packet.
The RS frame encoder 302 groups a plurality of synchronization bytes within the mobile service data packets that is randomized and inputted, so as to create a RS frame. Then, the RS frame encoder 302 performs at least one of an error correction encoding process and an error detection encoding process in RS frame units. Accordingly, robustness may be provided to the mobile service data, thereby scattering group error that may occur during changes in a frequency environment, thereby enabling the mobile service data to respond to the frequency environment, which is extremely vulnerable and liable to frequent changes. Also, the RS frame encoder 302 groups a plurality of RS frames so as to create a super frame, thereby performing a row permutation process in super frame units. The row permutation process may also be referred to as a row interleaving process. Hereinafter, the process will be referred to as row permutation for simplicity.
More specifically, when the RS frame encoder 302 performs the process of permuting each row of the super frame in accordance with a pre-determined rule, the position of the rows within the super frame before and after the row permutation process is changed. If the row permutation process is performed by super frame units, and even though the section having a plurality of errors occurring therein becomes very long, and even though the number of errors included in the RS frame, which is to be decoded, exceeds the extent of being able to be corrected, the errors become dispersed within the entire super frame. Thus, the decoding ability is even more enhanced as compared to a single RS frame.
At this point, as an example of the present invention, RS-encoding is applied for the error correction encoding process, and a cyclic redundancy check (CRC) encoding is applied for the error detection process. When performing the RS-encoding, parity data that are used for the error correction are generated. And, when performing the CRC encoding, CRC data that are used for the error detection are generated. The RS encoding is one of forward error correction (FEC) methods. The FEC corresponds to a technique for compensating errors that occur during the transmission process. The CRC data generated by CRC encoding may be used for indicating whether or not the mobile service data have been damaged by the errors while being transmitted through the channel. In the present invention, a variety of error detection coding methods other than the CRC encoding method may be used, or the error correction coding method may be used to enhance the overall error correction ability of the receiving system. Herein, the RS frame encoder 302 refers to a pre-determined transmission parameter and/or the transmission parameter provided from the service multiplexer 100 so as to perform operations including RS frame configuration, RS encoding, CRC encoding, super frame configuration, and row permutation in super frame units.
Pre-Processor within RS Frame Encoder
FIG. 5(a) to FIG. 5(e) illustrate error correction encoding and error detection encoding processed according to an embodiment of the present invention. More specifically, the RS frame encoder 302 first divides the inputted mobile service data bytes to units of a predetermined length. The predetermined length is decided by the system designer. And, in the example of the present invention, the predetermined length is equal to 187 bytes, and, therefore, the 187-byte unit will be referred to as a packet for simplicity. For example, when the mobile service data that are being inputted, as shown in FIG. 5(a), correspond to a MPEG transport packet stream configured of 188-byte units, the first synchronization byte is removed, as shown in FIG. 5(b), so as to configure a 187-byte unit. Herein, the synchronization byte is removed because each mobile service data packet has the same value.
Herein, the process of removing the synchronization byte may be performed during a randomizing process of the data randomizer 301 in an earlier process. In this case, the process of the removing the synchronization byte by the RS frame encoder 302 may be omitted. Moreover, when adding synchronization bytes from the receiving system, the process may be performed by the data derandomizer instead of the RS frame decoder. Therefore, if a removable fixed byte (e.g., synchronization byte) does not exist within the mobile service data packet that is being inputted to the RS frame encoder 302, or if the mobile service data that are being inputted are not configured in a packet format, the mobile service data that are being inputted are divided into 187-byte units, thereby configuring a packet for each 187-byte unit.
Subsequently, as shown in FIG. 5(c), N number of packets configured of 187 bytes is grouped to configure a RS frame. At this point, the RS frame is configured as a RS frame having the size of N(row)*187(column) bytes, in which 187-byte packets are sequentially inputted in a row direction. In order to simplify the description of the present invention, the RS frame configured as described above will also be referred to as a first RS frame. More specifically, only pure mobile service data are included in the first RS frame, which is the same as the structure configured of 187 N-byte rows. Thereafter, the mobile service data within the RS frame are divided into an equal size. Then, when the divided mobile service data are transmitted in the same order as the input order for configuring the RS framer and when one or more errors have occurred at a particular point during the transmitting/receiving process, the errors are clustered (or gathered) within the RS frame as well. In this case, the receiving system uses a RS erasure decoding method when performing error correction decoding, thereby enhancing the error correction ability. At this point, the N number of columns within the N number of RS frame includes 187 bytes, as shown in FIG. 5(c).
In this case, a (Nc,Kc)-RS encoding process is performed on each column, so as to generate Nc−Kc(=P) number of parity bytes. Then, the newly generated P number of parity bytes is added after the very last byte of the corresponding column, thereby creating a column of (187+P) bytes. Herein, as shown in FIG. 5(c), Kc is equal to 187 (i.e., Kc=187), and Nc is equal to 187+P (i.e., Nc=187+P). For example, when P is equal to 48, (235,187)-RS encoding process is performed so as to create a column of 235 bytes. When such RS encoding process is performed on all N number of columns, as shown in FIG. 5(c), a RS frame having the size of N(row)*(187+P)(column) bytes may be created, as shown in FIG. 5(d). In order to simplify the description of the present invention, the RS frame having the RS parity inserted therein will be referred to as 8 second RS frame. More specifically, the second RS frame having the structure of (187+P) rows configured of N bytes may be configured.
As shown in FIG. 5(c) or FIG. 5(d), each row of the RS frame is configured of N bytes. However, depending upon channel conditions between the transmitting system and the receiving system, error may be included in the RS frame. When errors occur as described above, CRC data (or CRC code or CRC checksum) may be used on each row unit in order to verify whether error exists in each row unit. The RS frame encoder 302 may perform CRC encoding on the mobile service data being RS encoded so as to create (or generate) the CRC data. The CRC data being generated by CRC encoding may be used to indicate whether the mobile service data have been damaged while being transmitted through the channel.
The present invention may also use different error detection encoding methods other than the CRC encoding method. Alternatively, the present invention may use the error correction encoding method to enhance the overall error correction ability of the receiving system. FIG. 5(e) illustrates an example of using a 2-byte (i.e., 16-bit) CRC checksum as the CRC data. Herein, a 2-byte CRC checksum is generated for N number of bytes of each row, thereby adding the 2-byte CRC checksum at the end of the N number of bytes. Thus, each row is expanded to (N+2) number of bytes. Equation 1 below corresponds to an exemplary equation for generating a 2-byte CRC checksum for each row being configured of N number of bytes.

g(x)=x16+x12+x5+1  Equation 1

The process of adding a 2-byte checksum in each row is only exemplary. Therefore, the present invention is not limited only to the example proposed in the description set forth herein. In order to simplify the understanding of the present invention, the RS frame having the RS parity and CRC checksum added therein will hereinafter be referred to as a third RS frame. More specifically, the third RS frame corresponds to (187+P) number of rows each configured of (N+2) number of bytes. As described above, when the process of RS encoding and CRC encoding are completed, the (N*187)-byte RS frame is expanded to a (N+2)*(187+P)-byte RS frame. Furthermore, the RS frame that is expanded, as shown in FIG. 5(e), is inputted to the block processor 303.
As described above, the mobile service data encoded by the RS frame encoder 302 are inputted to the block processor 303. The block processor 303 then encodes the inputted mobile service data at a coding rate of G/H (wherein, G is smaller than H (i.e., G<H)) and then outputted to the group formatter 304. More specifically, the block processor 303 divides the mobile service data being inputted in byte units into bit units. Then, the G number of bits is encoded to H number of bits. Thereafter, the encoded bits are converted back to byte units and then outputted. For example, if 1 bit of the input data is coded to 2 bits and outputted, then G is equal to 1 and H is equal to 2 (i.e., G=1 and H=2). Alternatively, if 1 bit of the input data is coded to 4 bits and outputted, then G is equal to 1 and H is equal to 4 (i.e., G=1 and H=4). Hereinafter, the former coding rate will be referred to as a coding rate of 1⁄2 (1⁄2-rate coding), and the latter coding rate will be referred to as a coding rate of 1⁄4 (1⁄4-rate coding), for simplicity.
Herein, when using the 1⁄4 coding rate, the coding efficiency is greater than when using the 1⁄2 coding rate, and may, therefore, provide greater and enhanced error correction ability. For such reason, when it is assumed that the data encoded at a 1⁄4 coding rate in the group formatter 304, which is located near the end portion of the system, are allocated to an area in which the receiving performance may be deteriorated, and that the data encoded at a 1⁄2 coding rate are allocated to an area having excellent receiving performance, the difference in performance may be reduced. At this point, the block processor 303 may also receive signaling information including transmission parameters. Herein, the signaling information may also be processed with either 1⁄2-rate coding or 1⁄4-rate coding as in the step of processing mobile service data. Thereafter, the signaling information is also considered the same as the mobile service data and processed accordingly.
Meanwhile, the group formatter inserts mobile service data that are outputted from the block processor 303 in corresponding areas within a data group, which is configured in accordance with a pre-defined rule. Also, with respect to the data deinterleaving process, each place holder or known data (or known data place holders) are also inserted in corresponding areas within the data group. At this point, the data group may be divided into at least one hierarchical area. Herein, the type of mobile service data being inserted in each area may vary depending upon the characteristics of each hierarchical area. Additionally, each area may, for example, be divided based upon the receiving performance within the data group. Furthermore, one data group may be configured to include a set of field synchronization data.
In an example given in the present invention, a data group is divided into A, B, and C regions in a data configuration prior to data deinterleaving. At this point, the group formatter 304 allocates the mobile service data, which are inputted after being RS encoded and block encoded, to each of the corresponding regions by referring to the transmission parameter. FIG. 6A illustrates an alignment of data after being data interleaved and identified, and FIG. 6B illustrates an alignment of data before being data interleaved and identified. More specifically, a data structure identical to that shown in FIG. 6A is transmitted to a receiving system. Also, the data group configured to have the same structure as the data structure shown in FIG. 6A is inputted to the data deinterleaver 305.
As described above, FIG. 6A illustrates a data structure prior to data deinterleaving that is divided into 3 regions, such as region A, region B, and region C. Also, in the present invention, each of the regions A to C is further divided into a plurality of regions. Referring to FIG. 6A, region A is divided into 5 regions (A1 to A5), region B is divided into 2 regions (B1 and B2), and region C is divided into 3 regions (C1 to C3). Herein, regions A to C are identified as regions having similar receiving performances within the data group. Herein, the type of mobile service data, which are inputted, may also vary depending upon the characteristic of each region.
In the example of the present invention, the data structure is divided into regions A to C based upon the level of interference of the main service data. Herein, the data group is divided into a plurality of regions to be used for different purposes. More specifically, a region of the main service data having no interference or a very low interference level may be considered to have a more resistant (or stronger) receiving performance as compared to regions having higher interference levels. Additionally, when using a system inserting and transmitting known data in the data group, and when consecutively long known data are to be periodically inserted in the mobile service data, the known data having a predetermined length may be periodically inserted in the region having no interference from the main service data (e.g., region A). However, due to interference from the main service data, it is difficult to periodically insert known data and also to insert consecutively long known data to a region having interference from the main service data (e.g., region B and region C).
Hereinafter, examples of allocating data to region A (A1 to A5), region B (B1 and B2), and region C (C1 to C3) will now be described in detail with reference to FIG. 6A. The data group size, the number of hierarchically divided regions within the data group and the size of each region, and the number of mobile service data bytes that can be inserted in each hierarchically divided region of FIG. 6A are merely examples given to facilitate the understanding of the present invention. Herein, the group formatter 304 creates a data group including places in which field synchronization data bytes are to be inserted, so as to create the data group that will hereinafter be described in detail.
More specifically, region A is a region within the data group in which a long known data sequence may be periodically inserted, and in which includes regions wherein the main service data are not mixed (e.g., A1 to A5). Also, region A includes a region (e.g., A1) located between a field synchronization region and the region in which the first known data sequence is to be inserted. The field synchronization region has the length of one segment (i.e., 832 symbols) existing in an ATSC system.
For example, referring to FIG. 6A, 2428 bytes of the mobile service data may be inserted in region A1, 2580 bytes may be inserted in region A2, 2772 bytes may be inserted in region A3, 2472 bytes may be inserted in region A4, and 2772 bytes may be inserted in region A5. Herein, trellis initialization data or known data, MPEG header, and RS parity are not included in the mobile service data. As described above, when region A includes a known data sequence at both ends, the receiving system uses channel information that can obtain known data or field synchronization data, so as to perform equalization, thereby providing enforced equalization performance.
Also, region B includes a region located within 8 segments at the beginning of a field synchronization region within the data group (chronologically placed before region A1) (e.g., region B1), and a region located within 8 segments behind the very last known data sequence which is inserted in the data group (e.g., region B2). For example, 930 bytes of the mobile service data may be inserted in the region B1, and 1350 bytes may be inserted in region B2. Similarly, trellis initialization data or known data, MPEG header, and RS parity are not included in the mobile service data. In case of region B, the receiving system may perform equalization by using channel information obtained from the field synchronization region. Alternatively, the receiving system may also perform equalization by using channel information that may be obtained from the last known data sequence, thereby enabling the system to respond to the channel changes.
Region C includes a region located within 30 segments including and preceding the 9th segment of the field synchronization region (chronologically located before region A) (e.g., region C1), a region located within 12 segments including and following the 9th segment of the very last known data sequence within the data group (chronologically located after region A) (e.g., region C2), and a region located in 32 segments after the region C2 (e.g., region C3). For example, 1272 bytes of the mobile service data may be inserted in the region C1, 1560 bytes may be inserted in region C2, and 1312 bytes may be inserted in region C3. Similarly, trellis initialization data or known data, MPEG header, and RS parity are not included in the mobile service data. Herein, region C (e.g., region C1) is located chronologically earlier than (or before) region A.
Since region C (e.g., region C1) is located further apart from the field synchronization region which corresponds to the closest known data region, the receiving system may use the channel information obtained from the field synchronization data when performing channel equalization. Alternatively, the receiving system may also use the most recent channel information of a previous data group. Furthermore, in region C (e.g., region C2 and region C3) located before region A, the receiving system may use the channel information obtained from the last known data sequence to perform equalization. However, when the channels are subject to fast and frequent changes, the equalization may not be performed perfectly. Therefore, the equalization performance of region C may be deteriorated as compared to that of region B.
When it is assumed that the data group is allocated with a plurality of hierarchically divided regions, as described above, the block processor 303 may encode the mobile service data, which are to be inserted to each region based upon the characteristic of each hierarchical region, at a different coding rate. For example, the block processor 303 may encode the mobile service data, which are to be inserted in regions A1 to A5 of region A, at a coding rate of 1⁄2. Then, the group formatter 304 may insert the 1⁄2-rate encoded mobile service data to regions A1 to A5.
The block processor 303 may encode the mobile service data, which are to be inserted in regions B5 and B2 of region B, at a coding rate of 1⁄4 having higher error correction ability as compared to the 1⁄2-coding rate. Then, the group formatter 304 inserts the 1⁄4-rate coded mobile service data in region B1 and region 52. Furthermore, the block processor 303 may encode the mobile service data, which are to be inserted in regions C1 to C3 of region C, at a coding rate of 1⁄4 or a coding rate having higher error correction ability than the 1⁄4-coding rate. Then, the group formatter 304 may either insert the encoded mobile service data to regions C1 to C3, as described above, or leave the data in a reserved region for future usage.
In addition, the group formatter 304 also inserts supplemental data, such as signaling information that notifies the overall transmission information, other than the mobile service data in the data group. Also, apart from the encoded mobile service data outputted from the block processor 303, the group formatter 304 also inserts MPEG header place holders, non-systematic RS parity place holders, main service data place holders, which are related to data deinterleaving in a later process, as shown in FIG. 6A. Herein, the main service data place holders are inserted because the mobile service data bytes and the main service data bytes are alternately mixed with one another in regions B and C based upon the input of the data deinterleaver, as shown in FIG. 6A. For example, based upon the data outputted after data deinterleaving, the place holder for the MPEG header may be allocated at the very beginning of each packet.
Furthermore, the group formatter 304 either inserts known data generated in accordance with a pre-determined method or inserts known data place holders for inserting the known data in a later process. Additionally, place holders for initializing the trellis encoding module 256 are also inserted in the corresponding regions. For example, the initialization data place holders may be inserted in the beginning of the known data sequence. Herein, the size of the mobile service data that can be inserted in a data group may vary in accordance with the sizes of the trellis initialization place holders or known data (or known data place holders), MPEG header place holders, and RS parity place holders.
The output of the group formatter 304 is inputted to the data deinterleaver 305. And, the data deinterleaver 305 deinterleaves data by performing an inverse process of the data interleaver on the data and place holders within the data group, which are then outputted to the packet formatter 306. More specifically, when the data and place holders within the data group configured, as shown in FIG. 6A, are deinterleaved by the data deinterleaver 305, the data group being outputted to the packet formatter 306 is configured to have the structure shown in FIG. 6B.
The packet formatter 306 removes the main service data place holders and the RS parity place holders that were allocated for the deinterleaving process from the deinterleaved data being inputted. Then, the packet formatter 306 groups the remaining portion and replaces the 4-byte MPEG header place holder with an MPEG header having a null packet PID (or an unused PID from the main service data packet). Also, when the group formatter 304 inserts known data place holders, the packet formatter 306 may insert actual known data in the known data place holders, or may directly output the known data place holders without any modification in order to make replacement insertion in a later process. Thereafter, the packet formatter 306 identifies the data within the packet-formatted data group, as described above, as a 188-byte unit mobile service data packet (i.e., MPEG TS packet), which is then provided to the packet multiplexer 240.
The packet multiplexer 240 multiplexes the mobile service data packet outputted from the pre-processor 230 and the main service data packet outputted from the packet jitter mitigator 220 in accordance with a pre-defined multiplexing method. Then, the packet multiplexer 240 outputs the multiplexed data packets to the data randomizer 251 of the post-processor 250. Herein, the multiplexing method may vary in accordance with various variables of the system design. One of the multiplexing methods of the packet formatter 240 consists of providing a burst section along a time axis, and, then, transmitting a plurality of data groups during a burst-on section within the burst section, and transmitting only the main service data during the burst-off section within the burst section. Herein, the burst section indicates the section starting from the beginning of the current burst until the beginning of the next burst.
At this point, the main service data may be transmitted during the burst-on section. The packet multiplexer 240 refers to the transmission parameter, such as information on the burst size or the burst period, so as to be informed of the number of data groups and the period of the data groups included in a single burst. Herein, the mobile service data and the main service data may co-exist in the burst-on section, and only the main service data may exist in the burst-off section. Therefore, a main data service section transmitting the main service data may exist in both burst-on and burst-off sections. At this point, the main data service section within the burst-on section and the number of main data service packets included in the burst-off section may either be different from one another or be the same.
When the mobile service data are transmitted in a burst structure, in the receiving system receiving only the mobile service data turns the power on only during the burst section, thereby receiving the corresponding data. Alternatively, in the section transmitting only the main service data, the power is turned off so that the main service data are not received in this section. Thus, the power consumption of the receiving system may be reduced.
Detailed Embodiments of the RS Frame Structure and Packet Multiplexing
Hereinafter, detailed embodiments of the pre-processor 230 and the packet multiplexer 240 will now be described. According to an embodiment of the present invention, the N value corresponding to the length of a row, which is included in the RS frame that is configured by the RS frame encoder 302, is set to 538. Accordingly, the RS frame encoder 302 receives 538 transport stream (TS) packets so as to configure a first RS frame having the size of 538*187 bytes. Thereafter, as described above, the first RS frame is processed with a (235,187)-RS encoding process so as to configure a second RS frame having the size of 538*235 bytes. Finally, the second RS frame is processed with generating a 16-bit checksum so as to configure a third RS frame having the sizes of 540*235.
Meanwhile, as shown in FIG. 6A, the sum of the number of bytes of regions A1 to A5 of region A, in which 1⁄2-rate encoded mobile service data are to be inserted, among the plurality of regions within the data group is equal to 13024 bytes (=2428+2580+2772+2472+2772 bytes). Herein, the number of byte prior to performing the 1⁄2-rate encoding process is equal to 6512 (=13024/2). On the other hand, the sum of the number of bytes of regions B1 and B2 of region B, in which 1⁄4-rate encoded mobile service data are to be inserted, among the plurality of regions within the data group is equal to 2280 bytes (=930+1350 bytes). Herein, the number of byte prior to performing the 1⁄4-rate encoding process is equal to 570 (=2280/4).
In other words, when 7082 bytes of mobile service data are inputted to the block processor 303, 6512 byte are expanded to 13024 bytes by being 1⁄2-rate encoded, and 570 bytes are expanded to 2280 bytes by being 1⁄4-rate encoded. Thereafter, the block processor 303 inserts the mobile service data expanded to 13024 bytes in regions A1 to A5 of region A and, also, inserts the mobile service data expanded to 2280 bytes in regions B1 and B2 of region B. Herein, the 7082 bytes of mobile service data being inputted to the block processor 303 may be divided into an output of the RS frame encoder 302 and signaling information. In the present invention, among the 7082 bytes of mobile service data, 7050 bytes correspond to the output of the RS frame encoder 302, and the remaining 32 bytes correspond to the signaling information data. Then, 1⁄2-rate encoding or 1⁄4-rate encoding is performed on the corresponding data bytes.
Meanwhile, a RS frame being processed with RS encoding and CRC encoding from the RS frame encoder 302 is configured of 540*235 bytes, in other words, 126900 bytes. The 126900 bytes are divided by 7050-byte units along the time axis, so as to produce 18 7050-byte units. Thereafter, a 32-byte unit of signaling information data is added to the 7050-byte unit mobile service data being outputted from the RS frame encoder 302. Subsequently, the RS frame encoder 302 performs 1⁄2-rate encoding or 1⁄4-rate encoding on the corresponding data bytes, which are then outputted to the group formatter 304. Accordingly, the group formatter 304 inserts the 1⁄2-rate encoded data in region A and the 1⁄4-rate encoded data in region B.
The process of deciding an N value that is required for configuring the RS frame from the RS frame encoder 302 will now be described in detail. More specifically, the size of the final RS frame (i.e., the third RS frame), which is RS encoded and CRC encoded from the RS frame encoder 302, which corresponds to (N+2)*235 bytes should be allocated to X number of groups, wherein X is an integer. Herein, in a single data group, 7050 data bytes prior to being encoded are allocated. Therefore, if the (N+2)*235 bytes are set to be the exact multiple of 7050(=30*235), the output data of the RS frame encoder 302 may be efficiently allocated to the data group. According to an embodiment of the present invention, the value of N is decided so that (N+2) becomes a multiple of 30. For example, in the present invention, N is equal to 538, and (N+2)(=540) divided by 30 is equal to 18. This indicates that the mobile service data within one RS frame are processed with either 1⁄2-rate encoding or 1⁄4-rate encoding. The encoded mobile service data are then allocated to 18 data groups.
FIG. 7 illustrates a process of dividing the RS frame according to the present invention. More specifically, the RS frame having the size of (N+2)*235 is divided into 30*235 byte blocks. Then, the divided blocks are mapped to a single group. In other words, the data of a block having the size of 30*235 bytes are processed with one of a 1⁄2-rate encoding process and a 1⁄4-rate encoding process and are, then, inserted in a data group. Thereafter, the data group having corresponding data and place holders inserted in each hierarchical region divided by the group formatter 304 passes through the data deinterleaver 305 and the packet formatter 306 so as to be inputted to the packet multiplexer 240.
FIG. 8 illustrates exemplary operations of a packet multiplexer for transmitting the data group according to the present invention. More specifically, the packet multiplexer 240 multiplexes a field including a data group, in which the mobile service data and main service data are mixed with one another, and a field including only the main service data. Thereafter, the packet multiplexer 240 outputs the multiplexed fields to the data randomizer 251. At this point, in order to transmit the RS frame having the size of 540*235 bytes, 18 data groups should be transmitted. Herein, each data group includes field synchronization data, as shown in FIG. 6A. Therefore, the 18 data groups are transmitted during 18 field sections, and the section during which the 18 data groups are being transmitted corresponds to the burst-on section.
In each field within the burst-on section, a data group including field synchronization data is multiplexed with main service data, which are then outputted. For example, in the embodiment of the present invention, in each field within the burst-on section, a data group having the size of 118 segments is multiplexed with a set of main service data having the size of 194 segments Referring to FIG. 8, during the burst-on section (i.e., during the 18 field sections), a field including 18 data groups is transmitted. Then, during the burst-off section that follows (i.e., during the 12 field sections), a field consisting only of the main service data is transmitted. Subsequently, during a subsequent burst-on section, 18 fields including 18 data groups are transmitted. And, during the following burst-off section, 12 fields consisting only of the main service data are transmitted.
Furthermore, in the present invention, the same type of data service may be provided in the first burst-on section including the first 18 data groups and in the second burst-on section including the next 18 data groups. Alternatively, different types of data service may be provided in each burst-on section. For example, when it is assumed that different data service types are provided to each of the first burst-on section and the second burst-on section, and that the receiving system wishes to receive only one type of data service, the receiving system turns the power on only during the corresponding burst-on section including the desired data service type so as to receive the corresponding 18 data fields. Then, the receiving system turns the power off during the remaining 42 field sections so as to prevent other data service types from being received. Thus, the amount of power consumption of the receiving system may be reduced. In addition, the receiving system according to the present invention is advantageous in that one RS frame may be configured from the 18 data groups that are received during a single burst-on section.
According to the present invention, the number of data groups included in a burst-on section may vary based upon the size of the RS frame, and the size of the RS frame varies in accordance with the value N. More specifically, by adjusting the value N, the number of data groups within the burst section may be adjusted. Herein, in an example of the present invention, the (235,187)-RS encoding process adjusts the value N during a fixed state. Furthermore, the size of the mobile service data that can be inserted in the data group may vary based upon the sizes of the trellis initialization data or known data, the MPEG header, and the RS parity, which are inserted in the corresponding data group.
Meanwhile, since a data group including mobile service data in-between the data bytes of the main service data during the packet multiplexing process, the shifting of the chronological position (or place) of the main service data packet becomes relative. Also, a system object decoder (i.e., MPEG decoder) for processing the main service data of the receiving system, receives and decodes only the main service data and recognizes the mobile service data packet as a null data packet. Therefore, when the system object decoder of the receiving system receives a main service data packet that is multiplexed with the data group, a packet jitter occurs.
At this point, since a multiple-level buffer for the video data exists in the system object decoder and the size of the buffer is relatively large, the packet jitter generated from the packet multiplexer 240 does not cause any serious problem in case of the video data. However, since the size of the buffer for the audio data is relatively small, the packet jitter may cause considerable problem. More specifically, due to the packet jitter, an overflow or underflow may occur in the buffer for the main service data of the receiving system (e.g., the buffer for the audio data). Therefore, the packet jitter mitigator 220 re-adjusts the relative position of the main service data packet so that the overflow or underflow does not occur in the system object decoder.
In the present invention, examples of repositioning places for the audio data packets within the main service data in order to minimize the influence on the operations of the audio buffer will be described in detail. The packet jitter mitigator 220 repositions the audio data packets in the main service data section so that the audio data packets of the main service data can be as equally and uniformly aligned and positioned as possible. The standard for repositioning the audio data packets in the main service data performed by the packet jitter mitigator 220 will now be described. Herein, it is assumed that the packet jitter mitigator 220 knows the same multiplexing information as that of the packet multiplexer 240, which is placed further behind the packet jitter mitigator 220.
Firstly, if one audio data packet exists in the main service data section (e.g., the main service data section positioned between two data groups) within the burst-on section, the audio data packet is positioned at the very beginning of the main service data section. Alternatively, if two audio data packets exist in the corresponding data section, one audio data packet is positioned at the very beginning and the other audio data packet is positioned at the very end of the main service data section. Further, if more than three audio data packets exist, one audio data packet is positioned at the very beginning of the main service data section, another is positioned at the very end of the main service data section, and the remaining audio data packets are equally positioned between the first and last audio data packets. Secondly, during the main service data section placed immediately before the beginning of a burst-on section (i.e., during a burst-off section), the audio data packet is placed at the very end of the corresponding section.
Thirdly, during a main service data section within the burst-off section after the burst-on section, the audio data packet is positioned at the very end of the main service data section. Finally, the data packets other than audio data packets are positioned in accordance with the inputted order in vacant spaces (i.e., spaces that are not designated for the audio data packets). Meanwhile, when the positions of the main service data packets are relatively re-adjusted, associated program clock reference (PCR) values may also be modified accordingly. The PCR value corresponds to a time reference value for synchronizing the time of the MPEG decoder. Herein, the PCR value is inserted in a specific region of a TS packet and then transmitted.
In the example of the present invention, the packet jitter mitigator 220 also performs the operation of modifying the PCR value. The output of the packet jitter mitigator 220 is inputted to the packet multiplexer 240. As described above, the packet multiplexer 240 multiplexes the main service data packet outputted from the packet jitter mitigator 220 with the mobile service data packet outputted from the pre-processor 230 into a burst structure in accordance with a pre-determined multiplexing rule. Then, the packet multiplexer 240 outputs the multiplexed data packets to the data randomizer 251 of the post-processor 250.
If the inputted data correspond to the main service data packet, the data randomizer 251 performs the same randomizing process as that of the conventional randomizer. More specifically, the synchronization byte within the main service data packet is deleted. Then, the remaining 187 data bytes are randomized by using a pseudo random byte generated from the data randomizer 251. Thereafter, the randomized data are outputted to the RS encoder/non-systematic RS encoder 252.
On the other hand, if the inputted data correspond to the mobile service data packet, the data randomizer 251 may randomize only a portion of the data packet. For example, if it is assumed that a randomizing process has already been performed in advance on the mobile service data packet by the pre-processor 230, the data randomizer 251 deletes the synchronization byte from the 4-byte MPEG header included in the mobile service data packet and, then, performs the randomizing process only on the remaining 3 data bytes of the MPEG header. Thereafter, the randomized data bytes are outputted to the RS encoder/non-systematic RS encoder 252. More specifically, the randomizing process is not performed on the remaining portion of the mobile service data excluding the MPEG header. In other words, the remaining portion of the mobile service data packet is directly outputted to the RS encoder/non-systematic RS encoder 252 without being randomized. Also, the data randomizer 251 may or may not perform a randomizing process on the known data (or known data place holders) and the initialization data place holders included in the mobile service data packet.
The RS encoder/non-systematic RS encoder 252 performs an RS encoding process on the data being randomized by the data randomizer 251 or on the data bypassing the data randomizer 251, so as to add 20 bytes of RS parity data. Thereafter, the processed data are outputted to the data interleaver 253. Herein, if the inputted data correspond to the main service data packet, the RS encoder/non-systematic RS encoder 252 performs the same systematic RS encoding process as that of the conventional broadcasting system, thereby adding the 20-byte RS parity data at the end of the 187-byte data. Alternatively, if the inputted data correspond to the mobile service data packet, the RS encoder/non-systematic RS encoder 252 performs a non-systematic RS encoding process. At this point, the 20-byte RS parity data obtained from the non-systematic RS encoding process are inserted in a pre-decided parity byte place within the mobile service data packet.
The data interleaver 253 corresponds to a byte unit convolutional interleaver. The output of the data interleaver 253 is inputted to the parity replacer 254 and to the non-systematic RS encoder 255. Meanwhile, a process of initializing a memory within the trellis encoding module 256 is primarily required in order to decide the output data of the trellis encoding module 256, which is located after the parity replacer 254, as the known data pre-defined according to an agreement between the receiving system and the transmitting system. More specifically, the memory of the trellis encoding module 256 should first be initialized before the received known data sequence is trellis-encoded. At this point, the beginning portion of the known data sequence that is received corresponds to the initialization data place holder and not to the actual known data. Herein, the initialization data place holder has been included in the data by the group formatter within the pre-processor 230 in an earlier process. Therefore, the process of generating initialization data and replacing the initialization data place holder of the corresponding memory with the generated initialization data are required to be performed immediately before the inputted known data sequence is trellis-encoded.
Additionally, a value of the trellis memory initialization data is decided and generated based upon a memory status of the trellis encoding module 256. Further, due to the newly replaced initialization data, a process of newly calculating the RS parity and replacing the RS parity, which is outputted from the data interleaver 253, with the newly calculated RS parity is required. Therefore, the non-systematic RS encoder 255 receives the mobile service data packet including the initialization data place holders, which are to be replaced with the actual initialization data, from the data interleaver 253 and also receives the initialization data from the trellis encoding module 256.
Among the inputted mobile service data packet, the initialization data place holders are replaced with the initialization data, and the RS parity data that are added to the mobile service data packet are removed and processed with non-systematic RS encoding. Thereafter, the new RS parity obtained by performing the non-systematic RS encoding process is outputted to the parity replacer 255. Accordingly, the parity replacer 255 selects the output of the data interleaver 253 as the data within the mobile service data packet, and the parity replacer 255 selects the output of the non-systematic RS encoder 255 as the RS parity. The selected data are then outputted to the trellis encoding module 256.
Meanwhile, if the main service data packet is inputted or if the mobile service data packet, which does not include any initialization data place holders that are to be replaced, is inputted, the parity replacer 254 selects the data and RS parity that are outputted from the data interleaver 253. Then, the parity replacer 254 directly outputs the selected data to the trellis encoding module 256 without any modification. The trellis encoding module 256 converts the byte-unit data to symbol units and performs a 12-way interleaving process so as to trellis-encode the received data. Thereafter, the processed data are outputted to the synchronization multiplexer 260.
The synchronization multiplexer 260 inserts a field synchronization signal and a segment synchronization signal to the data outputted from the trellis encoding module 256 and, then, outputs the processed data to the pilot inserter 271 of the transmission unit 270. Herein, the data having a pilot inserted therein by the pilot inserter 271 are modulated by the modulator 272 in accordance with a pre-determined modulating method (e.g., a VSB method). Thereafter, the modulated data are transmitted to each receiving system though the radio frequency (RF) up-converter 273.
Block Processor
FIG. 9 illustrates a block diagram showing a structure of a block processor according to the present invention. Herein, the block processor includes a byte-bit converter 401, a symbol encoder 402, a symbol interleaver 403, and a symbol-byte converter 404. The byte-bit converter 401 divides the mobile service data bytes that are inputted from the RS frame encoder 112 into bits, which are then outputted to the symbol encoder 402. The byte-bit converter 401 may also receive signaling information including transmission parameters. The signaling information data bytes are also divided into bits so as to be outputted to the symbol encoder 402. Herein, the signaling information including transmission parameters may be processed with the same data processing step as that of the mobile service data. More specifically, the signaling information may be inputted to the block processor 303 by passing through the data randomizer 301 and the RS frame encoder 302. Alternatively, the signaling information may also be directly outputted to the block processor 303 without passing though the data randomizer 301 and the RS frame encoder 302.
The symbol encoder 402 corresponds to a G/H-rate encoder encoding the inputted data from G bits to H bits and outputting the data encoded at the coding rate of G/H. According to the embodiment of the present invention, it is assumed that the symbol encoder 402 performs either a coding rate of 1⁄2 (also referred to as a 1⁄2-rate encoding process) or an encoding process at a coding rate of 1⁄4 (also referred to as a 1⁄4-rate encoding process). The symbol encoder 402 performs one of 1⁄2-rate encoding and 1⁄4-rate encoding on the inputted mobile service data and signaling information. Thereafter, the signaling information is also recognized as the mobile service data and processed accordingly.
In case of performing the 1⁄2-rate coding process, the symbol encoder 402 receives 1 bit and encodes the received 1 bit to 2 bits (i.e., 1 symbol). Then, the symbol encoder 402 outputs the processed 2 bits (or 1 symbol). On the other hand, in case of performing the 1⁄4-rate encoding process, the symbol encoder 402 receives 1 bit and encodes the received 1 bit to 4 bits (i.e., 2 symbols). Then, the symbol encoder 402 outputs the processed 4 bits (or 2 symbols).
FIG. 10 illustrates a detailed block diagram of the symbol encoder 402 shown in FIG. 9. The symbol encoder 402 includes two delay units 501 and 503 and three adders 502, 504, and 505. Herein, the symbol encoder 402 encodes an input data bit U and outputs the coded bit U to 4 bits (u0 to u4). At this point, the data bit U is directly outputted as uppermost bit u0 and simultaneously encoded as lower bit u1u2u3 and then outputted. More specifically, the input data bit U is directly outputted as the uppermost bit u0 and simultaneously outputted to the first and third adders 502 and 505. The first adder 502 adds the input data bit U and the output bit of the first delay unit 501 and, then, outputs the added bit to the second delay unit 503. Then, the data bit delayed by a pre-determined time (e.g., by 1 clock) in the second delay unit 503 is outputted as lower bit u1 and simultaneously fed-back to the first delay unit 501. The first delay unit 501 delays the data bit fed-back from the second delay unit 503 by a pre-determined time (e.g., by 1 clock). Then, the first delay unit 501 outputs the delayed data bit to the first adder 502 and the second adder 504. The second adder 504 adds the data bits outputted from the first and second delay units 501 and 503 as a lower bit u2. The third adder 505 adds the input data bit U and the output of the second delay unit 503 and outputs the added data bit as a lower bit u3.
At this point, if the input data bit U corresponds to data encoded at a 1⁄2-coding rate, the symbol encoder 402 configures a symbol with u1u0 bits from the 4 output bits u0u1u2u3. Then, the symbol encoder 402 outputs the newly configured symbol. Alternatively, if the input data bit U corresponds to data encoded at a 1⁄4-coding rate, the symbol encoder 402 configures and outputs a symbol with bits u1u0 and, then, configures and outputs another symbol with bits u2u3. According to another embodiment of the present invention, if the input data bit U corresponds to data encoded at a 1⁄4-coding rate, the symbol encoder 402 may also configure and output a symbol with bits u1u0, and then repeat the process once again and output the corresponding bits. According to yet another embodiment of the present invention, the symbol encoder outputs all four output bits U u0u1u2u3. Then, when using the 1⁄2-coding rate, the symbol interleaver 403 located behind the symbol encoder 402 selects only the symbol configured of bits u1u0 from the four output bits u0u1u2u3. Alternatively, when using the 1⁄4-coding rate, the symbol interleaver 403 may select the symbol configured of bits u1u0 and then select another symbol configured of bits u2u3. According to another embodiment, when using the 1⁄4-coding rate, the symbol interleaver 403 may repeatedly select the symbol configured of bits u1u0.
The output of the symbol encoder 402 is inputted to the symbol interleaver 403. Then, the symbol interleaver 403 performs block interleaving in symbol units on the data outputted from the symbol encoder 402. Any interleaver performing structural rearrangement (or realignment) may be applied as the symbol interleaver 403 of the block processor. However, in the present invention, a variable length symbol interleaver that can be applied even when a plurality of lengths is provided for the symbol, so that its order may be rearranged, may also be used.
FIG. 11 illustrates a symbol interleaver according to an embodiment of the present invention. Herein, the symbol interleaver according to the embodiment of the present invention corresponds to a variable length symbol interleaver that may be applied even when a plurality of lengths is provided for the symbol, so that its order may be rearranged. Particularly, FIG. 11 illustrates an example of the symbol interleaver when K=6 and L=8. Herein, K indicates a number of symbols that are outputted for symbol interleaving from the symbol encoder 402. And, L represents a number of symbols that are actually interleaved by the symbol interleaver 403.
In the present invention, the symbol intereleaver 403 should satisfy the conditions of T=2′′ (wherein n is an integer) and of L≧K. If there is a difference in value between K and L, (L−K) number of null (or dummy) symbols is added, thereby creating an interleaving pattern. Therefore, K becomes a block size of the actual symbols that are inputted to the symbol interleaver 403 in order to be interleaved. L becomes an interleaving unit when the interleaving process is performed by an interleaving pattern created from the symbol interleaver 403. The example of what is described above is illustrated in FIG. 11.
More specifically, FIG. 11(a) to FIG. 11(c) illustrate a variable length interleaving process of a symbol interleaver shown in FIG. 9. The number of symbols outputted from the symbol encoder 402 in order to be interleaved is equal to 6 (i.e., K=6). In other words, 6 symbols are outputted from the symbol encoder 402 in order to be interleaved. And, the actual interleaving unit (L) is equal to 8 symbols. Therefore, as shown in FIG. 11(a), 2 symbols are added to the null (or dummy) symbol, thereby creating the interleaving pattern. Equation 2 shown below described the process of sequentially receiving K number of symbols, the order of which is to be rearranged, and obtaining an L value satisfying the conditions of L=2′′ (wherein n is an integer) and of L≧K, thereby creating the interleaving so as to realign (or rearrange) the symbol order.
In relation to all places, wherein 0≦i≦L−1,

P(i)={S×i×(i+1)/2} mod L  Equation 2

Herein, L≧K, L=2′′, and n and S are integers. Referring to FIG. 11, it is assumed that S is equal to 89, and that L is equal to 8, and FIG. 11 illustrates the created interleaving pattern and an example of the interleaving process. As shown in FIG. 11(b), the order of K number of input symbols and (L−K) number of null symbols is rearranged by using the above-mentioned Equation 2. Then, as shown in FIG. 11(c), the null byte places are removed, so as to rearrange the order, by using Equation 3 shown below. Thereafter, the symbol that is interleaved by the rearranged order is then outputted to the symbol-byte converter.

if P(i)>K−1, then P(i) place is removed and rearranged  Equation 3

Subsequently, the symbol-byte converter 404 converts to bytes the mobile service data symbols, having the rearranging of the symbol order completed and then outputted in accordance with the rearranged order, and thereafter outputs the converted bytes to the group formatter 304.
FIG. 12A illustrates a block diagram showing the structure of a block processor according to another embodiment of the present invention. Herein, the block processor includes an interleaving unit 610 and a block formatter 620. The interleaving unit 610 may include a byte-symbol converter 611, a symbol-byte converter 612, a symbol interleaver 613, and a symbol-byte converter 614. Herein, the symbol interleaver 613 may also be referred to as a block interleaver.
The byte-symbol converter 611 of the interleaving unit 610 converts the mobile service data X outputted in byte units from the RS frame encoder 302 to symbol units. Then, the byte-symbol converter 611 outputs the converted mobile service data symbols to the symbol-byte converter 612 and the symbol interleaver 613. More specifically, the byte-symbol converter 611 converts each 2 bits of the inputted mobile service data byte (=8 bits) to 1 symbol and outputs the converted symbols. This is because the input data of the trellis encoding module 256 consist of symbol units configured of 2 bits. The relationship between the block processor 303 and the trellis encoding module 256 will be described in detail in a later process. At this point, the byte-symbol converter 611 may also receive signaling information including transmission parameters. Furthermore, the signaling information bytes may also be divided into symbol units and then outputted to the symbol-byte converter 612 and the symbol interleaver 613.
The symbol-byte converter 612 groups 4 symbols outputted from the byte-symbol converter 611 so as to configure a byte. Thereafter, the converted data bytes are outputted to the block formatter 620. Herein, each of the symbol-byte converter 612 and the byte-symbol converter 611 respectively performs an inverse process on one another. Therefore, the yield of these two blocks is offset. Accordingly, as shown in FIG. 12B, the input data X bypass the byte-symbol converter 611 and the symbol-byte converter 612 and are directly inputted to the block formatter 620. More specifically, the interleaving unit 610 of FIG. 12B has a structure equivalent to that of the interleaving unit shown in FIG. 12A. Therefore, the same reference numerals will be used in FIG. 12A and FIG. 12B.
The symbol interleaver 613 performs block interleaving in symbol units on the data that are outputted from the byte-symbol converter 611. Subsequently, the symbol interleaver 613 outputs the interleaved data to the symbol-byte converter 614. Herein, any type of interleaver that can rearrange the structural order may be used as the symbol interleaver 613 of the present invention. In the example given in the present invention, a variable length interleaver that may be applied for symbols having a wide range of lengths, the order of which is to be rearranged. For example, the symbol interleaver of FIG. 11 may also be used in the block processor shown in FIG. 12A and FIG. 12B.
The symbol-byte converter 614 outputs the symbols having the rearranging of the symbol order completed, in accordance with the rearranged order. Thereafter, the symbols are grouped to be configured in byte units, which are then outputted to the block formatter 620. More specifically, the symbol-byte converter 614 groups 4 symbols outputted from the symbol interleaver 613 so as to configure a data byte. As shown in FIG. 13, the block formatter 620 performs the process of aligning the output of each symbol-byte converter 612 and 614 within the block in accordance with a set standard. Herein, the block formatter 620 operates in association with the trellis encoding module 256.
More specifically, the block formatter 620 decides the output order of the mobile service data outputted from each symbol-byte converter 612 and 614 while taking into consideration the place (or order) of the data excluding the mobile service data that are being inputted, wherein the mobile service data include main service data, known data, RS parity data, and MPEG header data.
According to the embodiment of the present invention, the trellis encoding module 256 is provided with 12 trellis encoders. FIG. 14 illustrates a block diagram showing the trellis encoding module 256 according to the present invention. In the example shown in FIG. 14, 12 identical trellis encoders are combined to the interleaver in order to disperse noise. Herein, each trellis encoder may be provided with a pre-coder.
FIG. 15A illustrates the block processor 303 being concatenated with the trellis encoding module 256. In the transmitting system, a plurality of blocks actually exists between the pre-processor 230 including the block processor 303 and the trellis encoding module 256, as shown in FIG. 3. Conversely, the receiving system considers the pre-processor 230 to be concatenated with the trellis encoding module 256, thereby performing the decoding process accordingly. However, the data excluding the mobile service data that are being inputted to the trellis encoding module 256, wherein the mobile service data include main service data, known data, RS parity data, and MPEG header data, correspond to data that are added to the blocks existing between the block processor 303 and the trellis encoding module 256. FIG. 15B illustrates an example of a data processor 650 being positioned between the block processor 303 and the trellis encoding module 256, while taking the above-described instance into consideration.
Herein, when the interleaving unit 610 of the block processor 303 performs a 1⁄2-rate encoding process, the interleaving unit 610 may be configured as shown in FIG. 12A (or FIG. 12B). Referring to FIG. 3, for example, the data processor 650 may include a group formatter 304, a data deinterleaver 305, a packet formatter 306, a packet multiplexer 240, and a post-processor 250, wherein the post-processor 250 includes a data randomizer 251, a RS encoder/non-systematic RS encoder 252, a data interleaver 253, a parity replacer 254, and a non-systematic RS encoder 255.
At this point, the trellis encoding module 256 symbolizes the data that are being inputted so as to divide the symbolized data and to send the divided data to each trellis encoder in accordance with a pre-defined method. Herein, one byte is converted into 4 symbols, each being configured of 2 bits. Also, the symbols created from the single data byte are all transmitted to the same trellis encoder. Accordingly, each trellis encoder pre-codes an upper bit of the input symbol, which is then outputted as the uppermost output bit C2. Alternatively, each trellis encoder trellis-encodes a lower bit of the input symbol, which is then outputted as two output bits C1 and C0. The block formatter 620 is controlled so that the data byte outputted from each symbol-byte converter can be transmitted to different trellis encoders.
Hereinafter, the operation of the block formatter 620 will now be described in detail with reference to FIG. 9 to FIG. 12. Referring to FIG. 12A, for example, the data byte outputted from the symbol-byte converter 612 and the data byte outputted from the symbol-byte converter 614 are inputted to different trellis encoders of the trellis encoding module 256 in accordance with the control of the block formatter 620. Hereinafter, the data byte outputted from the symbol-byte converter 612 will be referred to as X, and the data byte outputted from the symbol-byte converter 614 will be referred to as Y, for simplicity. Referring to FIG. 13(a), each number (i.e., 0 to 11) indicates the first to twelfth trellis encoders of the trellis encoding module 256, respectively.
In addition, the output order of both symbol-byte converters are arranged (or aligned) so that the data bytes outputted from the symbol-byte converter 612 are respectively inputted to the 0th to 5th trellis encoders (0 to 5) of the trellis encoding module 256, and that the data bytes outputted from the symbol-byte converter 614 are respectively inputted to the 6th to 11th trellis encoders (6 to 11) of the trellis encoding module 256. Herein, the trellis encoders having the data bytes outputted from the symbol-byte converter 612 allocated therein, and the trellis encoders having the data bytes outputted from the symbol-byte converter 614 allocated therein are merely examples given to simplify the understanding of the present invention. Furthermore, according to an embodiment of the present invention, and assuming that the input data of the block processor 303 correspond to a block configured of 12 bytes, the symbol-byte converter 612 outputs 12 data bytes from X0 to X11, and the symbol-byte converter 614 outputs 12 data bytes from Y0 to Y11.
FIG. 13(b) illustrates an example of data being inputted to the trellis encoding module 256. Particularly, FIG. 13(b) illustrates an example of not only the mobile service data but also the main service data and RS parity data being inputted to the trellis encoding module 256, so as to be distributed to each trellis encoder. More specifically, the mobile service data outputted from the block processor 303 pass through the group formatter 304, from which the mobile service data are mixed with the main service data and RS parity data and then outputted, as shown in FIG. 13(a). Accordingly, each data byte is respectively inputted to the 12 trellis encoders in accordance with the positions (or places) within the data group after being data-interleaved.
Herein, when the output data bytes X and Y of the symbol-byte converters 612 and 614 are allocated to each respective trellis encoder, the input of each trellis encoder may be configured as shown in FIG. 13(b). More specifically, referring to FIG. 13(b), the six mobile service data bytes (X0 to X5) outputted from the symbol-byte converter 612 are sequentially allocated (or distributed) to the first to sixth trellis encoders (0 to 5) of the trellis encoding module 256. Also, the 2 mobile service data bytes Y0 and Y1 outputted from the symbol-byte converter 614 are sequentially allocated to the 7th and 8th trellis encoders (6 and 7) of the trellis encoding module 256. Thereafter, among the 5 main service data bytes, 4 data bytes are sequentially allocated to the 9th and 12th trellis encoders (8 to 11) of the trellis encoding module 256. Finally, the remaining 1 byte of the main service data byte is allocated once again to the first trellis encoder (0).
It is assumed that the mobile service data, the main service data, and the RS parity data are allocated to each trellis encoder, as shown in FIG. 13(b). It is also assumed that, as described above, the input of the block processor 303 is configured of 12 bytes, and that 12 bytes from X0 to X11 are outputted from the symbol-byte converter 612, and that 12 bytes from Y0 to Y11 are outputted from the symbol-byte converter 614. In this case, as shown in FIG. 13(c), the block formatter 620 arranges the data bytes that are to be outputted from the symbol-byte converters 612 and 614 by the order of X0 to X5, Y0, Y1, X6 to X10, Y2 to Y7, X1, and Y8 to Y11. More specifically, the trellis encoder that is to perform the encoding process is decided based upon the position (or place) within the transmission frame in which each data byte is inserted. At this point, not only the mobile service data but also the main service data, the MPEG header data, and the RS parity data are also inputted to the trellis encoding module 256. Herein, it is assumed that, in order to perform the above-described operation, the block formatter 620 is informed of (or knows) the information on the data group format after the data-interleaving process.
FIG. 16 illustrates a block diagram of the block processor performing an encoding process at a coding rate of 1/N according to an embodiment of the present invention. Herein, the block processor includes (N−1) number of symbol interleavers 741 to 74N−1, which are configured in a parallel structure. More specifically, the block processor having the coding rate of 1/N consists of a total of N number of branches (or paths) including a branch (or path), which is directly transmitted to the block formatter 730. In addition, the symbol interleaver 741 to 74N−1 of each branch may each be configured of a different symbol interleaver. Furthermore, (N−1) number of symbol-byte converter 751 to 75N−1 each corresponding to each (N−1) number of symbol interleavers 741 to 74N−1 may be included at the end of each symbol interleaver, respectively. Herein, the output data of the (N−1) number of symbol-byte converter 751 to 75N−1 are also inputted to the block formatter 730.
In the example of the present invention, N is equal to or smaller than 12. If N is equal to 12, the block formatter 730 may align the output data so that the output byte of the 12 symbol-byte converter 75N−1 is inputted to the 12th trellis encoder. Alternatively, if N is equal to 3, the block formatter 730 may arranged the output order, so that the data bytes outputted from the symbol-byte converter 720 are inputted to the 1st to 4th trellis encoders of the trellis encoding module 256, and that the data bytes outputted from the symbol-byte converter 751 are inputted to the 5th to 8th trellis encoders, and that the data bytes outputted from the symbol-byte converter 752 are inputted to the 9th to 12th trellis encoders. At this point, the order of the data bytes outputted from each symbol-byte converter may vary in accordance with the position within the data group of the data other than the mobile service data, which are mixed with the mobile service data that are outputted from each symbol-byte converter.
FIG. 17 illustrates a detailed block diagram showing the structure of a block processor according to another embodiment of the present invention. Herein, the block formatter is removed from the block processor so that the operation of the block formatter may be performed by a group formatter. More specifically, the block processor of FIG. 17 may include a byte-symbol converter 810, symbol-byte converters 820 and 840, and a symbol interleaver 830. In this case, the output of each symbol-byte converter 820 and 840 is inputted to the group formatter 850.
Also, the block processor may obtain a desired coding rate by adding symbol interleavers and symbol-byte converters. If the system designer wishes a coding rate of 1/N, the block processor needs to be provided with a total of N number of branches (or paths) including a branch (or path), which is directly transmitted to the block formatter 850, and (N−1) number of symbol interleavers and symbol-byte converters configured in a parallel structure with (N−1) number of branches. At this point, the group formatter 850 inserts place holders ensuring the positions (or places) for the MPEG header, the non-systematic RS parity, and the main service data. And, at the same time, the group formatter 850 positions the data bytes outputted from each branch of the block processor.
The number of trellis encoders, the number of symbol-byte converters, and the number of symbol interleavers proposed in the present invention are merely exemplary. And, therefore, the corresponding numbers do not limit the spirit or scope of the present invention. It is apparent to those skilled in the art that the type and position of each data byte being allocated to each trellis encoder of the trellis encoding module 256 may vary in accordance with the data group format. Therefore, the present invention should not be understood merely by the examples given in the description set forth herein. The mobile service data that are encoded at a coding rate of 1/N and outputted from the block processor 303 are inputted to the group formatter 304. Herein, in the example of the present invention, the order of the output data outputted from the block formatter of the block processor 303 are aligned and outputted in accordance with the position of the data bytes within the data group.
Signaling Information Processing
The transmitter 200 according to the present invention may insert transmission parameters by using a plurality of methods and in a plurality of positions (or places), which are then transmitted to the receiving system. For simplicity, the definition of a transmission parameter that is to be transmitted from the transmitter to the receiving system will now be described. The transmission parameter includes data group information, region information within a data group, the number of RS frames configuring a super frame (i.e., a super frame size (SFS)), the number of RS parity data bytes (P) for each column within the RS frame, whether or not a checksum, which is added to determine the presence of an error in a row direction within the RS frame, has been used, the type and size of the checksum if the checksum is used (presently, 2 bytes are added to the CRC), the number of data groups configuring one RS frame—since the RS frame is transmitted to one burst section, the number of data groups configuring the one RS frame is identical to the number of data groups within one burst (i.e., burst size (BS)), a turbo code mode, and a RS code mode.
Also, the transmission parameter required for receiving a burst includes a burst period—herein, one burst period corresponds to a value obtained by counting the number of fields starting from the beginning of a current burst until the beginning of a next burst, a positioning order of the RS frames that are currently being transmitted within a super frame (i.e., a permuted frame index (PFI)) or a positioning order of groups that are currently being transmitted within a RS frame (burst) (i.e., a group index (GI)), and a burst size. Depending upon the method of managing a burst, the transmission parameter also includes the number of fields remaining until the beginning of the next burst (i.e., time to next burst (TNB)). And, by transmitting such information as the transmission parameter, each data group being transmitted to the receiving system may indicate a relative distance (or number of fields) between a current position and the beginning of a next burst.
The information included in the transmission parameter corresponds to examples given to facilitate the understanding of the present invention. Therefore, the proposed examples do not limit the scope or spirit of the present invention and may be easily varied or modified by anyone skilled in the art. According to the first embodiment of the present invention, the transmission parameter may be inserted by allocating a predetermined region of the mobile service data packet or the data group. In this case, the receiving system performs synchronization and equalization on a received signal, which is then decoded by symbol units. Thereafter, the packet deformatter may separate the mobile service data and the transmission parameter so as to detect the transmission parameter. According to the first embodiment, the transmission parameter may be inserted from the group formatter 304 and then transmitted.
According to the second embodiment of the present invention, the transmission parameter may be multiplexed with another type of data. For example, when known data are multiplexed with the mobile service data, a transmission parameter may be inserted, instead of the known data, in a place (or position) where a known data byte is to be inserted. Alternatively, the transmission parameter may be mixed with the known data and then inserted in the place where the known data byte is to be inserted. According to the second embodiment, the transmission parameter may be inserted from the group formatter 304 or from the packet formatter 306 and then transmitted.
According to a third embodiment of the present invention, the transmission parameter may be inserted by allocating a portion of a reserved region within a field synchronization segment of a transmission frame. In this case, since the receiving system may perform decoding on a receiving signal by symbol units before detecting the transmission parameter, the transmission parameter having information on the processing methods of the block processor 303 and the group formatter 304 may be inserted in a reserved field of a field synchronization signal. More specifically, the receiving system obtains field synchronization by using a field synchronization segment so as to detect the transmission parameter from a pre-decided position. According to the third embodiment, the transmission parameter may be inserted from the synchronization multiplexer 240 and then transmitted.
According to the fourth embodiment of the present invention, the transmission parameter may be inserted in a layer (or hierarchical region) higher than a transport stream (TS) packet. In this case, the receiving system should be able to receive a signal and process the received signal to a layer higher than the TS packet in advance. At this point, the transmission parameter may be used to certify the transmission parameter of a currently received signal and to provide the transmission parameter of a signal that is to be received in a later process.
In the present invention, the variety of transmission parameters associated with the transmission signal may be inserted and transmitted by using the above-described methods according to the first to fourth embodiment of the present invention. At this point, the transmission parameter may be inserted and transmitted by using only one of the four embodiments described above, or by using a selection of the above-described embodiments, or by using all of the above-described embodiments. Furthermore, the information included in the transmission parameter may be duplicated and inserted in each embodiment. Alternatively, only the required information may be inserted in the corresponding position of the corresponding embodiment and then transmitted. Furthermore, in order to ensure robustness of the transmission parameter, a block encoding process of a short cycle (or period) may be performed on the transmission parameter and, then, inserted in a corresponding region. The method for performing a short-period block encoding process on the transmission parameter may include, for example, Kerdock encoding, BCH encoding, RS encoding, and repetition encoding of the transmission parameter. Also, a combination of a plurality of block encoding methods may also be performed on the transmission parameter.
The transmission parameters may be grouped to create a block code of a small size, so as to be inserted in a byte place allocated within the data group for signaling and then transmitted. However, in this case, the block code passes through the block decoded from the receiving end so as to obtain a transmission parameter value. Therefore, the transmission parameters of the turbo code mode and the RS code mode, which are required for block decoding, should first be obtained. Accordingly, the transmission parameters associated with a particular mode may be inserted in a specific section of a known data region. And, in this case, a correlation of with a symbol may be used for a faster decoding process. The receiving system refers to the correlation between each sequence and the currently received sequences, thereby determining the encoding mode and the combination mode.
Meanwhile, when the transmission parameter is inserted in the field synchronization segment region or the known data region and then transmitted, and when the transmission parameter has passed through the transmission channel, the reliability of the transmission parameter is deteriorated. Therefore, one of a plurality of pre-defined patterns may also be inserted in accordance with the corresponding transmission parameter. Herein, the receiving system performs a correlation calculation between the received signal and the pre-defined patterns so as to recognize the transmission parameter. For example, it is assumed that a burst including 5 data groups is pre-decided as pattern A based upon an agreement between the transmitting system and the receiving system. In this case, the transmitting system inserts and transmits pattern A, when the number of groups within the burst is equal to 5. Thereafter, the receiving system calculates a correlation between the received data and a plurality of reference patterns including pattern A, which was created in advance. At this point, if the correlation value between the received data and pattern A is the greatest, the received data indicates the corresponding parameter, and most particularly, the number of groups within the burst. At this point, the number of groups may be acknowledged as 5. Hereinafter, the process of inserting and transmitting the transmission parameter will now be described according to first, second, and third embodiments of the present invention.
First Embodiment
FIG. 18 illustrates a schematic diagram of the group formatter 304 receiving the transmission parameter and inserting the received transmission parameter in region A of the data group according to the present invention. Herein, the group formatter 304 receives mobile service data from the block processor 303. Conversely, the transmission parameter is processed with at least one of a data randomizing process, a RS frame encoding process, and a block processing process, and may then be inputted to the group formatter 304. Alternatively, the transmission parameter may be directly inputted to the group formatter 304 without being processed with any of the above-mentioned processes. In addition, the transmission parameter may be provided from the service multiplexer 100. Alternatively, the transmission parameter may also be generated and provided from within the transmitter 200. The transmission parameter may also include information required by the receiving system in order to receive and process the data included in the data group. For example, the transmission parameter may include data group information, and multiplexing information.
The group formatter 304 inserts the mobile service data and transmission parameter which are to be inputted to corresponding regions within the data group in accordance with a rule for configuring a data group. For example, the transmission parameter passes through a block encoding process of a short period and is, then, inserted in region A of the data group. Particularly, the transmission parameter may be inserted in a pre-arranged and arbitrary position (or place) within region A. If it is assumed that the transmission parameter has been block encoded by the block processor 303, the block processor 303 performs the same data processing operation as the mobile service data, more specifically, either a 1⁄2-rate encoding or 1⁄4-rate encoding process on the signaling information including the transmission parameter. Thereafter, the block processor 303 outputs the processed transmission parameter to the group formatter 304. Thereafter, the signaling information is also recognized as the mobile service data and processed accordingly.
FIG. 19 illustrates a block diagram showing an example of the block processor receiving the transmission parameter and processing the received transmission parameter with the same process as the mobile service data. Particularly, FIG. 19 illustrates an example showing the structure of FIG. 9 further including a signaling information provider 411 and multiplexer 412. More specifically, the signaling information provider 411 outputs the signaling information including the transmission parameter to the multiplexer 412. The multiplexer 412 multiplexes the signaling information and the output of the RS frame encoder 302. Then, the multiplexer 412 outputs the multiplexed data to the byte-bit converter 401.
The byte-bit converter 401 divides the mobile service data bytes or signaling information byte outputted from the multiplexer 412 into bits, which are then outputted to the symbol encoder 402. The subsequent operations are identical to those described in FIG. 9. Therefore, a detailed description of the same will be omitted for simplicity. If any of the detailed structures of the block processor 303 shown in FIG. 12, FIG. 15, FIG. 16, and FIG. 17, the signaling information provider 411 and the multiplexer 412 may be provided behind the byte-symbol converter.
Second Embodiment
Meanwhile, when known data generated from the group formatter in accordance with a pre-decided rule are inserted in a corresponding region within the data group, a transmission parameter may be inserted in at least a portion of a region, where known data may be inserted, instead of the known data. For example, when a long known data sequence is inserted at the beginning of region A within the data group, a transmission parameter may be inserted in at least a portion of the beginning of region A instead of the known data. A portion of the known data sequence that is inserted in the remaining portion of region A, excluding the portion in which the transmission parameter is inserted, may be used to detect a starting point of the data group by the receiving system. Alternatively, another portion of region A may be used for channel equalization by the receiving system.
In addition, when the transmission parameter is inserted in the known data region instead of the actual known data. The transmission parameter may be block encoded in short periods and then inserted. Also, as described above, the transmission parameter may also be inserted based upon a pre-defined pattern in accordance with the transmission parameter. If the group formatter 304 inserts known data place holders in a region within the data group, wherein known data may be inserted, instead of the actual known data, the transmission parameter may be inserted by the packet formatter 306. More specifically, when the group formatter 304 inserts the known data place holders, the packet formatter 306 may insert the known data instead of the known data place holders. Alternatively, when the group formatter 304 inserts the known data, the known data may be directly outputted without modification.
FIG. 20 illustrates a block diagram showing the structure of a packet formatter 306 being expanded so that the packet formatter 306 can insert the transmission parameter according to an embodiment of the present invention. More specifically, the structure of the packet formatter 306 further includes a known data generator 351 and a signaling multiplexer 352. Herein, the transmission parameter that is inputted to the signaling multiplexer 352 may include information on the length of a current burst, information indicating a starting point of a next burst, positions in which the groups within the burst exist and the lengths of the groups, information on the time from the current group and the next group within the burst, and information on known data.
The signaling multiplexer 352 selects one of the transmission parameter and the known data generated from the known data generator 351 and, then, outputs the selected data to the packet formatter 306. The packet formatter 306 inserts the known data or transmission parameter outputted from the signaling multiplexer 352 into the known data place holders outputted from the data interleaver 305. Then, the packet formatter 306 outputs the processed data. More specifically, the packet formatter 306 inserts a transmission parameter in at least a portion of the known data region instead of the known data, which is then outputted. For example, when a known data place holder is inserted at a beginning portion of region A within the data group, a transmission parameter may be inserted in a portion of the known data place holder instead of the actual known data.
Also, when the transmission parameter is inserted in the known data place holder instead of the known data, the transmission parameter may be block encoded in short periods and inserted. Alternatively, a pre-defined pattern may be inserted in accordance with the transmission parameter. More specifically, the signaling multiplexer 352 multiplexes the known data and the transmission parameter (or the pattern defined by the transmission parameter) so as to configure a new known data sequence. Then, the signaling multiplexer 352 outputs the newly configured known data sequence to the packet formatter 306. The packet formatter 306 deletes the main service data place holder and RS parity place holder from the output of the data interleaver 305, and creates a mobile service data packet of 188 bytes by using the mobile service data, MPEG header, and the output of the signaling multiplexer. Then, the packet formatter 306 outputs the newly created mobile service data packet to the packet multiplexer 240.
In this case, the region A of each data group has a different known data pattern. Therefore, the receiving system separates only the symbol in a pre-arranged section of the known data sequence and recognizes the separated symbol as the transmission parameter. Herein, depending upon the design of the transmitting system, the known data may be inserted in different blocks, such as the packet formatter 306, the group formatter 304, or the block processor 303. Therefore, a transmission parameter may be inserted instead of the known data in the block wherein the known data are to be inserted.
According to the second embodiment of the present invention, a transmission parameter including information on the processing method of the block processor 303 may be inserted in a portion of the known data region and then transmitted. In this case, a symbol processing method and position of the symbol for the actual transmission parameter symbol are already decided. Also, the position of the transmission parameter symbol should be positioned so as to be transmitted or received earlier than any other data symbols that are to be decoded. Accordingly, the receiving system may detect the transmission symbol before the data symbol decoding process, so as to use the detected transmission symbol for the decoding process.
Third Embodiment
Meanwhile, the transmission parameter may also be inserted in the field synchronization segment region and then transmitted. FIG. 21 illustrates a block diagram showing the synchronization multiplexer being expanded in order to allow the transmission parameter to be inserted in the field synchronization segment region. Herein, a signaling multiplexer 261 is further included in the synchronization multiplexer 260. The transmission parameter of the general VSB method is configured of 2 fields. More specifically, each field is configured of one field synchronization segment and 312 data segments. Herein, the first 4 symbols of a data segment correspond to the segment synchronization portion, and the first data segment of each field corresponds to the field synchronization portion.
One field synchronization signal is configured to have the length of one data segment. The data segment synchronization pattern exists in the first 4 symbols, which are then followed by pseudo random sequences PN 511, PN 63, PN 63, and PN 63. The next 24 symbols include information associated with the VSB mode. Additionally, the 24 symbols that include information associated with the VSB mode are followed by the remaining 104 symbols, which are reserved symbols. Herein, the last 12 symbols of a previous segment are copied and positioned as the last 12 symbols in the reserved region. In other words, only the 92 symbols in the field synchronization segment are the symbols that correspond to the actual reserved region.
Therefore, the signaling multiplexer 261 multiplexes the transmission parameter with an already-existing field synchronization segment symbol, so that the transmission parameter can be inserted in the reserved region of the field synchronization segment. Then, the signaling multiplexer 261 outputs the multiplexed transmission parameter to the synchronization multiplexer 260. The synchronization multiplexer 260 multiplexes the segment synchronization symbol, the data symbols, and the new field synchronization segment outputted from the signaling multiplexer 261, thereby configuring a new transmission frame. The transmission frame including the field synchronization segment, wherein the transmission parameter is inserted, is outputted to the transmission unit 270. At this point, the reserved region within the field synchronization segment for inserting the transmission parameter may correspond to a portion of or the entire 92 symbols of the reserved region. Herein, the transmission parameter being inserted in the reserved region may, for example, include information identifying the transmission parameter as the main service data, the mobile service data, or a different type of mobile service data.
If the information on the processing method of the block processor 303 is transmitted as a portion of the transmission parameter, and when the receiving system wishes to perform a decoding process corresponding to the block processor 303, the receiving system should be informed of such information on the block processing method in order to perform the decoding process. Therefore, the information on the processing method of the block processor 303 should already be known prior to the block decoding process. Accordingly, as described in the third embodiment of the present invention, when the transmission parameter having the information on the processing method of the block processor 303 (and/or the group formatter 304) is inserted in the reserved region of the field synchronization signal and then transmitted, the receiving system is capable of detecting the transmission parameter prior to performing the block decoding process on the received signal.
Receiving System
FIG. 22 illustrates a block diagram showing a structure of a digital broadcast receiving system according to the present invention. The digital broadcast receiving system of FIG. 22 uses known data information, which is inserted in the mobile service data section and, then, transmitted by the transmitting system, so as to perform carrier synchronization recovery, frame synchronization recovery, and channel equalization, thereby enhancing the receiving performance. Referring to FIG. 22, the digital broadcast receiving system may include a tuner 901, a demodulator 902, an equalizer 903, a known data detector 904, a block decoder 905, a data deformatter 906, a RS frame decoder 907, a derandomizer 908, a data deinterleaver 909, a RS decoder 910, and a data derandomizer 911. Herein, for simplicity of the description of the present invention, the data deformatter 906, the RS frame decoder 907, and the derandomizer 908 will be collectively referred to as a mobile service data processing unit. And, the data deinterleaver 909, the RS decoder 910, and the data derandomizer 911 will be collectively referred to as a main service data processing unit.
More specifically, the tuner 901 tunes a frequency of a particular channel and down-converts the tuned frequency to an intermediate frequency (IF) signal. Then, the tuner 901 outputs the down-converted IF signal to the demodulator 902 and the known data detector 904. The demodulator 902 performs self gain control, carrier recovery, and timing recovery processes on the inputted IF signal, thereby modifying the IF signal to a baseband signal. Then, the demodulator 902 outputs the newly created baseband signal to the equalizer 903 and the known data detector 904. The equalizer 903 compensates the distortion of the channel included in the demodulated signal and then outputs the error-compensated signal to the block decoder 905.
At this point, the known data detector 904 detects the known sequence position inserted by the transmitting end from the input/output data of the demodulator 902 (i.e., the data prior to the demodulation process or the data after the demodulation process). Thereafter, the known data detector 904 outputs the detected known sequence position indicator along with the known data generated from the detected known sequence position to the demodulator 902 and the equalizer 903. Herein, the equalizer 903 may also receive only the known sequence position indicators having the same pattern. Also, the known data detector 904 outputs a set of information to the block decoder 905. This set of information is used to allow the block decoder 905 of the receiving system to identify the mobile service data that are processed with additional encoding from the transmitting system and the main service data that are not processed with additional encoding.
In addition, although the connection status is not shown in FIG. 22, the information detected from the known data detector 904 may be used throughout the entire receiving system and may also be used in the data deformatter 906 and the RS frame decoder 907. The demodulator 902 uses the known sequence position indicator and the known data during the timing and/or carrier recovery, thereby enhancing the demodulating performance. Similarly, the equalizer 903 uses the known sequence position indicator and the known data so as to enhance the equalizing performance. Moreover, the decoding result of the block decoder 905 may be fed-back to the equalizer 903, thereby enhancing the equalizing performance. The equalizer 903 may perform channel equalization by using a plurality of methods. In the description of the present invention, the channel equalizing process will be described according to a plurality of embodiments. At this point, the transmitting system may periodically insert and transmit known data within a transmission frame, as shown in FIG. 6A.
FIG. 23 illustrates an example of known data sequence being periodically inserted and transmitted in-between actual data by the transmitting system. Referring to FIG. 23, D represents the number of known data symbols, and E represents the number of general data symbols. Therefore, D number of known data symbols are inserted and transmitted at a period of (D+E) symbols. Herein, E may correspond to data that are not known data, such as mobile service data, main service data, or a combination of mobile service data and main service data. In order to be differentiated from the known data, data corresponding to E will hereinafter be referred to as “general data”.
Referring to FIG. 23, known data sequence having the same pattern are included in each known data section that is being periodically inserted. Herein, the length of the known data sequence having identical data patterns may be either equal to or different from the length of the entire (or total) known data sequence of the corresponding known data section (or block) If the two lengths are different from one another, the length of the entire known data sequence is longer than the length of the known data sequence having identical data patterns. In this case, the same known data sequences are included in the entire known data sequence. For example, if a known data pattern F is inserted for channel equalizing, each known data section includes at least one known data pattern F.
Accordingly, when the known data are regularly inserted in the general data as described above, the channel equalizer included in the digital broadcast receiving system may use the inserted known data as training sequences, which may be used either for an accurate decision value or for estimating an impulse response of a channel. Meanwhile, when the known data having the same patterns are regularly inserted, each known data section (or block or interval) may be used as a guard interval in the channel equalizer according to the present invention. The guard interval prevents interference that occurs between blocks due to a multiple path channel. This is because the known data of the known data section located behind the data block corresponding to the (D+E) symbol may be considered as being copied in front of the data block corresponding to the (D+E) symbol, as shown in FIG. 23.
The above-described structure is referred to as a cyclic prefix. This structure provides circular convolution in a time domain between a data block transmitted from the transmitting system and a channel impulse response. Accordingly, this facilitates the channel equalizer of the receiving system to perform channel equalization in a frequency domain by using a fast fourier transform (FFT) and an inverse fast fourier transform (IFFT). More specifically, when viewed in the frequency domain, the data block received by the receiving system is expressed as a multiplication of the data block and the channel impulse response. Therefore, when performing the channel equalization, by multiplying the inverse of the channel in the frequency domain, the channel equalization may be performed more easily.
FIG. 24 and FIG. 25 illustrate examples of the known data section acting as a guard section in a multiple path channel environment, thereby preventing interference in adjacent (or neighboring) blocks. Referring to FIG. 24 and FIG. 25, the path having the largest amount of energy will be referred to as a main path for simplicity. Herein, as shown in FIG. 24(a), a ghost being received after the main path is defined as a post-ghost. Alternatively, as shown in FIG. 25(a), a ghost being received before the main path is defined as a pre-ghost. Referring to the drawings, assuming that both the post-ghost and the pre-ghost exist, the FFT block which corresponds to a section performing FFT operations is set to have a guard section located both in front of and behind the general data. Herein, the known data located in front of the general data within the FFT block is referred to as D2, and the known data located behind the general data within the FFT block is referred to as D1.
FIG. 24 illustrates correlations between a main signal and a ghost signal when a post-ghost exists. More specifically, FIG. 24(b) illustrates an example of a main signal, and FIG. 24(c) illustrates an example of the post-ghost signal. Referring to FIG. 24, when a time difference between the main signal and a ghost is t0, and when t0 is smaller than D2, the known data pattern that is regularly transmitted is identical. Therefore, signal B which is added to the main signal within the FFT block by the ghost corresponds to the same data as the end portion A of the main signal. More specifically, since a signal having a circularly shifted data block is added to the current data block of the main signal within the FFT block, interference from an adjacent data block may be prevented. In other words, the effect (or influence) of the ghost is shown in a circular convolution form within the time domain of the main signal and an impulse response of a channel.
FIG. 25 illustrates correlations between a main signal and a ghost signal when a pre-ghost exists. More specifically, FIG. 25(b) illustrates an example of a main signal, and FIG. 25(c) illustrates an example of the pre-ghost signal. Referring to FIG. 25, which is similar to the example of the post-ghost shown in FIG. 24, when the time difference t0 between the main signal and the ghost is smaller than D1, the effect (or influence) of the ghost is shown in a circular convolution form of the main signal and the impulse response of a channel.
As described above, when the time difference between the main signal and the pre-ghost is smaller than the D1 symbol time, or when the time difference between the main signal and the post-ghost is smaller than the D2 symbol time, the effect of the ghost is shown within the FFT block in a circular convolution form. More specifically, when a delay spread of a multiple path (or ghost) is smaller than the guard section, the effect of the multiple path becomes a circular convolution form of the general data block (or FFT block) and the channel impulse response within the time domain. Accordingly, in the frequency domain, the effect of the multiple path is shown as a multiplication of the data block and the channel impulse response. Therefore, by using such characteristics channel equalization may be easily performed in the frequency domain. Thus, the structure of the channel equalization may be simplified. The present invention may uses an indirect channel equalizing method, wherein known data sequences allocated in identical patterns during a pre-determined cycle period are used to estimate a channel impulse response (CIR). Herein, an indirect channel equalizing method refers to a method of performing channel equalization by estimating the impulse response of a channel, thereby obtaining an equalization coefficient. Alternatively, a direct channel equalizing method refers to a method of performing channel equalization by obtaining an error from a channel equalized signal, thereby updating the equalization coefficient.
FIG. 26 illustrates a block diagram of an example of a channel equalizer using an indirect channel equalizing method according to the present invention. Herein, the channel equalizing process is performed in a frequency domain. Referring to FIG. 26, the channel equalizer includes a first fast fourier transform (FFT) unit 1001, a CIR estimator 1002, a second FFT unit 1003, a coefficient calculator 1004, a distortion compensator 1005, and an inverse fast fourier transform (IFFT) unit 1006. More specifically, when a series of identical known data sequences is regularly inserted in the general data sequence and then transmitted, the first FFT unit 1001 performs FFT by FFT block units on the received data. Then, the first FFT unit 501 converts the processed data to frequency domain data, which are then outputted to the distortion compensator 1005. Herein, assuming that both post-ghost and pre-ghost exist, the FFT block section is set to have part of the known data corresponding to the known data section positioned both before (or in front of) and after (or behind) the general data. Any device performing multiplication of complex numbers may be used as the distortion compensator 1005.
The CIR estimator 1002 uses the data received during the known data section and the known data, which are known by the receiver according to an agreement between the receiving system and the transmitting system, in order to estimate a channel. Then, the CIR estimator 1002 outputs the estimated channel to the second FFT unit 1003. For this, the CIR estimator 1002 receives known sequence position indicators from the known data detector 904. In this case, the CIR estimator 1002 may also receive known sequence position indicators having identical patterns. Furthermore, since the known data sequence of the known data section (or block) corresponds to data already known according to an agreement between the receiving system and the transmitting system, the known data sequence may be stored in advance (or pre-stored) in the CIR estimator 1002. Alternatively, the known data sequences generated from the known data detector 904 may also be received.
According to the embodiment of the present invention, the known data sequences that is to be inserted as a reference data sequence is stored in advance in the CIR estimator 1002. Also, in addition to the embodiment shown in FIG. 26, the example of storing the known data in the CIR estimator 1002 in advance, or receiving the known data from the known data detector 904 may also be applied in other CIR estimators according to other embodiments of the present invention. More specifically, the CIR estimator 1002 performs the channel estimation process by using the known data being received only during the known data section and the pre-stored known data sequence. In other words, the CIR estimator 1002 estimates an impulse response of a discrete equalization channel through which a signal transmitted from the transmitter is assumed to have passed during the known data section. Thereafter, the CIR estimator 1002 outputs the estimated result to the second FFT unit 1003.
The second FFT unit 1003 performs a FFT process on the estimated channel and converts the processed channel to the frequency domain. Thereafter, the processed channel is outputted to the coefficient calculator 1004. The coefficient calculator 1004 uses the channel impulse response of the frequency domain to calculate the equalizer coefficient and outputs the calculated result to the distortion compensator 1005. The distortion compensator 1005 performs complex multiplication on the output of the coefficient calculator 1004 and the output of the first FFT unit 1001 after each frequency bin, thereby compensating the channel distortion of the data outputted from the first FFT unit 1001. Then, the distortion compensator 1005 outputs the processed data to the IFFT unit 1006. The IFFT unit 1006 performs an IFFT process of the data having the channel distortion compensated by the distortion compensator 1005, thereby converting the multiplied result to a time domain signal.
The coefficient calculator 1004 of FIG. 26 may calculate the equalizer coefficient by using a zero forcing method, which simply calculates the inverse of a channel. Alternatively, the coefficient calculator 1004 may also calculate the equalizer coefficient by using a minimum mean squared error (MMSE) method, which estimates the amount of noise in the channel so as to minimize a mean squared error corresponding to the output of the equalizer. As shown in FIG. 26, when equalization is performed in the frequency domain, the distortion of data caused by a multiple path may be compensated. However, a white noise element that is added to the output of the multiple path channel is amplified by the frequency domain equalizer, thereby changing to a colored noise. By removing the colored noise that has been amplified as described above, the equalization performance of the frequency domain channel equalizer may be enhanced.
FIG. 27 and FIG. 28 illustrate exemplary structures of a channel equalizer that is used for resolving noise amplification problems caused by the frequency domain equalizer as described above. FIG. 27 illustrates a block diagram showing the channel equalization device having a time domain equalizer 1100 added to the frequency domain equalizer shown in FIG. 26. Herein, the time domain equalizer 1100 includes an adder 1101, a decision device 1102, and a feedback filter 1103. More specifically, the data that are equalized by the frequency domain equalizer 1000 and converted to time domain data, as shown in FIG. 26, are inputted to the adder 1101 of the time domain equalizer 1100. The adder 1101 then adds the output of the frequency domain equalizer 1000 and the output of the feedback filter 1103. Thereafter, the added result is outputted for data recovery and simultaneously outputted to the decision device 1102.
The decision device 1102 compares the output signal outputted from adder 1101 with a predetermined reference signal level. Accordingly, the reference signal level that is the nearest to the output signal of the adder 1101 is decided and outputted as the decision value. Subsequently, the feedback filter 1103 receives the decision value of the decision device 1102, so as to perform a filtering process in the time domain. Then, the processed decision value is outputted to the adder 1101. At this point, if the decision is accurately made by the decision device 1102, since the decision value having the noise removed (or cancelled) from the output element of the frequency domain equalizer 1000 is re-inputted as the input of the feedback filter 1103, amplification of the noise does not occur. Therefore, the equalization performance of the channel equalizer of FIG. 27 is more excellent than the channel equalizer of FIG. 26.
FIG. 28 illustrates a block diagram showing the channel equalization device having a noise canceller 1200 added to the frequency domain equalizer 1000 shown in FIG. 26. Herein, the noise canceller 1200 includes a subtracter 1201, a decision device 1202, and a noise predictor 1203. More specifically, the data that have been equalized by the frequency domain channel equalizer 1000 shown in FIG. 26 and converted to time domain data are inputted to the subtracter 1201 of the noise canceller 1200. The subtracter 1201 removes the noise, which is predicted by the noise predictor 1203, from the signal equalized in the frequency domain. Then, the signal having the amplified noise removed therefrom is outputted for data recovery and simultaneously outputted to the decision device 1202.
The decision device 1202 outputs a decision value closest to the output of the subtracter 1201 to the noise predictor 1203. The noise predictor 1203 removes the output of the decision device 1202 from the signal that has been converted to the time domain by the frequency domain equalizer 1000, so as to calculate the noise element. Thereafter, the calculated noise element is used as an input of a filter (not shown) within the noise predictor 1203. The noise predictor 1203 uses the filter to predict the colored noise element included in the output symbol of the current frequency domain equalizer 1000. Then, the predicted colored noise element is outputted to the subtracter 1201. Subsequently, the subtracter 1201 removes the noise element predicted by the noise predictor 1203 from the output of the frequency domain equalizer 1000, thereby outputting the final data. As described above, by periodically inserting and transmitting general data in known data having identical patterns, and by having the receiving system perform channel equalization in the form of circular convolution, the structure of the channel equalizer according to the present invention becomes more simplified, and the channel equalizing performance may be enhanced.
Meanwhile, as described above, when the input data are converted to frequency domain data by the first FFT unit 101, the FFT block section should be configured so that part of the known data of the known data section is located both in front of and behind the general data section, as shown in FIG. 23. Thus, the influence of the channel may occur in the form of circular convolution, thereby allowing channel equalization to be performed correctly. However, when equalization is performed by the channel equalizer shown in FIG. 26 to FIG. 28, and when the CIR of point T1 and the CIR of point T2 (both shown in FIG. 23) are used for the equalization process, the point of the general data to which the actual equalization is applied and the point of the CIR used in the equalization process do not coincide with one another. This leads to a deficiency in the performance of the equalizer. More specifically, this is because the CIR is the value calculated (or obtained) from the known data section, and because the channel equalization process of the general data section is performed by using the CIR calculated (or obtained) from the known data section.
In order to resolve such problems, another example of an indirect equalization type channel equalizer is presented in FIG. 29. Herein, an average value of the CIRs is used for channel equalizing the general data. For example, when performing the equalization process, an average value of the CIR of point T1 and the CIR of point T2 is used to perform a channel equalization process on the general data section between point T1 and point T2, thereby enhancing the equalizing performance. In this case, each known data section may use the CIR obtained from each corresponding known data section so as to perform channel equalization. As another example, the channel equalization may be performed in the known data section including point T1, the known data section including point T2, and a general data section between point T1 and point T2 by using the average CIR value between point T1 and point T2. Accordingly, the channel equalizer shown in FIG. 29 further includes a first FFT unit 1301, a distortion compensator 1302, a CIR estimator 1303, an average calculator 1304, a second FFT unit 1305, a coefficient calculator 1306, and an inverse IFFT unit 1307. In the structure shown in FIG. 29, the operations of the first FFT unit 1301, the distortion compensator 1302, the CIR estimator 1303, and the IFFT unit 1307 may be identical to those shown in FIG. 26.
More specifically, the CIR estimator 1303 estimates the CIR by using the data received during the known data section and the known data sequence. Then, the estimated CIR is outputted to the average calculator 1304. Herein, the average calculator 1304 calculates and obtains an average value of the consecutive CIRs that are being inputted and, then, outputs the calculated average value to the second FFT unit 1305. For example, the average value between the CIR value estimated at point T1 and the CIR value estimated at point T2 is calculated, so that the calculated average value can be used in the channel equalization process of the general data located between point T1 and point T2. Accordingly, the calculated average value is outputted to the second FFT unit 1305. The second FFT unit 1305 converts the estimated CIR to the frequency domain CIR, which is then outputted to the coefficient calculator 1306. The coefficient calculator 1306 uses the average CIR of the frequency domain in order to calculate the equalization coefficient, thereby outputting the calculated coefficient to the distortion compensator 1302. Herein, for example, the coefficient calculator 1306 may obtain and to output the calculated the equalization coefficient domain that can provide minimum mean square error (MMSE) from the estimated average CIR of the frequency domain. The operations of the components that follow are identical to those shown in FIG. 26, and so the description of the same will, therefore, be omitted for simplicity.
FIG. 30 illustrates a block diagram of a channel equalizer according to another embodiment of the present invention. More specifically, FIG. 30 illustrates a block diagram of a frequency domain channel equalizer using an indirect equalization method according to another embodiment of the present invention. Herein, an overlap & save method is used to perform linear convolutional operation in the frequency domain. Referring to FIG. 30, the channel equalizer includes an overlap unit 1401, a first fast fourier transform (FFT) unit 1402, a distortion compensator 1403, a CIR estimator 1404, a second FFT unit 1405, a coefficient calculator 1406, an inverse fast fourier transform (IFFT) unit 1407, and a save unit 1408. Herein, any device performing complex number multiplication may be used as the distortion compensator 1403.
In the channel equalizer having the above-described structure, as shown in FIG. 30, the received data are overlapped by the overlap unit 1401 and then inputted to the first FFT unit 1402. The first FFT unit 1402 converts (or transforms) the overlapped data of the time domain to overlapped data of the frequency domain by using fast fourier transform (FFT). Then, the converted data are outputted to the distortion compensator 1403. The distortion compensator 1403 performs complex multiplication on the equalization coefficient calculated from the coefficient calculator 1406 and the overlapped data of the frequency domain, thereby compensating the channel distortion of the overlapped data being outputted from the first FFT unit 1402. Thereafter, the distortion-compensated data are outputted to the IFFT unit 1407. The IFFT unit 407 performs inverse fast fourier transform (IFFT) on the distortion-compensated overlapped data, so as to convert the corresponding data back to data (i.e., overlapped data) of the time domain. Thereafter, the converted data are outputted to the save unit 1408. The save unit 1408 extracts only the valid data from the overlapped data of the time domain, thereby outputting the extracted valid data.
Meanwhile, the CIR estimator 1404 estimates the CIR by using the data received during the known data section and the known data of the known data section, the known data being already known by the receiving system in accordance with an agreement between the receiving system and the transmitting system. Then, the estimated CIR is outputted to the second FFT unit 1405. For this, the CIR estimator 1404 receives known sequence position indicators from the known data detector 904. Furthermore, since the known data sequence of the known data section (or block) corresponds to data already known according to an agreement between the receiving system and the transmitting system, the known data sequence may be stored in advance (or pre-stored) in the CIR estimator 1404. Alternatively, the known data sequences generated from the known data detector 904 may also be received.
The second FFT unit 1405 performs FFT on the estimated CIR of the time domain in order to convert the time domain CIR to a frequency domain CIR. Then, the second FFT unit 1405 outputs the converted CIR to the coefficient calculator 1406.
The coefficient calculator 1406 uses the estimated CIR of the frequency domain, so as to calculate the equalization coefficient and to output the calculated equalization coefficient to the distortion compensator 1403. The coefficient calculator 1406 is an exemplary part of the channel equalizer according to the embodiment of the present invention. At this point, the coefficient calculator 1406 calculates a channel equalization coefficient of the frequency domain that can provide minimum mean square error (MMSE) from the estimated CIR of the frequency domain. The calculated channel equalization coefficient is outputted to the distortion compensator 1403. More specifically, the channel equalizer of FIG. 26 performs circular convolution calculation in the frequency domain in order to perform the channel equalization process. On the other hand, the frequency domain channel equalizer of FIG. 30 performs linear convolution calculation in the frequency domain in order to perform the channel equalization process. Other than this, the remaining components and the corresponding operations are identical to one another and so, a detailed description of the same will, therefore, be omitted for simplicity.
Since the channel equalizer of FIG. 30 does not use the characteristics of the guard interval, unlike in FIG. 26, the channel equalizer shown in FIG. 30 is advantageous in that there are no limitations when determining the FFT block section. More specifically, the known data do not necessarily have to be located in front of and behind the general data which are inputted to the first FFT unit FTT1. The channel equalizers are used to estimate the CIRs by using the known data that are periodically transmitted. Since the CIRs are used to calculate each equalization coefficient, the speed at which the equalization coefficient is updated largely depends the cycle period according to which the known data are being transmitted. Therefore, in a dynamic channel (i.e., in a channel wherein the characteristics change in accordance with the time), when the channel changing speed is faster than the transmission cycle of the known data, the equalization performance may be deteriorated. At this point, when the known data are frequently transmitted in order to compensate the channel that undergoes frequent and fast changes, the transmission efficiency of the general data, in which the actual valid contents are transmitted, may be deteriorated. Accordingly, there are limitations in reducing the transmission cycle of the known data.
In order to resolve such problems, another example of a channel equalizer is presented in FIG. 31. FIG. 31 illustrates a block diagram of a channel equalizer of the frequency domain according to another embodiment of the present invention. Instead of frequently transmitting the known data, the channel equalizer according to another embodiment of the present invention interpolates CIRs that are estimated in the known data section and uses the interpolated CIRs for the channel equalization of the general data. Herein, the channel equalizer of FIG. 31 further includes an interpolator 1409 between the CIR estimator 1404 and the second FFT unit 1405 of FIG. 30.
More specifically, the CIR estimator 1404 estimates the CIR by using the data received during the known data section and the known data of the known data section already known by the receiving system according to an agreement between the receiving system and the transmitting system. Then, the estimated CIR is outputted to the interpolator 1409. Herein, the interpolator 1409 uses the inputted CIR to estimate CIR of the section that does not include the known data by using a pre-determined interpolation method. Then, the interpolator 1409 outputs the estimated CIR to the second FFT unit 1405. The second FFT unit 1405 converts the inputted CIR to the frequency domain CIR, which is then outputted to the coefficient calculator 1406. The coefficient calculator 1406 uses the interpolated CIR of the frequency domain in order to calculate the equalization coefficient that can provide minimum mean square error (MMSE) and to output the calculated equalization coefficient to the distortion compensator 1403. The operations of the components that follow are identical to those shown in FIG. 30, and so the description of the same will, therefore, be omitted for simplicity.
Herein, the interpolation method of the interpolator 1409 corresponds to a method of estimating data of an unknown point by using the data known from a particular function. The simplest example of interpolation is the linear interpolation, which is illustrated in FIG. 32. More specifically, in a random function F(x), when given the values F(Q) and F(S) each from points x=Q and x=S, respectively, the estimated value {circumflex over (F)}(P) of the F(x) function at point x=P may be estimated by using Equation 4 below.




  
    
      
        
          
            
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If the known data sequence is periodically inserted and transmitted, as shown in FIG. 23, the distance between the general data section and the known data section positioned in front of or behind the general data section, according to the embodiment of the present invention, is determined as one cycle period. Herein, at least one of the data sections included in the one cycle period is divided into a plurality of sections. The CIR is estimated in each divided section by using the above-described interpolation method. However, when one data cycle is divided into a plurality of sections, not all FFT block sections can be configured to have the known data located (or positioned) before or behind the FFT block section, as shown in FIG. 23. Therefore, the above-described interpolation method cannot be used in the channel equalizer using the cyclic prefix. Nevertheless, when using the channel equalizer using the overlap & save method, as shown in FIG. 31.
FIG. 33 illustrates an example of overlap & save processes according to an embodiment of the present invention, when linearly interpolating the CIR. Referring to FIG. 33, data are overlapped so that the current FFT block and the previous FFT block are overlapped at an overlapping ratio of 50%, and the data cycle period including the general data section and the known data section positioned in front of the general data section is divided into 4 sections. In this example, the size and number of each section are decided so that a known data sequence is included in at least one section of the data cycle. This is to enable FFT block data of the section including the known data sequence directly to use the CIR estimated from the corresponding section for the channel equalization process. Furthermore, the CIR obtained (or calculated) from the data section including the known data sequence is used for interpolating the CIR of the section that does not include any known data sequence.
Herein, the data inputted to the first FFT unit 1402 are inserted in order from FFT block 1 to FFT block 5, as shown in FIG. 33. The inputted data are then inputted to the distortion compensator 1403 so as to be channel equalized. Subsequently, the equalized data are converted to time domain data by the IFFT unit 1407. Then, only the portion corresponding to valid data is extracted from the converted by the save unit 1408. Thereafter, the final data are outputted.
Referring to FIG. 33, sections 1 to 5 represent the valid data section corresponding to each FFT block. At this point, since a known data sequence is included in the FFT block 1, the CIR T2 may be estimated. Similarly, since a known data sequence is included in the FFT block 5, the CIR T3 may also be estimated. In other words, the data of the FFT block 1 use the estimated CIR T2 to perform channel equalization, and the data of the FFT block 5 uses the estimated CIR T3 to perform channel equalization. However, since the known data sequence is not included in FFT block 2 to FFT block 4, the interpolator 1409 interpolates CIR T2 and CIR T3, thereby estimating the CIRs that may each be used in the FFT block 2 to the FFT block 4. At this point, if linear interpolation is used, the CIRs corresponding to FFT block 2 to FFT block 4 may be estimated by using Equation 5 shown below.

FFT Block 2:0.75T2+0.25T3

FFT Block 3:0.5T2+0.5T3

FFT Block 4:0.25T2+0.75T3  Equation 5

Referring to FIG. 34, data are overlapped so that the current FFT block and the previous FFT block are overlapped at an overlapping ratio of 75%, and the data cycle period including the general data section and the known data section positioned in front of the general data section is divided into 4 sections. Similarly, in this example, the size and number of each section are decided so that a known data sequence is included in at least one section of the data cycle. Furthermore, the interpolated and estimated CIRs are identical as those shown in FIG. 33. Yet, the only difference is that the FFT block size is twice the size of the FFT blocks of FIG. 33. As described above, the examples shown in FIG. 33 and FIG. 34 are merely exemplary, and the degree and algorithm of the interpolation method and the size of the FFT block may be set diversely whenever required or necessary.
Herein, the data group that is inputted for the equalization process is divided into regions A to C, as shown in FIG. 6A. More specifically, in the example of the present invention, each region A, B, and C are further divided into regions A1 to A5, regions B1 and B2, and regions C1 to C3, respectively. Most particularly, an example of estimating the CIR in accordance with each region A (A1 to A5), B (B1 and B2), and C (C1 to C3) within the data group, which is hierarchically divided and transmitted from the transmitting system, and applying each CIR differently will also be described herein. Furthermore, by using the known data, the place and contents of which is known in accordance with an agreement between the transmitting system and the receiving system, and the field synchronization data, so as to estimate the CIR, the present invention may be able to perform channel equalization with more stability.
Referring to FIG. 6A, the CIR that is estimated from the field synchronization data in the data structure is referred to as CIR_FS. Alternatively, the CIRs that are estimated from each of the 5 known data sequences existing in region A are sequentially referred to as CIR_N0, CIR_N1, CIR_N2, CIR_N3, and CIR_N4. As described above, the present invention uses the CIR estimated from the field synchronization data and the known data sequences in order to perform channel equalization on data within the data group. At this point, each of the estimated CIRs may be directly used in accordance with the characteristics of each region within the data group. Alternatively, a plurality of the estimated CIRs may also be either interpolated or extrapolated so as to create a new CIR, which is then used for the channel equalization process.
Herein, as shown in FIG. 32 to FIG. 34, when a value F(Q) of a function F(x) at a particular point Q and a value F(S) of the function F(x) at another particular point S are known, interpolation refers to estimating a function value of a point within the section between points Q and S. Linear interpolation corresponds to the simplest form among a wide range of interpolation operations. The linear interpolation described herein is merely exemplary among a wide range of possible interpolation methods. And, therefore, the present invention is not limited only to the examples set forth herein. Alternatively, when a value F(Q) of a function F(x) at a particular point Q and a value F(S) of the function F(x) at another particular point S are known, extrapolation refers to estimating a function value of a point outside of the section between points Q and S. Linear extrapolation is the simplest form among a wide range of extrapolation operations. Similarly, the linear extrapolation described herein is merely exemplary among a wide range of possible extrapolation methods.
FIG. 35 illustrates an example of an extrapolation operation. Particularly, FIG. 35 illustrates the simplest form of linear extrapolation among a wide range of extrapolation operations. More specifically, since the values F(Q) and F(S) each from points Q and S, respectively, are known, a straight line passing between the Q−S section may be obtained so as to calculate an approximate value {circumflex over (F)}(P) of the F(x) function at point P. Herein, the equation of the straight line passing the coordinates (Q,F(Q)) and (S,F(S)) is shown in Equation 6 below:




  
    
      
        
          
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Therefore, in order to calculate the function value at point P using Equation 6, the equation shown in Equation 7 below may be used.




  
    
      
        
          
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The above-described linear extrapolation method is the simplest form of linear extrapolation among a wide range of extrapolation operations. However, the method described above is merely exemplary, and, therefore, the present invention is not limited only to the example presented above. Accordingly, a variety of other extrapolation may be used in the present invention.
FIG. 36 illustrates a conceptual diagram of the extrapolation operation according to the present invention. Most particularly, in the example of the extrapolation operation shown in FIG. 36, data of a current FFT block and data of a previous FFT block are overlapped at an overlapping ratio of 50%, then regions B and C are divided into a plurality of sections so that the CIR of each section is estimated by performing (or operating) extrapolation on the CIRs of region A. More specifically, the CIR of each section of regions B and C is estimated by performing extrapolation on at least one of the CIRs of region A. Then, by using each of the estimated CIRs, channel equalization is performed on the data corresponding to each section. When extrapolation is performed on CIR_N3 and CIR_N4 of region A, in order to estimate the CIRs of section 1 to section 4 of regions B and C, and when the length of one section is assumed to be equal to 4 segments, the CIRs of section 1 to section 4 having linear extrapolation performed thereon are as follows:

    
    
        Section 1:1.25*CIR_N4 ̃0.25*CIR_N3
        Section 2:1.5*CIR_N4−0.5*CIR_N3
        Section 3:1.75*CIR_N4−0.75*CIR_N3
        Section 4:2*CIR_N4−CIR_N3
    
    


More specifically, in case of region C1, any one of the CIR_N4 estimated from a previous data group, the CIR_FS estimated from the current data group that is to be processed with channel equalization, and a new CIR generated by extrapolating the CIR_FS of the current data group and the CIR_N0 may be used to perform channel equalization. Alternatively, in case of region B1, a variety of methods may be applied as described in the case for region C1. For example, a new CIR created by linearly extrapolating the CIR_FS estimated from the current data group and the CIR_N0 may be used to perform channel equalization. Also, the CIR_FS estimated from the current data group may also be used to perform channel equalization. Finally, in case of region A1, a new CIR may be created by interpolating the CIR_FS estimated from the current data group and CIR_N0, which is then used to perform channel equalization. Furthermore, any one of the CIR_FS estimated from the current data group and CIR_N0 may be used to perform channel equalization.
In case of regions A2 to A5, CIR_N(i−1) estimated from the current data group and CIR_N(i) may be interpolated to create a new CIR and use the newly created CIR to perform channel equalization. Also, any one of the CIR_N(i−1) estimated from the current data group and the CIR_N(i) may be used to perform channel equalization. Alternatively, in case of regions B2, C2, and C3, CIR_N3 and CIR_N4 both estimated from the current data group may be extrapolated to create a new CIR, which is then used to perform the channel equalization process. Furthermore, the CIR_N4 estimated from the current data group may be used to perform the channel equalization process. Accordingly, an optimum performance may be obtained when performing channel equalization on the data inserted in the data group.
FIG. 37 illustrates a block diagram of a channel equalizer according to another embodiment of the present invention. Referring to FIG. 37, the channel equalizer includes an overlap unit 1501, a first fast fourier transform (FFT) unit 1502, a distortion compensator 1503, a CIR estimator 1504, a first pre-CIR cleaner 1505, a CIR calculator 1506, a second pre-CIR cleaner 1507, a zero-padding unit 1508, a second FFT unit 1509, a coefficient calculator 1510, an inverse fast fourier transform (IFFT) unit 1511, and a save unit 1512. Herein, any device that performs complex number multiplication may be used as the distortion compensator 1503.
In the channel equalizer having the above-described structure, as shown in FIG. 37, the received data are overlapped by the overlap unit 1501 and are outputted to the first FFT unit 1502. The first FFT unit 1502 performs a FFT process to convert the overlapped data of the time domain to overlapped data of the frequency domain. Then, the converted overlapped data are outputted to distortion compensator 1503. The distortion compensator 1503 performs complex multiplication on overlapped data of the frequency domain and the equalization coefficient calculated by the coefficient calculator 1510, thereby compensating the channel distortion of the overlapped data being outputted from the first FFT unit 1502. Thereafter, the distortion-compensated data are outputted to the IFFT unit 1511. The IFFT unit 1511 performs inverse fast fourier transform (IFFT) on the distortion-compensated overlapped data, so as to convert the corresponding data back to data (i.e., overlapped data) of the time domain. Then, the converted data are outputted to the save unit 1512. The save unit 1512 extracts and outputs only the valid data from the overlapped data of the time domain.
Meanwhile, the CIR estimator 1504 uses the data being received during the known data section and the known data of the known data section already known by the receiving system in accordance with an agreement between the receiving system and the transmitting system in order to estimate to the channel impulse response (CIR). For this, the CIR estimator 1504 receives known sequence position indicators from the known data detector 904. Also, since the known data of the known data section correspond to data already known in accordance with an agreement between the receiving system and the transmitting system, the known data may be pre-stored in the CIR estimator 1504, or the known data generated from the known data detector 904 may also be received. The CIR estimator 1504 may estimate the CIR by using a least square (LS) method.
The CIR estimated by the CIR estimator 1504 either passes through the first pre-CIR cleaner 1505 or bypasses the first pre-CIR cleaner 1505, thereby being inputted to the CIR calculator 1506. The CIR calculator 150G then performs interpolation or extrapolation on the estimated CIR, which is then outputted to the second pre-CIR cleaner 1507. Herein, depending upon whether the CIR calculator 1506 performs interpolation or extrapolation on the estimated CIR, the first pre-CIR cleaner 1505 or the second pre-CIR cleaner 1507 may be operated. For example, if the CIR calculator 1506 performs interpolation on the estimated CIR, the second pre-CIR cleaner 1507 is operated. Alternatively, if the CIR calculator 1506 extrapolates the estimated CIR, the first pre-CIR cleaner 1505 is operated.
More specifically, the CIR estimated from the known data not only includes the channel element that is to be obtained, but also includes jitter elements caused by noise. Such jitter element results in a deterioration of the performance of the channel equalizer. Accordingly, it is preferable to remove the jitter element before using the CIR in the coefficient calculator 1510. Therefore, in the examples given herein, the first and second pre-CIR cleaners 1505 and 1507 respectively remove portions of the CIR element having a power level equal to and lower than a pre-determined threshold value from the CIR element (i.e., the first and second pre-CIR cleaners 1505 and 1507 respectively process the CIR element to ‘0’). Herein, the above-described process is referred to as a CIR cleaning process.
In other words, in the CIR calculator 1506, the CIR interpolation process is performed by multiplying and adding coefficients to each of the two CIR estimated by the CIR estimator 1504. At this point, a portion of the noise element of each CIR is added to one another, thereby offsetting (or canceling) one another. Therefore, when the CIR calculator 1506 performs CIR interpolation, the original CIR having the noise element remaining therein. More specifically, when the CIR calculator 1506 performs CIR interpolation, the CIR estimated by the CIR estimator 1504 bypasses the first pre-CIR cleaner 1505 and then inputted to the CIR calculator 1506. Then, the CIR interpolated by the CIR calculator 1506 is processed with CIR cleaning by the second pre-CIR cleaner 1507.
Conversely, in the CIR calculator 1506, the CIR extrapolation process is performed by using a difference value between two CIRS estimated by the CIR estimator 1504 so as to estimate a CIR located outside of the two estimated CIRs. In this case, the noise element is amplified. Therefore, when the CIR calculator 1506 performs CIR extrapolation, the CIR processed with CIR cleaning by the first pre-CIR cleaner 1505 is used. More specifically, when the CIR calculator 1506 performs CIR extrapolation, the extrapolated CIR bypasses the second pre-CIR cleaner 1507 and is inputted to the zero-padding unit 1508.
Meanwhile, when the second FFT unit 1509 converts the CIR that either bypasses the second pre-CIR cleaner 1507 or is processed with CIR cleaning to a frequency domain CIR, the length of the CIR being inputted may not be equal to the FFT size. In other words, the length of the CIR may be shorter than the FFT size. In this case, the zero-padding unit 1508 adds to the CIR the same amount of zeros (0) corresponding to difference between the FFT size and the length of the CIR being inputted. Thereafter, the processed data are outputted to the second FFT unit 1509. Herein, the CIR processed with zero-padding may correspond to any one of the interpolated CIR, the extrapolated CIR, and the CIR estimated from the known data section.
The second FFT unit 1509 performs FFT on the CIR of the time domain, which is being inputted, so as to convert the time domain CIR to a frequency domain CIR, which is then outputted to the coefficient calculator 1510. The coefficient calculator 1505 then uses the converted frequency domain CIR to calculate the equalization coefficient, thereby outputting the calculated coefficient to the distortion compensator 1503. At this point, the coefficient calculator 1503 calculates a channel equalization coefficient of the frequency domain that can provide minimum mean square error (MMSE) from the frequency domain CIR. Then, the calculated coefficient may be outputted to the distortion compensator 1503.
FIG. 38 illustrates a block diagram of a channel equalizer according to another embodiment of the present invention. In other words, FIG. 38 illustrates a block diagram showing another example of a channel equalizer by using different CIR estimation and application methods in accordance with regions A, B, and C, when the data group is divided into the structure shown in FIG. 6A. More specifically, as shown in FIG. 6A, known data that are sufficiently are being periodically transmitted in region A. Therefore, an indirect equalizing method using the CIR may be used herein. However, in regions B and C, the known data are neither able to be transmitted at a sufficiently long length nor able to be periodically and equally transmitted. Therefore, it is inadequate to estimate the CIR by using the known data. Accordingly, in regions B and C, a direct equalizing method in which an error is obtained from the output of the equalizer, so as to update the coefficient. The examples presented in the embodiments of the present invention shown in FIG. 38 include a method of performing indirect channel equalization by using a cyclic prefix on the data of region A, and a method of performing direct channel equalization by using an overlap & save method on the data of regions B and C.
Accordingly, referring to FIG. 38, the frequency domain channel equalizer includes a frequency domain converter 1610, a distortion compensator 1620, a time domain converter 1630, a first coefficient calculating unit 1640, a second coefficient calculating unit 1650, and a coefficient selector 1660. Herein, the frequency domain converter 1610 includes an overlap unit 1611, a select unit 1612, and a first FFT unit 1613. The time domain converter 1630 includes an IFFT unit 1631, a save unit 1632, and a select unit 1633. The first coefficient calculating unit 1640 includes a CIR estimator 1641, an average calculator 1642, and second FFT unit 1643, and a coefficient calculator 1644. The second coefficient calculating unit 1650 includes a decision unit 1651, a select unit 1652, a subtractor 1653, a zero-padding unit 1654, a third FFT unit 1655, a coefficient updater 1656, and a delay unit 1657. Also, a multiplexer (MUX), which selects data that are currently being inputted as the input data depending upon whether the data correspond to region A or to regions B/C, may be used as the select unit 1612 of the frequency domain converter 1610, the select unit 1633 of the time domain converter 1630, and the coefficient selector 1660.
In the channel equalizer having the above-described structure, as shown in FIG. 38, if the data being inputted correspond to the data of region A, the select unit 1612 of the frequency domain converter 1610 selects the input data and not the output data of the overlap unit 1611. In the same case, the select unit 1633 of the time domain converter 1630 selects the output data of the IFFT unit 1631 and not the output data of the save unit 1632. The coefficient selector 1660 selects the equalization coefficient being outputted from the first coefficient calculating unit 1640. Conversely, if the data being inputted correspond to the data of region A, the select unit 1612 of the frequency domain converter 1610 selects the output data of the overlap unit 1611 and not the input data. In the same case, the select unit 1633 of the time domain converter 1630 selects the output data of the save unit 1632 and not the output data of the IFFT unit 1631. The coefficient selector 1660 selects the equalization coefficient being outputted from the second coefficient calculating unit 1650.
More specifically, the received data are inputted to the overlap unit 1611 and select unit 1612 of the frequency domain converter 1610, and to the first coefficient calculating unit 1640. If the inputted data correspond to the data of region A, the select unit 1612 selects the received data, which are then outputted to the first FFT unit 1613. On the other hand, if the inputted data correspond to the data of regions B and C, the select unit 1612 selects the data that are overlapped by the overlap unit 1613 and are, then, outputted to the first FFT unit 1613. The first FFT unit 1613 performs FFT on the time domain data that are outputted from the select unit 1612, thereby converting the time domain data to frequency domain data. Then, the converted data are outputted to the distortion compensator 1620 and the delay unit 1657 of the second coefficient calculating unit 1650.
The distortion compensator 1620 performs complex multiplication on frequency domain data outputted from the first FFT unit 1613 and the equalization coefficient outputted from the coefficient selector 1660, thereby compensating the channel distortion detected in the data that are being outputted from the first FFT unit 1613. Thereafter, the distortion-compensated data are outputted to the IFFT unit 1631 of the time domain converter 1630. The IFFT unit 1631 of the time domain converter 1630 performs IFFT on the channel-distortion-compensated data, thereby converting the compensated data to time domain data. The converted data are then outputted to the save unit 1632 and the select unit 1633. If the inputted data correspond to the data of region A, the select unit 1633 selects the output data of the IFFT unit 1631. On the other hand, if the inputted data correspond to regions B and C, the select unit 1633 selects the valid data extracted from the save unit 1632. Thereafter, the selected data are outputted to be decoded and, simultaneously, outputted to the second coefficient calculating unit 1650.
The CIR estimator 1641 of the first coefficient calculating unit 1640 uses the data being received during the known data section and the known data of the known data section, the known data being already known by the receiving system in accordance with an agreement between the receiving system and the transmitting system, in order to estimate the CIR. Subsequently, the estimated CIR is outputted to the average calculator 1642. The average calculator 1642 calculates an average value of the CIRs that are being inputted consecutively. Then, the calculated average value is outputted to the second FFT unit 1643. For example, referring to FIG. 23, the average value of the CIR value estimated at point T1 and the CIR value estimated at point T2 is used for the channel equalization process of the general data existing between point T1 and point T2. Accordingly, the calculated average value is outputted to the second FFT unit 1643.
The second FFT unit 1643 performs FFT on the CIR of the time domain that is being inputted, so as to convert the inputted CIR to a frequency domain CIR. Thereafter, the converted frequency domain CIR is outputted to the coefficient calculator 1644. The coefficient calculator 1644 calculates a frequency domain equalization coefficient that satisfies the condition of using the CIR of the frequency domain so as to minimize the mean square error. The calculated equalizer coefficient of the frequency domain is then outputted to the coefficient calculator 1660.
The decision unit 1651 of the second coefficient calculating unit 1650 selects one of a plurality of decision values (e.g., 8 decision values) that is most approximate to the equalized data and outputs the selected decision value to the select unit 1652. Herein, a multiplexer may be used as the select unit 1652. In a general data section, the select unit 1652 selects the decision value of the decision unit 1651. Alternatively, in a known data section, the select unit 1652 selects the known data and outputs the selected known data to the subtractor 1653. The subtractor 1653 subtracts the output of the select unit 1633 included in the time domain converter 1630 from the output of the select unit 652 so as to calculate (or obtain) an error value. Thereafter, the calculated error value is outputted to the zero-padding unit 1654.
The zero-padding unit 1654 adds (or inserts) the same amount of zeros (0) corresponding to the overlapped amount of the received data in the inputted error. Then, the error extended with zeros (0) is outputted to the third FFT unit 1655. The third FFT unit 1655 converts the error of the time domain having zeros (0) added (or inserted) therein, to the error of the frequency domain. Thereafter, the converted error is outputted to the coefficient update unit 1656. The coefficient update unit 1656 uses the received data of the frequency domain that have been delayed by the delay unit 1657 and the error of the frequency domain so as to update the previous equalization coefficient. Thereafter, the updated equalization coefficient is outputted to the coefficient selector 1660.
At this point, the updated equalization coefficient is stored so as that it can be used as a previous equalization coefficient in a later process. If the input data correspond to the data of region A, the coefficient selector 1660 selects the equalization coefficient calculated from the first coefficient calculating unit 1640. On the other hand, if the input data correspond to the data of regions B and C, the coefficient selector 1660 selects the equalization coefficient updated by the second coefficient calculating unit 1650. Thereafter, the selected equalization coefficient is outputted to the distortion compensator 1620.
FIG. 39 illustrates a block diagram of a channel equalizer according to another embodiment of the present invention. In other words, FIG. 39 illustrates a block diagram showing another example of a channel equalizer by using different CIR estimation and application methods in accordance with regions A, B, and C, when the data group is divided into the structure shown in FIG. 6A. In this example, a method of performing indirect channel equalization by using an overlap & save method on the data of region A, and a method of performing direct channel equalization by using an overlap & save method on the data of regions B and C are illustrated.
Accordingly, referring to FIG. 39, the frequency domain channel equalizer includes a frequency domain converter 1710, a distortion compensator 1720, a time domain converter 1730, a first coefficient calculating unit 1740, a second coefficient calculating unit 1750, and a coefficient selector 1760. Herein, the frequency domain converter 1710 includes an overlap unit 1711 and a first FFT unit 1712. The time domain converter 1730 includes an IFFT unit 1731 and a save unit 1732. The first coefficient calculating unit 1740 includes a CIR estimator 1741, an interpolator 1742, a second FFT unit 1743, and a coefficient calculator 1744. The second coefficient calculating unit 1750 includes a decision unit 1751, a select unit 1752, a subtractor 1753, a zero-padding unit 1754, a third FFT unit 1755, a coefficient updater 1756, and a delay unit 1757. Also, a multiplexer (MUX), which selects data that are currently being inputted as the input data depending upon whether the data correspond to region A or to regions B and C, may be used as the coefficient selector 1760. More specifically, if the input data correspond to the data of region A, the coefficient selector 1760 selects the equalization coefficient calculated from the first coefficient calculating unit 1740. On the other hand, if the input data correspond to the data of regions B and C, the coefficient selector 1760 selects the equalization coefficient updated by the second coefficient calculating unit 1750.
In the channel equalizer having the above-described structure, as shown in FIG. 39, the received data are inputted to the overlap unit 1711 of the frequency domain converter 1710 and to the first coefficient calculating unit 1740. The overlap unit 1711 overlaps the input data to a pre-determined overlapping ratio and outputs the overlapped data to the first FFT unit 1712. The first FFT unit 1712 performs FFT on the overlapped time domain data, thereby converting the overlapped time domain data to overlapped frequency domain data. Then, the converted data are outputted to the distortion compensator 1720 and the delay unit 1757 of the second coefficient calculating unit 1750.
The distortion compensator 1720 performs complex multiplication on the overlapped frequency domain data outputted from the first FFT unit 1712 and the equalization coefficient outputted from the coefficient selector 1760, thereby compensating the channel distortion detected in the overlapped data that are being outputted from the first FFT unit 1712. Thereafter, the distortion-compensated data are outputted to the IFFT unit 1731 of the time domain converter 1730. The IFFT unit 1731 of the time domain converter 1730 performs IFFT on the distortion-compensated data, thereby converting the compensated data to overlapped time domain data. The converted overlapped data are then outputted to the save unit 1732. The save unit 1732 extracts only the valid data from the overlapped time domain data, which are then outputted for data decoding and, at the same time, outputted to the second coefficient calculating unit 1750 in order to update the coefficient.
The CIR estimator 1741 of the first coefficient calculating unit 1740 uses the data received during the known data section and the known data in order to estimate the CIR. Subsequently, the estimated CIR is outputted to the interpolator 1742. The interpolator 1742 uses the inputted CIR to estimate the CIRs (i.e., CIRs of the region that does not include the known data) corresponding to the points located between the estimated CIRs according to a predetermined interpolation method. Thereafter, the estimated result is outputted to the second FFT unit 1743. The second FFT unit 1743 performs FFT on the inputted CIR, so as to convert the inputted CIR to a frequency domain CIR. Thereafter, the converted frequency domain CIR is outputted to the coefficient calculator 1744. The coefficient calculator 1744 calculates a frequency domain equalization coefficient that satisfies the condition of using the CIR of the frequency domain so as to minimize the mean square error. The calculated equalizer coefficient of the frequency domain is then outputted to the coefficient calculator 1760.
The structure and operations of the second coefficient calculating unit 1750 is identical to those of the second coefficient calculating unit 1650 shown in FIG. 38. Therefore, the description of the same will be omitted for simplicity. If the input data correspond to the data of region A, the coefficient selector 1760 selects the equalization coefficient calculated from the first coefficient calculating unit 1740. On the other hand, if the input data correspond to the data of regions B and C, the coefficient selector 1760 selects the equalization coefficient updated by the second coefficient calculating unit 1750. Thereafter, the selected equalization coefficient is outputted to the distortion compensator 1720.
FIG. 40 illustrates a block diagram of a channel equalizer according to another embodiment of the present invention. In other words, FIG. 40 illustrates a block diagram showing another example of a channel equalizer by using different CIR estimation and application methods in accordance with regions A, B, and C, when the data group is divided into the structure shown in FIG. 6A. For example, in region A, the present invention uses the known data in order to estimate the CIR by using a least square (LS) method, thereby performing the channel equalization process. On the other hand, in regions B and C, the present invention estimates the CIR by using a least mean square (LMS) method, thereby performing the channel equalization process. More specifically, since the periodic known data do not exist in regions B and C, as in region A, the same channel equalization process as that of region A cannot be performed in regions B and C. Therefore, the channel equalization process may only be performed by using the LMS method.
Referring to FIG. 40, the channel equalizer includes an overlap unit 1801, a first fast fourier transform (FFT) unit 1802, a distortion compensator 1803, an inverse fast fourier transform (IFFT) unit 1804, a save unit 1805, a first CIR estimator 1806, a CIR interpolator 1807, a decision unit 1808, a second CIR estimator 1810, a selection unit 1811, a second FFT unit 1812, and a coefficient calculator 1813. Herein, any device performed complex number multiplication may be used as the distortion compensator 1803. In the channel equalizer having the above-described structure, as shown in FIG. 40, the overlap unit 1801 overlaps the data being inputted to the channel equalizer to a predetermined overlapping ratio and then outputs the overlapped data to the first FFT unit 1802. The first FFT unit 1802 converts (or transforms) the overlapped data of the time domain to overlapped data of the frequency domain by using fast fourier transform (FFT). Then, the converted data are outputted to the distortion compensator 1803.
The distortion converter 1803 performs complex multiplication on the equalization coefficient calculated from the coefficient calculator 1813 and the overlapped data of the frequency domain, thereby compensating the channel distortion of the overlapped data being outputted from the first FFT unit 1802. Thereafter, the distortion-compensated data are outputted to the IFFT unit 1804. The IFFT unit 1804 performs inverse fast fourier transform (IFFT) on the distortion-compensated overlapped data, so as to convert the corresponding data back to data (i.e., overlapped data) of the time domain. Subsequently, the converted data are outputted to the save unit 1805. The save unit 1805 extracts only the valid data from the overlapped data of the time domain. Then, the save unit 1805 outputs the extracted valid data for a data decoding process and, at the same time, outputs the extracted valid data to the decision unit 1808 for a channel estimation process.
The decision unit 1808 selects one of a plurality of decision values (e.g., 8 decision values) that is most approximate to the equalized data and outputs the selected decision value to the select unit 1809. Herein, a multiplexer may be used as the select unit 1809. In a general data section, the select unit 1809 selects the decision value of the decision unit 1808. Alternatively, in a known data section, the select unit 1809 selects the known data and outputs the selected known data to the second CIR estimator 1810. Meanwhile, the first CIR estimator 1806 uses the data that are being inputted in the known data section and the known data so as to estimate the CIR.
Thereafter, the first CIR estimator 1806 outputs the estimated CIR to the CIR interpolator 1807. Herein, the known data correspond to reference known data created during the known data section by the receiving system in accordance to an agreement between the transmitting system and the receiving system. At this point, according to an embodiment of the present invention, the first CIR estimator 1806 uses the LS method to estimate the CIR. The LS estimation method calculates a cross correlation value p between the known data that have passed through the channel during the known data section and the known data that are already known by the receiving end. Then, a cross correlation matrix R of the known data is calculated. Subsequently, a matrix operation is performed on R−1·p so that the cross correlation portion within the cross correlation value p between the received data and the initial known data, thereby estimating the CIR of the transmission channel.
The CIR interpolator 1807 receives the CIR from the first CIR estimator 1806. And, in the section between two sets of known data, the CIR is interpolated in accordance with a pre-determined interpolation method. Then, the interpolated CIR is outputted. At this point, the pre-determined interpolation method corresponds to a method of estimating a particular set of data at an unknown point by using a set of data known by a particular function. For example, such method includes a linear interpolation method. The linear interpolation method is only one of the most simple interpolation methods. A variety of other interpolation methods may be used instead of the above-described linear interpolation method. It is apparent that the present invention is not limited only to the example set forth in the description of the present invention. More specifically, the CIR interpolator 1807 uses the CIR that is being inputted in order to estimate the CIR of the section that does not include any known data by using the pre-determined interpolation method. Thereafter, the estimated CIR is outputted to the select unit 1811.
The second CIR estimator 1810 uses the input data of the channel equalizer and the output data of the select unit 1809 in order to estimate the CIR. Then, the second CIR estimator 1810 outputs the estimated CIR to the select unit 1811. At this point, according to an embodiment of the present invention, the CIR is estimated by using the LMS method. The LMS estimation method will be described in detail in a later process. In region A, the select unit 1811 selects the CIR outputted from the CIR interpolator 1807. And, in regions B and C, the select unit 1811 selects the CIR outputted from the second CIR estimator 1810. Thereafter, the select unit 1811 outputs the selected CIR to the second FFT unit 1812
The second FFT unit 1812 converts the CIR that is being inputted to a CIR of the frequency domain, which is then outputted to the coefficient calculator 1813. The coefficient calculator 1813 uses the CIR of the frequency domain that is being inputted, so as to calculate the equalization coefficient and to output the calculated equalization coefficient to the distortion compensator 1803. At this point, the coefficient calculator 1813 calculates a channel equalization coefficient of the frequency domain that can provide minimum mean square error (MMSE) from the CIR of the frequency domain. At this point, the second CIR estimator 1810 may use the CIR estimated in region A as the CIR at the beginning of regions B and C. For example, the last CIR value of region A may be used as the CIR value at the beginning of the C region. Accordingly, the convergence speed of regions B and C may be reduced.
The basic principle of estimating the CIR by using the LMS method in the second CIR estimator 1810 corresponds to receiving the output of an unknown transmission channel and to updating (or renewing) the coefficient of an adaptive filter (not shown) so that the difference value between the output value of the unknown channel and the output value of the adaptive filter is minimized. More specifically, the coefficient value of the adaptive filter is renewed so that the input data of the channel equalizer is equal to the output value of the adaptive filter (not shown) included in the second CIR estimator 1810. Thereafter, the filter coefficient is outputted as the CIR after each FFT cycle.
Referring to FIG. 41, the second CIR estimator 1810 includes a delay unit T, a multiplier, and a coefficient renewal unit for each tab. Herein, the delay unit T sequentially delays the output data {circumflex over (x)}(n) of the select unit 1809. The multiplier multiplies respective output data outputted from each delay unit T with error data e(n). The coefficient renewal unit renews the coefficient by using the output corresponding to each multiplier. Herein, the multipliers that are being provided as many as the number of tabs will be referred to as a first multiplying unit for simplicity. Furthermore, the second CIR estimator 1810 further includes a plurality of multipliers each multiplying the output data of the select unit 1809 and the output data of the delay unit T (wherein the output data of the last delay unit are excluded) with the output data corresponding to each respective coefficient renewal unit. These multipliers are also provided as many as the number of tabs. This group of multipliers will be referred to as a second multiplying unit for simplicity.
The second CIR estimator 1810 further includes an adder and a subtractor. Herein, the adder adds all of the data outputted from each multipliers included in the second multiplier unit. Then, the added value is outputted as the estimation value ŷ(n) of the data inputted to the channel equalizer. The subtractor calculates the difference between the output data ŷ(n) of the adder and the input data y(n) of the channel equalizer. Thereafter, the calculated difference value is outputted as the error data e(n). Referring to FIG. 41, in a general data section, the decision value of the equalized data is inputted to the first delay unit included in the second CIR estimator 1810 and to the first multiplier included in the second multiplier. In the known data section, the known data are inputted to the first delay unit included in the second CIR estimator 1810 and to the first multiplier included in the second multiplier unit. The input data {circumflex over (x)}(n) are sequentially delayed by passing through a number of serially connected delay units T, the number corresponding to the number of tabs. The output data of each delay unit T and the error data e(n) are multiplied by each corresponding multiplier included in the first multiplier unit. Thereafter, the coefficients are renewed by each respective coefficient renewal unit.
Each coefficient that is renewed by the corresponding coefficient renewal unit is multiplied with the input data the output data {circumflex over (x)}(n) and also with the output data of each delay unit T with the exception of the last delay. Thereafter, the multiplied value is inputted to the adder. The adder then adds all of the output data outputted from the second multiplier unit and outputs the added value to the subtractor as the estimation value ŷ(n) of the input data of the channel equalizer. The subtractor calculates a difference value between the estimation value ŷ(n) and the input data y(n) of the channel equalizer. The difference value is then outputted to each multiplier of the first multiplier unit as the error data e(n). At this point, the error data e(n) is outputted to each multiplier of the first multiplier unit by passing through each respective delay unit T. As described above, the coefficient of the adaptive filter is continuously renewed. And, the output of each coefficient renewal unit is outputted as the CIR of the second CIR estimator 1810 after each FFT cycle.
FIG. 42 illustrates a block diagram of a channel equalizer according to another embodiment of the present invention. Herein, by estimating and compensating a remaining carrier phase error from a channel-equalized signal, the receiving system of the present invention may be enhanced. Referring to FIG. 42, the channel equalizer includes a first frequency domain converter 2100, a channel estimator 2110, a second frequency domain converter 2121, a coefficient calculator 2122, a distortion compensator 2130, a time domain converter 2140, a remaining carrier phase error remover 2150, a noise canceller (NC) 2160, and a decision unit 2170.
Herein, the first frequency domain converter 2100 includes an overlap unit 2101 overlapping inputted data, and a fast fourier transform (FFT) unit 2102 converting the data outputted from the overlap unit 2101 to frequency domain data. The channel estimator 2110 includes a CIR estimator 2111 estimating a CIR from the inputted data, a phase compensator 2112 compensating the phase of the CIR estimated by the CIR estimator 2111, and a linear interpolator 2113 performing linear interpolation on the CIR having its phase compensated. The second frequency domain converter 2121 includes a FFT unit converting the CIR being outputted from the channel estimator 2110 to a frequency domain CIR.
The time domain converter 2140 includes an IFFT unit 2141 converting the data having the distortion compensated by the distortion compensator 2130 to time domain data, and a save unit 2142 extracting only valid data from the data outputted from the IFFT unit 2141. The remaining carrier phase error remover 2150 includes an error compensator 2151 removing the remaining carrier phase error included in the channel equalized data, and a remaining carrier phase error estimator 2152 using the channel equalized data and the decision data of the decision unit 2170 so as to estimate the remaining carrier phase error, thereby outputting the estimated error to the error compensator 2151. Herein, any device performing complex number multiplication may be used as the distortion compensator 2130 and the error compensator 2151.
At this point, since the received data correspond to data modulated to VSB type data, 8-level scattered data exist only in the real number element. Therefore, referring to FIG. 42, all of the signals used in the noise canceller 2160 and the decision unit 2170 correspond to real number (or in-phase) signals. However, in order to estimate and compensate the remaining carrier phase error and the phase noise, both real number (in-phase) element and imaginary number (quadrature) element are required. Therefore, the remaining carrier phase error remover 2150 receives and uses the quadrature element as well as the in-phase element. Generally, prior to performing the channel equalization process, the demodulator 902 within the receiving system performs frequency and phase recovery of the carrier. However, if a remaining carrier phase error that is not sufficiently compensated is inputted to the channel equalizer, the performance of the channel equalizer may be deteriorated. Particularly, in a dynamic channel environment, the remaining carrier phase error may be larger than in a static channel environment due to the frequent and sudden channel changes. Eventually, this acts as an important factor that deteriorates the receiving performance of the present invention.
Furthermore, a local oscillator (not shown) included in the receiving system should preferably include a single frequency element. However, the local oscillator actually includes the desired frequency elements as well as other frequency elements. Such unwanted (or undesired) frequency elements are referred to as phase noise of the local oscillator. Such phase noise also deteriorates the receiving performance of the present invention. It is difficult to compensate such remaining carrier phase error and phase noise from the general channel equalizer. Therefore, the present invention may enhance the channel equaling performance by including a carrier recovery loop (i.e., a remaining carrier phase error remover 2150) in the channel equalizer, as shown in FIG. 42, in order to remove the remaining carrier phase error and the phase noise.
More specifically, the receiving data demodulated in FIG. 42 are overlapped by the overlap unit 2101 of the first frequency domain converter 2100 at a pre-determined overlapping ratio, which are then outputted to the FFT unit 2102. The FFT unit 2102 converts the overlapped time domain data to overlapped frequency domain data through by processing the data with FFT. Then, the converted data are outputted to the distortion compensator 2130. The distortion compensator 2130 performs a complex number multiplication on the overlapped frequency domain data outputted from the FFT unit 2102 included in the first frequency domain converter 2100 and the equalization coefficient calculated from the coefficient calculator 2122, thereby compensating the channel distortion of the overlapped data outputted from the FFT unit 2102. Thereafter, the compensated data are outputted to the IFFT unit 2141 of the time domain converter 2140. The IFFT unit 2141 performs IFFT on the overlapped data having the channel distortion compensated, thereby converting the overlapped data to time domain data, which are then outputted to the error compensator 2151 of the remaining carrier phase error remover 2150.
The error compensator 2151 multiplies a signal compensating the estimated remaining carrier phase error and phase noise with the valid data extracted from the time domain. Thus, the error compensator 2151 removes the remaining carrier phase error and phase noise included in the valid data. The data having the remaining carrier phase error compensated by the error compensator 2151 are outputted to the remaining carrier phase error estimator 2152 in order to estimate the remaining carrier phase error and phase noise and, at the same time, outputted to the noise canceller 2160 in order to remove (or cancel) the noise.
The remaining carrier phase error estimator 2152 uses the output data of the error compensator 2151 and the decision data of the decision unit 2170 to estimate the remaining carrier phase error and phase noise. Thereafter, the remaining carrier phase error estimator 2152 outputs a signal for compensating the estimated remaining carrier phase error and phase noise to the error compensator 2151. In this embodiment of the present invention, an inverse number of the estimated remaining carrier phase error and phase noise is outputted as the signal for compensating the remaining carrier phase error and phase noise.
FIG. 43 illustrates a detailed block diagram of the remaining carrier phase error estimator 2152 according to an embodiment of the present invention. Herein, the remaining carrier phase error estimator 2152 includes a phase error detector 2211, a loop filter 2212, a numerically controlled oscillator (NCO) 2213, and a conjugator 2214. Referring to FIG. 43, the decision data, the output of the phase error detector 2211, and the output of the loop filter 2212 are all real number signals. And, the output of the error compensator 2151, the output of the NCO 2213, and the output of the conjugator 2214 are all complex number signals.
The phase error detector 2211 receives the output data of the error compensator 2151 and the decision data of the decision unit 2170 in order to estimate the remaining carrier phase error and phase noise. Then, the phase error detector 2211 outputs the estimated remaining carrier phase error and phase noise to the loop filter. The loop filter 2212 then filters the remaining carrier phase error and phase noise, thereby outputting the filtered result to the NCO 2213. The NCO 2213 generates a cosine corresponding to the filtered remaining carrier phase error and phase noise, which is then outputted to the conjugator 2214.
The conjugator 2214 calculates the conjugate value of the cosine wave generated by the NCO 2213. Thereafter, the calculated conjugate value is outputted to the error compensator 2151. At this point, the output data of the conjugator 2214 becomes the inverse number of the signal compensating the remaining carrier phase error and phase noise. In other words, the output data of the conjugator 2214 becomes the inverse number of the remaining carrier phase error and phase noise.
The error compensator 2151 performs complex number multiplication on the equalized data outputted from the time domain converter 2140 and the signal outputted from the conjugator 2214 and compensating the remaining carrier phase error and phase noise, thereby removing the remaining carrier phase error and phase noise included in the equalized data. Meanwhile, the phase error detector 2211 may estimate the remaining carrier phase error and phase noise by using diverse methods and structures. According to this embodiment of the present invention, the remaining carrier phase error and phase noise are estimated by using a decision-directed method.
If the remaining carrier phase error and phase noise are not included in the channel-equalized data, the decision-directed phase error detector according to the present invention uses the fact that only real number values exist in the correlation values between the channel-equalized data and the decision data. More specifically, if the remaining carrier phase error and phase noise are not included, and when the input data of the phase error detector 2211 are referred to as xi+jxq, the correlation value between the input data of the phase error detector 2211 and the decision data may be obtained by using Equation 8 shown below:

E{(xi+jxq)({circumflex over (x)}i+j{circumflex over (x)}q)*}  Equation 8

At this point, there is no correlation between x; and xq. Therefore, the correlation value between xi and xq is equal to 0. Accordingly, if the remaining carrier phase error and phase noise are not included, only the real number values exist herein. However, if the remaining carrier phase error and phase noise are included, the real number element is shown in the imaginary number value, and the imaginary number element is shown in the real number value. Thus, in this case, the imaginary number element is shown in the correlation value. Therefore, it can be assumed that the imaginary number portion of the correlation value is in proportion with the remaining carrier phase error and phase noise. Accordingly, as shown in Equation 9 below, the imaginary number of the correlation value may be used as the remaining carrier phase error and phase noise.

Phase Error=imag{(xi+jxq)({circumflex over (x)}i+j{circumflex over (x)}q)*}

Phase Error=xq{circumflex over (x)}i−xi{circumflex over (x)}q  Equation 9

FIG. 44 illustrates a block diagram of a phase error detector 2211 obtaining the remaining carrier phase error and phase noise. Herein, the phase error detector 2211 includes a Hilbert converter 2311, a complex number configurator 2312, a conjugator 2313, a multiplier 2314, and a phase error output 2315. More specifically, the Hilbert converter 2311 creates an imaginary number decision data {circumflex over (x)}q by performing a Hilbert conversion on the decision value {circumflex over (x)}i of the decision unit 2170. The generated imaginary number decision value is then outputted to the complex number configurator 2312. The complex number configurator 2312 uses the decision data {circumflex over (x)}i and {circumflex over (x)}q to configure the complex number decision data {circumflex over (x)}i+j{circumflex over (x)}q, which are then outputted to the conjugator 2313. The conjugator 2313 conjugates the output of the complex number configurator 2312, thereby outputting the conjugated value to the multiplier 2314. The multiplier 2314 performs a complex number multiplication on the output data of the error compensator 2151 and the output data {circumflex over (x)}i−j{circumflex over (x)}q of the conjugator 2313, thereby obtaining the correlation between the output data xi+jxq of the error compensator 2151 and the decision value {circumflex over (x)}i−j{circumflex over (x)}q of the decision unit 2170. The correlation data obtained from the multiplier 2314 are then inputted to the phase error output 2315. The phase error output 2315 outputs the imaginary number portion xq{circumflex over (x)}i−xi{circumflex over (x)}q of the correlation data outputted from the multiplier 2314 as the remaining carrier phase error and phase noise.
The phase error detector shown in FIG. 44 is an example of a plurality of phase error detecting methods. Therefore, other types of phase error detectors may be used in the present invention. Therefore, the present invention is not limited only to the examples and embodiments presented in the description of the present invention. Furthermore, according to another embodiment of the present invention, at least 2 phase error detectors are combined so as to detect the remaining carrier phase error and phase noise. Accordingly, the output of the remaining carrier phase error remover 2150 having the detected remaining carrier phase error and phase noise removed as described above, is configured of an addition of the original (or initial) signal having the channel equalization, the remaining carrier phase error and phase noise, and the signal corresponding to a white noise being amplified to a colored noise during the channel equalization.
Therefore, the noise canceller 2160 receives the output data of the remaining carrier phase error remover 2150 and the decision data of the decision unit 2170, thereby estimating the colored noise. Then, the noise canceller 2160 subtracts the estimated colored noise from the data having the remaining carrier phase error and phase noise removed therefrom, thereby removing the noise amplified during the equalization process. The data having the noise removed (or cancelled) by the noise canceller 2160 are outputted for the data decoding process and, at the same time, outputted to the decision unit 2170.
The decision unit 2170 selects one of a plurality of pre-determined decision data sets (e.g., 8 decision data sets) that is most approximate to the output data of the noise canceller 2160, thereby outputting the selected data to the remaining carrier phase error estimator 2152 and the noise canceller 2160. Meanwhile, the received data are inputted to the overlap unit 2101 of the first frequency domain converter 2100 included in the channel equalizer and, at the same time, inputted to the CIR estimator 2111 of the channel estimator 2110. The CIR estimator 2111 uses a training sequence, for example, data being inputted during the known data section and the known data in order to estimate the CIR, thereby outputting the estimated CIR to the phase compensator 2112. Herein, the known data correspond to reference known data generated during the known data section by the receiving system in accordance with an agreement between the receiving system and the transmitting system.
Furthermore, in this embodiment of the present invention, the CIR estimator 2111 estimates the CIR by using the least square (LS) method. The LS estimation method calculates a cross correlation value p between the known data that have passed through the channel during the known data section and the known data that are already known by the receiving end. Then, a cross correlation matrix R of the known data is calculated. Subsequently, a matrix operation is performed on R−1·p so that the cross correlation portion within the cross correlation value p between the received data and the initial known data, thereby estimating the CIR of the transmission channel.
The phase compensator 2112 compensates the phase change of the estimated CIR. Then, the phase compensator 2112 outputs the compensated CIR to the linear interpolator 2113. At this point, the phase compensator 2112 may compensate the phase change of the estimated CIR by using a maximum likelihood method. More specifically, the remaining carrier phase error and phase noise that are included in the demodulated received data and, therefore, being inputted change the phase of the CIR estimated by the CIR estimator 2111 at a cycle period of one known data sequence. At this point, if the phase change of the inputted CIR, which is to be used for the linear interpolation process, is not performed in a linear form due to a high rate of the phase change, the channel equalizing performance of the present invention may be deteriorated when the channel is compensated by calculating the equalization coefficient from the CIR, which is estimated by a linear interpolation method.
Therefore, the present invention removes (or cancels) the amount of phase change of the CIR estimated by the CIR estimator 2111 so that the distortion compensator 2130 allows the remaining carrier phase error and phase noise to bypass the distortion compensator 2130 without being compensated. Accordingly, the remaining carrier phase error and phase noise are compensated by the remaining carrier phase error remover 2150. For this, the present invention removes (or cancels) the amount of phase change of the CIR estimated by the phase compensator 2112 by using a maximum likelihood method. The basic idea of the maximum likelihood method relates to estimating a phase element mutually (or commonly) existing in all CIR elements, then to multiply the estimated CIR with an inverse number of the mutual (or common) phase element, so that the channel equalizer, and most particularly, the distortion compensator 2130 does not compensate the mutual phase element.
More specifically, when the mutual phase element is referred to as θ, the phase of the newly estimated CIR is rotated by θ as compared to the previously estimated CIR. When the CIR of a point t is referred to as hi(t), the maximum likelihood phase compensation method obtains a phase θML corresponding to when hi(t) is rotated by θ, the squared value of the difference between the CIR of hi(t) and the CIR of hi(t+1), i.e., the CIR of a point (t+1), becomes a minimum value. Herein, when i represents a tap of the estimated CIR, and when N represents a number of taps of the CIR being estimated by the CIR estimator 2111, the value of θML is equal to or greater than 0 and equal to or less than N−1. This value may be calculated by using Equation 10 shown below:




  
    
      
        
          θ
          ML
        
        =
        
          
            
              
                min
              
            
            
              
                θ
              
            
          
          ⁢
          
            
              ∑
              
                i
                =
                0
              
              
                N
                -
                1
              
            
            ⁢
            
              
                
                
                  
                    
                      
                        h
                        i
                      
                      ⁡
                      
                        (
                        t
                        )
                      
                    
                    ⁢
                    
                      e
                      jθ
                    
                  
                  -
                  
                    
                      h
                      i
                    
                    ⁡
                    
                      (
                      
                        t
                        +
                        1
                      
                      )
                    
                  
                
                
              
              2
            
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        10
      
    
  




Herein, in light of the maximum likelihood method, the mutual phase element θML is equal to the value of θ, when the right side of Equation 10 being differentiated with respect to θ is equal to 0. The above-described condition is shown in Equation 11 below:




  
    
      
        
          
            
              
                
                  d
                  
                    d
                    θ
                  
                
                ⁢
                
                  
                    ∑
                    
                      i
                      =
                      0
                    
                    
                      N
                      -
                      1
                    
                  
                  ⁢
                  
                    
                      
                      
                        
                          
                            
                              
                                
                                  
                                    h
                                    i
                                  
                                  ⁡
                                  
                                    (
                                    t
                                    )
                                  
                                
                                ⁢
                                
                                  e
                                  jθ
                                
                              
                              -
                            
                          
                        
                        
                          
                            
                              
                                h
                                i
                              
                              ⁡
                              
                                (
                                
                                  t
                                  +
                                  1
                                
                                )
                              
                            
                          
                        
                      
                      
                    
                    2
                  
                
              
              =
              
              ⁢
              
                
                  d
                  
                    d
                    θ
                  
                
                ⁢
                
                  
                    ∑
                    
                      i
                      =
                      0
                    
                    
                      N
                      -
                      1
                    
                  
                  ⁢
                  
                    
                      (
                      
                        
                          
                            
                              
                                
                                  
                                    h
                                    i
                                  
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                                i
                              
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                      )
                    
                    ⁢
                    
                      
                        (
                        
                          
                            
                              
                                
                                  
                                    
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                                      i
                                    
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              =
              
              ⁢
              
                
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                      i
                      =
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                      N
                      -
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                  ⁢
                  
                    {
                    
                      
                        
                          
                            
                              
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                                +
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                  }
                
              
            
          
        
        
          
            
              =
              
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                  ⁢
                  
                    
                      ∑
                      
                        i
                        =
                        0
                      
                      
                        N
                        -
                        1
                      
                    
                    ⁢
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      Im
                      ⁢
                      
                        
                      
                      ⁢
                      
                        {
                        
                          
                            
                              h
                              i
                              *
                            
                            ⁡
                            
                              (
                              t
                              )
                            
                          
                          ⁢
                          
                            
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                              i
                            
                            ⁡
                            
                              (
                              
                                t
                                +
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                              -
                              jθ
                            
                          
                        
                        }
                      
                    
                  
                
                =
                0
              
            
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        11
      
    
  




The above Equation 11 may be simplified as shown in Equation 12 below:




  
    
      
        
          
            Im
            ⁢
            
              
            
            ⁢
            
              {
              
                
                  e
                  
                    -
                    jθ
                  
                
                ⁢
                
                  
                    ∑
                    
                      i
                      =
                      0
                    
                    
                      N
                      -
                      1
                    
                  
                  ⁢
                  
                    {
                    
                      
                        
                          h
                          i
                          *
                        
                        ⁡
                        
                          (
                          t
                          )
                        
                      
                      ⁢
                      
                        
                          h
                          i
                        
                        ⁡
                        
                          (
                          
                            t
                            +
                            1
                          
                          )
                        
                      
                    
                    }
                  
                
              
              }
            
          
          =
          0
        
        ⁢
        
          

        
        ⁢
        
          
            θ
            ML
          
          =
          
            arg
            ⁢
            
              
            
            ⁢
            
              (
              
                
                  ∑
                  
                    i
                    =
                    0
                  
                  
                    N
                    -
                    1
                  
                
                ⁢
                
                  
                    
                      h
                      i
                      *
                    
                    ⁡
                    
                      (
                      t
                      )
                    
                  
                  ⁢
                  
                    
                      h
                      i
                    
                    ⁡
                    
                      (
                      
                        t
                        +
                        1
                      
                      )
                    
                  
                
              
              )
            
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        12
      
    
  




More specifically, Equation 12 corresponds to the θML value that is to be estimated by the argument of the correlation value between hi(t) and hi(t+1).
FIG. 45 illustrates a phase compensator according to an embodiment of the present invention, wherein the mutual phase element θML is calculated as described above, and wherein the estimated phase element is compensated at the estimated CIR. Referring to FIG. 45, the phase compensator includes a correlation calculator 2410, a phase change estimator 2420, a compensation signal generator 2430, and a multiplier 2440. The correlation calculator 2410 includes a first N symbol buffer 2411, an N symbol delay 2412, a second N symbol buffer 2413, a conjugator 2414, and a multiplier 2415. More specifically, the first N symbol buffer 2411 included in the correlation calculator 2410 is capable of storing the data being inputted from the CIR estimator 2111 in symbol units to a maximum limit of N number of symbols. The symbol data being temporarily stored in the first N symbol buffer 2411 are then inputted to the multiplier 2415 included in the correlation calculator 2410 and to the multiplier 2440.
At the same time, the symbol data being outputted from the CIR estimator 2111 are delayed by N symbols from the N symbol delay 2412. Then, the delayed symbol data pass through the second N symbol buffer 2413 and inputted to the conjugator 2414, so as to be conjugated and then inputted to the multiplier 2415. The multiplier 2415 multiplies the output of the first N symbol buffer 2411 and the output of the conjugator 2414. Then, the multiplier 2415 outputs the multiplied result to an accumulator 2421 included in the phase change estimator 2420. More specifically, the correlation calculator 2410 calculates a correlation between a current CIR hi(t+1) having the length of N and a previous CIR hi(t) also having the length of N. then, the correlation calculator 2410 outputs the calculated correlation value to the accumulator 2421 of the phase change estimator 2420.
The accumulator 2421 accumulates the correlation values outputted from the multiplier 2415 during an N symbol period. Then, the accumulator 2421 outputs the accumulated value to the phase detector 2422. The phase detector 2422 then calculates a mutual phase element θML from the output of the accumulator 2421 as shown in the above-described Equation 11. Thereafter, the calculated θML value is outputted to the compensation signal generator 2430. The compensation signal generator 2430 outputs a complex signal ejθML having a phase opposite to that of the detected phase as the phase compensation signal to the multiplier 2440. The multiplier 2440 multiplies the current CIR hi(t+1) being outputted from the first N symbol buffer 2411 with the phase compensation signal ejθML, thereby removing the amount of phase change of the estimated CIR.
As described above, the phase compensator 2112 using the maximum likelihood method calculates a phase element corresponding to the correlation value between the inputted CIR and the previous CIR being delayed by N symbols. Thereafter, the phase compensator 2112 generates a phase compensation signal having a phase opposite to that of the phase element calculated as described above. Subsequently, the phase compensator 2112 multiplies the generated phase compensation signal to the estimated CIR, thereby removing the amount of phase change of the estimated CIR. The CIR having the phase change compensated is inputted to the linear interpolator 2113. The linear interpolator 2113 linearly interpolates the CIRs having the phase changes compensated to the second frequency domain converter 2121.
More specifically, the linear interpolator 2113 receives the CIR having the phase change compensated from the phase compensator 2112. Accordingly, during the known data section, the linear interpolator 2113 outputs the received CIR, and during the data section in-between known data, the CTR is interpolated in accordance with a pre-determined interpolating method. Thereafter, the interpolated CIR is outputted. In this embodiment of the present invention, a linear interpolation method, which is one of the many pre-determined interpolating methods, is used to interpolate the CIRs. Herein, the present invention may also use other interpolation methods. Therefore, the present invention is not limited only to the examples given in the description of the present invention.
The second frequency domain converter 2121 performs FFT on the CIR being outputted from the linear interpolator 2113, thereby converting the CIR to a frequency domain CIR. Then, the second frequency domain converter 2121 outputs the converted CIR to the coefficient calculator 2122. The coefficient calculator 2122 uses the frequency domain CIR being outputted from the second frequency domain converter 2121 to calculate the equalization coefficient. Then, the coefficient calculator 2122 outputs the calculated coefficient to the distortion compensator 2130. Herein, for example, the coefficient calculator 2122 calculates a channel equalization coefficient of the frequency domain that can provide minimum mean square error (MMSE) from the CIR of the frequency domain, which is outputted to the distortion compensator 2130. The distortion compensator 2130 performs a complex number multiplication on the overlapped data of the frequency domain being outputted from the FFT unit 2102 of the first frequency domain converter 2100 and the equalization coefficient calculated by the coefficient calculator 2122, thereby compensating the channel distortion of the overlapped data being outputted from the FFT unit 2102.
Meanwhile, if the data being inputted to the block decoder 905 after being channel equalized from the equalizer 903 correspond to the mobile service data having additional encoding and trellis encoding performed thereon by the transmitting system, trellis decoding and additional decoding processes are performed on the inputted data as inverse processes of the transmitting system. Alternatively, if the data being inputted to the block decoder 905 correspond to the main service data having only trellis encoding performed thereon, and not the additional encoding, only the trellis decoding process is performed on the inputted data as the inverse process of the transmitting system. The data group decoded by the block decoder 905 is inputted to the data deformatter 906, and the main service data packet is inputted to the data deinterleaver 909.
More specifically, if the inputted data correspond to the main service data, the block decoder 905 performs Viterbi decoding on the inputted data so as to output a hard decision value or to perform a hard-decision on a soft decision value, thereby outputting the result. Meanwhile, if the inputted data correspond to the mobile service data, the block decoder 905 outputs a hard decision value or a soft decision value with respect to the inputted mobile service data. In other words, if the inputted data correspond to the mobile service data, the block decoder 905 performs a decoding process on the data encoded by the block processor and trellis encoding module of the transmitting system.
At this point, the RS frame encoder of the pre-processor included in the transmitting system may be viewed as an external code. And, the block processor and the trellis encoder may be viewed as an internal code. In order to maximize the performance of the external code when decoding such concatenated codes, the decoder of the internal code should output a soft decision value. Therefore, the block decoder 905 may output a hard decision value on the mobile service data. However, when required, it may be more preferable for the block decoder 905 to output a soft decision value.
Meanwhile, the data deinterleaver 909, the RS decoder 910, and the derandomizer 911 are blocks required for receiving the main service data. Therefore, the above-mentioned blocks may not be required in the structure of a digital broadcast receiving system that only receives the mobile service data. The data deinterleaver 909 performs an inverse process of the data interleaver included in the transmitting system. In other words, the data deinterleaver 909 deinterleaves the main service data outputted from the block decoder 905 and outputs the deinterleaved main service data to the RS decoder 910. The RS decoder 910 performs a systematic RS decoding process on the deinterleaved data and outputs the processed data to the derandomizer 911. The derandomizer 911 receives the output of the RS decoder 910 and generates a pseudo random data byte identical to that of the randomizer included in the digital broadcast transmitting system. Thereafter, the derandomizer 911 performs a bitwise exclusive OR (XOR) operation on the generated pseudo random data byte, thereby inserting the MPEG synchronization bytes to the beginning of each packet so as to output the data in 188-byte main service data packet units.
Meanwhile, the data being outputted from the block decoder 905 to the data deformatter 906 are inputted in the form of a data group. At this point, the data deformatter 906 already knows the structure of the data that are to be inputted and is, therefore, capable of identifying the signaling information, which includes the system information, and the mobile service data from the data group. Thereafter, the data deformatter 906 outputs the identified signaling information to a block for system information and outputs the identified mobile service data to the RS frame decoder 907. At this point, the data deformatter 906 removes the known data, trellis initialization data, and MPEG header that were inserted in the main service data and data group. The data deformatter 906 also removes the RS parity that was added by the RS encoder/non-systematic RS encoder or the non-systematic RS encoder of the transmitting system. Thereafter, the processed data are outputted to the RS frame decoder 907. More specifically, the RS frame decoder 907 receives only the RS encoded and CRC encoded mobile service data that are transmitted from the data deformatter 906.
The RS frame encoder 907 performs an inverse process of the RS frame encoder included in the transmitting system so as to correct the error within the RS frame. Then, the RS frame decoder 907 adds the 1-byte MPEG synchronization service data packet, which had been removed during the RS frame encoding process, to the error-corrected mobile service data packet. Thereafter, the processed data packet is outputted to the derandomizer 908. The operation of the RS frame decoder 907 will be described in detail in a later process. The derandomizer 908 performs a derandomizing process, which corresponds to the inverse process of the randomizer included in the transmitting system, on the received mobile service data. Thereafter, the derandomized data are outputted, thereby obtaining the mobile service data transmitted from the transmitting system.
FIG. 46 illustrates a series of exemplary step of an error correction decoding process of the RS frame decoder 907 according to the present invention. More specifically, the RS frame decoder 907 groups mobile service data bytes received from the data deformatter 906 so as to configure an RS frame. The mobile service data correspond to data RS encoded and CRC encoded from the transmitting system. FIG. 46(a) illustrates an example of configuring the RS frame. More specifically, the transmitting system divided the RS frame having the size of (N+2)*235 to 30*235 byte blocks. When it is assumed that each of the divided mobile service data byte blocks is inserted in each data group and then transmitted, the receiving system also groups the 30*235 mobile service data byte blocks respectively inserted in each data group, thereby configuring an RS frame having the size of (N+2)*235. For example, when it is assumed that an RS frame is divided into 18 30*235 byte blocks and transmitted from a burst section, the receiving system also groups the mobile service data bytes of 18 data groups within the corresponding burst section, so as to configure the RS frame. Furthermore, when it is assumed that N is equal to 538 (i.e., N=538), the RS frame decoder 907 may group the mobile service data bytes within the 18 data groups included in a burst so as to configure a RS frame having the size of 540*235 bytes.
Herein, when it is assumed that the block decoder 905 outputs a soft decision value for the decoding result, the RS frame decoder 907 may decide the ‘0’ and ‘1’ of the corresponding bit by using the codes of the soft decision value. 8 bits that are each decided as described above are grouped to create 1 data byte. If the above-described process is performed on all soft decision values of the 18 data groups included in a single burst, the RS frame having the size of 540*235 bytes may be configured. Additionally, the present invention uses the soft decision value not only to configure the RS frame but also to configure a reliability map. Herein, the reliability map indicates the reliability of the corresponding data byte, which is configured by grouping 8 bits, the 8 bits being decided by the codes of the soft decision value.
For example, when the absolute value of the soft decision value exceeds a pre-determined threshold value, the value of the corresponding bit, which is decided by the code of the corresponding soft decision value, is determined to be reliable. Conversely, when the absolute value of the soft decision value does not exceed the pre-determined threshold value, the value of the corresponding bit is determined to be unreliable. Thereafter, if even a single bit among the 8 bits, which are decided by the codes of the soft decision value and group to configure 1 data byte, is determined to be unreliable, the corresponding data byte is marked on the reliability map as an unreliable data byte.
Herein, determining the reliability of 1 data byte is only exemplary. More specifically, when a plurality of data bytes (e.g., at least 4 data bytes) are determined to be unreliable, the corresponding data bytes may also be marked as unreliable data bytes within the reliability map. Conversely, when all of the data bits within the 1 data byte are determined to be reliable (i.e., when the absolute value of the soft decision values of all 8 bits included in the 1 data byte exceed the predetermined threshold value), the corresponding data byte is marked to be a reliable data byte on the reliability map. Similarly, when a plurality of data bytes (e.g., at least 4 data bytes) are determined to be reliable, the corresponding data bytes may also be marked as reliable data bytes within the reliability map. The numbers proposed in the above-described example are merely exemplary and, therefore, do not limit the scope or spirit of the present invention.
The process of configuring the RS frame and the process of configuring the reliability map both using the soft decision value may be performed at the same time. Herein, the reliability information within the reliability map is in a one-to-one correspondence with each byte within the RS frame. For example, if a RS frame has the size of 540*235 bytes, the reliability map is also configured to have the size of 540*235 bytes. FIG. 46(a′) illustrates the process steps of configuring the reliability map according to the present invention. Meanwhile, if a RS frame is configured to have the size of (N+2)*235 bytes, the RS frame decoder 907 performs a CRC syndrome checking process on the corresponding RS frame, thereby verifying whether any error has occurred in each row. Subsequently, as shown in FIG. 46(b), a 2-byte checksum is removed to configure an RS frame having the size of N*235 bytes. Herein, the presence (or existence) of an error is indicated on an error flag corresponding to each row. Similarly, since the portion of the reliability map corresponding to the CRC checksum has hardly any applicability, this portion is removed so that only N*235 number of the reliability information bytes remain, as shown in FIG. 46(b′).
After performing the CRC syndrome checking process, the RS frame decoder 907 performs RS decoding in a column direction. Herein, a RS erasure correction process may be performed in accordance with the number of CRC error flags. More specifically, as shown in FIG. 46(c), the CRC error flag corresponding to each row within the RS frame is verified. Thereafter, the RS frame decoder 907 determines whether the number of rows having a CRC error occurring therein is equal to or smaller than the maximum number of errors on which the RS erasure correction may be performed, when performing the RS decoding process in a column direction. The maximum number of errors corresponds to a number of parity bytes inserted when performing the RS encoding process. In the embodiment of the present invention, it is assumed that 48 parity bytes have been added to each column.
If the number of rows having the CRC errors occurring therein is smaller than or equal to the maximum number of errors (i.e., 48 errors according to this embodiment) that can be corrected by the RS erasure decoding process, a (235,187)-RS erasure decoding process is performed in a column direction on the RS frame having 235 N-byte rows, as shown in FIG. 46(d). Thereafter, as shown in FIG. 46(f), the 48-byte parity data that have been added at the end of each column are removed. Conversely, however, if the number of rows having the CRC errors occurring therein is greater than the maximum number of errors (i.e., 48 errors) that can be corrected by the RS erasure decoding process, the RS erasure decoding process cannot be performed. In this case, the error may be corrected by performing a general RS decoding process. In addition, the reliability map, which has been created based upon the soft decision value along with the RS frame, may be used to further enhance the error correction ability (or performance) of the present invention.
More specifically, the RS frame decoder 907 compares the absolute value of the soft decision value of the block decoder 905 with the pre-determined threshold value, so as to determine the reliability of the bit value decided by the code of the corresponding soft decision value. Also, 8 bits, each being determined by the code of the soft decision value, are grouped to form 1 data byte. Accordingly, the reliability information on this 1 data byte is indicated on the reliability map. Therefore, as shown in FIG. 46(e), even though a particular row is determined to have an error occurring therein based upon a CRC syndrome checking process on the particular row, the present invention does not assume that all bytes included in the row have errors occurring therein. The present invention refers to the reliability information of the reliability map and sets only the bytes that have been determined to be unreliable as erroneous bytes. In other words, with disregard to whether or not a CRC error exists within the corresponding row, only the bytes that are determined to be unreliable based upon the reliability map are set as erasure points.
According to another method, when it is determined that CRC errors are included in the corresponding row, based upon the result of the CRC syndrome checking result, only the bytes that are determined by the reliability map to be unreliable are set as errors. More specifically, only the bytes corresponding to the row that is determined to have errors included therein and being determined to be unreliable based upon the reliability information, are set as the erasure points. Thereafter, if the number of error points for each column is smaller than or equal to the maximum number of errors (i.e., 48 errors) that can be corrected by the RS erasure decoding process, an RS erasure decoding process is performed on the corresponding column. Conversely, if the number of error points for each column is greater than the maximum number of errors (i.e., 48 errors) that can be corrected by the RS erasure decoding process, a general decoding process is performed on the corresponding column.
More specifically, if the number of rows having CRC errors included therein is greater than the maximum number of errors (i.e., 48 errors) that can be corrected by the RS erasure decoding process, either an RS erasure decoding process or a general RS decoding process is performed on a column that is decided based upon the reliability information of the reliability map, in accordance with the number of erasure points within the corresponding column. For example, it is assumed that the number of rows having CRC errors included therein within the RS frame is greater than 48. And, it is also assumed that the number of erasure points decided based upon the reliability information of the reliability map is indicated as 40 erasure points in the first column and as 50 erasure points in the second column. In this case, a (235,187)-RS erasure decoding process is performed on the first columns Alternatively, a (235,187)-RS decoding process is performed on the second column. When error correction decoding is performed on all column directions within the RS frame by using the above-described process, the 49-byte parity data which were added at the end of each column are removed, as shown in FIG. 46(f).
As described above, even though the total number of CRC errors corresponding to each row within the RS frame is greater than the maximum number of errors that can be corrected by the RS erasure decoding process, when the number of bytes determined to have a low reliability level, based upon the reliability information on the reliability map within a particular column, while performing error correction decoding on the particular column. Herein, the difference between the general RS decoding process and the RS erasure decoding process is the number of errors that can be corrected. More specifically, when performing the general RS decoding process, the number of errors corresponding to half of the number of parity bytes (i.e., (number of parity bytes)/2) that are inserted during the RS encoding process may be error corrected (e.g., 24 errors may be corrected). Alternatively, when performing the RS erasure decoding process, the number of errors corresponding to the number of parity bytes that are inserted during the RS encoding process may be error corrected (e.g., 48 errors may be corrected).
After performing the error correction decoding process, as described above, a RS frame configured of 187 N-byte rows (or packets) maybe obtained, as shown in FIG. 46(f). Furthermore, the RS frame having the size of N*187 bytes is sequentially outputted in N number of 187-byte units. Herein, as shown in FIG. 46(g), the 1-byte MPEG synchronization byte that was removed by the transmitting system is added at the end of each 187-byte packet, thereby outputting 188-byte mobile service data packets.
As described above, the digital broadcasting system and the data processing method according to the present invention have the following advantages. More specifically, the digital broadcasting receiving system and method according to the present invention is highly protected against (or resistant to) any error that may occur when transmitting mobile service data through a channel. And, the present invention is also highly compatible to the conventional receiving system. Moreover, the present invention may also receive the mobile service data without any error even in channels having severe ghost effect and noise. Additionally, by inserting known data in a particular position (or place) within a data region and transmitting the processed data, the receiving performance of the receiving system may be enhanced even in a channel environment that is liable to frequent changes. Also, by multiplexing mobile service data with main service data into a burst structure, the power consumption of the receiving system may be reduced.
Moreover, by having the receiving system use the known data information to perform channel equalization, the channel equalization process may be performed with more stability. Particularly, by performing different channel equalization processes in accordance with the characteristic of each region within the data group being divided into a plurality of regions, the channel equalization process may be performed with more stability in each region, thereby enhancing the receiving performance of the present invention. Further, by estimating a remaining carrier phase error and by compensating the estimated remaining carrier phase error from the channel-equalized signal, the receiving performance of the present invention may be even more enhanced. Finally, the present invention is even more effective when applied to mobile and portable receivers, which are also liable to a frequent change in channel and which require protection (or resistance) against intense noise.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

## Claims

1. A digital broadcast transmitter, comprising:
a pre-processor configured to pre-process mobile service data, the mobile service data being included in a first data group, wherein the pre-processor is further configured to de-interleave the first data group to output a second data group, the first data group having first and second segments, the first segments having first known data, the second segments having second known data, the number of data bytes for the first known data being different from the number of data bytes for the second known data, M second segments being positioned between an Nth first segment and an (N+k)th first segment, L second segments being positioned between the (N+k)th first segment and (N+k+i)th first segment, wherein M, L, N, k and i are natural numbers, M≠L, and each packet in the second data group has a length of 207 bytes; and
a multiplexer configured to multiplex mobile service data packets having the mobile service data with main service data packets having main service data.

2. A digital broadcast receiver, comprising:
a tuner configured to receive a DTV signal comprising main service data and mobile service data multiplexed with the main service data, wherein the DTV signal results from generating a second data group by de-interleaving a first data group by a DTV transmitter, the first data group having first and second segments, the first segments having first known data, the second segments having second known data, the number of data bytes for the first data being different from the number of data bytes for the second data, M second segments being positioned between an Nth first segment and an (N+k)th first segment, L second segments being positioned between the (N+k)th first segment and (N+k+i)th first segment, wherein M, L, N, k and i are natural numbers, M≠L, and each packet in the second data group has a length of 207 bytes;
a demodulator configured to demodulate the DTV signal; and
a decoder configured to decode the demodulated DTV signal.

3. A method of processing a DTV signal in a digital broadcast transmitter, comprising:
pre-processing mobile service data, the mobile service data being included in a first data group, wherein a second data group is generated from de-interleaving the first data group, the first data group having first and second segments, the first segments having first known data, the second segments having second known data, the number of data bytes for the first known data being different from the number of data bytes for the second known data, M second segments being positioned between an Nth first segment and an (N+k)th first segment, L second segments being positioned between the (N+k)th first segment and (N+k+i)th first segment, wherein M, L, N, k and i are natural numbers, M#L, and each packet in the second data group has a length of 207 bytes; and
multiplexing mobile service data packets having the mobile service data with main service data packets having main service data.

4. A method of processing a DTV signal in a digital broadcast receiver, comprising:
receiving a DTV signal comprising main service data and mobile service data multiplexed with the main service data, wherein the DTV signal results from generating a second data group by de-interleaving a first data group by a DTV transmitter, the first data group having first and second segments, the first segments having first known data, the second segments having second known data, the number of data bytes for the first known data being different from the number of data bytes for the second known data, M second segments being positioned between an Nth first segment and an (N+k)th first segment, L second segments being positioned between the (N+k)th first segment and (N+k+i)th first segment, wherein M, L, N, k and i are natural numbers, M≠L, and each packet in the second data group has a length of 207 bytes;
demodulating the DTV signal; and
decoding the demodulated DTV signal.