# Patent

## Title
Stacked semiconductor devices

## Abstract

A stacked semiconductor device includes a first and a second semiconductor device. A first major surface of each of the first and second devices which includes the active circuitry directly face each other. The first major surface of each of the devices includes a beveled edge on at least one edge, and a probe pad which extends onto the beveled edge. A first opening is located between the beveled edges of the first and second devices on a vertical side of the stacked semiconductor device.

## Background
BACKGROUND
1. Field of the Invention
This invention relates in general to semiconductor devices and more specifically to stacking multiple semiconductor devices.
2. Description of the Related Art
Conventional through-silicon-via (TSV) plugs for die stacking are formed at the single wafer level. The die are then interconnected into a stack with an interconnection at each wafer or die face. Height is added to the stack as a result of the bump standoff height at each die-to-die transition. Electrically, each interface contributes to reflections and added impedance which together reduce the high frequency signal integrity. Additionally, it is always desirable to dissipate heat from semiconductor devices to achieve smaller device sizes and higher frequency operation. In particular, stacked die generate heat in a small volume requiring additional thermal paths for heat dissipation.



BRIEF DESCRIPTION OF THE DRAWINGS
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
FIG. 1 is a partial side cross-sectional view of a semiconductor device after a phase of manufacture in accordance with an embodiment of the present invention.
FIG. 2 is a partial side cross-sectional view of the semiconductor device of FIG. 1 after another phase of manufacture.
FIG. 3 is a partial side cross-sectional view of the semiconductor device of FIG. 2 after another phase of manufacture.
FIG. 4 is a partial side cross-sectional view of the semiconductor device of FIG. 3 after another phase of manufacture.
FIG. 5 is a partial side cross-sectional view of the semiconductor device of FIG. 4 after another phase of manufacture.
FIG. 6 is a partial top view of the semiconductor device of FIG. 5.
FIG. 7 is a partial side cross-sectional view of a group of stacked semiconductor device in accordance with an embodiment of the invention.
FIG. 8 is a partial side cross-sectional view of a group of stacked semiconductor device with continuous-fill vias, test probe, and heat sink structure in accordance with an embodiment of the invention.
FIG. 9 is a flow diagram of an embodiment of a method for forming the semiconductor device of FIGS. 1-8.



The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The features shown in the Figures are not necessarily drawn to scale.
DETAILED DESCRIPTION
The following sets forth a detailed description of a mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting.
Embodiments of a contiguous via plug through a die stack are disclosed that reduce the stack height and also improve high speed signaling performance. Thermal performance is improved by dissipating heat from conductive planes formed with beveled edges with a self-aligning heat sink. The beveled edges of the die also accommodate a self-aligning test probe that can be used to test functionality of the stacked semiconductor die.
FIG. 1 is a partial side cross-sectional view of an embodiment of semiconductor wafer 100 after a phase of manufacture that includes a semiconductor substrate 102 on which active surface and interconnect region 103 is formed that includes components such as N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors 104, capacitors, resistors, diodes, photo-diodes, fuses 105, and the like, interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only to further explain applications of the present invention and are not meant to limit the present invention in any manner. Other circuitry may be used as appropriate for a given application.
One or more layers of interconnects 106 can be formed to electrically couple active circuit components to other internal and/or external components. Electrical devices may also be formed in one or more dielectric layers. A dielectric or other insulating material can be formed in one or more layers as active surface and interconnect region 103 is formed to electrically isolate components from one another. A last layer of conductive interconnects including capture pads 108 is covered with passivation layer 110. Passivation layer 110 can be made of inorganic and/or organic layer of material such as silicon nitride, polyimide, or benzocyclobutene, to name a few.
Capture pads 108 and other interconnects may be formed, for example, by using photolithography techniques to deposit and pattern a photoresist material on an interlayer dielectric (ILD) material to expose portions of the ILD layer that are to become capture pads 108 and/or other interconnects. An etch process, such as an anisotropic dry etch process, may be used to create openings in the ILD layer. The openings can be lined with a diffusion barrier layer and/or an adhesion layer (not shown), and filled with a conductive material. The diffusion barrier layer can include one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, and the conductive material can include copper, tungsten, aluminum, silver, and combinations thereof, or the like.
Substrate 102 may comprise, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used.
A grid of die 111 may be formed on wafer 100, with die 111 separated from one another by scribe streets 112. Individual, independent semiconductor devices are formed by separating die 111 along scribe streets 112 once processing is completed.
FIG. 2 is a partial side cross-sectional view of the wafer 100 of FIG. 1 after another phase of manufacture in which V-shaped bevels 114 are formed through passivation layer 110 and a portion of active surface and interconnect region 103 that is adjacent to passivation layer 110. Bevels 114 can be formed can be formed along horizontal and vertical scribe streets 112 using a saw, laser, or other suitable equipment. Any suitable dimension of bevel 114 to form test probe pads on exposed surfaces of the bevel can be used, and can be based on the size of the probe to be used during wafer testing. For example, for a probe with a contact tip that is 25 microns in diameter, bevels 114 can be approximately 70 microns in length along a bevel 114 that is angled, for example at 45 degrees, to the top surface of the semiconductor device. For a 25 micron diameter probe tip, a probe pad (not shown) formed on the bevel 114 can be 45 microns in width and spaced at least 5 microns from the next closest probe pad on the bevel. Other suitable dimensions can be used for the probe contact tip and probe pads.
FIG. 3 is a partial side cross-sectional view of the wafer 100 of FIG. 2 after another phase of manufacture in which openings 116 are formed around an opening 117 in capture pads 108. Openings 116 typically are larger than and extend beyond the opening 117 in capture pads 108. Openings 117 can be in the range of 2-20 microns in diameter and openings 116 can be in the range of 5-60 microns, or other suitable dimensions. Depending on the material used for passivation layer 110, openings 116 can be formed using a standard etch and/or photoimageable or patterning techniques.
FIG. 4 is a partial side cross-sectional view of the wafer 100 of FIG. 3 after another phase of manufacture in which a patterned conductive layer including contact pads 118 are formed over edge bevels 114, capture pads 108, and portions of passivation layer 110, but not over openings 116 in capture pads 108. The patterned conductive layer also includes conductive planes 120 patterned over other portions of passivation layer 110 with gaps 121 in the conductive layer to separate contact pads 118 from conductive planes 120. A portion of contact pads 118 are in contact with the exposed portion of capture pads 108 around opening 117 in capture pads 108. The conductive material can include copper, tungsten, aluminum, silver, and combinations thereof, or the like that is formed with electroplating, sputtering, or other suitable process. Contact pads 118 and conductive planes 120 form a top layer of wafer 100.
FIG. 5 is a partial side cross-sectional view A-A′ of the wafer 100 of FIG. 6 after another phase of manufacture in which openings 116 are extended to create openings 502 for through substrate vias through active surface and interconnect region 103 and substrate 102. Openings 502 may be formed by etching or other suitable technique. It should be understood that the etch processes may be accomplished in single etch processes or multiple etch processes. It should also be understood that the openings 502 may be formed by other methods, such as milling, laser techniques, or the like.
Once openings 502 are formed, a layer of electrical isolation material such as an insulator layer 122 is formed on the sidewalls of openings 502. Insulator layer 122 may be formed using a CVD, spin-on coating or epitaxial process to form a dielectric layer that covers the sidewalls of the openings 116. The dielectric constant of the insulator layer 122 can be less than about 6 or other suitable value and may be formed, for example, of materials used to form interconnects, by any suitable method known in the art. Other suitable materials and application methods may be used for insulator layer 122. The insulator 122 also provides additional isolation between the conductive material and the substrate 102 thereby achieving a reduction in capacitance along the sidewall of the TSV. Furthermore, the relatively thin isolation structure of insulator 122 creates an increased effective area the conductive material of through silicon vias (TSV) 802 (FIG. 8), thus increasing the effectiveness of the TSV 802.
FIG. 6 is a partial top view of single die 111 of FIG. 5. Contact pads 118 are formed with a circular portion 602 having central opening 117, and a rectangular pad 604 extending from a subsection of the outer edge of circular portion 602 to bevels 114 (FIG. 5). Other suitable shapes for contact pads 118 and openings 117 can be used. Gaps 121 between contact pads 118 and conductive plane 120 extend around the circular portion 602 of contact pads 118 to separate contact pads 118 from conductive plane 120. Conductive plane 120 typically covers inner sections of die 111 around contact pads 118, and in some sections, covers edge bevels 114. Die 111 will typically be independent of other circuitry/die on the wafer 100 after die 111 is singulated along scribe lines 112.
FIG. 7 is a partial side cross-sectional view of a semiconductor device 700 that includes a group of stacked die 111 in wafers 100 in accordance with an embodiment of the invention in which openings 116, 502 (FIG. 5) are aligned and coincident with one another to form a continuous opening through two or more die 111 in the stack. The top layer 126 of each wafer 100 faces the top layer 126 of an adjacent wafer 100. The bottoms of substrate 102 of wafer 100 in the inner layers 706 face the bottoms of another wafer 100, while the bottom of the substrate 102 of wafer 100 at the top and bottom of semiconductor device 700 face outward and are thus exposed to the external environment. V-shaped openings 702 are formed by pairs of edge bevels 114 (FIGS. 1-5) around the edges of the top layers 126 of wafers 100. Enlarged areas 704 are formed in the inner layers of semiconductor device 700 at the top of the openings 116 (FIG. 5) surrounded by contact pads 118 aligned and pairs of edge bevels 114 facing one another to form V-shaped openings 702.
The top layers 126 of wafers 100 may be joined using a suitable adhesive insulating material 710 such as glass, epoxy, polyimide, acrylic, silicone, or other suitable attachment, bonding or fastening technique. The bottom sides of wafers 100 may be joined to one another using a layer of adhesive 712 such as insulative materials like glass, epoxy, polyimide, acrylic, silicone, or conductive attachment material, such as solder or eutectic alloys, or other suitable attachment, bonding, mounting, or fastening techniques.
FIG. 8 is a partial side cross-sectional view of semiconductor device 700 of FIG. 7 with openings 116, 502 (FIG. 5) filled with conductive material after wafers 100 are stacked with openings 116, 502 aligned. Conductive material forms continuous through-silicon vias (TSVs) 802 through at least 2 of the stacked die 111 the semiconductor device 700. A greater amount of conductive material collects at enlarged areas 704 than in the rest of openings 116, 117, 502, thereby strengthening and improving the reliability of electrical coupling between the contact pads 118 of facing wafers 100.
Any suitable material for conducting electrical and/or optical signals can be used to form TSVs 802 in openings 116, 117, 502, such as copper, copper alloys, aluminum, tungsten, silver, polysilicon, silicon, conductive polymers, doped carbon nanotubes, polyacrylates, polystyrenics, and combinations thereof. In one embodiment at least one via comprises an electrically conducting material and at least on other via comprises an optically conductive material such as silicon. One alternative is forming the conductive material in openings 116, 117, 502 by depositing a seed layer and then performing an electroplating process. Other alternatives that can be used to form the conductive material in TSVs 802 include: fusible metal powder such as titanium or molybdenum powder; plastic balls coated with a conductive material, such as the Micropearl SOL product from Sekisui America Corporation in Mt. Laurel, N.J.; reinforced solder columns, such as those available from Six Sigma Corporation in Milpitas, Calif.; a core wire inserted through openings 116 as a seed layer combined with copper, conductive polymer, or other suitable electroplating process; and/or nickel nanotubes or nanotubes formed of carbon that can be doped with iodine or bromine to achieve the desired conductive properties
Once wafers 100 are stacked, the TSVs 802 are formed, and the die 111 are singulated, openings 702 are formed between the die 111 by bevels 114 Test probe 804 can be used to test the functionality of wafers 100 individually by aligning the probe 804 to the openings 702 and contacting at least one contact pad a bevel 114 on die 111. The tip 805 of probe 804 can be V-shaped so that probe 804 will be aligned with respect to opening 702. Since there are edge bevels 114 between each pair of wafers 100, all wafers 100 can be tested by probe 804 independently of one another as long as the tip 805 of probe 804 is only coupling to one side or probe pad of the edge bevel 702 that corresponds to the wafer 100 being tested.
When two die 111 are stacked face to face, a first die 111 is in a first orientation and a second die 111 is in a mirror image orientation relative to the first die. Die 111 can be configured so that the capture pads 108 for the first die 111 align to the mirror imaged capture pads 108 of the second die 111. In one embodiment capture pads 108 are aligned to the center spine of the die 111 so the capture pads 108 will align to corresponding inputs or outputs of the two die 111 after stacking. In some embodiments, capture pads 108 functionally coupling address or data signals may be placed symmetrically away from the center spine of die 111 so that when active surfaces of first and second die 111 are stacked face to face, a first capture pad 108 coupling to first address input of said first die 111 will couple to a second address input of said second die 111 and second capture pads 108 of said first die 111 will couple to a first data input of said first die 111 and to a second data input of said second die 111.
Note that wafers 100 can be singulated, or separated into stacks of die 111 to allow individual stacks of die 111 to be tested. Thus in some embodiments, the term semiconductor device 700 as used herein can be considered a stack of die 111 or a stack of wafers 100. Additionally, some wafers 100 or die 111 in a stack may not include edge bevels 114, but may still be interspersed in a stack of wafers 100 and die 11 with edge bevels 114.
Once testing is complete, probe 804 can be used to selectively apply current to program fuses in the semiconductor device 700. Heat sink structure 806 can be attached to opening 702 on one or more sides 807 of semiconductor device 700. Heat sink structure 806 can have one or more protruding portions 808 that are spaced and shaped to Thermally couple to the inner surfaces of corresponding openings 702 when heat sink structure 806 is positioned adjacent to semiconductor device 700. A layer of thermally conductive material 810 can be positioned between heat sink 806 and semiconductor device 700 to improve heat transfer from the device to the heat sink. Conductive material 810 can include protruding portions 812 that are spaced and shaped to contact inner surfaces of corresponding openings 702 when heat sink structure 806 is positioned adjacent to semiconductor device 700. The heat sink may comprise an electrically conductive material or an insulating material. The heat sink 806 can be formed of aluminum, aluminum alloys, copper, copper alloys, boron nitride, aluminum nitride, diamond, carbon nanotubes, and combinations thereof. The thermally conductive material 810 can be a silicone or epoxy-resin based material containing suspended carbon nanotubes, or beryllium oxide, aluminum nitride, boron nitride, or diamond powders. In other embodiments, the thermally conductive material can be a phase-change metal alloy, a graphene-based adhesive or the like. In one embodiment the heat sink thermally couples to conductive plane 120 for improved heat removal.
FIG. 9 is a flow diagram of an embodiment of a method for forming semiconductor device 700 starting with wafer 100 of FIG. 1 in process 902. The wafer has been processed to include one or more layers of active circuitry and interconnects. A layer of passivation material is typically applied over the circuitry and interconnects. Process 904 includes forming bevels along vertical and horizontal scribe lines of the wafer using a laser, saw, or other suitable equipment. The bevels can have a V-shape or other suitable shape. Process 906 includes forming openings in the passivation material to expose openings in capture pads that have been formed in the last or uppermost metal layer of the wafer. The openings in the passivation material are typically larger than the openings in the capture pads to allow portions of a patterned conductive layer to contact capture pads when the conductive layer is formed in process 908. The conductive layer typically includes contact pads and conductive planes that are separated from one another by gaps in the conductive material. The contact pads are patterned over bevels 114 and at least some of the capture pads. The conductive planes may be formed over other capture pads as required by the circuitry on the wafer. The openings in the capture pads are left uncovered by the passivation material and the conductive layer, however.
Process 910 can include extending the openings in the capture pads through the other layers of the wafer to form through substrate vias (TSVs). Process 912 can include forming an electrical isolation layer on the sidewalls of the TSVs by depositing insulating material, epitaxially growing insulating material, or other suitable technique.
Process 914 includes forming a stack of wafers so that the openings in the TSVs are aligned in a continuous column through the stack. If the wafers have been singulated into individual die, then the die may be stacked so that the openings in the TSVs are aligned in a continuous column through the stack.
Process 916 includes filling the TSVs with conductive material using electroplating, fusible metal powder, plastic balls coated with a conductive material, reinforced solder columns, a core wire inserted through the openings as a seed layer combined with copper, conductive polymer, or other suitable electroplating process; and/or nanotubes formed of carbon or metals, as just some examples. Other suitable techniques and materials for filling the TSVs can be used. The conductive material forms a continuous conductive path through the TSVs with additional build-up of conductive material at the openings between TSVs on each die (as shown for example by enlarged areas 704 in FIGS. 7 and 8).
If the wafers have not already been singulated into individual die, then the stacked die may be singulated in process 918 after the TSVs are filled with conductive material. Since the V-shaped grooves in the scribe streets are covered with conductive material, probe pads are exposed at the edge bevels once the die are singulated.
Process 920 includes probing the stacked semiconductor device by inserting one or more probe tips into a respective opening between the edge bevels. The probe tips electrically contact at least one of the probe pads for a pair of wafers or die in the stack to test functionality of each wafer or die. Additionally, if the active circuitry of the semiconductor devices includes one or more fuses coupled to a respective probe pad, current may be selectively applied to the probe pad(s) via the probe(s) to program the fuses
After test probing, process 922 can include attaching a heat sink to the vertical side of the stacked semiconductor device. The heat sink can comprise one or more protruding portions that are inserted into the beveled edges of the stacked semiconductor device to contact the probe pads of respective semiconductor devices. Further, a layer of thermally conductive material may be inserted between the stacked semiconductor device and the heat sink to improve heat transfer. The thermally conductive material may be configured to conform to the protrusions that contact the probe pads at the edge bevels of the stack to increase the amount of area from which heat may be dissipated from the stacked semiconductor device.
By now it should be appreciated that an embodiment of a stacked semiconductor device 700, 800 can comprise a first semiconductor device 111 having a first major surface and a second major surface opposite the first major surface. The first major surface of the first semiconductor device 111 having: active circuitry 103; a beveled edge 114 on at least one edge of the first semiconductor device 111; and a probe pad which extends onto the beveled edge 114 of the first semiconductor device 111. A second semiconductor device 111 can include a first major surface and a second major surface opposite the first major surface, the first major surface of the second semiconductor device 111 having: active circuitry 103; a beveled edge 114 on at least one edge of the second semiconductor device 111; and a probe pad which extends onto the beveled edge 114 of the second semiconductor device 111. The first major surface of the first semiconductor device 111 faces the first major surface of the second semiconductor device 111 such that the first major surfaces of the first and second semiconductor devices 111 are between the second major surfaces of the first and second semiconductor devices 111 and wherein the beveled edge 114 of the first semiconductor device 111 faces the beveled edge 114 of the second semiconductor device 111 such that a first opening is formed between the beveled edges 114 of the first and second semiconductor devices 111 on a first vertical side of the stacked semiconductor device 700, 800.
In another aspect of the stacked semiconductor device 700, 800, the beveled edges 114 of the first opening can be capable of aligning a probe tip 805 to the probe pad of the first semiconductor device 111.
In another aspect of the stacked semiconductor device 700, 800, the probe pad of the first semiconductor device 111 can be electrically coupled to the active circuitry 103 of the first semiconductor device 111. The probe pad of the second semiconductor device 111 is electrically coupled to the active circuitry 103 of the second semiconductor device 111.
In another aspect of the stacked semiconductor device 700, 800, each of the first and second semiconductor devices 111 can comprise a conductive plane. The probe pad of the first semiconductor device 111 is electrically coupled to the conductive plane of the first semiconductor device 111. The probe pad of the second semiconductor device 111 is electrically coupled to the conductive plane of the second semiconductor device 111.
In another aspect of the stacked semiconductor device 700, 800, a heat sink 806 attached to the first vertical side of the stacked semiconductor device 700, 800. The heat sink 806 can include a first protruding portion 808 inserted into the first opening between the beveled edges 114 of the first and second semiconductor devices 111 and contacting the probe pad of each of the first and second semiconductor devices 111.
In another aspect, the stacked semiconductor device 700, 800 can include a plurality of continuous conductive vias 802. Each continuous conductive via 802 of the plurality of continuous conductive vias 802 extends from the second major surface of the first semiconductor device 111, through the first semiconductor device 111 to the first major surface of the second semiconductor device 111.
In another aspect of the stacked semiconductor device 700, 800, at least one continuous conductive via 802 of the plurality of continuous conductive vias 802 is coupled to the active circuitry 103 of each of the first and second semiconductor device 111.
In another aspect of the stacked semiconductor device 700, 800, the active circuitry 103 of the first semiconductor device 111 can comprise a fuse 105 which is coupled to the probe pad of the first semiconductor device 111 and a first continuous conductive via 802 of the plurality of continuous conductive vias 802. The active circuitry 103 of the second semiconductor device 111 comprises a fuse 105 which is coupled to the probe pad of the second semiconductor device 111 and a second continuous conductive via 802 of the plurality of conductive vias 802.
In another aspect of the stacked semiconductor device 700, 800, each of the first and second semiconductor devices 111 can be further characterized as a memory device.
In another aspect of the stacked semiconductor device 700, 800, the first major surface of the first semiconductor device 111 can have a second beveled edge 114 on at a second edge of the first semiconductor device 111 and a second probe pad which extends onto the second beveled edge 114 of the first semiconductor device 111. The first major surface of the second semiconductor device 111 has a second beveled edge 114 on at a second edge of the second semiconductor device 111 and a second probe pad which extends onto the second beveled edge 114 of the second semiconductor device 111.
In another aspect of the stacked semiconductor device 700, 800, a third semiconductor device 111 having a first major surface and a second major surface opposite the first major surface. The first major surface of the third semiconductor device 111 can include active circuitry 103; a beveled edge 114 on at least one edge of the third semiconductor device 111; and a probe pad which extends onto the beveled edge 114 of the third semiconductor device 111. A fourth semiconductor device 111 can have a first major surface and a second major surface opposite the first major surface. The first major surface of the fourth semiconductor device 111 can include active circuitry 103; a beveled edge 114 on at least one edge of the fourth semiconductor device 111; and a probe pad which extends onto the beveled edge 114 of the fourth semiconductor device 111. The first major surface of the third semiconductor device 111 faces the first major surface of the fourth semiconductor device 111 such that the first major surfaces of the third and fourth semiconductor devices 111 are between the second major surfaces of the third and fourth semiconductor devices 111 and wherein the beveled edge 114 of the third semiconductor device 111 faces the beveled edge 114 of the fourth semiconductor device 111 such that a second opening is formed between the beveled edges 114 of the third and fourth semiconductor devices 111 on the first vertical side of the stacked semiconductor device 700, 800. The second major surface of the second semiconductor device 111 faces the second major surface of the third semiconductor device 111, such that the second major surfaces of the second and third semiconductor devices 111 are between the first major surfaces of the second and third semiconductor devices 111.
In another aspect of the stacked semiconductor device 700, 800, each of third and fourth semiconductor devices 111 can comprise a conductive plane. The probe pad of the third semiconductor device 111 can be electrically coupled to the conductive plane of the third semiconductor device 111, and the probe pad of the fourth semiconductor device 111 can be electrically coupled to the conductive plane of the fourth semiconductor device 111.
In another aspect of the stacked semiconductor device 700, 800, a heat sink 806 can be attached to the first vertical side of the stacked semiconductor device 700, 800. The heat sink 806 can have a second protruding portion 808 inserted into the second opening between the beveled edges 114 of the third and fourth semiconductor devices 111 and contacting the probe pad of each of the third and fourth semiconductor devices 111.
In another embodiment, a method for probing a stacked semiconductor device 700, 800 can comprise: providing a stacked semiconductor device 700, 800, comprising: a first semiconductor device 111 having a first major surface and a second major surface opposite the first major surface, the first major surface of the first semiconductor device 111 having active circuitry 103, a beveled edge 114 on at least one edge of the first semiconductor device 111, and a probe pad which extends onto the beveled edge 114 of the first semiconductor device 111. A second semiconductor device 111 having a first major surface and a second major surface opposite the first major surface can be provided. The first major surface of the second semiconductor device 111 can have active circuitry 103, a beveled edge 114 on at least one edge of the second semiconductor device 111, and a probe pad which extends onto the beveled edge 114 of the second semiconductor device 111. The first major surface of the first semiconductor device 111 faces the first major surface of the second semiconductor device 111 such that the first major surfaces of the first and second semiconductor devices 111 are between the second major surfaces of the first and second semiconductor devices 111 and wherein the beveled edge 114 of the first semiconductor device 111 faces the beveled edge 114 of the second semiconductor device 111 such that a first opening is formed between the beveled edges 114 of the first and second semiconductor devices 111 on a first vertical side of the stacked semiconductor device 700, 800. The stacked semiconductor device 700, 800 can be probed by inserting a first probe tip 805 into the first opening, wherein the first probe tip 805 is coupled to at least one of the probe pad of the first semiconductor device 111 and the probe pad of the second semiconductor device 111.
In another aspect of the method for probing a stacked semiconductor device 700, 800, the active circuitry 103 of the first semiconductor device 111 comprises a fuse 105 which is coupled to the probe pad of the first semiconductor device 111; and the active circuitry 103 of the second semiconductor device 111 comprises a fuse 105 which is coupled to the probe pad of the second semiconductor device 111. The method further comprises: programming each of the fuses 105 of the first and second semiconductor devices 111 by selectively applying a signal to each probe pad of the first and second semiconductor devices 111.
In another aspect of the method for probing a stacked semiconductor device 700, 800, the active circuitry 103 of each of the first and second semiconductor devices 111 comprises at least one fuse 105, each of the at least one fuse 105 coupled to a corresponding probe pad extending onto a corresponding beveled edge 114. The programming comprises programming each of the plurality of fuses 105 of the first and second semiconductor devices 111 by selectively applying signals to each corresponding probe pad to program a first semiconductor device 111 address into the plurality of fuses 105 of the first semiconductor device 111, and a second semiconductor device 111 address into the plurality of fuses 105 of the second semiconductor device 111.
In another aspect of the method for probing a stacked semiconductor device 700, 800, each of the first and second semiconductor devices 111 comprises a conductive plane. The probe pad of the first semiconductor device 111 can be coupled to the conductive plane of the first semiconductor device 111. The probe pad of the second semiconductor device 111 can be coupled to the conductive plane of the second semiconductor device 111. The method can further comprise attaching a heat sink 806 to the first vertical side of the stacked semiconductor device 700, 800 after the probing. The heat sink 806 can comprise a first protruding portion 808 inserted into the first opening between the beveled edges 114 of the first and second semiconductor devices 111 and contacting the probe pad of each of the first and second semiconductor devices 111.
In yet another embodiment, a stacked semiconductor device 700, 800 can comprise a first semiconductor device 111 having a first major surface and a second major surface opposite the first major surface. The first major surface of the first semiconductor device 111 having active circuitry 103 and having a beveled edge 114 on at least one edge of the first semiconductor device 111. A second semiconductor device 111 can have a first major surface and a second major surface opposite the first major surface. The first major surface of the second semiconductor device 111 can have active circuitry 103 and a beveled edge 114 on at least one edge of the second semiconductor device 111. A third semiconductor device 111 can have a first major surface and a second major surface opposite the first major surface, the first major surface of the third semiconductor device 111 can have active circuitry 103 and a beveled edge 114 on at least one edge of the third semiconductor device 111. A fourth semiconductor device 111 can have a first major surface and a second major surface opposite the first major surface. The first major surface of the fourth semiconductor device 111 can have active circuitry 103 and having a beveled edge 114 on at least one edge of the fourth semiconductor device 111. The first major surface of the first semiconductor device 111 can face the first major surface of the second semiconductor device 111 such that the first major surfaces of the first and second semiconductor devices 111 are between the second major surfaces of the first and second semiconductor devices 111 and wherein the beveled edge 114 of the first semiconductor device 111 faces the beveled edge 114 of the second semiconductor device 111 such that a first opening is formed between the beveled edges 114 of the first and second semiconductor devices 111 on a first vertical side of the stacked semiconductor device 700, 800. The first major surface of the third semiconductor device 111 can face the first major surface of the fourth semiconductor device 111 such that the first major surfaces of the third and fourth semiconductor devices 111 are between the second major surfaces of the third and fourth semiconductor devices 111 and wherein the beveled edge 114 of the third semiconductor device 111 faces the beveled edge 114 of the fourth semiconductor device 111 such that a second opening is formed between the beveled edges 114 of the third and fourth semiconductor devices 111 on the first vertical side of the stacked semiconductor device 700, 800. The second major surface of the second semiconductor device 111 can face the second major surface of the third semiconductor device 111, such that the second major surfaces of the second and third semiconductor devices 111 are between the first major surfaces of the second and third semiconductor devices 111. A heat sink 806 can be attached to the first vertical side of the stacked semiconductor device 700, 800, the heat sink 806 having a first protruding portion 808 inserted into the first opening between the beveled edges 114 of the first and second semiconductor devices 111 and a second protruding portion 808 inserted into the second opening between the beveled edges 114 of the third and fourth semiconductor devices 111.
In another aspect, the stacked semiconductor device 700, 800 can comprise a plurality of continuous conductive vias 802, wherein each continuous conductive via 802 of the plurality of continuous conductive vias 802 extends from the second major surface of the first semiconductor device 111, through the first semiconductor device 111, second semiconductor device 111, and third semiconductor device 111.
In another aspect, at least one continuous conductive via 802 of the plurality of continuous conductive vias 802 can be electrically coupled to the active circuitry 103 at the first major surface of each of the first, second, third, and fourth semiconductor device 111.
Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
The term “coupled,” as used herein, is not intended to be limited to a direct coupling or a mechanical or optical coupling. Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

## Claims

1. A stacked semiconductor device comprising:
a first semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first semiconductor device having:
active circuitry;
a beveled edge on at least one edge of the first semiconductor device; and
a probe pad which extends onto the beveled edge of the first semiconductor device; and

a second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the second semiconductor device having:
active circuitry;
a beveled edge on at least one edge of the second semiconductor device; and
a probe pad which extends onto the beveled edge of the second semiconductor device;

wherein:
the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device such that the first major surfaces of the first and second semiconductor devices are between the second major surfaces of the first and second semiconductor devices and wherein the beveled edge of the first semiconductor device faces the beveled edge of the second semiconductor device such that a first opening is formed between the beveled edges of the first and second semiconductor devices on a first vertical side of the stacked semiconductor device.

2. The stacked semiconductor device of claim 1, wherein the beveled edges of the first opening are capable of aligning a probe tip to the probe pad of the first semiconductor device.

3. The stacked semiconductor device of claim 1, wherein:
the probe pad of the first semiconductor device is electrically coupled to the active circuitry of the first semiconductor device;
the probe pad of the second semiconductor device is electrically coupled to the active circuitry of the second semiconductor device.

4. The stacked semiconductor device of claim 1, wherein each of the first and second semiconductor devices comprises a conductive plane, wherein:
the probe pad of the first semiconductor device is electrically coupled to the conductive plane of the first semiconductor device; and
the probe pad of the second semiconductor device is electrically coupled to the conductive plane of the second semiconductor device.

5. The stacked semiconductor device of claim 4, further comprising:
a heat sink 806 attached to the first vertical side of the stacked semiconductor device, the heat sink having:
a first protruding portion inserted into the first opening between the beveled edges of the first and second semiconductor devices and contacting the probe pad of each of the first and second semiconductor devices.

6. The stacked semiconductor device of claim 1, further comprising:
a plurality of continuous conductive vias, wherein each continuous conductive via of the plurality of continuous conductive vias extends from the second major surface of the first semiconductor device, through the first semiconductor device to the first major surface of the second semiconductor device.

7. The stacked semiconductor device of claim 6, wherein at least one continuous conductive via 802 of the plurality of continuous conductive vias is coupled to the active circuitry 103 of each of the first and second semiconductor device.

8. The stacked semiconductor device of claim 6, wherein:
the active circuitry of the first semiconductor device comprises a fuse which is coupled to the probe pad of the first semiconductor device and a first continuous conductive via of the plurality of continuous conductive vias; and
the active circuitry of the second semiconductor device comprises a fuse which is coupled to the probe pad of the second semiconductor device and a second continuous conductive via of the plurality of conductive vias.

9. The stacked semiconductor device of claim 1, wherein each of the first and second semiconductor devices is further characterized as a memory device.

10. The stacked semiconductor device of claim 1, wherein:
the first major surface of the first semiconductor device has a second beveled edge on at a second edge of the first semiconductor device and a second probe pad which extends onto the second beveled edge of the first semiconductor device; and
the first major surface of the second semiconductor device has a second beveled edge on at a second edge of the second semiconductor device and a second probe pad which extends onto the second beveled edge of the second semiconductor device.

11. The stacked semiconductor device of claim 1, further comprising:
a third semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the third semiconductor device having:
active circuitry;
a beveled edge on at least one edge of the third semiconductor device; and
a probe pad which extends onto the beveled edge of the third semiconductor device;

a fourth semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the fourth semiconductor device having:
active circuitry;
a beveled edge on at least one edge of the fourth semiconductor device; and
a probe pad which extends onto the beveled edge of the fourth semiconductor device;

wherein:
the first major surface of the third semiconductor device faces the first major surface of the fourth semiconductor device such that the first major surfaces of the third and fourth semiconductor devices are between the second major surfaces of the third and fourth semiconductor devices and wherein the beveled edge of the third semiconductor device faces the beveled edge of the fourth semiconductor device such that a second opening is formed between the beveled edges of the third and fourth semiconductor devices on the first vertical side of the stacked semiconductor device; and
the second major surface of the second semiconductor device faces the second major surface of the third semiconductor device, such that the second major surfaces of the second and third semiconductor devices are between the first major surfaces of the second and third semiconductor devices.

12. The stacked semiconductor device of claim 11, wherein each of third and fourth semiconductor devices comprises a conductive plane, wherein:
the probe pad of the third semiconductor device is electrically coupled to the conductive plane of the third semiconductor device;
the probe pad of the fourth semiconductor device is electrically coupled to the conductive plane of the fourth semiconductor device.

13. The stacked semiconductor device of claim 12, further comprising:
a heat sink attached to the first vertical side of the stacked semiconductor device, the heat sink having:
a second protruding portion inserted into the second opening between the beveled edges of the third and fourth semiconductor devices and contacting the probe pad of each of the third and fourth semiconductor devices.

14. A stacked semiconductor device comprising:
a first semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the first semiconductor device having active circuitry and having a beveled edge on at least one edge of the first semiconductor device;
a second semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the second semiconductor device having active circuitry and having a beveled edge on at least one edge of the second semiconductor device;
a third semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the third semiconductor device having active circuitry and having a beveled edge on at least one edge of the third semiconductor device;
a fourth semiconductor device having a first major surface and a second major surface opposite the first major surface, the first major surface of the fourth semiconductor device having active circuitry and having a beveled edge on at least one edge of the fourth semiconductor device, wherein:
the first major surface of the first semiconductor device faces the first major surface of the second semiconductor device such that the first major surfaces of the first and second semiconductor devices are between the second major surfaces of the first and second semiconductor devices and wherein the beveled edge of the first semiconductor device faces the beveled edge of the second semiconductor device such that a first opening is formed between the beveled edges of the first and second semiconductor devices on a first vertical side of the stacked semiconductor device;
the first major surface of the third semiconductor device faces the first major surface of the fourth semiconductor device such that the first major surfaces of the third and fourth semiconductor devices are between the second major surfaces of the third and fourth semiconductor devices and wherein the beveled edge of the third semiconductor device faces the beveled edge of the fourth semiconductor device such that a second opening is formed between the beveled edges of the third and fourth semiconductor devices on the first vertical side of the stacked semiconductor device; and
the second major surface of the second semiconductor device faces the second major surface of the third semiconductor device, such that the second major surfaces of the second and third semiconductor devices are between the first major surfaces of the second and third semiconductor devices;

a heat sink 806 attached to the first vertical side of the stacked semiconductor device, the heat sink having a first protruding portion inserted into the first opening between the beveled edges of the first and second semiconductor devices and a second protruding portion inserted into the second opening between the beveled edges of the third and fourth semiconductor devices.

15. The stacked semiconductor device of claim 14, further comprising:
a plurality of continuous conductive vias, wherein each continuous conductive via 802 of the plurality of continuous conductive vias extends from the second major surface of the first semiconductor device, through the first semiconductor device, second semiconductor device, and third semiconductor device.

16. The stacked semiconductor device of claim 15, wherein at least one continuous conductive via of the plurality of continuous conductive vias are electrically coupled to the active circuitry at the first major surface of each of the first, second, third, and fourth semiconductor device.