# Patent

## Title
Voltage control oscillator and quadrature modulator

## Abstract

A voltage control oscillator includes: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor; and a second capacitor.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. patent application Ser. No. 12/783,345 filed on May 19, 2010, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2009-198368, filed on Aug. 28, 2009; the entire contents of which are incorporated herein by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a voltage control oscillator and a quadrature modulator, and, more particularly is suitably applied to a voltage control oscillator and a quadrature modulator that can obtain oscillation outputs for four phases different from one another by 90°.
2. Description of the Related Art
In a communication system employing quadrature modulation, local oscillation signals having phases different from one another by 90° are used in both a modulating circuit in a transmitting unit and a demodulating circuit in a receiving unit. To generate such local oscillation signals, in some case, a quadrature voltage-controlled oscillator (QVCO) is used.
For example, Japanese Patent Application Laid-Open No. 2004-120728 discloses, in an LC resonant oscillator in which a plurality of capacitative elements are connected to output nodes, voltage for selecting an oscillation frequency band is applied to terminals on the opposite side of the capacitative elements, and the oscillation frequency band can be changed stepwise according to the selection voltage, a method of configuring the capacitative elements with variable capacitative elements.
However, in the QVCO in the past, the phases of the local oscillation signal are shifted from one another by 90° according to mutual inductance of an inductor connected to a source side of a certain field effect transistor and an inductor connected to a drain side of another field effect transistor. Therefore, in the QVCO in the past, when drain-to-source capacitance of the field effect transistors fluctuates, a phase error increases.
BRIEF SUMMARY OF THE INVENTION
A voltage control oscillator according to an embodiment of the present invention comprises: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor.
A quadrature modulator according to an embodiment of the present invention comprises: first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one; a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor; a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor; a third inductor magnetically coupled to the first inductor; a fourth inductor magnetically coupled to the second inductor; a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor; a first variable capacitance element connected to the one end of the third inductor; a second variable capacitance element connected to the one end of the fourth inductor; a third variable capacitance element connected to the other end of the third inductor; and a fourth variable capacitance element connected to the other end of the fourth inductor.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of the schematic configuration of a voltage control oscillator according to a first embodiment of the present invention;
FIG. 2 is a perspective view of an example of the schematic configuration of inductors L1 to L4 shown in FIG. 1;
FIGS. 3A-3E are perspective views for explaining a process for inducing an electric current flowing to the inductors L1 to L4 shown in FIG. 1;
FIGS. 3F-3J are waveform charts corresponding to FIGS. 3A-3E for explaining the process for inducing the electric current flowing to the inductors L1 to L4 shown in FIG. 1;
FIG. 4 is a diagram for explaining phase states of the electric current flowing to the inductors L1 to L4 shown in FIG. 1;
FIG. 5 is a circuit diagram of the schematic configuration of a quadrature modulator according to a second embodiment of the present invention; and
FIG. 6 is a perspective view of an example of the schematic configuration of the inductors L1 to L4 shown in FIG. 5.



DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of the present invention are explained in detail below with reference to the accompanying drawings. The present invention is not limited by the embodiments.
FIG. 1 is a circuit diagram of the schematic configuration of a voltage control oscillator according to a first embodiment of the present invention.
In FIG. 1, a drain of a field effect transistor M1 is connected to a gate of a field effect transistor M2. A drain of the field effect transistor M2 is connected to a gate of the field effect transistor M1. A drain of the field effect transistor M3 is connected to a gate of the field effect transistor M4. A drain of the field effect transistor M4 is connected to a gate of the field effect transistor M3.
An inductor L1 is connected between the drain of the field effect transistor M1 and the drain of the field effect transistor M2. An inductor L2 is connected between the drain of the field effect transistor M3 and the drain of the field effect transistor M4. An inductor L3 is magnetically coupled to the inductor L1. An inductor L4 is magnetically coupled to the inductor L2.
One end of the inductor L3 and one end of the inductor L4 are capacitively coupled via a capacitor C1. The other end of the inductor L3 and the other end of the inductor L4 are capacitively coupled via a capacitor C2.
Variable capacitance elements P1 and P2 are connected to each other in series. A series circuit of the variable capacitance elements P1 and P2 is connected between the drain of the field effect transistor M1 and the drain of the field effect transistor M2. Variable capacitance elements P3 and P4 are connected to each other in series. A series circuit of the variable capacitance elements P3 and P4 is connected between the drain of the field effect transistor M3 and the drain of the field effect transistor M4. A control signal ctrl for controlling the capacitances of the variable capacitance elements P1 to P4 can be input to a connection point of the variable capacitance elements P1 and P2 and a connection point of the variable capacitance elements P3 and P4.
A current source D is connected to the middle of the inductor L1 and the middle of the inductor L2. A node N1 is connected to the middle of the inductor L3. A node N2 is connected to the middle of the inductor L4. The nodes N1 and N2 are connected to common potential (power supply potential, ground potential, or bias potential) or in a floating state.
The drain of the field effect transistor M1 is connected to the gate of the field effect transistor M1 via the inductor L1 and the drain of the field effect transistor M2 is connected to the gate of the field effect transistor M2 via the inductor L1. Consequently, feedback of 360° is applied only on the drain sides of the field effect transistors M1 and M2. The field effect transistors M1 and M2 can oscillate.
The drain of the field effect transistor M3 is connected to the gate of the field effect transistor M3 via the inductor L2 and the drain of the field effect transistor M4 is connected the gate of the field effect transistor M4 via the inductor L2. Consequently, feedback of 360° is applied only on the drain sides of the field effect transistors M3 and M4. The field effect transistors M3 and M4 can oscillate.
When an electric current flows to the inductor L1, an oscillation signal S1 is generated. Subsequently, when a magnetic flux is generated in the inductor L1 based on the electric current flowing to the inductor L1 and the magnetic flux generated in the inductor L1 interlinks with the inductor L3 to induce an electric current in the inductor L3, an oscillation signal S2 having a phase different from that of the oscillation signal S1 by 90° is generated. When the electric current flowing to the inductor L3 flows to the inductor L4 via the capacitors C1 and C2, an oscillation signal S3 having a phase different from that of the oscillation signal S2 by 90° is generated. When a magnetic flux is generated in the inductor L4 based on the electric current flowing to the inductor L4 and the magnetic flux generated in the inductor L4 interlinks with the inductor L2 to induce an electric current in the inductor L2, an oscillation signal S4 having a phase different from that of the oscillation signal S3 by 90° is generated.
This makes it possible to generate the oscillation signals S1 to S4 having phases different from one another by 90° while applying feedback of 360° only on the drain sides of the field effect transistors M1 to M4. Therefore, it is unnecessary to apply feedback to the source sides of the field effect transistors M1 to M4. Even when drain-to-source capacitance of the field effect transistors M1 to M4 fluctuates, it is possible to reduce a phase error of the oscillation signals S1 to S4.
FIG. 2 is a perspective view of an example of the schematic configuration of the inductors L1 to L4 shown in FIG. 1.
In FIG. 2, the field effect transistors M1 to M4 and wires H1 to H4 are formed on a semiconductor chip S1. The wires H1 and H2 are formed in a loop shape. The wires H1 and H2 are arranged in parallel to each other. Gaps G1 and G2 are respectively formed in the wires H1 and H2.
The wires H3 and H4 are formed in a loop shape. Gaps G3 and G4 are formed between the wires H3 and H4. Capacitive elements or variable capacitance elements can also be used instead of the gaps G3 and G4. The wires H1 and H3 are arranged to overlap each other. The wires H2 and H4 are arranged to overlap each other. The wires H1 and H2 can be placed on the wires H3 and H4 or the wires H3 and H4 can be placed on the wires H1 and H2. The wires H1 to H4 can be made of metal such as Al or Cu. The wires H1 to H4 can be integrated on a semiconductor chip on which the field effect transistors M1 to M4 are formed.
The wire H1 can form the inductor L1 shown in FIG. 1. The wire H2 can form the inductor L2 shown in FIG. 1. The wire H3 can form the inductor L3 shown in FIG. 1. The wire H4 can form the inductor L4 shown in FIG. 1. The gap G3 can form the capacitor C1 shown in FIG. 1. The gap G4 can form the capacitor C2 shown in FIG. 2.
FIGS. 3A-3E are perspective views for explaining a process for inducing an electric current flowing to the inductors L1 to L4 shown in FIG. 1. FIGS. 3F-3J are waveform charts of an induced current corresponding to the inducing process shown in FIGS. 3A-3E. FIG. 4 is a diagram for explaining phase states of the electric current flowing to the inductors L1 to L4 shown in FIG. 1.
In FIG. 3A, FIG. 3F, and FIG. 4, when voltage V1 is applied to the gap G1 of the wire H1 shown in FIG. 2, an electric field E1 is generated in the wire H1. When an electric current I1 flows to the wire H1, a magnetic flux φ1 is generated in the wire H1. When magnetic flux density at this point is represented as B1 and an interlink area is represented as S, the magnetic flux φ1 is given by φ1=B1S. A relation among the voltage V1, the electric field E1, the electric current I1, and the magnetic flux density B1 can be given by the following formula, where, μ represents magnetic permeability and H1 represents the intensity of a magnetic field:



  
    
      V
      1
    
    ≈
    
      E
      1
    
    ≈
    
      
        ∂
        
          
            I
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      
        ∂
        t
      
    
  




  
    
      
        ∂
        
          
            V
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      
        ∂
        t
      
    
    ∝
    
      
        ∮
        C
      
      ⁢
      
        
          H
          ->
        
        ·
        
          d
          
            s
            ->
          
        
      
    
  



As shown in FIG. 3B and FIG. 3G, when the magnetic flux φ1 generated in the wire H1 interlinks with the wire H3, an electric current I2 having a phase different from that of the electric current I1 by 90° is induced in the wire H3. Charge Q1 is accumulated in the gaps G3 and G4 between the wires H3 and H4 and a charge-up voltage V2 is generated. The electric current I2 induced in the wire H3 can be given by the following formula:




  
    I
    2
  
  =
  
    -
    
      
        ∂
        
          
            φ
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      
        ∂
        t
      
    
  




As shown in FIG. 3C and FIG. 3H, when the charge Q1 is accumulated in the gaps G3 and G4 between the wires H3 and H4, the charge Q1 is discharged to the wire H4. Then, an electric current I3 having a phase different from that of the electric current I2 by 90° flows to the wire H4. The electric current I3 flowing to the wire H4 can be given by the following formula:




  
    I
    3
  
  =
  
    
      
        ∂
        
          
            Q
            1
          
          ⁡
          
            (
            t
            )
          
        
      
      
        ∂
        t
      
    
    =
    
      C
      ⁢
      
        
          ∂
          
            
              V
              2
            
            ⁡
            
              (
              t
              )
            
          
        
        
          ∂
          t
        
      
    
  




Subsequently, as shown in FIG. 3D and FIG. 3I, when the electric current I3 flows to the wire H4, a magnetic flux φ2 is generated in the wire H4. Voltage V3 is generated between both ends of the wire H4 and an electric field is generated in the wire H4. When magnetic flux density at this point is represented as B2 and an interlink area is represented as S, φ2 is given by φ2=B2S.
A relation among the voltage V3, the electric field E2, and the electric current I3 can be given by the following formula:



  
    
      V
      3
    
    ≈
    
      E
      2
    
    ≈
    
      
        ∂
        
          
            I
            3
          
          ⁡
          
            (
            t
            )
          
        
      
      
        ∂
        t
      
    
  




  
    
      
        ∂
        
          
            V
            3
          
          ⁡
          
            (
            t
            )
          
        
      
      
        ∂
        t
      
    
    ∝
    
      
        ∮
        C
      
      ⁢
      
        
          H
          ->
        
        ·
        
          d
          
            s
            ->
          
        
      
    
  



As shown in FIG. 3E and FIG. 3J, when the magnetic flux φ2 generated in the wire H4 interlinks with the wire H2, an electric current I4 having a phase different from that of the electric current I3 by 90° is induced in the wire H2. The electric current I4 induced in the wire H2 can be given by the following formula:




  
    I
    4
  
  =
  
    -
    
      
        ∂
        
          
            φ
            2
          
          ⁡
          
            (
            t
            )
          
        
      
      
        ∂
        t
      
    
  




As a result, even when feedback of 360° is applied only on the drain sides of the field effect transistors M1 to M4 shown in FIG. 1, it is possible to generate the oscillation signals S1 to S4 having phases different from one another by 90°. Therefore, it is possible to reduce a phase error due to fluctuation in drain-to-source capacitance of the field effect transistors M1 to M4. In the embodiment explained above, the method of integrating the inductors L1 to L4 on the semiconductor chip on which the field effect transistors M1 to M4 are formed is explained as an example. However, the configuration of the inductors L1 to L4 can be discrete.
FIG. 5 is a circuit diagram of the schematic configuration of a quadrature modulator according to a second embodiment of the present invention.
In FIG. 5, in the quadrature modulator, variable capacitance elements E1 to E4 are provided in addition to the components shown in FIG. 1. One end of the inductor L3 and one end of the inductor L4 are capacitively coupled via the variable capacitance elements E1 and E2. The other end of the inductor L3 and the other end of the inductor L4 are capacitively coupled via the variable capacitance elements E3 and E4. A control signal ctrlQ for controlling the capacitance of the variable capacitance elements E1 and E2 is input to a connection point of the variable capacitance elements E1 and E2. A control signal ctrlI for controlling the capacitance of the variable capacitance elements E3 and E4 is input to a connection point of the variable capacitance elements E3 and E4.
This makes it possible to generate quadrature modulation signals I and Q having phases different from each other by 90° while reducing a phase error.
FIG. 6 is a perspective view of an example of the schematic configuration of the inductors L1 to L4 shown in FIG. 5.
In FIG. 6, the field effect transistors M1 to M4, the wires H1 to H4, and the variable capacitance elements E1 to E4 are formed on a semiconductor chip S2.
One end of the wire H3 and one end of the wire H4 are capacitively coupled via the variable capacitance elements E1 and E2. The other end of the wire H3 and the other end of the wire H4 are capacitively coupled via the variable capacitance elements E3 and E4.
This makes it possible to integrate the inductors L1 to L4 and the variable capacitance elements E1 to E4 on the semiconductor chip S2 on which the field effect transistors M1 to M4 are formed.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

## Claims

1. A voltage control oscillator comprising:
first and second field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one;
third and fourth field effect transistors, a drain of one of which is connected to a gate of the other and a drain of the other of which is connected to a gate of the one;
a first inductor connected between the drain of the first field effect transistor and the drain of the second field effect transistor;
a second inductor connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor;
a third inductor magnetically coupled to the first inductor;
a fourth inductor magnetically coupled to the second inductor;
a first capacitor that capacitively couples one end of the third inductor and one end of the fourth inductor; and
a second capacitor that capacitively couples the other end of the third inductor and the other end of the fourth inductor; wherein
a first wire forms the first inductor and is formed in a loop shape;
a second wire forms the second inductor and is formed in a loop shape in parallel to the first wire;
first and second gaps respectively separate the first and second wires;
third and fourth wires respectively form the third inductor and the fourth inductor and are formed in a loop shape to respectively overlap the first and second wires; and
third and fourth gaps respectively form the first capacitor and the second capacitor and separate the third and fourth wires.

2. The voltage control oscillator according to claim 1, further comprising:
a current source connected to a middle of the first inductor and a middle of the second inductor;
a first node that connects a middle of the third inductor to common potential or a floating state; and
a second node that connects a middle of the fourth inductor to common potential or a floating state.

3. The voltage control oscillator according to claim 2, further comprising:
first and second variable capacitance elements connected between the drain of the first field effect transistor and the drain of the second field effect transistor and connected to each other in series; and
third and fourth variable capacitance elements connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor and connected to each other in series.

4. The voltage control oscillator according to claim 3, wherein
a first magnetic flux is generated in the first inductor when a first electric current flows to the first inductor,
a second electric current having a phase different from that of the first electric current by 90° is induced in the third inductor when the first magnetic flux generated in the first inductor interlinks with the third inductor,
a third electric current having a phase different from that of the second electric current by 90° is generated when the second electric current flows to the fourth inductor via the first and second capacitors,
a second magnetic flux is generated in the fourth inductor when the third electric current flows to the fourth inductor, and
a fourth electric current having a phase different from that of the third electric current by 90° is induced in the second inductor when the second magnetic flux generated in the fourth inductor interlinks with the second inductor.

5. The voltage control oscillator according to claim 1, further comprising:
first and second variable capacitance elements connected between the drain of the first field effect transistor and the drain of the second field effect transistor and connected to each other in series; and
third and fourth variable capacitance elements connected between the drain of the third field effect transistor and the drain of the fourth field effect transistor and connected to each other in series.

6. The voltage control oscillator according to claim 5, wherein
a first magnetic flux is generated in the first inductor when a first electric current flows to the first inductor,
a second electric current having a phase different from that of the first electric current by 90° is induced in the third inductor when the first magnetic flux generated in the first inductor interlinks with the third inductor,
a third electric current having a phase different from that of the second electric current by 90° is generated when the second electric current flows to the fourth inductor via the first and second capacitors,
a second magnetic flux is generated in the fourth inductor when the third electric current flows to the fourth inductor, and
a fourth electric current having a phase different from that of the third electric current by 90° is induced in the second inductor when the second magnetic flux generated in the fourth inductor interlinks with the second inductor.

7. The voltage control oscillator according to claim 1, wherein
a first magnetic flux is generated in the first inductor when a first electric current flows to the first inductor,
a second electric current having a phase different from that of the first electric current by 90° is induced in the third inductor when the first magnetic flux generated in the first inductor interlinks with the third inductor,
a third electric current having a phase different from that of the second electric current by 90° is generated when the second electric current flows to the fourth inductor via the first and second capacitors,
a second magnetic flux is generated in the fourth inductor when the third electric current flows to the fourth inductor, and
a fourth electric current having a phase different from that of the third electric current by 90° is induced in the second inductor when the second magnetic flux generated in the fourth inductor interlinks with the second inductor.