# Patent

## Title
Air cell thermal isolation for a memory array formed of a programmable resistive material

## Abstract

A memory device includes, a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surface and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cylindrical cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cap layer, composed of dielectric fill material, extend between the first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element.

## Background
REFERENCE TO RELATED APPLICATION
This application claims the benefit of U.S. Provisional Patent Application No. 60/739,089, entitled “Air Cell Thermal Isolation for a Phase Change Memory Array” filed on Nov. 21, 2005. That application is incorporated by reference for all purposes.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally related to the field of non-volatile memory devices, and more particularly to the field of memory devices that employ programmable resistive materials.
2. Description of Related Art
Materials that have the property of changing resistive state from a high value to a low value in a rapid, predictable fashion have found wide use. Because both states are stable, such materials lend themselves to memory-oriented applications. One important class of such materials are those that accomplish the resistance shift by changing phase.
Phase change based memory materials are widely used in read-write optical disks, and such materials are seeing increasing use in computer memory devices. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change, and electrical pulses are employed for the same purpose in integrated circuit memory devices.
Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, and resistance of the material can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.
One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000, and Reinberg, “Chalcogenide Memory Cell with a Plurality of Chalcogenide Electrodes,” U.S. Pat. No. 5,920,788, issued Jul. 6, 1999.
A specific issue arising from conventional the phase change memory and structures is the heat sink effect of conventional designs. Generally, the prior art teaches the use of metallic electrodes on both sides of the phase change memory element, with electrodes of approximately the same size as the phase change member. Such electrodes act as heat sinks, the high heat conductivity of the metal rapidly drawing heat away from the phase change material. Because the phase change occurs as a result of heating, the heat sink effect results in a requirement for higher current, in order to effect the desired phase change.
One approach to the heat flow problem is seen in U.S. Pat. No. 6,815,704, entitled “Self Aligned Air-Gap Thermal Insulation for Nano-scale Insulated Chalcogenide Electronics (NICE) RAM”, in which an attempt is made to isolate the memory cell. That structure, and the attendant fabrication process, is overly complex, yet it does not promote minimal current flow in the memory device.
It is desirable therefore to provide a memory cell structure having small dimensions and low reset currents, as well as a structure that addresses the heat conductivity problem, and a method for manufacturing such structure that meets tight process variation specifications needed for large-scale memory devices. It is further desirable to provide a manufacturing process and a structure, which are compatible with manufacturing of peripheral circuits on the same integrated circuit.
SUMMARY OF THE INVENTION
An aspect of the invention is a memory device. The device includes a first electrode element, generally planar in form, having an inner contact surface. Then there is a cylindrical cap layer, spaced from the first electrode element, and a phase change element having contact surfaces in contact with the first electrode contact surfaces and the cap layer, in which the lateral dimension of the phase change element is less than that of the first electrode element and the cap layer. A second electrode element extends through the cap layer to make contact with the phase change element. Side walls aligned with the cylindrical lateral surface of the cap layer, composed of dielectric fill material, extend between the first electrode element and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas filled thermal isolation cell adjacent the phase change element.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view that illustrates an embodiment of a phase change memory element employing an air cell thermal isolation element.
FIG. 1a illustrates a current path in a phase change memory element as shown in FIG. 1.
FIG. 2 schematically illustrates a circuit employing the phase change memory element of FIG. 1.
FIG. 3 illustrates a memory array employing the phase change memory element as shown in FIG. 1.
FIGS. 4a-4h illustrate an embodiment of a process for fabricating a phase change memory element as shown in FIG. 1.



DETAILED DESCRIPTION
The following discussion describes embodiments of the invention with reference to the Figures. It will be understood that the examples and features shown are exemplary and illustrative in nature and not intended to limit the scope of the invention. That scope is defined solely by the claims appended hereto.
The present invention concerns memory elements and memory cells. As used herein, and as is well known in the art, a memory cell is a circuit device designed to have an alterable characteristic to indicate the logic level representing one bit or multiple bits of data per cell. Memory cells are arrayed to provide, for example, the random access memory for a computer.
A memory element 10, an embodiment of the present invention, is illustrated generally in FIG. 1. As seen there, the memory element 10 is shown as a single unit, for purposes of clarity. In practice, each element is a part of a memory cell, which in turn is part of a larger memory array, as will be seen more fully below. The structure of a memory element will be discussed first, followed by a description of the process for fabricating the same.
The memory element 10 is formed on a substrate 12, which is preferably a dielectric fill material such as silicon dioxide formed over a semiconductor substrate which may have logic circuitry integrated therein to support access to the device. A lower electrode 14, preferably formed from a metal such as tungsten, is formed on a contact 13 in the substrate 12. Other suitable metals include Ti, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru. The memory element 10 is separated from other such elements by a dielectric material which appears as partitions 16 in cross-section, which extend from the substrate 12 upward to the height of the memory element 10. The dielectric material of the partitions 16 can comprise a variety of suitable low-k dielectric materials, such as silicon dioxide, silicon oxynitride, silicon nitride or Al2O3, as known in the art.
A pillar-shaped stack of materials on the lower electrode 14 includes a phase change element 22, an insulating cap layer 20, and an insulating spacer 26 with an electrode element 30 extending through the insulating spacer 26 and insulating cap layer 22 at the top of the phase change element 22. The cap layer 20 has a cylindrical lateral surface with a maximum lateral dimension. In preferred embodiments, the cap layer 20 has a circularly cylindrical, or approximately circularly cylindrical, lateral surface. However, other cylindrical shapes with noncircular lateral curves can be implemented, including rectangular cylindrical surfaces. Likewise, the insulating spacer 26 has a cylindrical lateral surface substantially aligned with the cylindrical lateral surface of the cap layer. The phase change element 22 also has a cylindrical lateral surface with a maximum lateral dimension. A maximum lateral dimension of the cylindrical lateral surface of the phase change element 22 is less than the maximum lateral dimension of the cylindrical lateral surface of the cap layer 20.
Side walls 18 aligned with the cylindrical lateral surface of the cap layer 20 formed from dielectric fill material, extend from the upper surface of the lower electrode 14 to the top of the insulating spacer 26 in the illustrated embodiment, surrounding the pillar-shaped stack in the central portion of the memory element 10. The side walls 18 enclose gas filled thermal isolation regions 24 between a lateral surface of the phase change element 22 and the side walls 18. The gas-filled thermal isolation regions 24 are further delimited by the top surface of the lower electrode 14 and the bottom surface of the cap layer 20.
Embodiments of the memory element 10 include resistive RAM based memory materials, including chalcogenide based materials and other materials, for the phase change memory element 22. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many resistive RAM based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b). One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky '112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7 (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.
Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.
Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a PCRAM described herein is Ge2Sb2Te5.
Other programmable resistive memory materials may be used in other embodiments of the invention, including N2 doped GST, GexSby, or other material that uses different crystal phase changes to determine resistance; PrxCayMnO3, PrSrMnO, ZrOx, or other material that uses an electrical pulse to change the resistance state; 7,7,8,8-tetracyanoquinodimethane (TCNQ), methanofullerene 6,6-phenyl C61-butyric acid methyl ester (PCBM), TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other metal, or any other polymer material that has bistable or multi-stable resistance state controlled by an electrical pulse.
The following are short summaries describing four types of resistive memory materials. The first type is chalcogenide material, such as GexSbyTe, where x:y:z=2:2:5, or other compositions with x: 0 ̃5; y: 0 ̃5; z: 0 ̃10. GeSbTe with doping, such as N—, Si—, Ti—, or other element doping is alternatively used.
An exemplary method for forming chalcogenide material uses PVD-sputtering or magnetron-sputtering method with source gas(es) of Ar, N2, and/or He, etc. at the pressure of 1 mTorr ̃100 mTorr. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1 ̃5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several tens of volts to several hundreds of volts is also used. On the other hand, the combination of DC bias and the collimator can be used simultaneously.
A post-deposition annealing treatment in vacuum or in an N2 ambient is optionally performed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges from 100° C. to 400° C. with an anneal time of less than 30 minutes.
The thickness of chalcogenide material depends on the design of cell structure. In general, a chalcogenide material with thickness of higher than 8 nm can have a phase change characterization so that the material exhibits at least two stable resistance states.
A second type of memory material suitable for use in embodiments is colossal magnetoresistance (“CMR”) material, such as PrxCayMnO3 where x:y=0.5:0.5, or other compositions with x: 0 ̃1; y: 0 ̃1. CMR material that includes Mn oxide is alternatively used.
An exemplary method for forming CMR material uses PVD sputtering or magnetron-sputtering method with source gases of Ar, N2, O2, and/or He, etc. at the pressure of 1 mTorr ̃100 mTorr. The deposition temperature can range from room temperature to  ̃600° C., depending on the post deposition treatment condition. A collimator with an aspect ratio of 1 ̃5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several tens of volts to several hundreds of volts is also used. On the other hand, the combination of DC bias and the collimator can be used simultaneously. A magnetic field of several tens of Gauss to as much as a Tesla (10,000 Gauss) may be applied to improve the magnetic crystallized phase.
A post-deposition annealing treatment in vacuum or in an N2 ambient or O2/N2 mixed ambient is optionally used to improve the crystallized state of CMR material. The annealing temperature typically ranges from 400° C. to 600° C. with an anneal time of less than 2 hours.
The thickness of CMR material depends on the design of the cell structure. The CMR thickness of 10 nm to 200 nm can be used for the core material. A buffer layer of YBCO (YBaCuO3, which is a type of high temperature superconductor material) is often used to improve the crystallized state of CMR material. The YBCO is deposited before the deposition of CMR material. The thickness of YBCO ranges from 30 nm to 200 nm.
A third type of memory material is two-element compounds, such as NixOy; TixOy; AlxOy; WxOy; ZnxOy; ZrxOy; CuxOy; etc, where x:y=0.5:0.5, or other compositions with x: 0 ̃1; y: 0 ̃1. An exemplary formation method uses a PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N2, O2, and/or He, etc. at the pressure of 1 mTorr ̃100 mTorr, using a target of metal oxide, such as NixOy; TixOy; AlxOy; WxOy; ZnxOy; ZrxOy; CuxOy; etc. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1 ̃5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several tens of volts to several hundreds of volts is also used. If desired, the combination of DC bias and the collimator can be used simultaneously.
A post-deposition annealing treatment in vacuum or in an N2 ambient or O2/N2 mixed ambient is optionally performed to improve the oxygen distribution of metal oxide. The annealing temperature ranges from 400° C. to 600° C. with an anneal time of less than 2 hours.
An alternative formation method uses a PVD sputtering or magnetron-sputtering method with reactive gases of Ar/O2, Ar/N2/O2, pure O2, He/O2, He/N2/O2 etc. at the pressure of 1 mTorr ̃100 mTorr, using a target of metal oxide, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1 ̃5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several tens of volts to several hundreds of volts is also used. If desired, the combination of DC bias and the collimator can be used simultaneously.
A post-deposition annealing treatment in vacuum or in an N2 ambient or O2/N2 mixed ambient is optionally performed to improve the oxygen distribution of metal oxide. The annealing temperature ranges from 400° C. to 600° C. with an anneal time of less than 2 hours.
Yet another formation method uses oxidation by a high temperature oxidation system, such as a furnace or a rapid thermal pulse (“RTP”) system. The temperature ranges from 200° C. to 700° C. with pure O2 or N2/O2 mixed gas at a pressure of several mTorr to 1 atm. The time can range several minute to hours. Another oxidation method is plasma oxidation. An RF or a DC source plasma with pure O2 or Ar/O2 mixed gas or Ar/N2/O2 mixed gas at a pressure of 1 mTorr to 100 mTorr is used to oxidize the surface of metal, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The oxidation time ranges several seconds to several minutes. The oxidation temperature ranges from room temperature to 300° C., depending on the degree of plasma oxidation.
A fourth type of memory material is a polymer material, such as TCNQ with doping of Cu, C60, Ag etc. or PCBM-TCNQ mixed polymer. One formation method uses evaporation by thermal evaporation, e-beam evaporation, or molecular beam epitaxy (“MBE”) system. A solid-state TCNQ and dopant pellets are co-evaporated in a single chamber. The solid-state TCNQ and dopant pellets are put in a W-boat or a Ta-boat or a ceramic boat. A high electrical current or an electron-beam is applied to melt the source so that the materials are mixed and deposited on wafers. There are no reactive chemistries or gases. The deposition is done at a pressure of 10−4 Torr to 10−10 Torr. The wafer temperature ranges from room temperature to 200° C.
A post-deposition annealing treatment in vacuum or in an N2 ambient is optionally performed to improve the composition distribution of polymer material. The annealing temperature ranges from room temperature to 300° C. with an anneal time of less than 1 hour.
Another technique for forming a layer of polymer-based memory material is to use a spin-coater with doped-TCNQ solution at a rotation of less than 1000 rpm. After spin-coating, the wafer held (typically at room temperature or temperature less than 200° C.) for a time sufficient for solid-state formation. The hold time ranges from several minutes to days, depending on the temperature and on the formation conditions.
It is preferred to employ phase change materials for the memory element of the present invention, but it should be understood that any of the programmable resistance materials discussed above could be incorporated as the active memory material.
Cap layer 20 fills the central portion of the memory element 10, from the top surface of the phase change element 22 extending upward. The cap layer 20 is formed of a dielectric fill material, such as silicon dioxide or another known low-k material. Alternatively, the cap layer 20 may comprise one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C. Above the cap layer 20 is insulating spacer 26, extending to the top of the partitions 16 and preferably formed of SiN or a similar material. Alternative materials include fluorine doped silicate glass (FSG), borophosphate silicate glass (BPSG), or phosphosilicate glass (PSG) can also be employed as dielectric fill material. Those in the art will understand that the primary selection criterion in this situation is the relative selectivity of the chosen materials in the etching processes, discussed below.
A central passage extends completely through the cap element 20 and the spacer element 26, and an upper electrode 28, formed atop and extending across the memory element 10, includes a contact element 30, which extends downward and occupies the entire central passage to make electrical contact with the phase change element 22. Contact element 30 has a significantly smaller cross-sectional area than does the upper surface of the phase change element 22. The preferred material for the upper electrode is TiN or TaN. Alternatively, the electrode may be TiAlN or TaAlN, or may comprise, for further examples, combinations or allows including one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru.
The phase change element 22 does not occupy all of the space between lower electrode 14 and cap layer 20. Rather, the phase change element 22 lies at the center of that space, surrounded by a thermal isolation cell 24, preferably containing air. Air provides considerably lower thermal conductivity than do any of the available dielectric materials known in the art, and thus the air cell provides improved thermal isolation for the phase change element 22.
In operation, current flows through the memory element 10 from lower electrode 14, into the phase change element 22, and out through the contact 30 and upper electrode 28. Of course, the current direction could be altered by changes in element geometry, as will be understood by those in the art. In either event, the phase change material is subject to joule heating as current flows, as discussed above, resulting in a temperature rise in the center of the GST material. As the temperature exceeds that required for phase change, a portion of the phase change material changes state. The temperature of the phase change material determines the effect produced, so the current is chosen to produce a temperature sufficient to create the desired result—either an amorphous state or a crystalline state—in the GST material. If it is desired to read the element status, a low current is employed for sensing purposes. The read operation is non-destructive, as the element temperature is kept below the threshold for a phase change.
The thermal isolation cell 24 functions to contain heat within the phase change element 22, which has several positive effects. First, by preventing the migration of heat away from the phase change element 22, this design reduces the total heat required to effect phase changes, which in turn reduces the current required for each SET or RESET operation. At the same time, retaining heat within the phase change element reduces the heat transferred to the remainder of the memory array, which translates directly into increased lifespan for the device. Given the vast numbers of memory elements within a complete integrated circuit—at least eight billion elements for a 1 GB memory device, for example—it can be appreciated that the effects of such a heat reduction will be significant. The efficiency of the phase change element is further enhanced by the small contact area of the contact element 30. A small contact area concentrates the current, and a higher current density leads to higher temperatures in the vicinity of the contact, which in turn promotes rapid phase change in the area of the contact. This effect is shown in the detail view of FIG. 1a, in which arrows I in enter from lower electrode 14 (not shown) with a relatively uniform current density, but are concentrated at the contact with contact element 30, producing an area 31 of high temperature, which with proper current selection leads to a phase change in that area. That design leads to reduced current consumption by the memory element.
As noted above, the memory element 10 is a component of a memory cell, which in turn is part of a memory array. A memory cell is formed by adding to the memory element access circuitry, together with appropriate connection lines. The access circuitry could be a single transistor, or multiple transistors, configured as known in the art. The transistor circuitry is not shown, but it could be located, for example, in the integrated circuit below the memory element 10. Connection lines typically include word and bit lines, arranged in a matrix. Here, the upper electrode 28 could be employed as a bit line and lower electrode 14 could be used as a word line.
It is preferred that the total width of a cell (measured from the centerline of one partition to the centerline of the adjacent partition) be between about 100 and 500 nm, preferably 300 nm. The phase change element 22 should be between about 10 and 50 nm, preferably 20 nm, with is thickness between about 20 and 80 nm, preferably 40 nm. The air cell 24 should be between about 5 and 50 nm, preferably 25 nm, as measured from the end of the phase change element 22 to the side wall 18.
The schematic drawing of FIG. 2 shows the memory elements 10a and 10b employed in a memory cell 50, which in turn is a component of memory array 100. It will be understood that the array structure illustrated in FIG. 2 can be implemented using other cell structures. In the schematic illustration of FIG. 2, the common source line 148, the word line 143 and the word line 144 are arranged generally parallel in the Y-direction. Bit lines 141 and 142 are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in block 145 are coupled to the word lines 143, 144. An X-decoder and set of sense amplifiers in block 146 are coupled to the bit lines 141 and 142. The common source line 148 is coupled to the source terminals of access transistors 150, 151, 152 and 153. The gate of access transistor 150 is coupled to the word line 143. The gate of access transistor 151 is coupled to the word line 144. The gate of access transistor 152 is coupled to the word line 143. The gate of access transistor 153 is coupled to the word line 144. The drain of access transistor 150 is coupled to the electrode member 14 for phase change memory element 10a, which is in turn coupled to electrode member 28 (not shown in this drawing). Likewise, the drain of access transistor 151 is coupled to the electrode member 14 for phase change memory element 10b, which is in turn coupled to the electrode member 30. The electrode member 30 is coupled to the bit line 141. Access transistors 152 and 153 are coupled to corresponding memory cells as well on line 142. It can be seen that the common source line 128 is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic.
FIG. 3 shows a portion of a memory array 100, including memory elements 10a and 10b. As can be seen, the memory elements 10a, 10b are formed side-by-side in the integrated circuit, separated by partitions 16. In an embodiment of the invention, memory elements are arranged in a square matrix, with upper electrodes 28 spanning multiple elements in a direction parallel to the surface of the drawing and lower electrodes 14 spanning multiple elements in a direction perpendicular to the surface of the drawing, respectively functioning as bit lines and word lines. Upper electrode 28 has a contact element 30a/30b for each memory element 10a/10b. Each memory element includes all individual components discussed above, which will not be repeated here.
FIG. 4a depicts the first step in an embodiment of the process of fabricating memory elements according to the present invention. There, an initial structure 110 is shown, composed of deposited layers including the substrate dielectric layer 112, the lower electrode layer 114, the GST layer 122, the interelectrode dielectric layer 120 to be used as the cap layer, and a top layer to be used as a sacrificial spacer layer as described below, composed of SiN.
FIG. 4b depicts the results of a pillar patterning step, in which the layered structure 110 is converted to a series of pillars 111a-111c, each comprising a multilayer stack including phase change layer 122, an interelectrode dielectric layer, or cap element, 120 and a top layer 123. The drawing depicts individual pillar components labeled with the appropriate subscript, such as 122a, for example. The patterning step is conducted in accordance with conventional practice, preferably following a lithographic process of applying a photoresistive film; imprinting a pattern, as through a mask or reticle; exposing the pattern to visible light or other radiation; stripping the undesired portions of resist material to form an etch mask; and etching the material layers. It is preferred to employ a dry, anisotropic etch, which may be controlled with an optical device that senses arrival at the lower electrode layer or otherwise.
It should be noted that in this and the succeeding drawing depicting the process of the present invention, only the components of the left-hand pillar are labeled, as well as common elements and other elements particularly involved in the step being discussed. Also, the drawings will show only one memory element being formed, but those in the art will understand that the process is simultaneously forming all memory elements in an entire integrated circuit die.
The thermal isolation cells are initially formed in the next step, the results of which are shown in FIG. 4c. The structure shown in FIG. 4b is subjected to an etch process which acts selectively on the GST material, undercutting it with respect to the overlying interelectrode dielectric layer 120 to form thermal isolation cell areas 124 (shown circled for greater clarity). By careful selection of the etch chemistry and control of the process, the amount of the undercut, and thus the shape of the cylindrical lateral surface of the remaining GST material, can be obtained consistently.
Here, a dry etch chemistry could include Cl2, BCl3 or HBr, either in combination or singly, together with some combination of Ar, O2 or CF4. The method could employ Reactive Ion Etch (RIE) technology, controlled by an end-point detection system, as known in the art. That control technique senses etching beyond the desired control point, permitting an over-etch amount of 10-50%, as can be set when designing the process details.
Next, side walls are formed, as seen in FIG. 4d, by first depositing a layer of dielectric fill material over the structure of FIG. 4c, to produce a deposited film aligned with the cap layer 120a on the walls of the pillars 111. The dielectric fill material on the cylindrical lateral surface of the cap layer 120a encloses the thermal isolation cells as described above, and traps gas present in the reaction chamber at the time of the deposition within gas-filled thermal isolation cells. Chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) are preferred for this step. A following etch step removes material at the bottom of the spaces between pillars, separating the deposited films and defining sidewalls 118. A following etch step, preferably a dry, anisotropic etch selective for the electrode layer 114, serves to separate the electrode layer into separate electrode elements, such as electrode 114a, also having a cylindrical lateral shape aligned with the outside extent of the sidewalls 118. In this case, and the substrate would include contact the underlying access circuitry as illustrated in FIG. 2.
The preferred etch methods for these steps involve first etching the oxide spacer, preferably employing CF4, C4F8, CHF3, or C4F6, or some combination of the same, together with Ar, O2 or N2, preferably employing RIE with end-point control. The stage is selective to the lower TiN layer. _The second etch step, for the TiN layer, is performed preferably with Cl2, BCl3 or some combination of them, with Ar, O2 or N2, again employing RIE with end-point control.
A dielectric fill establishing partitions between individual memory elements is added in the following step, seen in FIG. 4e. A suitable dielectric material, as discussed above, is deposited into the area between the pillars, completely filling that space. It is preferred to overfill that space and to employ a planarizing step, as with chemical-mechanical polishing (CMP) to reduce the size of the partitions to a desired amount.
FIG. 4f depicts the results of the next step, removing the remaining portions of the top sacrificial spacer layer. When this layer is formed from SiN, as preferred, the preferred etchant is H3PO4, in a wet dip, thus producing higher selectivity regarding the SiO2 layers 120a and 116a. 
The following step calls for the formation of a spacer element 126 atop the cap element within the void formed by removing a sacrificial spacer layer 123a. The spacer element is preferably formed of SiN, as discussed above, and it is deposited and a cup-shaped cavity is etched away, extending completely through the element. A second etch is performed on the underlying cap element, preferably an anisotropic etch that opens a narrow, straight passage completely through the element. An end point stop can be utilized to control the etch, stopping on arrival at the GST material.
The final step, seen in FIG. 4h, results in the formation of the upper electrode 128, including the contact elements 130. The deposition must be controlled using atomic layer deposition or chemical vapor deposition technologies to ensure that the contact elements are formed so as to completely fill the openings formed by the previous etch step, to make contact with the phase change elements 130
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

## Claims

1. A memory device, comprising:
a first electrode element having a top surface;
a cap layer overlying the first electrode element, the cap layer having an outer surface with a lateral dimension;
a programmable resistive element having an outer surface with a lateral dimension, a bottom surface in contact with the top surface of the first electrode element, and a top surface in contact with a bottom surface of the cap layer, wherein the lateral dimension of the programmable resistive element is less than the lateral dimension of the cap layer;
a second electrode element extending through an opening in the cap layer to contact the top surface of the programmable resistive element; and
side walls comprising dielectric fill material, on the outer surface of the cap layer and extending to the top surface of the first electrode element, such that at least a portion of the outer surface of the programmable resistive element is spaced away from the side walls to define a gas-filled thermal isolation cell surrounding at least a portion of the outer surface of the programmable resistive element.

2. The memory device of claim 1, wherein the cap layer is composed of a dielectric fill material; the first electrode element is composed of a metal material; and the second electrode element is composed of TiN.

3. The memory device of claim 1, wherein the programmable resistive element comprises a combination of Ge, Sb, and Te.

4. The memory device of claim 1, wherein the programmable resistive element comprises a phase change element.

5. The memory device of claim 4, wherein the phase change element comprises a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.

6. The memory device of claim 1, wherein the thermal isolation cell contains air.

7. A memory device, comprising:
a first electrode element, generally planar in form, having an inner contact surface;
a cap layer, spaced from the first electrode element, the cap layer having a cylindrical lateral surface of a maximum lateral dimension;
a programmable resistive element having a cylindrical lateral surface with a maximum lateral dimension and having a bottom surface in contact with the inner contact surface of the first electrode element, and a top surface in contact with a bottom surface of the cap layer, wherein the maximum lateral dimension of the programmable resistive element is less than the maximum lateral dimension of the cap layer;
a second electrode element, including a filament extending through the cap layer to make contact with a top surface of the programmable resistive element;
side walls composed of dielectric fill material, aligned with the cylindrical lateral surface of the cap layer and extending between the first electrode element and the cap layer, such that the programmable resistive element, the inner contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell surrounding at least a portion of the cylindrical lateral surface of the programmable resistive element; and
a spacer element between the cap element and the second electrode, composed of SiN.

8. The memory device of claim 1, wherein the programmable resistance material is a colossal magnetoresistance material.

9. The memory device of claim 4, wherein the programmable resistive material comprises a combination of two or more materials from the group of NixOy; TixOy; AlxOy; WxOy; ZnxOy; ZrxOy; CuxOy; where x:y=0.5:0.5.

10. The memory device of claim 1, wherein the programmable resistive material is a polymer material from the group TCNQ, PCBM, TCNQ with doping of Cu, C60.

11. A memory array, comprising:
a plurality of first electrode elements having respective top surfaces and arrayed along a first direction;
a plurality of memory elements, separated by partitions, each memory element comprising:
a cap layer overlying a corresponding first electrode element in the plurality of first electrode elements;
a programmable resistive element having a bottom surface in contact with the top surface of the corresponding first electrode element and having a top surface in contact with a bottom surface of the cap layer, wherein a lateral dimension of the programmable resistive element is less than that of the corresponding first electrode element and the cap layer; and
side walls comprising dielectric fill material, on an outer surface of the cap layer and extending to the top surface of the corresponding first electrode element, such that at least portion of an outer surface of the programmable resistive element is spaced away from the side walls to define a gas-filled thermal isolation cell; and

a plurality of second electrode elements arrayed in a second direction, each second electrode element overlying memory elements in the plurality of memory elements, and extending through the cap layer of each of said memory elements to contact top surfaces of the programmable resistive element of each of said memory elements.

12. The memory device of claim 11, wherein the cap layers are composed of a dielectric fill material; the first electrode elements are composed of a metal material; and the second electrode elements are composed of TiN.

13. The memory device of claim 11, wherein the programmable resistive elements comprise a combination of Ge, Sb, and Te.

14. The memory device of claim 11, wherein the programmable resistive elements comprise a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.

15. The memory device of claim 11, wherein the thermal isolation cell contains air.

16. A memory array, comprising:
a plurality of first electrode elements, generally planar in form, having an inner contact surface and arrayed mutually parallel in a first direction;
a plurality of pillar-shaped memory elements, separated by partitions, each element comprising:
a cap layer, spaced from the first electrode element;
a phase change element having contact surfaces in contact with the first electrode contact surfaces and the cap layer, wherein the lateral dimension of the phase change element is less than that of the first electrode element and the cap layer; and
side walls aligned with the cap layer, composed of dielectric fill material, extending between a first electrode elements and the cap layer, such that the phase change element, the contact surface of the first electrode element and the side walls define a gas-filled thermal isolation cell adjacent the phase change element;

a plurality of second electrode elements arrayed mutually parallel in a direction generally orthogonal to the direction of the first electrode elements, each second electrode element spanning a plurality of memory elements, and having at each memory element a contact element extending through the cap layer to make contact with the phase change element; and
a spacer element between the cap element and the second electrode, composed of SiN.

17. The memory device of claim 1, wherein the second electrode element has a lateral dimension at the top surface of the programmable resistive element less than that of the programmable resistive element.

18. The memory device of claim 1, wherein:
the second electrode element contacts the top surface of the programmable resistive element at a first contact surface;
the first electrode element contacts the bottom surface of the programmable resistive element at a second contact surface; and
the first contact surface has a contact area less than that of the second contact surface.

19. The memory device of claim 1, wherein the programmable resistive element has a phase change region adjacent the second electrode element.

20. The memory device of claim 1, wherein the side walls have side wall surfaces extending above the cap layer, and further comprising a spacer element on the cap layer and on the sidewall surfaces of the side walls, the spacer element having an inner surface defining an opening aligned with the opening in the cap layer, and the second electrode element further within the opening in the spacer element.