Exhibit 4.10





Cisco Proprietary & Confidential
NP-4 NP-4C Architectural Specifications


CISCO, MARVELL AND EZCHIP


BUSINESS TERM AGREEMENT





The purpose of this Business Term Agreement (“Agreement”) is to agree on key business terms between Cisco Systems, Inc. a California corporation, having principal offices at 170 West Tasman Drive, San Jose, California 95134-1706 (“Cisco”), Marvell International Ltd., a Bermuda corporation, with offices at Argyle House, 41a Cedar Avenue, Hamilton, HM 12, Marvell Israel Ltd. (formerly know as Marvell Semiconductor Israel Ltd), an Israeli corporation, with offices at 6 Hamada Street, Mordot HaCarmel Industrial Park, Yokneam, Israel 20692, (Marvell International Ltd. and Marvell Israel Ltd. are collectively referred to as “Marvell”), EZchip Technologies Ltd., an Israel corporation, having principal offices at 1 Hatamar Street, Yokneam 20692, Israel, and EZchip Inc., a Delaware corporation, having principal offices at 900 E. Hamilton Avenue, Suite 100, Campbell, California 95008, (EZchip Technologies Ltd. and EZchip Inc. are collectively referred to as “EZchip”) to meet Cisco’s technical and business requirements for certain Cisco products.  This Agreement shall be effective as of the date last signed by the parties below (the “Effective Date”) between and among the parties and their affiliates identified below.





BACKGROUND




A.           Marvell International Limited, a Bermuda corporation with offices at Argyle House, 41a Cedar Avenue, Hamilton, HM 12, together with Marvell Semiconductor Israel Ltd (which subsequently changed its name and currently operates under the name Marvell Israel Ltd), an Israeli corporation located at 6 Hamada Street, Mordot HaCarmel Industrial Park, Yokneam, Israel 20692, and EZchip Technologies Ltd,  an Israeli corporation located at 1 Hatamar Street, PO Box 527 Yokenam, 20692, (“EZchip”) are parties to the Technology Development, License and Manufacturing Agreement dated April 12, 2006 (“DLA”), and




B.           Cisco Systems International B.V., a Netherlands corporation, with offices at Hoogoorddreef 9, 1101 BA, Amsterdam, Netherlands, and Marvell Technology Group Ltd., a Bermuda corporation, with business offices at Richmond House, 3rd Floor, #12 Par la Ville Road, Hamilton, HM DX Bermuda 1, are parties to a [*]Agreement (“[*]”) dated [*].




C.           Cisco Systems, Inc., Marvell International Ltd., and Marvell Israel Ltd., together with EZchip have previously agreed to a “Cisco/Marvell/EZChip Business Term Agreement,” pertaining to the “NP3C” network processor.




D.           Cisco Systems, Inc., Marvell International Ltd. and EZchip Technologies Ltd. are parties to a Software License Agreement for EZChip Design Development Tools, dated on or about April 11, 2007, pursuant to which certain EZchip software is licensed to Cisco (the “SLA”).




E.           Cisco, Marvell and EZchip now wish to establish the terms and conditions for the development, licensing and manufacture of the next generation network processor, identified as “NP4” (also known as NP4-G) and “NP4C (also known as NP4-C).”








* This portion of the Agreement has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Agreement, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.









Cisco Proprietary & Confidential
NP-4 NP-4C Architectural Specifications


1.           Identification of Parties




Cisco Systems, Inc. and Cisco Systems International B.V., and their affiliates, are collectively referred to as “Cisco”.




Marvell Technology Group, Marvell International Ltd., and Marvell Israel Ltd are collectively referred to as “Marvell.”




EZchip Technologies Ltd. and EZchip Inc. are collectively referred to as “EZchip.”




Marvell and EZchip are each a “Supplier” and collectively referred to as the “Suppliers”.





2.           Representations and Warranties:





Marvell and EZchip represent and warrant that they have entered into the DLA which includes support obligations by EZchip, protection of confidential information, intellectual property licenses from EZchip and intellectual property (IP) escrow provisions. Marvell represents that the terms of the DLA are sufficient for Marvell to fulfill its obligations to Cisco under this Agreement.





Marvell represents that it has entered into appropriate support arrangements and Marvell represents that it possesses sufficient rights and licenses to EZchip’s intellectual property rights, needed by Marvell Technology Group Ltd., a Bermuda corporation with offices at Richmond House, 3rd Floor, #12 Par la Ville Road, Hamilton, HM DX Bermuda 1, (“Marvell Technology Group”) to fulfill its obligations to Cisco with respect to manufacture, sale and support of network processors described herein for the duration of time set forth in the [*]


List of intellectual property licensed by Marvell from EZchip for the purposes of developing the network processor described in this Agreement:





(i)
Network processor technology


(ii)
Traffic management technology


(iii)
The EZchip Intellectual Property Listed on Exhibit B





3.           Escrow





Without limiting any other right or remedy of Cisco, the requisite EZchip intellectual property, manufacturing information and materials relating to the network processors described in this Addendum shall be placed in escrow by EZchip for release to Marvell at any time upon the occurrence of any of the events set forth in Exhibit C (each a “Trigger Event”) to allow Marvell to manufacture and sell the network processors to Cisco.  Marvell will ensure that all such EZchip intellectual property, manufacturing information and materials are placed in escrow.





4.           Ownership





As between EZchip and Marvell, EZchip acknowledges that Marvell shall own the mask set for the NP4C network processor (excluding any Cisco intellectual property and any EZchip intellectual property). Notwithstanding, EZchip shall retain ownership of the EZchip intellectual property and derivatives thereof, excluding any Cisco intellectual property.




* This portion of the Agreement has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Agreement, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.




2




Cisco Proprietary & Confidential
NP-4 NP-4C Architectural Specifications


5.           Marvell Responsibilities




Marvell will be responsible for manufacturing, qualification and selling of the network processor described in this Agreement to Cisco, at Cisco’s election.  Subject to the terms of the DLA, EZchip shall be responsible for the qualification of the EZchip intellectual property licensed by EZchip to Marvell.




Subject to the terms of the DLA, Marvell shall license EZchip intellectual property rights and combine it with Marvell intellectual property to develop the NP4 and NP4C.  The NP4C will have and perform the features and functionalities described in Exhibit A in accordance with any technical or other specifications for the NP4C.




Marvell will promptly disclose to EZchip the non-bindingtwelve (12)month forecasts and shipping plans of Cisco’s requirements for the NP4C and NP3C on a monthly basis.




6.           Exclusivity




Definitions:




“NP4” means the next version to the NP3 network processor that EZchip will make generally available to customers as set forth herein.




“NP4C” means the Cisco-specific version of the NP4 network processor.  Marvell and EZchip will make the NP4C available to Cisco on an exclusive basis as set forth herein.




“General Merchant Silicon” for the purposes of this Agreement shall mean off-the-shelf network processors made generally available to third parties by Marvell or EZchip (i.e., the NP3 and NP4).




“NP4 Samples” means pre-production NP4 network processors that have not completed or passed electrical testing and reliability testing, and are not deemed to be production qualified by EZchip.




[*]




Exclusivity periods:




[*]




Exclusivity periods for [*]:




[*]




* This portion of the Agreement has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Agreement, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.




3




Cisco Proprietary & Confidential
NP-4 NP-4C Architectural Specifications
  If NP4C Product Unavailable to Cisco:
  If at any time Cisco reasonably believes (i) Marvell or EZChip is or will be unable to manufacture, deliver, or sell the NP4C to Cisco and its designated third parties in the quantities requested by Cisco or (ii) there are significant bugs or performance issues in the NP4C, then the Suppliers agree that they will offer to sell and deliver the NP4 to Cisco and its designated third parties in the quantities requested by Cisco, subject to the exclusivity terms.  After the Distribution Exclusivity Period has expired, the Suppliers may sell and distribute the NP4 to third parties. The price for each NP4 purchased by Cisco or on its behalf by Cisco’s designated third parties shall be [*].
  [*]


7.           Pricing:




[*]




8.           Schedule and Milestone:





Milestone
Committed
DescriptionFull chip final RTL drop
[*]
Fully verified, Timing fixed, Final netlistLast ECO
[*]
No ECO beyond this dateTape-Out  (base layers)
[*]Samples @ Marvell Israel
[*]
With Expedites, Hand Carry, Super Hot LotsSamples @ Cisco
[*]
Blind samples can be available earlier





9.           NP4 and NP4C Marking Requirement





[*]





10.         Confidentiality




The parties have executed a non disclosure agreement dated Feb 2, 2006 (“NDA”). To the extent that the term stated in the NDA terminates prior to the termination of this Agreement, the parties agree that the term of the NDA shall be automatically extended to the term of this Agreement.  In addition, notwithstanding any limitations in the NDA, the NDA shall apply to all Confidential Information disclosed in connection with this Agreement, and the purpose of such disclosures shall include the purposes of this Agreement.  The parties agree that the contents of this Agreement are Confidential Information within the meaning of that term in the NDA, and that neither will disclose to any third party the existence, intent or terms of this Agreement or the occurrence, content or other information about any discussions, or negotiations which have occurred or will occur, except in accordance with the NDA.  To the extent there is a conflict between the confidentiality obligations of this Agreement and the NDA with respect to the [*], the confidentiality obligations of this Agreement will control.




* This portion of the Agreement has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Agreement, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.




4




Cisco Proprietary & Confidential
NP-4 NP-4C Architectural Specifications


11.         Limitation of Liability





NOTWITHSTANDING ANYTHING TO THE CONTRARY IN THIS AGREEMENT, EXCEPT FOR I) BREACH OF CONFIDENTIALITY OBLIGATIONS HEREUNDER; OR II) BREACH OF ANY OBLIGATION PURSUANT TO SECTION 6, EXCLUSIVITY, UNDER NO CIRCUMSTANCES WILL A PARTY, ITS EMPLOYEES, OFFICERS OR DIRECTORS, AGENTS, SUCCESSORS OR ASSIGNS BE LIABLE TO THE OTHER PARTIES UNDER ANY CONTRACT, STRICT LIABILITY, TORT (INCLUDING NEGLIGENCE) OR OTHER LEGAL OR EQUITABLE THEORY, FOR ANY SPECIAL, INDIRECT, INCIDENTAL OR CONSEQUENTIAL DAMAGES OR COSTS, INCLUDING, WITHOUT LIMITATION, LOST PROFITS, ARISING OUT OF, OR RELATING IN ANY WAY TO, THE SUBJECT MATTER OF THIS AGREEMENT, REGARDLESS OF WHETHER A PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.  THIS SECTION DOES NOT LIMIT A PARTY'S LIABILITY FOR BODILY INJURY (INCLUDING DEATH), OR PHYSICAL DAMAGE TO TANGIBLE PROPERTY.  EACH PARTY ACKNOWLEDGES THAT THIS WAIVER OF CONSEQUENTIAL AND OTHER DAMAGES REFLECTS THE ALLOCATION OF RISKS BETWEEN THEM AND FORMS AN ESSENTIAL PART OF THE BARGAIN BETWEEN THEM.





12.         General Terms




Any terms not defined in this Agreement shall have the meaning stated in the DLA, [*], and/or SLA.  Except as modified by this Agreement, all terms and conditions of the DLA, [*], and SLA shall remain in full force and effect.  In the event of a conflict between the terms and conditions of this Agreement and any terms and conditions of the DLA, [*], and/or SLA, this Agreement will prevail with regard to the subject matter herein to the extent that a party is a party to such an agreement.




This Agreement and the DLA, [*], and SLA are the complete agreements between the parties to the extent that a party is a party to such an agreement and supersede all prior oral and written agreements, representations, warranties and commitments of the parties regarding subject matter herein.





[SIGNATURE PAGE FOLLOWS]





* This portion of the Agreement has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Agreement, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.




5





Cisco Proprietary & Confidential
NP-4 NP-4C Architectural Specifications


IN WITNESS WHEREOF, the parties hereto have caused this Agreement to be duly executed.  Each party warrants and represents that its respective signatories whose signatures appear below have been and are on the date of signature duly authorized to execute this Agreement.





CISCO SYSTEMS, INC.

Marvell International Ltd.By
/s/ Prasad Sabada

By
/s/ Ken GoertzenName
Prasad Sabada

Name
Ken GoertzenTitle
Senior Director, CVCM

Title
Alternate DirectorDate
December 7, 2010

Date
September 3, 2010EZchip Technologies Ltd.

EZchip Inc.By
/s/ Eli Fruchter

By
/s/ Eli FruchterName
Eli Fruchter

Name
Eli FruchterTitle
CEO

Title
CEODate
November 11, 2010

Date
November 11, 2010
 
 Marvell Israel Ltd
 
 By
/s/ Eliaz LavyName
Eliaz LavyTitle
Sr. V.P. and G.M M.I.S.L.Date
October 17, 2010


6




Cisco Proprietary & Confidential
NP-4 NP-4C Architectural Specifications







Exhibit A





[*]




* This portion of the Agreement has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Agreement, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.




7


Cisco Proprietary & Confidential
NP-4 NP-4C Architectural Specifications
  Exhibit B




List of EZchip IP




NP-4 Features




§
Single-chip, programmable, 100-Gigabit throughput (50-Gigabit full duplex)


wire-speed network processor


§
On-chip scaling bus options for up to 100G full duplex processing and TM


§
Line card, services card and pizza box applications


§
Based on EZchip’s NP-3 with performance scaling and an enhanced feature set


§
On-chip Control CPU, and host offload


§
On-chip Fabric Interface Controller for interfacing with Ethernet fabrics as well as third-party fabric solutions


§
System-wide traffic management


§
Ingress and egress traffic management with hierarchical scheduling


§
Flexible processing with programmable packet parsing, classifying, modifying and forwarding


§
Embedded search engines eliminating the need for external search co-processors


§
On-chip OAM protocol processing offload


§
Internal switch, for line card scaling, and enhanced data flow flexibility


§
FIC (Fabric Interface Chip) functionality integration for direct connection to cell based and packet based switching complex, including basic Ethernet fabrics


§
System-wide traffic management with end-to-end QoS, dedicated QOS CPU


§
Ten XAUI interfaces


§
Supports RXAUI protocol


§
24 quad-speed SGMII ports or


48 tri-speed QSGMII ports


§
Support for OC-768


§
Support for 100G Ethernet


§
On-chip hardware time stamping supporting IEEE1588v2


§
Support for CES and Synchronous Ethernet ITU-T8261


§
PCI-Express external host interface


§
Comprehensive on-chip diagnostic hardware support




8








Embedded search engines


§
Table entries stored in DRAM; no CAM or SRAM necessary


§
Reducing system chip count, power dissipation and cost


§
Providing up to 2 Gbytes lookup tables headroom


§
Multiple routing, classification and policy lookup tables with millions of entries per table


§
Flexible keys and results (associated information) programmed per table


§
Support for long keys (up to 80 bytes) and long results (up to 96 bytes) per table entry Content-aware stateful classifying and processing


§
Access to all 7 layers for classify and modify


§
Maintain state of millions of sessions simultaneously


§
On-chip state updates and learning of millions of sessions per second


Programming


§
Large code space memory for multiple and complex applications


§
[*]


§
Hitless code upgrades


§
Single-image programming model with no parallel programming or multi-threading


§
Automatic ordering of frames


§
Automatic allocation of frames to processing engines (TOPs)


§
Automatic passing of messages among TOPs


§
Microcode compatible with EZchip’s NP-3 and NP-2 (NP-2a and NP-2b) network processors




* This portion of the Agreement has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Agreement, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.




9








Interfaces


§
Ten XAUI interfaces:


§
Ten on-chip 10G/20G MACs


§
3.125Gbps; 6.25Gbps per lane


§
Channelized operation with up to 256 channels


§
In band and out of band flow control


§
Connection to Ethernet and TDM framers


§
Cell-based and packet-based operation


§
Support for SPAUI and Interlaken


§
Supports RXAUI protocol


§
24 quad-speed SGMII Ethernet interfaces or


48 tri-speed QSGMII Ethernet interfaces


§
External Host interface:


§
1-lane PCI-Express 2.5Gbps for control CPU interface


§
Additional 2xSGMII GE ports


§
MDC/MDIO master port for 1G copper PHY; continuous polling mode by HW


§
There are 3 master interfaces: 2 for SGMII ports, 1 for XAUI ports


§
All masters support both clause 24 (1G) and clause 45 (10G)


§
LED interface for port status exporting


§
External memory interfaces:


§
External TM memory interface (optional):


§
DDR3 SDRAM


§
666 MHz DDR; 8x16 bit


§
4 GB max. (16M frames)


§
External lookup table memory interface:


§
DDR3


§
666 MHz DDR; 4x32 bit


§
4 GB max.


§
8 DDR3 devices


§
External statistics memory interface:


§
RLDRAM2-SIO


§
533 MHz DDR; 2x18 bit


§
1/2 devices


§
ECC protected internal and external memories


§
External TCAM interface:


§
Especially useful for fast lookups through large tables with wildcards, such as Access Control Lists (ACL)


§
Interlaken-LA, 24 lanes, 6.25Gbps, 400Mkps, 1600sps


Integrated Traffic Management


§
Unified 50/100Gbps Traffic Manager


§
200Mpps throughput


§
Combines both ingress and egress functionality


§
Dynamic hitless resource allocation


§
Dynamic hitless reconfiguration


§
Dynamic concatenated TM scheme


§
LAG shaping


§
Work conserving and non-work conserving schedulers




10







§
Frame sizes from 1 byte to 16 KB


§
Up to 4 Gbytes total frame memory


§
Up to 16M frames


§
Per Flow Queuing (PFQ) with 5-level hierarchical scheduling:


§
32 interfaces


§
256 ports


§
4K subports


§
32K classes/users


§
256K flows (8-16 per subscriber)


§
8 classes of service per subscriber


§
Advanced per packet control:


§
Per packet IPG


§
Per packet internal switch destination & COS


§
Per packet WRED profile reference


§
Dynamic mapping of all hierarchies


§
Dual shaper in each hierarchy


§
Programmable priority propagation in all hierarchies


§
External TM control bus for external user-defined scheduler


§
Policing: Per-flow metering, marking and policing for millions of flows


§
Configurable WRED profiles


§
Per flow per color WRED statistics


§
Shaping: Single and Dual leaky bucket on committed/peak rate/bursts (CIR, CBS, PIR, PBS), with IFG emulation for accurate rate control


§
Scheduling: WFQ and priority scheduling at each hierarchy level


§
Per frame statistics


§
Per frame timestamp and timeout drop


§
Hardware flow control per port


§
Flow control generation management scheme based on a per source and/or destination port accounting


Operations and Management Offload


§
KeepAlive frame generation for precise and accurate session maintenance operations


§
KeepAlive watchdog timers for fastest detection time


§
802.1ag compliant full offload


§
Per OAM session state tracking and reporting


§
Flexible statistics and performance monitoring


Data Flow Features


[*]


TOP Features


[*]


Statistics and Counters


§
Up to 16M 64-bit counters via external memory




* This portion of the Agreement has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Agreement, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.




11







§
Per-flow statistics for programmable events, traffic metering, policing and shaping


§
Programmable threshold settings and threshold exceeded notification


§
Dynamic allocation and auto association between counters and flows. Counters are automatically recycled when a flow is deleted or aged.


§
Auto implementation of token bucket per flow (srTCM or trTCM or MEF5):


§
Hardware implementation of token bucket calculations and coloring (i.e. green, yellow, red)


Power Management


§
Per interface power-up/power-down


§
Configurable number of active TOP engines at each stage, for best power optimization per application




Diagnostics


§
Interface built-in self test (BIST) for all NP-4 memory interfaces


§
Remote and internal loopback on all SGMII/QSGMII and XAUI interfaces


§
Externally controlled 64-bit RTC with time stamping and time loading support


§
Activity meters for all NP-4 clock domains with 64-bit phase meters per clock, supporting synchronous time stamp latching


§
PLL status monitors


§
Power management monitors on all NP-4 clock and power domains




12







Exhibit C




A Triggering Event refers to any of the following:





1.  Termination by Marvell of the Technology Development, License and Manufacturing Agreement dated April 12, 2006 (“DLA”) due to any of the following.





(a)           EZchip becomes insolvent or makes a general assignment for the benefit of its creditors, or EZchip dissolves, except where such dissolution results directly from:





(i)
a corporate reorganization which results in the holders of a majority of EZchip’s voting securities - prior to such reorganization - (x) continuing to hold at least 51% of the voting securities of the entity surviving such reorganization, or (y) holding substantially all of the assets of EZchip and continuing to operate the business of EZchip, or


(ii)
EZchip merging with or into a third party, as a result of which holders of EZchip’s equity securities prior to the merger hold less than 50% of the equity securities of EZchip after the closing of such merger; or, EZchip sells all or substantially all of its assets to a third party, and based on Marvell’s reasonable discretion, said third party is not a competitor of Marvell with respect to the subject matter of this Agreement;





(b)           a voluntary or involuntary petition or proceeding is commenced by or against EZchip under the Federal Bankruptcy Act or any other statute of any state or country relating to insolvency or the protection of the rights of creditors, or any other insolvency or bankruptcy proceeding or other similar proceeding for the settlement of EZchip’s debt is instituted and is not dismissed within 60 days from the date of such filing; or





(c)           a receiver of all or substantially all of EZchip’s property is appointed, and is not removed within 30 days;





In these situations, Marvell shall be entitled deliver to the Escrow Agent and EZchip a Release Notice together with an affidavit. The Escrow Agent shall be required to promptly confirm receipt by EZchip.





The Escrow Agent shall release the escrowed technology to Marvell between 5 and 10 business days from the escrow agent receiving notice confirmation from EZchip; unless the triggering event is cured. A triggering event is cured if EZchip provides sufficient evidence to this effect.





2.            Additional Triggering Events




(a)           EZchip materially breaches the DLA providedthe breachrequires Marvell’s use of any escrowed technology to remedy said breach.




13







(b)           EZchip materially fails to perform its support obligations under the Statement of Work applicable to the NP4-C (other than due to Marvell’s failure to perform its obligations in connection with such development) after the occurrence of (i) an “M&A Transaction” (as defined herein) or (ii) a Change of Control (as defined below) in EZchip, LanOptics Ltd., or any other parent company of EZchip.





For purposes of this Exhibit C, “M&A Transaction” means the merger of EZchip with or into a third party, as a result of which holders of EZchip’s equity securities prior to the merger hold less than 50% of the equity securities of EZchip after the closing of such merger, or EZchip sells all or substantially all of its assets to a third party and “Change of Control” means a transaction or series of transactions in which EZchip, LanOptics Ltd. or any other parent company of EZchip undergoes a change in the party or parties that directly or indirectly own more than fifty percent (50%) of the voting stock or shares or other form of entity ownership (e.g. partnership interests).





In these situations, Marvell shall provide EZchip with a written notice informing EZchip of the occurrence of such event in reasonable detail.  By no later than 30 days following the receipt of such written notice, EZchip shall be required to provide Marvell with a written cure plan in reasonable detail with the steps which EZchip intends to take in order to cure such plan. Marvell shall be entitled to disclose such plan to Cisco under an obligation of confidentiality.





In the event that EZchip fails to (i) provide Marvell an acceptable cure plan within such thirty (30) day period, or (ii) EZchip fails to cure the triggering event within the period specified in an accepted plan, Marvell shall be entitled to deliver the Release notice and Affidavit to the Escrow Agent (with a copy to EZchip).  The Escrow Agent shall be required to promptly obtain Notice Confirmation from EZchip.




The Escrow Agent shall release the escrowed technology to Marvell between 5 and 10 business days from the escrow agent receiving notice confirmation from EZchip; unless EZchip provides sufficient evidence that it has provided a plan within the 30 day period above or it has complied or is in compliance with the plan. Marvell shall return the escrowed technology to the Escrow Agent upon the sooner of (a) the date twelve (12) months after the release date, or (b) the date that the applicable triggering event is cured.





(c)           EZchip does not, or revokes, the license to its requisite Intellectual Property Rights to Marvell to (xx) enable Marvell combine the EZchip Intellectual Property Rights with Marvell’s intellectual property and (yy) develop the NP4 and NP4C for Cisco, without material cause by Marvell.





3.             EZchip’s material and ongoing failure to perform or propose a Bug Fix deemed by Cisco to be required with respect to the NP4-C, the applicable Deliverables or the applicable Design Materials.





·
Deliverables and Design Materials include EZchip IP, licensed software, technology and materials associated with the NP4-C.




14









In this situation, EZchip shall have a period of 90 days following the receipt of Marvell’s written notice and demand for cure to provide a plan that describes EZchip’s plan to provide a bug fix. Marvell agrees to provide assistance and shall have the right to audit EZchip on a weekly basis. Should it be determined by Marvell, acting reasonably, that the plan is not being executed in accordance with its terms due to a failure by EZchip, Marvell shall be entitled to deliver a Release Notice and Affidavit to the Escrow Agent (with a copy to EZchip). The Escrow Agent shall be required to promptly confirm the receipt by EZchip (with a copy to EZchip) ad EZchip’s confirmation that the plan is not being executed in accordance with its due to a failure on its part.





The Escrow Agent shall release the escrowed technology to Marvell between 5 and 10 business days from the escrow agent receiving notice confirmation from EZchip; unless EZchip provides sufficient evidence that it has provided the Bug Fix or it has complied or is in compliance with the plan. Marvell shall return the escrowed technology to the Escrow Agent upon the sooner of (a) the date twelve (12) months after the release date, or (b) the date that EZchip provides the applicable Bug Fix.





15