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|   | 1. | Marvell and EZchip Technology Agreement |
|--------|----|-----------------------------------------|

|   | 2. | Exclusivity |
|--------|----|-------------|

|   | 3. | Software quote |
|--------|----|----------------|

|   | 4. | Pricing |
|--------|----|---------|

|   | 5. | Schedule and Milestone |
|--------|----|------------------------|

*

|   | (i) | Network processor technology |
|--------|-----|------------------------------|

|   | (ii) | Traffic management technology |
|--------|------|-------------------------------|

|   | (iii) | The EZchip Intellectual Property Listed on Exhibit B |
|--------|-------|------------------------------------------------------|

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|   | · | Training |
|--------|--------|----------|

|   | – | To be provided as requested and agreed upon by the parties. |
|--------|---------|-------------------------------------------------------------|

|   | · | Support |
|--------|--------|---------|

|   | – | On-site dedicated EZchip microcode engineer for 3 months. |
|--------|---------|-----------------------------------------------------------|

|   | – | On-site EZchip SW driver engineer for 1 month. |
|--------|---------|------------------------------------------------|

|   | – | On-site EZchip and Marvell HW engineer(s) for HW bring-up. |
|--------|---------|------------------------------------------------------------|

|   | – | On-going local Marvell and EZchip FAE support with EZchip Support team as back-up. |
|--------|---------|------------------------------------------------------------------------------------|

|   | · | Sample code made available by EZchip, which is well documented and includes the following applications: |
|--------|--------|---------------------------------------------------------------------------------------------------------|

|   | – | L2 switch, IPv4 & IPv6 router, VPLS. |
|--------|---------|------------------------------------------|

|   | – | New metro application in progress, available in August 2006. |
|--------|---------|--------------------------------------------------------------|

| Milestone                         | Date | Comment                                                                        |
|-----------------------------------|------|--------------------------------------------------------------------------------|
| Specification Closure and Kickoff | [*]  |                                                                           |
| uArch spec closed                 | [*]  |                                                                           |
| Floor Plan Start                  | [*]  | Initial netlist for floor planning, layout view of all IP (Memory SerDes, PLL) |

----

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| Milestone          |   Date |   Comment                                             |
|--------------------|-------------|------------------------------------------------------------|
| First Netlist      | [*]         | 90% netlist, Ops stack on timing, 80% logic verification   |
| Final Netlist      | [*]         | 100% netlist ready, 99% verification, +12% slack on timing |
| ECO Round Complete | [*]         |                                                       |
| T/O                | [*]         |                                                       |
| Samples at Marvell | [*]         | Internal Samples. +1 WW to Cisco                           |

|   | 1. | Cisco/Marvell/EZchip to conclude a Software licensing agreement. |
|--------|----|------------------------------------------------------------------|

|   | 2. | Cisco/Marvell/EZchip need to agree on business agreement of NP4c & future generation exclusivity features. |
|--------|----|----------------------------------------------------------------------------------------------------------------|

|   | 3. | Cisco and Marvell to conclude a SOW for the development of NP3C. |
|--------|----|------------------------------------------------------------------|

|   | 4. | Cisco and Marvell to conclude an addendum to the [*] for the purchase of Cisco of NP3C. |
|--------|----|-----------------------------------------------------------------------------------------|

----

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| CISCO SYSTEMS, INC.  |                    | Marvell International Ltd. |   |
|---------------------------|-------------------------|----------------------------|--------|
| By                        | /s/ Prasad Sabada       |                       | By     | /s/ Carol Feathers |   |
| Name                      | Prasad Sabada           |                       | Name   | Carol Feathers |   |
| Title                     | Director, Manufacturing |                       | Title  | General Manager |   |
| Date                      | November 15, 2006       |                       | Date   | October 3, 2006 |   |

| EZchip Technologies Ltd.  |             |
|--------------------------------|------------------|
| By                             | Eli Fruchter     |   |
| Name                           | /s/ Eli Fruchter |   |
| Title                          | CEO              |   |
| Date                           | October 25, 2006 |   |

| Marvell Semiconductor Israel Ltd.  |                            |
|-----------------------------------------|---------------------------------|
| By                                      | /s/ [Authorized Representative] |   |
| Name                                    |                            |   |
| Title                                   |                            |   |
| Date                                    | October 15, 2006                |   |

----

----

* This portion of the Exhibit has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Exhibit, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.

----

|   | · | Single chip, programmable, 10-Gigabit full-duplex (20-Gigabit simplex) wire-speed network processor |
|--------|--------|-----------------------------------------------------------------------------------------------------|

|   | · | Line card, services card and pizza box applications |
|--------|--------|-----------------------------------------------------|

|   | · | Full-duplex and simplex modes of operation |
|--------|--------|--------------------------------------------|

|   | · | Flexible processing with programmable packet parsing, classifying, modifying and forwarding |
|--------|--------|---------------------------------------------------------------------------------------------|

|   | · | Ingress and egress traffic management with hierarchical scheduling |
|--------|--------|--------------------------------------------------------------------|

|   | · | Embedded search engines eliminating the need for external search co-processors |
|--------|--------|--------------------------------------------------------------------------------|

|   | · | On-chip OAM protocol processing offload |
|--------|--------|-----------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | PCI-Express external host interface |
|--------|--------|-------------------------------------|

|   | · | Table entries stored in DRAM; no CAM or SRAM necessary |
|--------|--------|--------------------------------------------------------|

|   | · | Multiple routing, classification and policy lookup tables with millions of entries per table |
|--------|--------|----------------------------------------------------------------------------------------------|

|   | · | Flexible keys and results (associated information) programmed per table |
|--------|--------|-------------------------------------------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | Off-loading control tasks from the control CPU |
|--------|--------|------------------------------------------------|

|   | · | Access to all 7 layers for classify and modify |
|--------|--------|------------------------------------------------|

|   | · | Maintain state of millions of sessions simultaneously |
|--------|--------|-------------------------------------------------------|

|   | · | On-chip state updates and learning of millions of sessions per second |
|--------|--------|-----------------------------------------------------------------------|

|   | · | Large code space memory for multiple and complex applications |
|--------|--------|---------------------------------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | Hitless application upgrades |
|--------|--------|------------------------------|

|   | · | Single-image programming model with no parallel programming or multi-threading |
|--------|--------|--------------------------------------------------------------------------------|

|   | · | Automatic ordering of frames |
|--------|--------|------------------------------|

|   | · | Automatic allocation of frame to processing engines (TOPs) |
|--------|--------|------------------------------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | [*] |
|--------|--------|-----|

|   | · | User-defined system configuration modes, i.e. user-defined ingress or egress functionality for each traffic manager |
|--------|--------|---------------------------------------------------------------------------------------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | LAG shaping |
|--------|--------|-------------|

|   | · | Work conserving and non-work conserving schedulers |
|--------|--------|----------------------------------------------------|

|   | · | Frame size from 1 byte to 16KB |
|--------|--------|--------------------------------|

|   | · | Up to 1 Gbyte total frame memory |
|--------|--------|----------------------------------|

|   | · | [*] |
|--------|--------|-----|

----

* This portion of the Exhibit has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Exhibit, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.

----

|   | · | Policing: Per-flow metering, marking and policing for millions of flows |
|--------|--------|-------------------------------------------------------------------------|

|   | · | Enhanced IFG emulation with packet- and cell-based interfaces configurable per user |
|--------|--------|-------------------------------------------------------------------------------------|

|   | · | Configurable WRED profiles |
|--------|--------|----------------------------|

|   | · | Per flow per color WRED statistics |
|--------|--------|------------------------------------|

|   | · | Packet based accounting WRED configurable in each level |
|--------|--------|---------------------------------------------------------|

|   | · | Shaping: Single and Dual leaky bucket controlling committed/peak rate/bursts (CIR, CIB, PIR, PIB) with IFG emulation for accurate rate control |
|--------|--------|------------------------------------------------------------------------------------------------------------------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | Scheduling: WFQ and priority scheduling at each hierarchy level |
|--------|--------|-----------------------------------------------------------------|

|   | · | Hardware flow control per port |
|--------|--------|--------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | KeepAlive frame generation for precise and accurate session maintenance operations |
|--------|--------|------------------------------------------------------------------------------------|

|   | · | KeepAlive watchdog timers for fastest detection time |
|--------|--------|------------------------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | Per-flow statistics for programmable events, traffic metering, policing and queuing |
|--------|--------|-------------------------------------------------------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | Programmable threshold settings and threshold exceeded notification |
|--------|--------|---------------------------------------------------------------------|

|   | · | Dynamic allocation and auto association between counters and flows. Counters are automatically recycled when a flow is aged or deleted. |
|--------|--------|-----------------------------------------------------------------------------------------------------------------------------------------|

|   | · | [*] |
|--------|--------|-----|

|   | · | Auto implementation of token bucket per flow (srTCM or trTCM or MEF5): |
|--------|--------|------------------------------------------------------------------------|

|   | · | Hardware implementation of token bucket calculations and coloring (i.e. green, yellow, red) |
|--------|--------|---------------------------------------------------------------------------------------------|

----

* This portion of the Exhibit has been omitted pursuant to a Request for Confidential Treatment under Rule 24b-2 of the Securities Exchange Act of 1934. The complete Exhibit, including the portions for which confidential treatment has been requested, has been filed separately with the Securities and Exchange Commission.

----

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