# Patent

## Title
Locally boosted top plate sampling for a sampling capacitor

## Abstract

An analog sampling network (100) includes a sampling capacitor being coupled between a bottom plate sampling switch and a top plate sampling switch implemented as NMOS transistors. The top plate sampling switch has source/drain terminals coupled respectively to the sampling capacitor and a first reference voltage. The analog sampling network includes a top plate boosting circuit (150) providing a boosted gate voltage to a gate terminal of the top plate sampling switch during a sampling phase, the boosted gate voltage being the sum of a first voltage and a second voltage. The first voltage is approximately equal to the first reference voltage and tracks process, temperature, power supply voltage and biasing condition variations. The second voltage is a maximum operating voltage from the gate to drain/source terminal for a fabrication process used to fabricate the second MOS transistor.

## Background
FIELD OF THE INVENTION
The invention relates to switched capacitor circuits and, in particular, to a voltage boosting circuit for boosting the top plate sampling voltage for a sampling capacitor.
DESCRIPTION OF THE RELATED ART
As sampling clock rate and dynamic range of analog-to-digital converters (ADCs) increase and power supply voltage continues to decrease with deep sub-micron or even nano-meter Complementary Metal Oxide Semiconductor (CMOS) fabrication processes in order to achieve higher operating rate and lower power dissipation and ultimately lower manufacturing and operation cost, it is becoming more difficult to design a highly linear analog sampling network using a switched capacitor circuit because of the lower effective gate to source voltage of the sampling transistors when the lower power supply voltages are used.
FIG. 1 is a circuit diagram of an exemplary switched capacitor circuit. Referring to FIG. 1, switched capacitor circuit 1 is configured as a single ended circuit. An analog input signal, VIN, is sampled across a sampling capacitor CS while 0V is sampled across a feedback capacitor CF during the sampling clock period (QS and QSE active). The top plate sampling switch 2 (driven by clock QSE) turns off prior to the bottom plate sampling switch 3 (driven by clock QS). During the holding or amplification clock period (QH active), the sampled charge on sampling capacitor CS is transferred onto feedback capacitor CF due to the negative feedback around an amplifier AMP. Therefore, the amplifier output voltage VOUT becomes VIN×CS/CF.
FIG. 2 is a circuit diagram of another exemplary switched capacitor circuit. Referring to FIG. 2, switched capacitor circuit 10 is configured as a differential input circuit. Differential analog input signals, VIN+ and VIN−, are sampled across sampling capacitors CS while 0V is sampled across corresponding feedback capacitors CF during the sampling clock period (QS and QSE active). The top plate sampling switch, implemented as NMOS transistors M1 and M2 and driven by clock QSE, turn off prior to the bottom plate sampling switches 13a and 13b (driven by clock QS). During the holding or amplification clock period (QH active), the sampled charges on sampling capacitors CS are transferred onto feedback capacitors CF due to the negative feedback around amplifier AMP. Therefore, the amplifier output voltage VOUT+/− becomes VIN+/−×CS/CF.
Bootstrapping techniques have been widely used for the bottom plate sampling switch of the sampling capacitor to provide a boosted gate voltage to the bottom plate sampling switch. By boosting the gate voltage, the “on” resistance variation at the bottom plate sampling switch is minimized over the input signal range. Bootstrapping techniques fit well into the switched capacitor circuit design with low power supply voltage.
FIG. 3 is a circuit diagram of an exemplary analog sampling network forming part of the switched capacitor circuit. Referring to FIG. 3, analog sampling network 20 includes a sampling capacitor CS for sampling an analog input signal VIN. A bottom plate sampling switch, implemented using an NMOS transistor MB, is coupled to the bottom plate (or left side) of sampling capacitor CS. A top plate sampling switch, implemented using an NMOS transistor MT, is coupled to the top plate (or right side) of sampling capacitor CS. During the sampling phase defined by the logically high period of clock signals QS and QSE, transistors MB and MT are turned on to sample the analog input signal VIN onto sampling capacitor CS. The top plate sampling switch MT, controlled by clock QSE, turns off slightly prior to the bottom sampling switch MB, controlled by clock QS, to prevent any input signal dependent charge injection. This sampling technique is referred to as bottom plate sampling. When the analog sampling network 20 is used in a switched capacitor circuit, the top plate of sampling capacitor CS (node 54) is coupled to the input terminal of the amplifier. The amplifier includes an NMOS input transistor pair receiving the input signal from sampling capacitor CS.
In most applications, the top plate sampling switch MT is connected between the top plate of sampling capacitor CS and a voltage VREFI (node 56). When applied in a switched capacitor circuit, voltage VREFI is the input common mode voltage of the amplifier. Circuit block 60 in FIG. 3 illustrates an exemplary circuit for generating the input common voltage VREFI. In circuit block 60, input common mode voltage VREFI is the node voltage connected to both the common gate node of cascaded NMOS transistors M11 and M12 and further to the drain node of transistor M12. A bias current IB, provided by a current source 62, flows though transistors M11 and M12.
In the implementation shown in FIG. 3, a bottom plate bootstrapping circuit 52 is applied to boost the gate voltage of bottom plate sampling switch MB. The bootstrapping circuit 52 includes a bootstrap capacitor CBS and switches 21-24 controlled by the clock signal QS and its inverse QSB. The bootstrapping circuit operates as follows. A fixed voltage, such as VDD, is sampled across bootstrap capacitor CBS during the QSB clock phase, which is the opposite clock phase of clock QS. Then, during the QS clock phase, capacitor CBS is connected between the gate and drain terminal of transistor MB. The drain terminal of transistor MB is coupled to the input voltage VIN. Accordingly, the gate voltage of transistor MB follows input voltage VIN and is shifted up by the VDD voltage as long as capacitor CBS is much larger than the gate capacitance of transistor MB. As the result of the bootstrap voltage applied by capacitor CBS, the “on” resistance of transistor MB remains constant regardless of the magnitude of the input voltage VIN, at least for the first order. There is a small higher order non-linearity due to the secondary effects of an NMOS transistor, such as body effect and voltage dependent drain-to-substrate and/or source-to-substrate junction capacitance, where the secondary effects are not being considered here.
In the analog sampling network shown in FIG. 3, the signal path from the input voltage VIN through the drain-to-source terminals of bottom plate sampling switch MB, through capacitor CS and through the drain-to-source terminals of top plate sampling switch MT and down to voltage VREFI (node 56) is the critical signal path for the sampling network. On the other hand, switches 22 and 24 in the bootstrap circuit 52, controlled by clock signal QSB, are not on the critical signal path. Long term reliability for these switches could be ensured by either using low speed but high voltage transistor devices if available or by appropriately cascading transistors.
The situation with top plate sampling switch MT is different compared to that of bottom plate sampling switch MB. First of all, the “on” resistance of transistor MT is constant regardless of the magnitude of input voltage VIN as long as the “on” resistance of transistor MT is small and voltage VREFI does not change instantaneously. Secondly, common mode voltage VREFI tracks power supply, temperature and process variations and thus does not behave as a fixed common mode for input voltage VIN. The total “on” resistance of both transistors MB and MT has to be small and consistent over the voltage range of input voltage VIN in order to maintain a high linearity for the sampling network. If the total “on” resistance is too large or varies, distortion at a high input frequency may occur due to the inherent non-linearity of both transistors MB and MT.
Other design issues for the top plate sampling switch are as follows. First, in conventional analog sampling networks, the gate voltage of transistor MT is not bootstrapped but is driven to a constant voltage, such as the power supply voltage, when clock QSE is active high. When an attenuated input signal VIN is presented across the drain-source node of transistor MT at a high input frequency, non-linear charge injection from transistor MT during clock phase QSE results in deteriorated linearity. Second, the power supply voltage decreases for smaller geometry CMOS processes due to the lower break-down voltage from gate to substrate or the lower tunneling voltage from drain to source node of the transistor. But as the power supply voltage decreases, the threshold voltage of the transistors does not decrease as fast as the supply voltage reduction mainly to maintain low leakage current between the source/drain terminals.
Furthermore, when voltage VREFI is close to half of the power supply voltage, the amount of effective voltage from the gate to source terminals of transistor MT becomes smaller. Consequently, the “on” resistance of transistor MT becomes larger instead of smaller as the geometry of CMOS processes becomes finer. However, the “on” resistance of transistor MT needs to be smaller to accommodate higher frequency sampling.
While it is possible to resolve the above issues by simply increasing the channel length of transistor MT. However, an increased channel length transistor MT increases the amount of switching and supply noise. Also, a larger MT transistor increases the amount of charge injection at the moment when the transistor is turning off so that the input common mode voltage of the gain amplifier actually gets moved down. It becomes harder to compensate for the increased charge injection with a dummy transistor connected to an inverted clock of QS because larger switch size for both transistors increases the absolute mismatch between the two transistors. The mismatch issue becomes more severe with narrower headroom margin of the amplifier at lower power supply voltage. Lastly, the larger dummy transistor requires an amplifier with wider bandwidth and higher DC gain to compensate the reduced feedback factor (β) so that the amplifier has to consume more power. Input referred noise increases as β decreases with gaining nothing at a given signal transfer gain.
When transistor MT is driven directly from the power supply voltage, the voltage of the gate to drain-source node of transistor MT is dependent on the change of supply voltage so that the “on” resistance of transistor MT increases with low supply voltage. Accordingly, it is hard to optimize the linearity of the sampling network and the tight input common mode control at same time over a wide operating range of power supply voltages.
One solution to decreasing the “on” resistance of transistor MT without increasing its channel width is to use a fixed boosted voltage VBOOST higher than the power supply VDD voltage to drive the gate terminal of transistor MT during the clock phase QS. FIG. 4 illustrates one exemplary circuit for generating such a boosted voltage. Referring to FIG. 4, a dedicated charge pump 82 drives a non-inverting negative feedback circuit formed by an amplifier 84 and two resistors R1 and R2. The output voltage of charge pump 82 has to be higher than voltage VBOOST for the headroom margin of the amplifier 84. In the example shown in FIG. 4, the output voltage of charge pump 82, denoted VCP, is set to close to 2 times of the power supply VDD voltage, assuming that the amount of average sinking current through the feedback circuit is negligibly smaller than that of the sourcing current from the charge pumping capacitor CCP2. For instance, a voltage VBOOST of 2.3V can be generated with the configuration of VREF=1.0V and R2=1.3×R1. Voltage VBOOST is given as (R1+R2)/R1*VREF. The maximum gate voltage for transistor MT can be higher than 2.3V with a given VREFI, but 2.3V is already higher than the maximum voltage of operating supply range of a common 0.18 um CMOS process.
The method of generating a boost voltage shown in FIG. 4 has many shortcomings. First, the boosted voltage VBOOST is a constant DC voltage independent of the power supply voltage, process and temperature variations only when the reference voltage VREF is a constant voltage. Even if voltage VREF tracks all three variations completely, voltage VBOOST could not match all three variations directly because of the amplification gain of the feedback circuit. Second, the switches connected to the charge pump voltage VCP node is exposed to a high voltage, which is even higher than voltage VBOOST. The long term reliability of devices is more susceptible whenever voltage at any node is high. Maximum voltage of every node has to be kept as low as possible for every transistor to be reliable. Third, the clock jitter of the sampling network increases due to the wide bandwidth of voltage VBOOST and the components on the signal path in the feedback circuit during clock QS. Fourth, a level shift circuit might be required to transfer the control clock signal from the clock signal chain to the gate of transistor MT when voltage VBOOST is higher than the power supply VDD voltage and the difference between two is larger than the threshold voltage of NMOS/PMOS transistor. Lastly, the high voltage VCP and the static current flowing through the feedback circuit causes power dissipation with low efficiency.
In summary, as supply voltage decreases with smaller geometry CMOS processes, it is becoming more difficult to keep the “on” resistance of top plate sampling switch of a switched capacitor sampling network low. Bootstrapping techniques have been used for the bottom plate sampling switch but the linearity of the sampling network starts to be limited by the top plate sampling switch at low supply and high frequency input signals.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of an exemplary switched capacitor circuit.
FIG. 2 is a circuit diagram of another exemplary switched capacitor circuit.
FIG. 3 is a circuit diagram of an exemplary analog sampling network forming part of the switched capacitor circuit.
FIG. 4 illustrates one exemplary circuit for generating such a boosted voltage.
FIG. 5 is a circuit diagram of a top plate boosting circuit incorporated in an analog sampling network according to one embodiment of the present invention.
FIG. 6 is a circuit diagram of a top plate boosting circuit incorporated in an analog sampling network according to an alternate embodiment of the present invention.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In accordance with the principles of the present invention, an analog sampling network for a switched capacitor circuit including a sampling capacitor and bottom plate and top plate sampling switches incorporates a top plate boosting circuit to boost the drive voltage of the top plate sampling switch. In this manner, the “on” resistance of the top plate sampling switch is kept small while the size of the switch is also kept small. More specifically, the gate voltage of the top plate sampling switch is driven to an optimal value and the maximum possible gate voltage is used for a given fabrication process regardless of power supply voltage, process, temperature and bias current variations by tracking these variable all at once. The top plate boosting circuit allows the maximum possible gate voltage to be used without damaging the top plate sampling switch. Furthermore, neither a local charge pump nor a feedback circuit is required.
FIG. 5 is a circuit diagram of a top plate boosting circuit incorporated in an analog sampling network according to one embodiment of the present invention. Referring to FIG. 5, analog sampling network 100 includes a sampling capacitor CS for sampling an analog input signal VIN. A bottom plate sampling switch, implemented using an NMOS transistor MB, is coupled to the bottom plate (or left side) of sampling capacitor CS. A top plate sampling switch, implemented using an NMOS transistor MT, is coupled to the top plate (or right side) of sampling capacitor CS. During the sampling phase defined by the logically high period of clock signals QS and QSE, transistors MB and MT are turned on to sample the analog input signal VIN onto sampling capacitor CS. The top plate sampling switch MT, controlled by clock QSE, turns off slightly prior to the bottom sampling switch MB, controlled by clock QS, to prevent any input signal dependent charge injection.
When the analog sampling network 100 is used in a switched capacitor circuit, the top plate of sampling capacitor CS (node 54) is coupled to the input terminal of the amplifier. In most applications, the top plate sampling switch MT is connected between the top plate of sampling capacitor CS and a voltage VREFI (node 56). When applied in a switched capacitor circuit, voltage VREFI is the input common mode voltage of the amplifier.
Analog sampling network 100 is shown with a bottom plate bootstrapping circuit 52 for boosting the gate voltage of the bottom plate sampling switch MB. The bottom plate bootstrapping circuit and its exact configuration thereof is not critical to the practice of the present invention. Any bootstrapping circuit can be used to boost the gate voltage of the bottom plate sampling switch in the analog sampling network 100 of the present invention.
In the present embodiment, analog sampling network 100 includes a boost voltage generation circuit 110 and a top plate boosting circuit 150 operating in conjunction to generate a boosted gate voltage VTOP for the top plate sampling switch MT. The boosted gate voltage VTOP has a maximum value that is within the reliability limit of transistor MT. In one embodiment, the boosted gate voltage VTOP is the sum of the common mode voltage VREFI and a voltage VMAX. Voltage VMAX is maximum operating voltage for a given fabrication process. In one embodiment, voltage VMAX is maximum operating voltage that can be applied across the gate to drain/source terminal of transistor MT for a given fabrication process without negatively affecting the reliability of the transistor.
In the present embodiment, boost voltage generation circuit 110 generates a boosted voltage VBOOST that not a fixed voltage but rather is the sum of the common mode voltage VREFI and a fixed DC voltage VDC from a voltage source 112. Boost voltage generation circuit 100 uses the same circuitry as in circuit block 60 for generating the common mode voltage VREFI. That is, common mode voltage VREFI (node 114) is generated using a bias current source 62 providing a current IB to cascaded NMOS transistors M11 and M12. The common mode voltage VREFI is added to the fixed DC voltage VDC to form the boosted voltage VBOOST (node 152).
At the top plate boosting circuit 150, the boosted voltage VBOOST is sampled onto a capacitor CBOOST during the clock phase defined by clock signal QSB. Clock phase QSB is the inverted clock phase of clock signal QS. Clock signal QS is active during the sampling phase of sampling capacitor CS. Thus, clock signal QSB is active outside of the sampling phase, that is, when sampling capacitor CS is not sampling the input voltage VIN. During the clock phase QSB, a first plate (node 154) of capacitor CBOOST is connected to the boosted voltage VBOOST (node 152) through a switch S11 and a second plate (node 156) of capacitor CBOOST is referenced to ground through a switch S12.
Then, during the clock phase defined by clock signal QSE, switches S11 and S12 are open while switches S21 and S22 are closed. Clock signal QSE is the same as the sampling clock signal QS but is deactivated earlier to prevent input signal dependent charge injection. When clock signal QSE is active, the first plate (node 154) of capacitor CBOOST is connected through switch S21 to the output node 158 providing the boosted gate voltage VTOP. The second plate (node 156) of capacitor CBOOST is connected through switch S22 to the power supply VDD voltage. When the second plate (node 156) of capacitor CBOOST is connected to the VDD voltage, the voltage value at the first plate (node 154) of capacitor CBOOST is pushed up by the VDD voltage as well. As a result, a boosted gate voltage VTOP is provided to drive the gate terminal of transistor MT, being the top side sampling switch for sampling capacitor CS. A switch S23, controlled by the inverse of the clock signal QSE, operates to discharge the boosted gate voltage VTOP outside of the sampling phase of the analog sampling network.
In the boosted voltage generation circuit 110, the common mode voltage VREFI thus generated automatically tracks fabrication process variation as well as temperature and bias current (IB) changes. The boosted voltage VBOOST is the sum of the common mode voltage VREFI and the DC voltage VDC (Eq. (1)). If voltage VDC is equal to voltage VMAX subtracted by VDD (Eq. (2)), then the boosted gate voltage VTOP will be given as VREFI plus VMAX of transistor MT (Eq. (3)) during the sample clock phase QS. The voltage relationships are expressed as follows:

VBOOST=VREFI+VDC;  Eq. (1)

VDC=VMAX−VDD;  Eq. (2)





  
    
      
        
          
            
              
                V
                TOP
              
              =
              
                
                  V
                  BOOST
                
                +
                
                  V
                  DD
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  REFI
                
                +
                
                  V
                  DC
                
                +
                
                  V
                  DD
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  REFI
                
                +
                
                  
                    V
                    MAX
                  
                  .
                
              
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        
          (
          3
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As thus generated, voltage VTOP is proportional to process variation, temperature and bias current IB changes, as well as supply voltage variation.

Another feature of the top plate boosting circuit is that the gate terminal of transistor MT is driven by the power supply VDD voltage through capacitor CBOOST instead of through voltage VBOOST during the sampling clock phase (clock signal QS). Accordingly, voltage VTOP (node 158) can settle down at the final voltage level quickly. The total integrated noise of voltage VBOOST can be made small by making the bandwidth of voltage VBOOST as narrow as possible. Even though the final voltage across capacitor CBOOST is not completely settled down at the end of the sampling period defined by clock QSB due to the narrow bandwidth of voltage VBOOST, voltage VTOP is not drifting but is level shifted by the amount of voltage sampled on capacitor CBOOST from the power supply VDD voltage. In fact, the amount of charge to be provided by voltage VBOOST onto capacitor CBOOST is just the amount of residual charge loss from the switches around capacitor CBOOST between the clock period QSE and QSB, and the residual charge is a small amount.
FIG. 6 illustrates an implementation of the boost voltage generation circuit for providing a boosted voltage to the top plate boosting circuit for use in the analog sampling network according to one embodiment of the present invention. Referring to FIG. 6, the voltage source providing voltage VDT is implemented using a first current source 220 providing a current IFIX and a second current source 222 providing a current IVDD, and a resistor R. Current source 220 and current source 222 are connected in series between the power supply VDD voltage and the ground voltage. Resistor R11 is connected to the common mode voltage VREFI node 214 and the common node 218 between the two current sources.
The value “1/gm” is the impedance as seen from the common node voltage VREFI node 214 toward the diode connected cascaded transistors M1 and M2. The 1/gm impedance has to be small enough in order to hold the top plate node 54 of sampling capacitor CS at a solid constant voltage even in the presence of a large amount of charge injection from transistors MT and MB at the beginning of clock signals QS and QSE. When the serially connected resistor R11 is much larger than 1/gm and currents IFIX and IVDD are VMAX/R11 and VDD/R11, respectively, the current IR1 flowing through resistor R11 is (VMAX−VDD)/R11. The boosted voltage VBOOST is given as:

VBOOST=VREFI+VMAX−VDD.

In the present embodiment, voltage VMAX could be equal to or greater than the power supply VDD voltage. A constant reference voltage VREF from a bandgap reference circuit can be used to generate current IFIX with appropriate ratio of resistors. That is:

VMAX=VREF·R2/R11,

IFIX=VMAX/R11=VREF·R2/(R11)2.

The resistor value of R2 is the function of voltage VMAX, voltage VREF and resistor R11 as shown above.

A large bypass capacitor CBY is added to the boosted voltage output node 218 to reduce the bandwidth of voltage VBOOST for small total integrated noise and to provide strong drive capability for capacitor CBOOST without using any dedicated power hungry and noisy amplifier.
In conclusion, as CMOS fabrication processes move toward finer geometry for faster and lower power supply voltage, and accordingly lower power dissipation and higher level system integration into a single device, it is becoming more difficult to keep the “on” resistance of a top plate sampling switch low without increasing the channel width of the switch. This is particularly problematic when the threshold voltage is not scaling down as aggressively as the power supply voltage. The top plate boosting circuit and method of the present invention consumes less power and introduces lower total integrated noise. Furthermore, the top plate boosting circuit and method of the present invention enables the gate voltage of the top plate sampling transistor MT to be driven by an optimal and maximum voltage with a given fabrication process technology and the gate voltage is independent of process and temperature variations as well as supply voltage and bias current changes.
The above detailed descriptions are provided to illustrate specific embodiments of the present invention and are not intended to be limiting. Numerous modifications and variations within the scope of the present invention are possible. The present invention is defined by the appended claims.

## Claims

1. An analog sampling network (100) including a sampling capacitor (CS) for sampling an analog input voltage (VIN), the sampling capacitor being coupled between a bottom plate sampling switch (MB) and a top plate sampling switch (MT) implemented as respective first and second NMOS transistors, the bottom plate sampling switch having source and drain terminals coupled respectively to the analog input voltage and one plate of the sampling capacitor, the top plate sampling switch having source and drain terminals coupled respectively to the other plate of the sampling capacitor and a first reference voltage (VREFI), the analog sampling network comprising:
a top plate boosting circuit (150) providing a boosted gate voltage (VTOP) to a gate terminal of the top plate sampling switch during a sampling phase of the analog sampling network, the boosted gate voltage being the sum of a first voltage and a second voltage (VMAX),
wherein the first voltage has a value approximately equal to the first reference voltage and the first voltage tracks fabrication process, temperature, power supply voltage and biasing condition variations, and the second voltage is a maximum operating voltage from the gate to drain or gate to source terminal for a fabrication process used to fabricate the second MOS transistor.

2. The analog sampling network of claim 1, further comprising:
a boost voltage generation circuit (110) generating a boosted voltage (VBOOST), the boosted voltage being the sum of the first reference voltage and a third voltage (VDC), the third voltage being the second voltage less a positive power supply voltage, the booted voltage being applied to the top plate boosting circuit to generate the boosted gate voltage.

3. The analog sampling network of claim 2, wherein the top plate boosting circuit comprises a first capacitor (CBOOST) being precharged to the boosted voltage outside of the sampling phase of the analog sampling network, and the precharged first capacitor being coupled across the positive power supply voltage and an output node (158) providing the boosted gate voltage, the precharged voltage across the first capacitor being pushed up by the positive power supply voltage to generate the boosted gate voltage being the sum of the first voltage and the second voltage.

4. The analog sampling network of claim 3, wherein the top plate boosting circuit further comprises:
a first switch (S11) coupled between the boosted voltage and a first plate (154) of the first capacitor, the first switch being controlled by a first clock signal being an inverse of the sampling phase of the analog sampling network;
a second switch (S12) coupled between a second plate (156) of the first capacitor and a ground voltage, the second switch being controlled by the first clock signal;
a third switch (S21) coupled between the first plate of the first capacitor and the output node (158), the third switch being controlled by a second clock signal indicating the sampling phase of the analog sampling network; and
a fourth switch (S22) coupled between the second plate of the first capacitor and the positive power supply voltage, the fourth switch being controlled by the second clock signal.

5. The analog sampling network of claim 4, wherein the top plate boosting circuit further comprises a fifth switch (S23) coupled between the output node and the ground voltage, the fifth switch being controlled by a third clock signal being an inverse of the sampling phase of the analog sampling network.

6. The analog sampling network of claim 1, wherein the first reference voltage comprises a common mode voltage of an amplifier to which the analog sampling network is coupled.

7. The analog sampling network of claim 2, wherein the boost voltage generation circuit comprises:
a third transistor (M22), being diode-connected, and a fourth transistor (M21) connected in series between a bias current source (212) providing a bias current and the ground voltage, the first reference voltage being developed at a node between the bias current source and the third transistor;
a first current source (220) providing a first current and a second current source (222) providing a second current, the first and second current sources being connected in series between the positive power supply voltage and the ground voltage;
a resistor connected between a gate terminal of the third transistor and a common node (218) between the first current source and the second current source, the common node being an output node of the boost voltage generation circuit providing the boosted voltage; and
a bypass capacitor connected between the output node of the boost voltage generation circuit and the ground voltage.

8. The analog sampling network of claim 1, wherein the second voltage comprises a maximum operating voltage that can be applied across the gate to drain or gate to source terminal of the second MOS transistor fabricated using a given fabrication process without negatively affecting the reliability of the second MOS transistor.

9. A method in an analog sampling network (100) including a sampling capacitor (CS) for sampling an analog input voltage (VIN), the sampling capacitor being coupled between a bottom plate sampling switch (MB) and a top plate sampling switch (MT) implemented as respective first and second NMOS transistors, the top plate sampling switch having source and drain terminals coupled respectively to the sampling capacitor and a first reference voltage (VREFI), the method comprising:
generating a first voltage having a value approximately equal to the first reference voltage and tracking tracks fabrication process, temperature, power supply voltage and biasing condition variations;
determining a second voltage being a maximum operating voltage from the gate to drain or gate to source drain/source terminal for a fabrication process used to fabricate the second MOS transistor;
generating a third voltage (VDC) being the second voltage less a positive power supply voltage;
generating a boosted voltage (VBOOST) being the sum of the first voltage and the third voltage;
precharging a first capacitor with the boosted voltage outside of a sampling phase of the analog sampling network;
connecting the precharged first capacitor across an output node and a positive power supply voltage during the sampling phase of the analog sampling network, the precharged voltage across the first capacitor being pushed up by the positive power supply voltage to generate a boosted gate voltage (VTOP) being the sum of the first voltage and the second voltage; and
applying the boosted gate voltage to a gate terminal of the top plate sampling switch during the sampling phase of the analog sampling network.

10. The method of claim 9, wherein the first reference voltage comprises a common mode voltage of an amplifier to which the analog sampling network is coupled.

11. The method of claim 9, wherein the second voltage comprises a maximum operating voltage that can be applied across the gate to drain or gate to source terminal of the second MOS transistor fabricated using a given fabrication process without negatively affecting the reliability of the second MOS transistor.