# Patent

## Title
Architectures for data analytics using computational NAND memory

## Abstract

A data analytic system allows for analytic operations be moved from a server on to a solid state drive (SSD) type analytic system, where a CAM NAND structure can be used in the analytic operations. The server can run a software using database language can issue command to the analytic system. On the data analytic system (that can interface with common, existing database language), the software commands are translated into firmware language and broken down into multiple small tasks. The small tasks are executed on the SSD flash controllers or on NAND flash according to the task specifications. The mid-product from the NAND flash or the SSD controllers can be merged within each SSD blade and also further merged on the top server level.

## Background
CROSS-REFERENCE TO RELATE APPLICATION
This application is a Continuation-In-Part of U.S. patent application Ser. No. 13/756,076, filed on Jan. 31, 2013, which is itself a Continuation-In-Part of U.S. patent application Ser. No. 13/749,361, filed on Jan. 24, 2013, which in turn claims priority from U.S. Provisional Applications Nos. 61/724,401, filed on Nov. 9, 2012, and 61/730,884 filed on Nov. 28, 2012, which are all hereby incorporated in their entirety by this reference.


FIELD OF THE INVENTION
This invention relates generally to non-volatile memories and, more specifically, to using non-volatile memory of a NAND-type architecture perform on-chip data analytics.
BACKGROUND OF THE INVENTION
Content addressable memories, also known as associative memories, are different from standard memories in the way that data is addressed and retrieved. In a conventional memory, an address is supplied and the data located at this specified address is retrieved. In contrast, in a content addressable memory (CAM), data is written as a key-data pair. To retrieve the data, a search key is supplied and all the keys in the memory are searched for a match. If a match is found, the corresponding data is retrieved.
Content Addressable Memories, or CAMs, can be implemented in several ways. In one sort of embodiment, a CAM is implemented using a conventional memory and an associated CPU which searches through the memory to find a matching key. The keys in the memory may be sorted, in which case a binary search can be used; or they can be unsorted, in which case they are usually hashed into buckets and each bucket is searched linearly. A CAM can also be implemented as a semiconductor memory, where every memory location contains an n-bit comparator. When an n-bit key is provided, each entry in the CAM will compare the search key with the entry's key, and signal a match if the two are equal.
SUMMARY OF INVENTION
A first set of aspects concern a method of performing data analytics using a server and a memory system connected to the server. The memory system includes control circuitry and a plurality of sets of memory arrays having a NAND type of architecture. The control circuitry including a plurality of memory controllers each associated with a corresponding set of memory arrays. The server runs software that issues commands to the memory system to perform one or more data analytic operations. The memory system receives the issued commands and translates them into a plurality of analytic tasks by firmware operating on the control circuitry. The firmware distributes the analytic tasks across the memory controllers to be executed by the memory controllers and corresponding sets memory of memory arrays. The analytic tasks are executed on the memory controllers and corresponding sets memory of memory arrays, wherein each of the analytic tasks are executed on the memory controller, the associated sets of memory arrays, or a combination of them as specified by the firmware. The final or medium results (final or inter mediate) from the analytic tasks are merged (by the server or firmware). The result can then be transferred out by the server as a graphical display. In this arrangement, the bottom memory layer can execute simple task on massive data. The middle layer of the flash controller or more sophisticated microprocessor can crunch more complicated data on lesser amounts of data. The combination of lower level data selection and upper level complicated computation can overcome the input/output limitations of the traditional data analytic system. Moving computing closer to the data also can save power as there is not the need to transfer all the data out.
Other aspects relate to methods of performing analytic operations on a plurality of sets of data. A memory system receives from a server a plurality of data sets and instructions for analytics to perform upon the data sets. The memory system includes control circuitry having one or more memory controllers and one or more memory circuits each having one or more memory arrays of non-volatile memory cells having a NAND type of architecture. The control circuitry breaks down the received instructions into a plurality of sub-operations and assigns one or more of the sub-operations to be performed on the control circuitry and one or more of the sub-operations to be performed within the memory circuits. The control circuitry derives from the received data sets a plurality of corresponding derived data sets for use in the sub-operations to be performed within the memory circuits and the derived data sets are written into one or more of the memory arrays, where the first derived data sets are written into the memory arrays oriented along bit lines. In some embodiments, duplicated data sets can be stored in the memory along word lines with normal ECC protection. The sub-operations can be operated on the data sets stored along the bit line direction for fast, but rough operations. Then operation results can be read out from the data set stored along the word line direction and more data analytics can be performed on the data sets. For any of the embodiments, the result of the analytics performed on the data sets are provided to the server.
Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic representation of a NAND array used as a CAM memory.
FIG. 2 is a schematic illustration of the network of some of the elements to supply the word line in a NAND array for conventional operation.
FIG. 3 is a schematic illustration of the network of some of the elements to supply the word line in a NAND array for CAM operation.
FIG. 4 shows one embodiment for how keys can be written along bit lines of an NAND array and searched.
FIG. 5 given some detail on how a key/inverse pair from FIG. 4 is programmed into a pair of NAND strings.
FIGS. 6A-C shows another embodiment for how keys can be written along bit lines of an NAND array and searched.
FIG. 7 shows an exemplary encoding of 2-bits per cells for four state memory cell operation.
FIG. 8 shows how the data states and the complementary data used for the inverted keys correspond in the 2-bit per cell example.
FIG. 9 shows an example of how a key would be encoded onto a 4 cell NAND string on bit line BL and its inverse on bit line BLB.
FIG. 10 illustrates the process of matching of content in word line direction.
FIG. 11 illustrates how the position of a conducting bit line can be used as an index in to another table that can be used to retrieve data associated with the target key.
FIG. 12 schematically illustrates how a key-value pair is stored in a NAND based CAM and how the value is accessed using the key.
FIG. 13 illustrates a memory arrangement for transposing the data keys.
FIG. 14 represents a first hardware embodiment for transposing data using a FIFO-type structure.
FIG. 15 represents another hardware embodiment for transposing data.
FIG. 16 shows one embodiment of a memory system incorporating a CAM type NAND into a solid state drive (SSD) for performing data analytic within the memory system.
FIG. 17 illustrates how data analytics with numerical range detection can be performed by exploiting an array's NAND structure.
FIG. 18 is an example of data latch assignments for the process illustrated by FIG. 17.
FIGS. 19 and 20 illustrate some steps of two search processes.
FIGS. 21 and 22 illustrate a maximum and a minimum search operation.
FIGS. 23 and 24 respectively give a schematic representation of an on-chip arithmetical operation and a corresponding latch utilization.
FIGS. 25A-C illustrate some detail of how arithmetic operations can be performed.
FIGS. 26A and 26B show how more latches can be used to perform arithmetic operations involving more n
FIGS. 27 and 28 illustrate an application to financial data analysis.
FIGS. 29-31 show some examples of how a data set can placed on more than on NAND string and corresponding latch structures.
FIGS. 32 and 33 respectively illustrate digital and analog counting techniques for analytics results.
FIG. 34 gives an example of file mapping for performing analytics on large file systems.
FIG. 35 illustrates a conventional architecture for server CPU based data analytics.
FIG. 36 illustrates an architecture using computational NAND in data analytics.
FIG. 37 shows a more detailed hardware architecture for a part of the data analytics system.
FIGS. 38A-D illustrate various aspects related performing to a “price summary report” query.
FIGS. 39A and 39B is a schematic representation of the division of tasks between the controller and NAND memory for the query of FIGS. 38A-D.
FIGS. 40A-D illustrate various aspects related performing to a “minimum cost supplier” query.
FIGS. 41A and 41B is a schematic representation of the division of tasks between the controller and NAND memory for the query of FIGS. 40A-D.
FIG. 42 illustrates the data structure using column and row storage.
FIG. 43 presents the relationship between the building blocks in the analytic system.
FIG. 44 is a schematic representation of a server based map reduce data analysis and how this can be moved to an CAM NAND based analytic system.
FIG. 45A illustrates a hardware architecture for a Hadoop arrangement and how CAM NAND can be incorporated.
FIG. 45B compares performance versus storage capacity for NAND based computing with CPU based computing.
FIG. 46 illustrates the use of CAM NAND memory based analytics for the sort and merge of un-structures data.
FIG. 47 schematically illustrates an example of when the sort is partially done in the SSD ASIC.
FIGS. 48-54 provides examples of analytic operations performed the CAM NAND based data analytics system.



DESCRIPTION OF THE PREFERRED EMBODIMENTS
Content Addressable Memory Based on NAND Flash Memory
The following presents a method of using a Flash based NAND memory array as a content addressable memory (CAM) that can be realized in both binary and ternary embodiments. As described in more detail below, keys can be programmed along the bit lines of a block. The search key is then input along the word lines of the blocks, so that a bit line on which a corresponding key has been programmed will be conducting. This allows for all the keys of a block to be checked at the same time.
The typical way by which a NAND memory array is read is that data is read out a single word line (or portion of a word line) at a time, with the non-selected word lines along the NAND strings being biased so that they are fully turned on regardless of the data state, removing the non-selected memory from affecting the read operation. In this way, the data content of the memory is read out a page (the unit of read) at a time. In contrast, to use a NAND flash memory as a content addressable memory, all of the word lines are set to a specific data dependent value, where the data is the key, and the memory determines which bit lines then conduct, thereby determining particular bit lines correspond to the input key, rather that the data of individual cells. An operation where sensing voltages are applied to multiple word lines in the context of an enhanced post-write read operation is given in U.S. patent application Ser. No. 13/332,780 filed on Dec. 21, 2011, (and which also presents more detail on NAND flash memory in general); however, even in that case only a few of the word lines receive a sensing voltage. Also, in prior art NAND memories, data was aligned along word lines, where data pages (for both read and write) are aligned along the word lines. Here, data is aligned along bit lines and many, or even all, of the word lines along the bit lines can receive either a high voltage sufficient to turn on a cell in a programmed state, or a low voltage sufficient to turn on a cell in the erased state. The following discussion will use the EEPROM based flash memory as the exemplary embodiment, but other memory devices having a NAND type of architecture, including 3D NAND (such as described in T. Maeda et al., “Multi-stacked 1 G cell/layer Pipe-shaped BiCS flash memory”, 2009 Symposium on VLSI Circuits, pages 22-23) for example, can also be used.
In a binary, EEPROM based flash memory, in a write operation each cell is either left in an erased state or charge is placed on the cell's floating gate to put the cell in a programmed state, which here are respectively taken as the 1 and 0 states. When a low value for the read voltage is applied to its control gate, only a cell in the erased, or 1, state will conduct. For cells in the programmed, or 0, state, a high value of the read voltage needs to be applied to the control gate for a cell to conduct. The keys will be arranged along bit lines of a block of the memory array. Since a cell in the 1 state will conduct for either read voltage, each key needs to be written twice, in inverted and non-inverted form. As discussed below, this can be done by writing the target key along one bit line and its inverse along another, or writing half the bit line with the (non-inverted) target key and the other half of the bit line with the inverted target key. More key info can be compressed into the NAND chain using multiple bits programming. For example, in a 2-3 bits per cell case, the key can be sorted in the controller RAM and the bits will be programmed as lower, (middle) or upper pages. The following discussion will mostly be given in terms of a binary embodiment, with some specifics of the multi-state case are discussed later.
The general concept can be illustrated by FIG. 1. Target keys Key 0, Key 1, . . . are programmed down bit lines BL0, BL1, . . . of a NAND block. Data is programmed in a separate location that can be indexed by the target key's column address number. To search the block for a key, the search key is broadcasted on the block's word lines by setting all of the word lines according to either the high or low read voltage according to the search key. (In addition to setting the word line voltages according to the key, the select gates at the end of the NAND string will also need to be turned on.) Each BL effectively compares itself to the WL key pattern for all of the bit lines in the block at the same time. If the bit line key matches the search key, the whole of the bit line will be conducting and a “1” will be read out. (Note that, as discussed further, this discussion is somewhat simplified for the reasons discussed in the last paragraph.) Once the column index of the key is found, it can be used to fetch the corresponding data from a “data” block. The key can be the hash code of the data page that will lead to the right data page by the column address of the matched NAND chain. For content matching applications, such as data compression or de-duplication, each 16 KB, say, of content can generate a corresponding hash code that can be stored along the NAND chain. If the key along the NAND chain is matched, then the data page will be compared with the comparing data along the word line to avoid hash collision cases. In other cases, the content along the word line may not be a hash value, but characteristics of the data elements that can be searched as a keys to data; or the bits lines themselves main be the elements of the data themselves, rather than a pointer to a data base.
Under the arrangement illustrated by FIG. 1, all of the bit lines of the array, and consequently all of the keys, are searched at the same time. In arrays that do not use an all bit line type of architecture, the number of keys searched simultaneously would be the number of bit line sensed in parallel, such as half of the total in an odd-even arrangement. The size of the key is the number of word lines. In practice, these maximum values of the keys will typically be somewhat less, since some column are usually set aside for defects, for instance.
As noted above, since a memory cell in either the 0 or 1 state will conduct for a high read voltage, the key will need to be entered twice, both non-inverted and inverted. This can be done by either programming the target key on two bit lines, reducing the number of keys by half, or programming both versions of the key on the same bit line, reducing the key size by half. However, given the size of available NAND blocks, even with these reductions the number of keys that can be checked in parallel is quite large. Relative to some other memory technologies, NAND flash memory has relatively large latencies in its operation, but in many applications this would more than be offset by the number of keys (bit lines) that can be checked in parallel (128K, for example). The process can all be done on-chip and, as only the bit lines that meet the matching case conducting current, with relatively low power consumption, so that compared to toggling out all of the data from the memory and doing the compare in the controller, it is a process of relatively low power and higher speed.
Looking at some implementation detail, an exemplary embodiment can be based on a flash memory where the indices are saved on the 128 Gb NAND chains. An all bit line (ABL) architecture is used where one sensing operations will perform a match operation on all of the indices on a block at the same time. Extra column redundancy is included to avoid any bad columns (more detail on such redundancy and the accessing of columns, as well as flash memory in general, can be found in the following US patent publication/application numbers: US-2005-0141387-A1; US-2008-0266957-A1; US-2011-0002169-A1; US-2010-0329007-A1; Ser. No. 13/463,422; and Ser. No. 13/420,961.) Two copies of the same data, Data and Data Bar, are written into the NAND chain. In the example, this allows for 16 KB/2/2=32000 sets of information with a 128 bit key.
When writing in the keys, these will be typically written on a page by page basis, although in memories that allow it, partial page programming can be used to write part of the keys, with more added later. Such partial page programming is typically more limited for multi-states implementations than in binary blocks. As one example, the data can be shifted on to the memory and the inverted data can be generated on the memory to save effort on the controller for these data manipulations, where the data and data bar can be written without shifting in the data twice, with the data being written first, and the generated inverse next. Both the keys and the data can be input into the memory system, or in some cases the keys could be generated on the memory system by the controller from the data, such as by generating hash values from the data to use as keys. If the keys are to be sorted before being written along the bit lines, this will typically be done on the controller due to the amount of data involved, such as multiple blocks' worth of data. For example, the data could initially be written in a particular area, say die 0, plane 0, blocks 0-15, and then sorted and written into the blocks having been sorted to the block level. Alternately, the keys could be assembled in RAM (either on the controller or on a separate chip) or cache NAND memory (such as described in U.S. provisional application No. 61/713,038) before sorting them to the desired level of granularity and writing them into a set of blocks.
As discussed further below, the data/data bar pairs can be written on two bits lines or on a single bit line. When the data/data bar pairs are written on two bit lines, such as discussed with respect to FIG. 4, the pairs can be written next to each other or in other patterns, such as writing the data bit lines in one area and the inverted data bit lines in another zone. When both parts of the pair on written on the same bit line, as discussed below with respect to FIG. 6A, they can be written in a top/bottom format or interleaved. For example, when the data and inverted data are interleaved to alternates down the word lines, this has the advantage that at most two elements in a row are the same down the bit line; further, interleaving can lead to efficient data transfer on to the memory as first a page of data is transferred on the memory and the next page can just be generated in the latches by inverting all the bits, as the next page is the inverted data of the first page.
The matched index can then be linked to other data corresponding to the determined column address; for instance, the keys could be a hash value, such as from a Secure Hash Algorithm (SHA), used to point to the actual data that can also be stored elsewhere on the memory itself. All the matching can be done inside of the NAND chip and, when the match is found, the column address can also be transferred out if needed or just the data, if also stored on the NAND chip, can be transferred out.
To efficiently implement the use of a NAND array as a CAM memory, changes can be made to the word line driving circuitry. To broadcast a search key down the word lines of a block, in addition to turning on the select gates on either end of the NAND strings, each word line of the block needs to be set to either the high or low read voltage according to the search key. This is in contrast to typical NAND operation, where only a single word line at a time is selected for a read voltage, with all of the other word lines receiving a pass voltage sufficient to remove them from influencing the sensing regardless of their data state.
FIG. 2 is a schematic illustration of the network of some of the elements to supply the word line in a NAND array for conventional operation. At 201 is the cell array for a plane of a NAND chip, with two blocks explicitly marked out at 203 and 205. Each block's word lines are feed by a word line select gate WLSW 213 or 215 as controlled from select circuitry at 217. The bit lines are not indicated, but would run down to the sense amp block S/A 207. The various control gate voltage CGI are then supplied to the select gates 213 and 215 from the drivers CG drivers 231 and UCG drivers 233 and 235 by way of switches 223 and 225, respectively. In the exemplary embodiment shown here, a block is taken to have 132 word lines, where a pair of dummy word lines are included on both the drain and source sides of the NAND strings. The UCG Drivers 233 and 235 are for supplying the pass voltages used on unselected word lines during program, (standard, non-CAM) read or verify operations. As this level is used on the large majority of word lines, these can be lumped together for a single driver. The selected control gates are biased to VPGM at program, CGR voltage at read or verify. In FIG. 2, CGI<126:1> is the decoded global CG lines. CGI<0> and CGI<127>, that are here biased differently from other 126 word lines due to edge word line effects. The dummy word line bias CGD0/1 is for the drain side dummy word lines and CGDS0/1 is for the source side ones.
For a typical NAND memory operation, only a few word lines at a time are individually biased. In addition to a selected word line, adjacent or edge word lines may receive special bias levels to improve operations. Consequently, existing word line drivers are arranged so that they can only take care of a handful of word lines. With logic changes, it may be possible to drive up to perhaps two dozen or so word lines. However, to drive all the word lines of a block (here 128, ignoring dummies) will require additional analog drivers. FIG. 3 illustrates some of these changes.
The array 301, blocks 303 and 305, select circuitry 317, CG Drivers 331, and switches 313 and 315 can be the same as in FIG. 2. The additional word line drivers are shown at 343 and 345 and can supply the word lines through respective switches at 353 and 355. In each of 343 and 345, the level shifter HVLSHIFT receives the voltage VREAD and a digital value DFF(0/1) for each word line. The level shifter then converts the digital values of 0, 1 for the broadcast key to the analog high and low word line levels. As the memory cells will still need to be written (both programmed and program verified), the other circuit sketched out in FIG. 2 will still be present, though not shown in FIG. 3 to simplify the discussion. It may also be preferable to make some changes to the sensing circuitry S/A 307 to more efficiently perform the XOR operation described below between the pairs of bit lines holding a key and its inverse.
FIG. 4 shows the encoding of the keys along bit lines, where the key is entered twice, in non-inverted and inverted form. Here the bit lines are labeled BL for the non-inverted key and BLB for the inverted version. Here the pairs are shown as being adjacent, although this need not be the case, but will typically make XOR-ing and keeping track of data easier. Also, this arrangement readily lends itself to NAND arrays using an odd/even BL arrangement. As shown in the half of FIG. 4, for reference a key of all 1s is written along BL1 and a key of all 0s is written along BLn, with the corresponding inverted keys at BLB1 and BLBn. For the defective bit lines, the bit line either stuck “0” or stuck “1” regardless of the word line voltage bias. The XOR results between the two read results will always yield “1”. The BL and BLB data pattern will eliminate the defected bit lines from yielding match results mistakenly. In this example, only seven word lines are used. A more interesting key of (1001101) is entered on BLn+1, with its inverted version at BLBn+1, as also illustrated in FIG. 5.
FIG. 5 shows the two corresponding NAND strings, where 0 is a programmed cell, 1 a cell left in its erased state, the cells being connected in series down the NAND strings to the common source line CELSRC. To search for this key, it is encoded as low read voltage for the 0 entries and high read voltage for the 1s. The search key is shown at the left of the top of FIG. 5. When put onto the word lines, this correspondingly finds that BLn+1 is conducting (and BLBn+1 is non-conducting), as shown by the “c” (and “nc”) in the sense 1 row. However, BL1 and BLBn are also both conducting, as a cell in the 1 state will conduct for either read value.
The second sensing (these can be performed in either order) is then made with the search reversed. Although BL1 and BLBn are still conducting, the result from the key actually sought has changed: BLn+1 is now non-conducting and BLBn+1 conducts. By taking the result of the two reads and XOR-ing them, the sought key will give a 0 on the corresponding bit line and also on its inverted version. Consequently, by searching for the 00 pattern in the XOR data, the output column address can be found and the corresponding data block accessed. Under the sort of embodiment used in FIG. 4, two reads are needed for the pattern match and internal pattern detection on the NAND device can judge if there is a match. The redundancy of the BL/BLB pairs provides redundancy to help protect from bad bit lines, but a second pair can also be kept for further protection. A copy of the key can also be kept with any associated data and used to check the match, where this copy can be ECC protected. Additional protection can also be provided by each bit line including several (8, for example) parity bits, for error detection and correction purposes, where the redundancy bit are preferable along the same bit lines for all of the keys so that these parity bits can either be read or taken out to the comparisons by use of a “don't care” value applied to these word lines, as described below. For example, the data can be read when checking when checking the data, as either part of a post-write read or other data integrity check, but ignored during CAM-type operations.
Generally, for both this and other embodiments described here, a post-write read can be used to insure that the keys have been successfully written into the NAND memory, as any error bits could prevent a NAND string from conducting and would give rise to “false negatives” when matching. If an error is found, the bad data can be rewritten. In the exemplary NAND flash example, the incorrectly written data can rewritten to another data block and any key-data correspondences updated accordingly. More detail on post-write read operations can be found in U.S. patent application Ser. No. 13/332,780 and references cited therein.
In terms of performance, in the case of a 16 KB page of 128 bit keys, if two copies of the both the data and its inverse are stored, the corresponds to 4 KB of keys, or 32000 keys. (As all of the word lines are sensed at once, so that here, a “page” involves a sensing of all the word lines of a block rather than a single word line.) If this page of 32000 keys is sensed in 50 us, this is a rate of 0.64 GC (Giga-compares) per second per plane. If four planes are sensed in parallel, this can lead to 2.56 GC/s at a consumption of about 200 mW.
FIG. 6A illustrates a second embodiment for how the key can be stored along a bit line. In this case, both the key and its inverse are written onto the same bit line. For a given block, this means that the maximum key size is only half the number of word lines, but this allows for the search key and inverted key to be broadcast at the same time. Consequently, the search can be done in a single read.
Referring to FIG. 6A, this shows 14 different word lines with the keys entered in the top half and the inverted versions of these same keys entered in inverted form in the bottom half of the same bit line. Thus, taking the bit line at D7, rows 1-7 hold a 7 bit key, and rows 8-14 the inverted version of the same key. (Although arranged similarly to FIG. 4, in FIG. 6A the top and bottom halves represent 14 different word lines where the top-bottom division is the key/inverted key boundary, whereas in FIG. 4, the top and bottom are the same seven word lines repeated twice for two different sensing operations.) For comparison purposes, the keys shown in FIG. 6A are the same as in FIG. 4, with the bit line of D7 holding the sought for key in the top half and its inverse in the bottom half, and D8 holding the inverted key so that these two halves are switched.
To search for a key, the search pattern is then broadcast on the top half word lines and its inverse on the bottom half word lines. Any bit lines with a matching keys, in this case D7, will then conduct, as shown at bottom where “nc” is non-conducting and “c” conducting. If redundancy is desired, the non-inverted version can also be programmed in as at D8 and then detected by broadcasting the non-inverted search key, and the bit lines reads searched for a 11 pattern, which can then be output as a data pointer. If further redundancy is wanted, the key or key/inverse pair can be written into the array a second time and parity bits can also be included, much the same way as discussed for the embodiments based on FIG. 4. The defective bit line should be isolated with isolation latch and not used. If some defect shows up as a stuck “0”, it can potentially generate the “false” match. In this case, the data content should be compared in order to confirm whether this is a real match or a false match. The other most common reliability issue is that some cells may have lost some charges after some time, that will also produce a “false” match. Then a content match check will eliminate the “false” match error. The word line voltage bias can be budgeted a little higher to avoid “missing” a match, which is very harmful error. A “false” match can be double checked with the content check.
FIG. 6B schematically illustrates the key/inverse pairs along NAND strings. Two strings are shown (for bit lines BLn and BLm) each having a drain and source select gate (SGD, SGS) on either end, where the source ends are then connected along the source line CELSRC. In between are the memory cells on the strings connected in series. In this example, the stings has cell capacity to hold a 48 bit key, its 48 bit inverse, and some parity bits. Although shown here with the key along the first 48 word lines followed by the inverse along the next 48 word lines, more generally they can interleaved in various ways; for example, each of the key bits can be followed it inverse in the next word line as, when programming, this allows for a page to loading in and written, after which the programming data can be inverted in the latches and written into the next word line. The parity bits can also be variously located along the NAND string, although having them grouped can lead to easier decoding when searching the keys.
Each of bit lines BLn and BLm show a portion of a key along four adjacent word lines and the corresponding four adjacent word lines holding the inverse. To search the keys of the block, the word lines are then biased according to the search key, where the high sensing voltage used to checking for “0” values and the low sensing voltage to check for ‘1” values. The high value is here taken as VREAD, and can be the same used in a typical NAND memory for non-selected word lines, and the low sensing values is labeled as V0. The select gates will also need to be on and VREAD should also be applied to the word lines holding parity bits as these as used for data integrity checks and are not meant factor into key search operations.
To make the stored keys more robust, the memory can shift the sensing margins to favor “false” matches rather than misses. (Similarly, the programming parameters can be shifter relative to those typically used.) The “false” matches can be examined by the data check later to help remove any false positives. A duplicated key can be used to check for preventing error, where these duplicates can be stored on other NAND strings, with the associated data, or other locations on the system. Relative to a standard NAND memory, this arrangement will need to add extra circuitry, as described with respect to FIGS. 2 and 3.
Rather than sense the search for the full key (or key/inverse) in a single sensing, a partial key can be searched, allowing the full key/inverse matching to be done incrementally. This can allows for the less independently settable word line levels, resulting in less circuitry changes relative to a standard NAND memory, but it can require some logic changes. The full key/inverse can be searched sequentially, where each subsequent sensing will be judged based on previous sensing results. For the example of FIG. 6B, rather than check all 24+24 word lines of the key/inverse in one go, a partially key check of, say 24 bits at a time can be done: if no matches are found, the process can move on to any other blocks holding keys; if a match is found, a second partial key can be checked, and so on. The subsequent checks can either do all of the NAND string again and compare the results of the partial searches, or only check those which have conducted in the previous partial key matches. FIG. 6C illustrated such a partial key comparison, where only 24 bits of the 48 bits in the key are being checked. The other bits of the key and its inverse are then set to the “don't care” value, as shown at the corresponding bits of the inverse that are set at VREAD.
As each key is written in twice (non-inverted, inverted) on a bit line, a block with 128 word lines can hold 64 bit keys, while 128 bit keys would need blocks of 256 word lines. Also, it should be noted that although the key/inverted keys are here shown as being written respectively into the top half/bottom half of the word lines. More generally, the keys and inverse pairs could be interleaved in any desired fashion, as long as it was consistent for all of the keys in the block; however, this would require keeping track of the arrangement. The interleaved pattern along the NAND chain may be preferred since the data can be inversely program in another WL without loading the data again. There are some other coupling effect may also benefit from interleaving the inverted and non-inverted data on adjacent word lines. In terms of performance for this type of embodiment, for a 16 KB page of 64 bit keys, if a duplicate key/inverted key pair is kept, this is 8 KB, or 64,000 keys. At 35 us per sensing, this gives 1.82 C/s/plane. If 4 planes are operated in parallel, this is 7.3 CG/s at around 200 mW.
For either of the embodiments of FIG. 4 or FIG. 6A, the method uses the inherent “AND” functionality available in a NAND Flash memory to compare thousands of keys in a single sensing operation. This method has several major advantages over traditional CPU- or semiconductor-based CAM memories. For one, as the comparison is done “on die”, there is no need to transfer the data out of the memory. This saves both time and IO power. Furthermore the actual comparison operations use less power than conventional memories. As all of the bit lines are sensed at the same time, with only the matching NAND chain is conducting current, the NAND based CAM is highly parallel; for example, in a NAND flash memory with 4×8 KB planes, (32K×8 bits/byte)/2=128K keys can be checked in one sense per die. If a sense can be done in 35 us, an even/odd sense as described above with respect to FIG. 4 will take 50 us. This is 128K keys in 50 us, so that an entire 8 GB die (2000 blocks) could be sensed in  ̃100 ms. The corresponding energy consumption is on the order of 200 mW. To increase performance, multiple die can be operated in parallel.
As noted in the Background section, keys can be stored in a CAM as either sorted, in which case a binary search can be used; or as unsorted, in which case a linear search is used. This is also true of a NAND based CAM, except that as NAND based CAM can be searched at the block level, in a sorted CAM the keys need only be sorted to the granularity of the block or the number of blocks that are sensed in parallel. The CAM allows for a binary search, but at the block level due to this parallelism. Even for linear searches, this degree of parallelism can make linear searching comparable or even faster than binary searches for fairly large data sets. Again, for any of these arrangements, performance here can also be improved by running multiple die in parallel.
The keys can be sorted based on a given number of most (or least) significant bits. A sorting based on significant bits is generally most useful when the key or content being searched is not a hash value, but a set of characteristics or data itself. In this case, the sorted data in each block would all share a certain number of most significant bits for their keys.
Content addressable memory exist in both binary form, where the search key consists of 0s and 1s as described above, and ternary form, where the search key can also include “don't care” value. As discussed above, when a high read value is broadcast along a word line, all of the cells along that word line will conduct regardless of its state. This property allows for a “don't care” value to be implemented by setting the corresponding word line to the high read voltage for both the key and its inverse; that is, when sensing with the key and its inverse (in either the second read of FIG. 4, or the lower half of the word lines), the don't care values are set to the high read value for both the key and its inverse, while the other values of the key are inverted as before.
These properties of a NAND based CAM also make it particularly suited to a number of other uses. For instance, as large numbers of keys can be searched in parallel, this allows for all copies of the same key in the searched blocks to be determined in the process, improving efficiency of de-duplication operations of the sort that are valuable in cleaning up data bases. The NAND structure also makes for a CAM useful as a Bloom filter as an intersection of multiple search keys can be formed by setting any values that differ between the keys to the high read voltage in the combined search key, which can then be used to search the horizontally stored keys of one or more blocks in parallel. (More detail on using bloom filter with the sort of memory can be found in a US patent application entitled “Data Search Using Bloom Filters and NAND Based Content Addressable Memory” by Steven Sprouse and Yan Li filed on Mar. 14, 2013.)
The use of “don't care” values can also be used to perform a type of “iterative” search. This can be used the keys may have, or possibly have, some number of bit errors. One or a series of reduced keys, where some subset of values are set to “don't care” for different entries, are used for searching. Several different such keys, where a different subset of values is masked out in each, are then iteratively used to check for matches among the written keys.
Another example of where a series of reduced search keys can be employed is where the content is itself a data set, as opposed to say a hash value. For example, it could be values from image processing. In such a case, the content of the block could be searched to a desired number of significant bits, by setting bits of lower significance to “don't care”. Similar arrangement could also be used for patterning matching of the content or for cases where the keys are properties of main data content.
Consequently, due to its parallelism, relatively low power consumption, or both, NAND based CAM can be used in many applications, such as data base searching, voice recognition, DNA matching/genome searches, cryptography and so on. It can lend itself to CAM based indexing and can be incorporated, for example into CAM indexed SSD systems.
So far the discussion has mainly considered the ease of binary NAND memory for CAM use. More generally, multi-state (MLC) memory can also be used; for example, in a mixed binary-MLC memory, the keys could be stored in binary memory for CAM use, while data to which the keys pointed could be stored in MLC areas. It is also possible to use MLC NAND memory for CAM, using 2 to 3 bits per cell, for example, in key matching. Using 2 to 3 bits per cell, the NAND chain can store longer keys. In the sort of embodiment described with respect to FIG. 6A, where a key and its inverse are written into the same word line, a 128 cell NAND chain in binary operation can store 64 bit keys, while a 128 NAND chain with 2-bits per cell can store 128 bits keys. Similarly, 3-bits per cell operation can store 192 bit keys.
FIG. 7 shows an exemplary encoding of 2-bits per cells for four state memory cell operation. As shown, the erased state is encoded as 11, the first state up (or “a” state) is 10, followed by 00 (for the “b” state) and 01 (or “c” state). The various sensing levels are also shown. FIG. 8 shows how the data states and the complementary data used for the inverted keys correspond. FIG. 9 shows an example of how a key ({00111001}) would be encoded onto a 4 cell NAND string on bit line BL and its complement on bit line BLB. In the MLC CAM embodiment, the system can use one or two word lines along the NAND chains to store the parity bits of each NAND chain in order to check on the integrity of the NAND chain. As with the binary case, manufacture defective columns can be isolated out and more redundancy along the word lines (duplicated data) can further protect the keys' integrity. Also, the complementary data shifted as illustrated in the figures to provide more sensing margins.
In the above, keys were written down the bit lines of the array, with the search key broadcast along the word lines, allowing the keys along a block's bit lines to be searched in parallel. The arrangement can also be reversed, where NAND array can also be operated so that the content or key matching is in the word line direction. Under this arrangement, one or more keys would be written along each word line (that can be very long keys), an arrangement that can be useful in several different circumstances. Multiple short keys can be stored along the word line direction as well. If the keys are encoded so as to have significance as a 2D array of values, this would allow for content searching in both of the bit line and word line directions, although the more typical situation would just be for content matching in the word line direction. For instance, as word lines are much long than bit lines, a word line based CAM allows for the use of longer keys. Also, as data is written in page along word lines, it may be more convenient, at least initially, to write incoming key data along word lines. This would then allow for key to be searched as written along the word lines. If desired, the keys could then be rewritten along bit lines, where they could then be searched as described above. Due to the amount of data involved, to move the keys from a word line orientation onto a bit line orientation, once a block worth of the keys are assembled they could be read off of the NAND memory into the controller and then rearranged and written along bit lines; alternately, this rotation of the keys could be performed on the NAND device, although this will typically require the memory chip's structure to modified to accomplish this. This process of initially writing the keys along word lines, transferring the keys to the controller, and rearranging them to be rewritten onto bit lines can also include the sort of sorting process described above prior to rewriting them back in a bit line orientation.
The process of matching of content in word line direction is illustrated with respect to FIG. 10. As the system receives keys, these can be formed into pages of one or more keys and written into the memory array 901 along word lines. To match content, the system inputs the matching content of one or more search keys into a matching buffer or register 905, which can then be used to look for duplication content along the word line. The data along a word line is read from memory array 901 into a buffer or register 903. The memory can then perform internal match operations between the read data in buffer 903 and search data in buffer 905, where some number of bits ignored, if desired. The ignored bits can either be to “don't care” values, because some read error can occur on the read. These ignored bits can be corrected with error correction in the controller when a match is found. Typically, the smallest length of key/content along the word line that can be compared is 1 KB, while the longest length of key/content that can be compared in one plane is 16 KB. If the key length is smaller than 1 KB, the key can be duplicated in chunks patterns to do the pattern matching with more parallelism. Then the matched case will produce a group of “1” and the un-matched case will produce 50% “1”s. Circuitry can detect if a word is all “1”s to judge the match or miss. If there are some “0”s in a word, this word can be discarded as a miss. In order to prevent that some read errors produce a miss when it should be a match, a majority voting circuitry can be employed to choose the word with majority “1”s for matching. Some words can be masked out by marking the isolation latch to be “ignored”. To simplify operations, it is typically preferable to write the beginning of a file to aligned with certain columns. After finishing a compare on one word line, the next word line content can be compared in a similar sequence.
Key-Value Addressed Storage Drive Using NAND Flash Based CAM
This section considers the incorporation of the sort of NAND Flash content addressable memory (CAM) or content addressable storage (CAS) described above in a storage drive. Conventional storage drives, such as solid state dives or hard-disk drives (SSD or HDD), are addressed by a logical block address (LBA) to read and write data stored on their physical media. These employ logical to physical address translation tables to locate the data, where the address translation table is stored on flash, in DRAM, or on magnetic media and is updated on the basis of sectors, bytes, or pages. Typical sizes for such addresses are 32, 48, or 64-bits. In some applications, such as in databases, it is desirable to have large keys (of hundreds or thousands of bits) that can address a space much larger than the number of elements in the database. In these cases a content addressable memory utilizing key-value pairs is used to index the elements stored in the device.
In a content addressable memory, data is written as a key-data pair. To retrieve the data, a search key is supplied; all the keys in the memory are searched for a match. If a match is found, the corresponding data is retrieved. This section presents a storage drive using a Flash based NAND array as described in the preceding section as a content addressable memory that is addressed using key-value pairs instead of a logical block address. This drive can provide both Binary and Ternary search capability, meaning that bit patterns in the key can have the values 1 or 0 as well as “don't care” entries. This type of NAND based CAS drive can then be used to replace other implementations of CAM or CAS functionality, such as those employing a database, that would usually include a host CPU, DRAM, and storage media.
Consequently, this section applies the of operation of a NAND flash memory as a pattern matching engine from the last section to a storage device that is indexed using key-value pairs instead of conventional logical block addresses. The device can use a standard transport protocol such as PCI-E, SAS, SATA, eMMC, SCSI, and so on. When used in a pattern matching mode, the NAND cells not only store values, but can also be used to compare their stored values with an input value. In the examples of this section, target patterns are stored along bit lines, although the word line based storage discussed above can also be used. In the bit line example, the pattern to be matched is broadcast down word lines. If all the elements in the NAND chain match their target pattern, the NAND chain (bit line) will conduct. The position of the conducting bit line can be used as an index in to another table that can be used to retrieve data that is associated with the target key. This is shown in FIG. 11, that expands upon FIG. 1.
In FIG. 11, the bit lines BL0, BL1, . . . run down the columns of the array and are written with corresponding keys Key 0, Key 1, . . . as previously described. The word lines are then biased according to the search key (here Key 2) so that it is broad to all of the bit lines spanned by the word lines. When a matching key or keys are found, the column address of the bit line is then input as an index to find the data set, also stored on the drive. A number of arrangements are possible, where, for example, the keys could be stored in binary or MLC arrays optimized for CAM use, while the data is stored in more standard MLC arrays.
A drive using such a mechanism can then be used to search for key-value pairs in a large search space, perform general pattern matching (using bloom filters), or be used for determining set membership. Some of the advantages of a drive using such a scheme include low power usage and high bandwidth. As data does not need to be moved from the NAND array to a separate computational module for comparison, power consumed on IO operations is reduced. Furthermore, since only bit lines that match a given search pattern will conduct, the NAND comparison operation is also low power. With respect to bandwidth, a single NAND die is capable of doing, say, 256K 64-bit comparisons in under 50 us, working out to under 200 ps per comparison. Additionally, multiple die can be operated in parallel to increase bandwidth or to increase the effective key-length. Potentially 8 Gb ( ̃8 G keys) of 64-bit keys can be searched in  ̃100 ms in a single die based on current design.
The idea of using a storage drive with a common interface, such as SAS, PCI-E, SATA, and so on, but which is written using key-value pairs instead of a conventional logical addressing is consider further with respect to FIG. 12. In the write method, the host will write Key-Value pair (K, V) to the drive. The drive will store the Value V in a data store at some address in the Data table of FIG. 12, as illustrate at (1). The drive will store the key value K on a bit line “i” in a block of an array of the drive, as shown at (2) of FIG. 12. The drive will make an entry in the block table at address i, with a pointer to the value V, as shown at (3). The column address which has the matching key can be output from NAND memory from status bits.
In NAND flash memory, data is written in word line based pages. Because of this, as previously discussed, the keys may be initially written along word lines, then rearranged to be written along bit lines, or first stored in RAM and then sorted into bit lined oriented keys. (It could also be possible for the host to have already taken care of this bit line based orientation for the keys, although it will generally be preferable for this operation to be transparent as seen from outside of the drive, with a host just providing basic key-value pairs and not having to engage in such data manipulations.) The controller will take care of assigning the keys and values to physical addresses and of determining the needed addressing structures to translate the key into the corresponding data location. The key to value mapping tables can be maintained in much the same way as the usual logical to physical mapping tables as far storing them and updating them, such as mappings using look up tables or based a correspondence formula. For example, the column address can be mapped to metadata in the primary storage flash management layers.
In a variation, if the drive itself has a key generating ability, such as a hashing algorithm using by the controller, just the data set itself could be sent to the drive and the corresponding keys generated on the drive. This would also allow a different host without the key generating ability to send data to the drive, where the key-value then be generated and stored. Under this sort of arrangement, for a host to access a value using a key, the host would need to use the same key generating algorithm (such as from a Secure Hash Algorithm (SHA), for example) as being used by the drive.
Looking now at the read process, the host will send the drive a key (K) that is then used to search key blocks. As discussed in the previous section, the key blocks may be sorted, in which case a binary search can be used; or they can be unsorted, in which case a linear search is used. For each key block, the drive will apply the key K to the word lines. If a matching key exists along a bit line in the block, NAND flash will register a “1” at the bit position “j” associated with the matching key. The value “j” can then be used as an index to the associated block table, as represented at (4) in FIG. 12, to retrieve a pointer, (3), to the associated value V in the Data Table. If all key blocks are searched without finding a match, the drive can return an “element not found status” or error.
The CAM NAND can be incorporate into the same memory system as that in which the associated data is stored, such as an SSD, in which case the data corresponding to the search key can be provided directly to the host. In other embodiments, the CAM NAND could be a separate device used to provide the sort of CAM-based operations described here, while the associated data could be stored separately, in which case as address or other pointer to the corresponding data on the separated device would be provided.
Consequently, storage drive can benefit by use of the inherent “AND” functionality available in a NAND Flash memory to compare thousands of keys in a single sensing operation. A storage drive of this type has several major advantages over traditional CPU- or semiconductor-based CAM memories. First, because the key comparison is done “on die”, there is no need to transfer the data out of the memory. This saves both time and IO Power. Furthermore the actual comparison operations use less power than conventional memories.
In addition to the low power and high bandwidth advantages discussed in more detail earlier, this scheme has the advantage that write times can be shorter if data is searched in a linear mode. Most databases spend time and energy sorting and maintaining tables to enable fast, binary type, search capability for when data is read. In one embodiment of this invention, the writes of data and keys can be done in a random fashion making writes times of O(1) complexity. Searches will use a linear search mechanism which is highly parallelized but is still O(N) complexity. This is less efficient than the O(Log N) of most binary searches and is a tradeoff between insertion time vs. lookup time. Also, it should be noted that even when data is stored in a sorted manner, the high degree of parallelism in searching mean that the sorting only needs to be done to the level at which the search is done, namely to the granularity of block or number of blocks searchable in parallel.
The sort of NAND flash base CAS drives can be applied to a number of applications, including those described in the previous section. One set of examples of these exemplary applications is for de-duplication using pattern matching (CAM) NAND to store the hash keys. Incoming data can be sent through the hash function to generate the content related fingerprints. The fingerprints can then be searched with the existing hash keys to see whether the data already exists in the data storage. If it does already exist, no write action is taken; but if the data does not yet exit, then the new data will be written into the storage. The de-duplication can be done when the data is backing up, during garbage collection operations of the primary storage, or in-line as the data comes in from host. Another application is for virtual memory management, which can be done similarly to de-duplication. (More detail on de-duplication can be found in U.S. patent application Ser. Nos. 13/794,398 and 13/794,428, both filed on Mar. 11, 2013, that develop these concepts further.) The drive can also be applied to the Human Genome, where the drives stores signatures in the CAM NAND so that any segment of the DNA sequence can be searched. The drive also lends itself to parallel computing where, a mathematical NAND function can be done inside of the NAND memory.
As noted above, the CAM NAND operation has the keys oriented along bit line, whereas NAND memory written along word lines. Consequently, as the keys come in from a host, they need to be accumulated in a buffer memory of some sort, transposed to a bit line orientation, formed into pages (including adding any inverse keys as needed), and transferred to the NAND device for writing. This is illustrated schematically in FIG. 13.
As shown in FIG. 13, a host 1301 (a PC, for example) can take the data files and generate the corresponding keys, such as using a Secure Hash Algorithm (SHA) to generate a 64 bit hash key, which can then be transferred over to a buffer memory 1303 on the memory system, where the keys can be accumulated. The transposing buffer memory 1303 is used to align the keys for writing in the NAND CAM memory 1305. Once a sufficient number of keys, say 4 MB keys for a NAND memory 1305 with 4 MB blocks, the data can be transferred over for programming as pages along the word lines. FIGS. 14 and 15 give some examples of hardware implementations for the transposing buffer memory, but this can be implemented in various other ways, such as by use of a field programmable gate array (FPGA). For example, a blocks worth of keys could be accumulated in an FPGA and then read out a word line at a time and transferred over to the CAM NAND for writing.
FIG. 14 is a schematic illustration of a hardware implementation of the transposing memory in FIFO style. The data can come in as, say, 64 bits keys or indices and is saved in column-oriented 64 bits registers. The registers are chained into a FIFO arrangement so that when a new key comes in, the previous keys shift over by one column to the right. Once there are enough keys for one page (i.e., 8 KB to 16 KB for a typical design) to be programmed into the CAM NAND memory (or early, if smaller number of keys are to be used), the pages are shifted over to the NAND for programming into the array there. Under this arrangement, if desired, the keys may be searched while still in the FIFO before being programmed, as the keys can be shifted out one at a time for comparison.
FIG. 15 is a schematic illustration of another hardware implementation for transposing the data keys using more of a RAM style arrangement. The data can come in as, for example, 64 bit keys or indices and be saved in 64 bits registers, being accumulated in a relatively small, 16×64 array 1509 in latches. The 16×64 bits of the small array 1509 can then be shifted over a bus 1507 a word (16 bits) at a time into the RAM 1503. After shifting the 64 words into RAM, the small array 1509 can accumulate next 16×64 bits. This process can continue until the RAM 1503 is full or it is otherwise desired to write in the keys, at which point is programmed in the CAM NAND memory. Under the arrangement of FIG. 15, if it is desired to search the keys before they are written into the CAM NAND, another RAM buffer storing the keys without transpose can be kept for this search purpose.
Applications to Data Analytics
On-Device Data Analytics Using NAND Flash Based Intelligent Memory
The sort of highly parallel operations using a memory device of a NAND structure as a content addressable memory described in the preceding sections can also be applied to performing data analytics. This allows for massively parallel computing to be applied to various analytic applications, where the computing be performed inside of the storage and remotely from the server. This arrangement can also allow processing to be done in real time, using inline processing, and also allow for the analytics to be executed without input/output transmission limitations. Consequently, these techniques and structures can be applied to many applications, from crunching large amounts of data in data warehousing applications, quantitative analysis of financial data, and other data analysis intensive uses.
A number of topologies can be used, with one example shown in FIG. 16. In this example, a memory system 1601 is a computing solid state drive (SSD) that includes a main storage SSD section 1603, the NAND device used can be normal NAND devices as well as CAM type NAND. In the exemplary embodiment, the NAND portion 1605 as again taken as an EEPROM based flash memory when a specific concrete example is needed. A host 1611, such as a PC or even a network connection, provides data and any instructions for analytics to perform on the data to the memory system 1601. The data can be supplied to the NAND section 1605 to be stored for analyzing and then to the main storage section 1603, allowing for in-line analysis if desired, or stored directly in the main storage section 1603 and retrieved to NAND module 1605 when analysis is requested. In some cases, such as when the data are key/associated data pairs, the keys could be stored on the NAND 1605 and the associated data going to the main storage section 1603, where the system can maintain a key-data correspondence as described in preceding sections. In case where, in response to a request from the host, data is transferred from the main storage section 1603 to the NAND section 1605 to have analytics performed, the CPU or GPU or SSD controller could be used to perform some initial manipulations (choosing data subsets, generating hash values, and so on) as needed before writing the data into the NAND structure of 1605.
The arrangement of FIG. 16 will be used as the exemplary embodiment in the following, but a number of variations or other topologies can be used. For example, the main data storage section 1603 need not be a SSD, but could be hard drives or other data storage. Also, the NAND portion 1605 need not be incorporated into the same system as the main storage 1603, but a separate system for this portion used in conjunction with a bulk data storage system. In other cases, where the amounts of data are manageable by the CAM-based. NAND system itself, the NAND system can be used directly with the host for performing data analytics. For instance, a portable device incorporating the CAM NAND and some additional flash storage may be sufficient.
FIGS. 17-20 illustrate how the NAND array can be used to perform analytics in parallel for all of the columns of the array when the data includes both categorical (i.e., data that can fit into multiple categories, such as (red, blue, green) or (yes, no)) data as well as numerical range detection. Due to the CAM nature of the memory described here, multiple categories can be handled. In this example, categorical and numerical data can be stored along the same NAND strings, but the categorical data is saved in a binary format, while the numerical data can be save as binary (D1), 2-bit per cell (D2), 3-bit per cell (D3) or other multi-state format. It should also be noted that the categorical/numerical distinction is not necessarily hard and fast, as the techniques described here allow for the processing of numerical data to make it into categorical data for purposes of analysis as, in some case this can be faster than performing numerical comparisons. The more bits per cell, the fewer the number of word lines that will be used to store the data, but with the increased complexity involved in such multi-state operations. The analytics will generate a match for the specific query and the match results can be counted inside the NAND or outside of NAND. As discussed further below with respect to FIGS. 30 and 31, the counting can be done inside NAND digitally, which is precise, or in an analog, which is faster but less accurate. When counting outside NAND, the match results will be transferred to controller and the number of “1” or “0” will be counted there.
FIG. 17, at left, shows how two of the data sets of a block are written onto NAND strings along bit lines BLn and BLm. At upper portion of each string is entered categorical data in binary form, with some numerical data further down, where a 3-bit per cell format is shown, the bits arranged top to bottom as least to most significant bits. Here the shown categorical data word lines can be searched first, with the analytics then performed on numerical data for the matched “category”. The categorical data can be “don't care” or not written with the numerical data at the same memory block. The numerical data can then be sequentially analyzed, here starting with the most significant bit, by reading one word line at a time, placing the appropriate read level (CGRV) on the MSB word line. At right is a schematic representation of how the numerical data can be compared as a sequence of queries. Each of the bit lines has an associated set of latches that can be used to keep track of the results of the sequence of analytic operation, where an example of how the results are assigned to the latches is shown in FIG. 18. (The data latches here are labeled XDL, UDL, and, further down, LDL for transfer, upper, and lower data latch respectively, to correspond to the arrangement such as that described in U.S. Pat. Nos. 7,206,230 and 8,102,705, where more detail on such latch structures can be found, and also see FIGS. 28 and 29 below.)
The table of FIG. 19 shows an example of a compare to see whether a number is greater than 010011001 for four data values. The search is here done from the most significant bit down towards the least. When the most significant bit (MSB9) is searched, the top value is found to be greater than the search number, the latches are set accordingly, subsequent reads are ignored and no updates are made. For the other three values, the results are indeterminate. When the next bit, MSB8, is checked, the second data is still indeterminate, but the lower two values are found to be less than the search values so that the latches are set accordingly and no more updates are needed afterwards. Continuing with the second data value, the MSB7 result would again be indeterminate and is not shown, but the MSB value establishes that it is greater than the search values and the latches are set accordingly. At this point, the final search values for this data set are established, as shown in the right hand most column. If there were still indeterminate data, the process would continue on towards the least significant bit until the final search results were all established. The final results will be shown on one of the data latches, such as XDL=1 in this case. The match to fit the query can be counted later or saved to another word line for further analysis in combination with other query criteria.
FIG. 20 is an example of another search to see which data values are between 123 and 231. For the first read, the first digit of the data values are checked against the upper bound, which is found to have exceeded for the first number, putting it out of the range so that any subsequent reads can be ignored. The second number is found to equal the MSB upper bound, with the bottom data to be under the MSB upper bound. At the second read, the second digit of the second number is found to exceed the upper bound, so the latches are set and no further updates are needed. For the fourth data, the second read finds this below the lower MSB values and, consequently, outside the range so that the latches are again set and no further updates needed. The second read for the third row data finds it to equal the MSB of the lower bound, so that the next digit is checked against the second digit of the search's upper value in the third read and the second digit of the search's lower value in the fourth read. The final search result is then shown in the far right column.
FIGS. 21 and 22 illustrate how to perform to maximum and minimum value searches. In FIG. 21 for the max search, the process illustrated for 5 NAND strings each with 9 bits arranged with LSB to MSB top to bottom. At left, the MSB row is searched and loaded into the UDL latch. In this example, the left two most NAND strings have a “1” for the most significant bit. The other columns can be ignored for the rest of the search. The process works its way up the rows, where the next two most MSBs are indeterminate. In the fourth row up, the two left columns are different, where the results as loaded into LDL show that the second column has the max value. (Here, two latches are shown for illustrative purposes, but this process can be done in a single latch per bit line by overwriting as the row is read one at a time.) FIG. 22 similarly illustrates a min search, again working its way up from the MSB. At left is shown the situation after working up to the fifth most significant bit, where the outermost column have both had zeros up until that point, as reflected in UDL. At right of FIG. 22 shows the result of two reads later as loaded into LDL, showing the left most column to be the minimum.
Max and min search can be performed on file size. For a max, the memory can find the file size with most number of digits along the NAND chain, then find the next largest files by eliminating the small numbers. For a min, the memory can find the file size with least number of digits along the NAND chain, and then search for the next smallest files by eliminating the larger numbers. Parts of a file system can be stored in this manner.
The array structure allows for the data analytics to be done one row at a time, as they can be done by reading one word line at a time. For example, the array structure can also be used to perform arithmetical operation, such as addition, subtraction and multiplication, on the numeral data along the NAND strings. The process is schematically illustrated in FIG. 23 for a summing operation. Here the data sets of block N 2301 can added to the corresponding data sets of block M 2301 on a row by row basis for each bit line. The result can then be written into a SUM block 2305. Here, block N has NAND strings N1 to N128K, block M has NAND strings M1 to M128K, and the SUM block similarly has NAND strings SUM1 to SUM128K. Selected numerical data values can then be added by reading the values of each word line from NAND string i of blocks M 2301 and N 2303 into the associated latches 2307 a word line at a time, added there, are written back to the SUM block from the latches, SUMi=Ni+Mi. If the NAND has more data latches, more bits can be accumulated before writing to the SUM block. In the case of 3 data latches, there are 4 numbers can be added before writing to the SUM block. In the case of 5 data latches, 16 numbers can be added before writing to SUM block.
In the example of FIG. 23, and also in those discussed below, the NAND array is organized as to have a block structure, such as found in flash memory. More generally, the word lines can be any of the word lines of the array; and when the memory has a block structure, these need not be from different blocks, as, for example, when adding two different word lines of numerical data from the same data set. Also, more than two data can be processed and saved into the data latches before writing the result to a new word line. For example, with 3 data latches the memory can add 4 pages before writing to a word line, saving the carry in the data latches for the next bit addition. For 5 data latches, it can add 1.6 pages and then write to different word line once, and so on.
FIG. 24 illustrates an example of how the latches can be used in this process for addition. The latches associated with each bit line are here labeled as UDL, LDL, and XDL. FIG. 24 illustrates a single one of each of these latches with values read from different word lines holding different values as these are read sequentially for a 13 bit number from LSB to MSB. (That is, the arrow represents the sequence of reads in time or, equivalently, down word lines for a single UDL, LDL, XDL set of latches associated with a single word line. UDL contains the data set collected at time A from a first block (such as block N of FIG. 23) and LDL contains the data set collected at time B from a second block (such block M). The XDL latch can hold any carry bits. The two data sets can be added and stored back in LDL, with the summation then programmed back into another block. Other operations (multiplication, subtraction, division, etc.) can be similarly performed: for example, subtraction can be done as one data added to the complement of the other data. In addition, floating point operations can similarly be performed by properly aligning the digital information so that the points align for the operands.
FIGS. 25A-C give some more detail on the mechanics of some arithmetic operations as these are execute in the latches. FIG. 25A looks at addition, specifically 10+3, as noted at top. Here “10”, or 1010 in binary, is read from block A and “3” (0011 binary) is read from a block B. These number are shown listed for blocks A and B in the left column, MSB to LSB written bottom to top. At times T0, T1, T2, and T3 these are read into a the latches UDL and LDL, with the carry being held in the XDL latch, as shown underneath. The results are written back into Block C from the values shown latched there.
FIG. 25B illustrates how to perform subtraction of two numbers N1 and N2 to form the difference N1−N2. This is done by adding N1 to the 2's complement of N2 plus 1. A specific example, here again using 10 and 3 to determine 10-3 in the latch structure is shown: in the top row is the binary form of 10, in the second row the 2's complement of 3 plus 1 (3c+1), and the result is shown at bottom. Any overflow bits need to be discarded, with the result being the binary form of 7. FIG. 25C shows how multiplication can be done using bit shift and addition, where 10 and 3 are again used as the inputs.
FIGS. 26A and 26B look at examples of where, in addition to the XDL latches there are additional latches available on each bit line beyond UDL and LDL, such as is found in a multi-state memory device. FIG. 26A looks at the case of 3 data latches. As shown, data from four blocks (or, more generally, four pages) are written in. This allows for four numbers to be added or subtracted in a single write. FIG. 26B shows a 5 latch case, allowing for up to 16 numbers to be added or subtracted in one write.
Some examples of an application to financial data analysis are illustrated with respect to FIGS. 27 and 28. FIG. 27 illustrates an example of loading the stock data for a single stock historical data analysis, where for the 128k (in this example) bit lines can each be assigned to given stock or other financial instrument, with day for each day written to a different block. The data for each stock can be lined up along the NAND strings. With each stock taking a bit line, for an array of 128K bit lines a total 128,000 stocks can be evaluated simultaneously. The price per day can then take different blocks or different locations of the NAND chain. Using the blocks for different days, operation such as averages, linear regression, and so on can be performed using the data from the corresponding blocks, where the analyzed data can be saved in a new block.
To perform other types of analyses, the data can be arranged differently on the array. An example is shown in FIG. 28 where the data sets are arranged to perform a correlation study. In a first block the data for up to 128K stocks on a given day are entered. In the second block, the data from different stock B pre-processed from same chip or different chip will align up with the pre-processed data for stock A on the same bit line. Then the correlation between stock A and B can be calculated accordingly. Depending on the complexity of the desired operations and the on-chip ability given the NAND device, these operations can be performed on chip or with the help of the controller. For example, if needed for particular applications, the NAND can include fairly complex, but specific, operations.
FIGS. 29-31 consider data arrangement for analytics in more detail. So far, the discussion of this and the preceding sections have largely considered the data sets or keys being analyzed on the NAND array as being on a single NAND string. However, more generally, as each bit line can have many NAND strings formed along it that are connectable to the same data latches, this allows for data (a schema) to be arranged in few separate blocks along the same NAND bit line. This is illustrated schematically in FIG. 29, where some numeric data of a data set, arranged from most to least significant bit, is stored on the same bit line, but in NAND strings from separate blocks. (Here these are shown as adjacent, but need not be so in the more general case.) The bit line then is connectable to the transfer data latch XDL and, through XS W (transistor switch), the corresponding sense amp (SA) and data latches UDL, LDL, where these can correspond to upper and lower page data latches in a more typical multi-state operation. (More detail on the latch structure described in FIG. 30 and, in the next paragraph, FIG. 31 can be found in U.S. Pat. Nos. 7,206,230 and 8,102,705.)
Data can also be arranged inside a group of (typically adjacent) bits lines that share the same data bus to communicate with a set of data latches. For example, a set of 8 or 16 adjacent bit lines with such shared structure could store each data set on multiple ones of these bit line groups. FIG. 31 schematically illustrates a latch structure where 8 NAND bit lines can process the data with shared SBUS and DBUS through logic operations from YBOX circuitry, so that a schema can be stored in up to 8 associated bit lines sharing same data latch set.
The results of the analytic operations can be computed according to various data counting methods. As illustrated schematically in FIG. 32, the counting can be done digitally inside the CPU, toggling the data out to RAM for counting. Digital counting can also be performed inside the NAND device, such as by binary search or shooting chain. Analog counting can also be done inside the NAND, which, while less accurate can be done more quickly. FIG. 33 shows some elements of such circuitry for counting quickly with analog wired OR circuitry: here, the data is applied to the gates of a set of transistor connected in parallel, each connected in series with a transistor controlled by an analog bias. The transistors are fed by one leg of a current mirror, the other leg of which is connected to ground through a transistor acting as acting to set a digitized current level.
FIG. 34 illustrates how analytics can be applied to large file systems. As file systems grow, there is an increasing demand to perform complex queries, such as “How many files have been updated since 10 days?” and “Which are the top five largest files that belong to John?” The first is an example of aggregate queries which provide a high-level summary of all or part of the file system, while the second is top-k queries which locate the k files and/or directories that have the highest score according to a scoring function. The incorporation of the NAND section as described with respect to FIG. 16 provides a simple solution for performing such queries.
At left, FIG. 34 shows a file system. The basic file data (owner, time stamp, file size, etc.) is saved into NAND in vertical NAND chains as shown at the right of FIG. 34. Performing the analytics by the NAND SSD in this way saves the trouble needed to build the data tree structure as shown in the file structure on the left. Then aggregate queries can, for example, be searched on the time stamp that can be located in a few word lines against a certain date. Top-k queries can be done, for example, by identifying “John” and the file size. (As noted above, min and max searches can also be done for file sizes, allowing for portions of file systems to be stored on this basis.)
The material in this section is developed more in U.S. patent application Ser. No. 13/756,076.
Architectures for Data Analytics Using Computational NAND
This section considers some architectures and data structures for using the sort of analytic operations discussed in the preceding section. For comparison, FIG. 35 a conventional arrangement of a server 3501 used along with a data system 3503 of one or more SSD drives such as 3507. In the conventional architecture, the CPU of the server 3501 does all of the computational operations for any sort of data analytics, where the storage system 3503 is just used for storing data, so that has to flow from storage device to the server CPU to perform analytics on any data stored there. Although an individual element 3507, such as an SSD blade, of the storage system 3503 will have a controller, this is traditionally used for managing of the data storage on the device, rather than any sort of analytics. In contrast to this traditional arrangement, the current section describes techniques whereby some or all of the data analytics are instead done on the memory system that is now used as a data analytics system.
FIG. 36 schematically illustrates an architecture using the sort of computational NAND described in the preceding section. This has several layers: the server, the solid state drives; and, within the drives, the memory controllers and their associated memory devices. As shown in FIG. 36, the server 3601 issues software commands that can be in an existing data base languages. On the Data Analytic System 3603, these commands are translated into firmware to be executed there. Various tasks can then distributed between the flash memory controllers, such as 3611, and their associated flash arrays, such as 3613. This allows for the various sub-operations of analytics to be spread out between the server, the microprocessor circuitry on the SSDs, the flash controllers, and the computational NAND areas based upon the relative abilities and to exploit the increasing level of parallelism as you go lower down the system to more efficiently performing the analytics and provide the final or intermediate results back to the server 3601. The server itself can also be used in performing some to the task, such as any final or complicated computations, where the results could then be provided on a graphical display 3607, for example. Examples of functions that can be performed on the flash controller can include sort, merge, addition, subtraction, multiplication, division, squaring, exponentiation, etc. while for the NAND memory the functions could include operations such as searching, matching, minimum, maximum, greater than, less than, addition, subtraction and so on as discussed in more detail above.
This arrangement can save on power, as data does not need to go out of the SSDs. It can also save on servers, as it can handle more data without a need to expand servers with large DRAM memory. Since this is a distributed system, with multiple controllers and associated flash array, the controllers and the associated sets of flash array do not need to be executing parts of the same job. Instead, multiple jobs can be executed in parallel, as indicated by the different Job numbers above the lash control circuitry of FIG. 36. This ability to run multiple jobs in parallel can be particularly useful for computational NAND as in some cases a user's data may not be large enough to compete with the performance of a server-based implementation; however, the system described here has the advantage that it can process multiple jobs in parallel to exploit the benefits from utilizing the degree of parallelism in the NAND based flash SSD of the data analytics system.
Whether the data analytic system is doing one or multiple jobs in parallel, the software running on the server will issue the commands using a database language. This software, which can interface with a common, existing database language, is translated into firmware language and then into multiple small tasks. Depending on the details of analytic jobs, the software level can also optimize the analytics to choose the best way to arrange data or distribute the task among the microprocessors or flash controllers or NAND memory units. The small tasks will be executed on the SSD flash controllers or on NAND flash according to the task specifications. The mid-product from the NAND flash or the SSD controllers can be merged within each SSD blade and then, if needed, further merged on the top server level. The task to distribute the jobs and merge the jobs can be executed with proprietary software or it can also be interfaced with open source computing, such as Hadoop Map Reduce platform.
FIG. 37 shows an example of the hardware architecture in more detail for one SDD unit. The SSD controller includes interface circuitry as well as components to parse and distribute commands and data across the 16 (in this example) flash controllers. The flash controllers perform the usual functions, such as logical to physical address conversion and so on, but also the analytic functions. During the execution of data analytics, the SSD controller can focus analytic operations. Memory maintenance operations, such as garbage collection, can be delayed and not be triggered until the analytics operations finished, releasing the SSD controllers to execute analytics jobs. As far as hardware changes, the SSD controllers, and the flash controllers within these, often a fair amount of capability that can directed towards analytic operations, particularly if maintenance and other non-analytic functions, are suspended. Consequently, the larger changes to the system is with respect to the firmware for the SSD controllers have to be controlled with firmware, although the hardware can also be optimized to do various analytics jobs.
FIGS. 38A-D illustrate an example of a particular benchmark operation, a pricing summary report query (TPC-H Q1 benchmark), where FIG. 38A is some corresponding pseudo-code for the analytic operation. These operations can then be distributed between NAND operations and controller operation based upon which is most efficient: for example, addition can be done in NAND, where it is faster, while multiplication will be done more quickly in the controller. FIG. 38B illustrates how the data sets are arranged in the NAND memory for analytic operation to be done there, where the NAND bit lines run up and down. As discussed in previous sections, this may require the data to be transposed form a word line orientation prior being written into the arrays. FIG. 38C illustrates some of the parameters for determining “120 days Sum of Quantity”, where the operations on NAND are indicated by the bracket from the left, those in the controller by the bracket from the right. FIG. 38D shows the same information for the query “120 days Sum of discount price=price*(1−discount)”.
FIGS. 39A and 39B schematically illustrate examples of this division of tasks between the NAND memory and memory controller for the respective queries of FIGS. 38C and 38D. For the query “120 days Sum of Quantity”, the CAM type NAND 3901 can provide the controller 3903 with the Quantity(i,j) results, which it then buffers in the RAM 3911. These can then be summed up (represented at 3919) by the circuitry on the controller 3903. The single number of the result, SUM(Quantity(i)), can then be sent back to the memory chips. FIG. 39B illustrates operations for the query “120 days Sum of discount price=price*(1−discount)”. The NAND 3901 now provides two sets of quantities, Price(i,j) and discount(i,j), to the controller 3903 that are respectively buffered in RAM1 3911 and RAM2 3913. (Although shown as separate for illustrative purposes, in practice these can be stored in a single RAM memory used by the controller.) These quantities are then multiplied and summed by the controller's logic, schematically represented by 3915 and 3919, to generate the result SUM(disucount_price(i)), where this result can then be written back into the non-volatile memory.
FIGS. 40A-D illustrate another example of a particular benchmark operation, a minimum cost supplier query (TPC-H Q2 benchmark), where FIG. 40A is some corresponding pseudo-code for the analytic operation. These operations can again be distributed between NAND operations and controller operation based upon which is most efficient: for example, search operations and minimum operations are done in NAND, with results being in the controller. FIG. 40B illustrates how the data sets are arranged in the NAND memory for analytic operation to be done there, where the NAND bit lines run up and down and the left-most column shows an example of how may digits can be assigned to the various line items. FIG. 40C lists steps of the operation and the amount of time typically involved for these, where steps 6 and 8 are controller operations and rest NAND operations. FIG. 40D illustrates some of the parameters for determining “minimum cost supplier” in this way.
FIGS. 41A and 41B are respectively more detailed versions of portions of FIGS. 40B and 40C. In particular, FIG. 41A illustrates the first two steps in FIG. 41B of the steps 1-5 from FIG. 40C that are executed on the NAND array. At the upper part of FIG. 41A, for each line item the supplier and region are lined up along the NAND strings, where region is searched. The results of the search are then shown, followed by an AND operation for the search result with supplier. Below that is a similar search for “partNo1”. Similar searches are then done for type and size, followed by a Min(Price). In doing this, only two functions (Search and Min) are used on the NAND array, where these are described in more detail in the last section. To compare the results from the different die, the controller then performs the “Merge Min from all die”, shown as step 6 in FIG. 40C. As noted, when data is transferred to the NAND devices, some data will be stored vertically along the NAND chains for Search operations. Consequently, the data, whether being retrieved from elsewhere in the memory system or being received from a server, will likely need a rotation to be done inside the SSD controller. Both here and in the other examples, this transposing of selected data into a bit line arrangement can be done when the data is initially shifted in from other storage to the analytic storage. The transpose can also be done when certain specific search commands are issued and the needed data has to be re-arranged to accelerate the search.
As with the other applications discussed above, in addition to stored data on columns along the NAND there will often be some associated data stored in rows along NAND pages, where both of these pieces are derived or extracted from the data on which the analytics are being performed. This sort of row and column storage data structure for data analytics is illustrated by FIG. 42 for the example of the data used in queries of FIGS. 38-41. The upper, left portion shows portions of the data sets as stored along columns for the search operations shown in FIG. 41A. For each of the columns, associated data is then stored along word lines in NAND pages. One such correspondence is shown for the line item with (region1, partNo1) is associated with the shown (quantity). Column addresses can be linked with a row address by an offset in a fixed mapping, a formula, or by something like a logical-to-physical mapping, but now the metadata would associate column addresses with associated row oriented data. This is similar to the sort of key-data associations described above for more general CAM NAND arrangements. A search can then be done in the Column (along bit line) Store (such as for (region1, partNo1)) and the corresponding data (such as the associated (quantity)) can then be fetched from Row (along word line) Store.
FIG. 43 considers the building blocks to convert a flash SSD to a computational SSD drive. At the top layer is the Software Layer running on the serve, where this takes a database language query and turns this into a set of commands to send to the data analytic system. On the data analytic system, the SSD controller compiles the commands into executable SSD firmware layers. The firmware can then direct the flash controllers to fetch needed data and perform computations on them, where this can done using hardware merge and sort operations as these typically deal with small amounts of data. The flash controllers then issue the needed commands, such as for normal operations or searches, on to the NAND memories. The NAND memories can have the sort of enhanced search capabilities described in the last section above. A single analytic job can be divided up into many small jobs and distributed to each flash controller and associated sets NAND flash memory for execution. The flash controllers can then issue parallel command sequences to execute the analytics jobs in parallel in multiple memory chips and controllers. The execution of some analytics in the SSD controllers can be done in parallel with the NAND analytics operations, where the two operations do not interfere with each other; for example, counting in the controller while doing a sensing read inside an associated NAND device for a search operation. The multiple flash controllers on SSD drive are controlled by the interface controllers and can coordinate the merge and transfer of partial results out of the SSD drive to the server, which can merge the final results and display them to the customer.
As discussed at the beginning of this section, data analytics of this type have typically be done on the server (or several severs), with the SSD drives used for mass data storage. FIG. 44 can be used to contrast the techniques of this section with this sort of server based approach, here in the context of a Hadoop Distributed File System (HDFS) used for the first system. This is shown to the left. In a Hadoop arrangement, the MapReduce engine is used for the computing, forming <key, value> pair, which then undergo the network intensive operation of a “shuffle”, with the results then be assembled (a count). (The process by which the Hadoop system performs the sort, and transfers the map outputs to the reduces as inputs, is known as the “shuffle”.) The data is split into HDFS blocks of 64 MBs or 128 MBs chunks dependent on the server's DRAM size. Map tasks writes the intermediate output to the local disk.
To the right of FIG. 44 illustrates how the analytics can be moved from the server to the SSD drive, where the CAM NAND can be used for as part of a data analytics system. Now the key value pairs (in this example <year, temperature>) are sent to the data analytics system, with the data being rotated as needed in map phase. The key can be mapped according to the column address. Only the value need be stored, where it can be rotated and stored during a Map phase. The Reduce (or computing) phase is done along the NAND strings. On the Data Analytic System described in this section, the split can be 2 MB/block times 4*16*8 blocks, or 1 GB, for one SSD blade, compared to the 64 MB split of the HDFS block. As discussed in more detail several sections above, data can be duplicated twice for improved accuracy. If the data is spread across multiple die, such as the temperatures spread across two die in this example, a join operation will program the (here) two maxima to the same die and the same bit lines for comparison. The final maxima results can also be sorted out by a microprocessor or top level servers. To prevent errors, a few top max value from each NAND memory can be found first. These few Max values will be fetched out from a ROW (or word line) stored page with ECC correction. These few Max values will be sorted out again on the top flash controller or microprocessor. By being able to use larger splits, the data analytic system will result in fewer merges and less data toggling relative to a server-based implementation.
FIG. 45A illustrate the architecture for a server CPU-based implementation and FIG. 45B compares its performance with that of data analytic system using NAND flash based computing. As shown, as the storage capacity increases, the performance of the NAND based system increases, while that of the CPU based implementation stays flat. As far as integrating the NAND flash based data analytic system, the SSD can be located inside of the data node, where the SSD preferably has the capability to needed data rotation quickly. Server then provides a series of queries to trigger firmware execution to do the needed data re-arrangement and low level NAND commands. The computing SSD can be with compatible top level language, with possible modifications of NOT cutting the jobs to small chunks of 64 MB and skipping the replications by using RAID inside SSD to protect data, so as to be open to systems using HDFS. As HDFS is limited to each Split=64 MB-128 MB of data processing, while NAND based computing can process 8 Giga data sets at a time (1 block/plane/die), this leads to the sort of relative performance shown in FIG. 45B.
The sort and merge process of the data analytic system for un-structured data is looked at in more detail with respect to FIG. 46. On the left of FIG. 46, the year and temperature are saved along the NAND chains for two memory blocks of CAM NAND. This corresponds to the right side of FIG. 44. The CAM NAND array is then used to search for the maximum(s) for each year within each block of data. The columns are then associated with the corresponding original data, at top, center stored with a word line orientation, based on the column location. The maximums from the blocks are collected into another block, where the original data can be fetched from normal storage with ECC protection. This new block (shown center, bottom) with merged maximums from the different blocks of the earlier max operation is linked to original data through the address map. The new block is then searched for the overall maximum for each year and referred back to the address table to provide the final results for outputting the <year, max> result. Another option is to get the intermediate results of Maximums out to the controller or microprocessor to sort out the maxima with high to low orders. The values in this group far from the top group of maxima can be thrown out.
The sort can also partially be done on the SSD controller ASIC. This can be illustrated with respect to FIG. 47. In this example, the search for word frequency, where the sort is done partially on the CAM NAND, using a greater than operation to find the top 100 frequencies. The words and their frequencies are stored in word line oriented pages and the frequencies are mapped vertically in CAM. NAND. In the CAM NAND, the frequencies searched for the top 100-300 record of highest frequency for each block. To find the top 100-300, this can be done by shifting the criterion for the > operation until approximately 100-300 frequencies pass, where in practice “100” would be about 100 or somewhat above like 300. (For example, if a criterion yields, say 106 highest frequency, it will typically not be worth refining the search to get this closer to 100.) For extra error protection, it is preferred to margin the read to yield more results, such as 300. For each record, there is a word associated by the column mapping. The CAM NAND can then shift the top 100 records to the SSD ASIC, which can then sort and output the sorted results.
Several examples will now be looked at in more detail. The first example is a Distributed Grep operation, where Grep is a command-line utility for searching plain-text data sets for lines matching a regular expression. Here, a supplied pattern is searched for. The map function emits a line if it matches a supplied pattern. The reduce function is an identity function that copies the supplied intermediate data to the output. This is illustrated in FIG. 48. If the URL matches the search criteria, the corresponding source is fetched. In a CAM NAND implementation, during the map phase, the patterns are stored the in flash memory along bit lines. These are then searched for a matched pattern. When there is a match (the Reduce phase), the controller can go to the corresponding location of the row oriented data to read out the source content, where the searched key is linked to source content through column address.
Another example is for a count of URL access frequency: The map function processes logs of web page requests and outputs <URL, 1>. The reduce function adds together all values for the same URL and emits a <URL, total count> pair. FIG. 49 illustrates this process for a CAM NAND implementation. During the map phase, the memory stores the patterns (URLs) along the NAND strings. The search is then made for the matched pattern (URL1 in this example). The matched “1”s can then be counted up on the NAND or on the controller for query result. The more precise counting can be done in the way that the matched results will be read out from the corresponding ROW (word line) storage locations and the controller can check the match of these roughly chosen data to be counted, while throwing away the false results. The performance speed-up comes from the reduced amount of data to be counted by the top level controller or servers.
Next is a Reverse Web-Link graph: the map function outputs <target, source> pairs for each link to a target URL found in a page named source. The reduce function concatenates the list of all source URLs associated with a given target URL and emits the pair <target, list(source)>. FIG. 50 illustrates this process for a CAM NAND implementation. As with the last example, during the map phase the memory stores the patterns (URLs) along bit lines in the flash memory. This is then searched for the matching pattern (here URL1). When there is a match in the reduce phase, the memory then foes to the corresponding location of the row oriented memory and reads out the source content. The system then saves all of the source data related to a match to the same location (in this example, source 1, 3, 5, 6, 9), where the searched key is linked through to the source content though the column address as described above.
FIG. 51 illustrates the example of a term-vector per host query. In this example, a term vector summarizes the most important words that occur in a document or set of documents as a list of <word, frequency> pairs. The map function emits a <hostname, term vector> pair for each input document, where the hostname is extracted from the URL of the document. The reduce function is then passed all per-document term vectors for a given host. It adds these term vectors together, where it can throw away infrequent terms, and then emits a final <hostname, term vector> pair. For the CAM NAND implementation, during the map phase, the memory stores word frequencies along the NAND strings in flash. The words are saved horizontally along the word lines with frequency by column address versus word line address. The frequencies of occurrence in different documents are saved in different blocks or different sets of word lines. The frequency of occurrence in the different documents are then added and stored in another block of word line address. The final result can streamed out and the data can be rotated back for later access.
The next example is an inverted index. The map function parses each document and emits a sequence of <word, document ID> pairs. The reduce function accepts all pairs for a given word, sorts the corresponding document IDs, and emits a <word, list(document ID)> pair. The set of all output pairs forms a simple inverted index. It is easy to augment this computation to keep track of word positions. FIG. 52 illustrates this example for a CAM NAND implementation. During the map, words are stored along the NAND strings in flash. The document ID is saved along the word line direction, linked with the words by column address versus word line address. The words can be matched one at a time. The document ID associated with the matched word can be read out according to the matched column address. The associated document ID read out can be saved in another location.
The next example is a distributed sort, as illustrated by FIG. 53. In a distributed sort, the map function extracts the key from each record and emits a <key, record> pair. The reduce function then emits all pairs unchanged. For a CAM NAND implementation, the memory arranges both key and record along the NAND strings in flash. Key-record pair can also be stored along the word line direction, linked to the column address. A search is then done for un-changed <key, record> pairs, which are the read out from the word line stored information. The record can be sorted, with all the keys related to record1 saved together, all the keys related to record2 saved together, and so on. The sort process can be break into the following sub-operations: a) Search the 1st record; b) Get the keys for 1st record; c) Repeat a)&b) for 2nd record, and so on.
A final example considers the joining of two tables. In this example, the first table matches Station IDs to Station Names. The second table associates the Station IDs with a Timestamp and a Temperature. As shown at the left of FIG. 54, these are to be merged into a single table where the station IDs are matched with Station Names. Timestamp, and Temperature. The right of FIG. 54 illustrates how this can be implemented in CAM NAND. At top right, the data corresponding to the second table is entered in a page based manner. (Note that when entered in along the word lines, these different table entries need not line up on a 1 to 1 basis.) The station IDs, which is the common element between the original two tables, are arranged along the bit lines. The station ID data is stored in a column format. A search for each station ID is done first, all the matched station ID will be read out from the ROW store location for the corresponding station names. The station name will be loaded into the ROW store locations corresponding to the selected station ID in the second table. After each station ID is searched and their corresponding station name is inserted into the second table, the Join operation is finished.
CONCLUSION
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting to the precise faint disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the disclosed technology and its practical application, to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated.

## Claims

1. A method of performing data analytics using a server and a memory system connected thereto, where the memory system comprises control circuitry and a plurality of sets of memory arrays having a NAND type of architecture, the control circuitry including a plurality of memory controllers each associated with a corresponding set of memory arrays, the method comprising:
running software on the server that issues commands to the memory system to perform one or more data analytic operations;
receiving the issued commands on the memory system;
translating of the received commands into a plurality of analytic tasks by firmware operating on the control circuitry;
distributing by the firmware of the analytic tasks across the memory controllers to be executed by the memory controllers and corresponding sets of memory arrays;
executing the analytic tasks on the memory controllers and corresponding sets memory of memory arrays, wherein each of the analytic tasks are executed on the memory controller, the associated sets of memory arrays, or a combination thereof as specified by the firmware;
merging results from the analytic tasks by the firmware; and
transferring out the merged results to the server.

2. The method of claim 1, further comprising:
receiving the merged results at the server; and
subsequently further merging the received results by the software to complete the analytic operations.

3. The method of claim 1, wherein the software is proprietary.

4. The method of claim 1, wherein the software is open source.

5. The method of claim 1, wherein the server and the memory system interface using a database language.

6. The method of claim 1, wherein the analytic operations are performed on data stored on the memory system.

7. The method of claim 1, wherein the analytic operations are performed on data received from the server.

8. The method of claim 1, wherein performing analytic tasks on the memory arrays includes writing data sets oriented along bit lines of the memory arrays.

9. The method of claim 8, further comprising:
transposing on the memory system of the data sets from a word line orientation to a bit line orientation prior to writing the data sets oriented along bit lines of the memory arrays.

10. The method of claim 1, wherein the analytic operations include a plurality of jobs, wherein analytic tasks corresponding to differing jobs are executed in parallel on different memory controllers and associated sets of memory arrays.

11. A method of performing analytic operations on a plurality of sets of data, comprising:
receiving on a memory system from a server a plurality of data sets and instructions for analytics to perform upon the data sets, wherein the memory system includes control circuitry having one or more memory controllers and one or more memory circuits each having one or more memory arrays of non-volatile memory cells having a NAND type of architecture;
breaking down by the control circuitry of the received instructions into a plurality of sub-operations and assigning one or more of the sub-operations to be performed on the control circuitry and one or more of the sub-operations to be performed within the memory circuits;
deriving from the received data sets by the control circuitry of a plurality of corresponding first derived data sets for use in the sub-operations to be performed within the memory circuits;
writing the first derived data sets into one or more of the memory arrays, wherein the first derived data sets are written into the memory arrays oriented along bit lines;
subsequently performing the sub-operations; and
providing the result of the analytics performed on the data sets to the server.

12. The method of claim 11, wherein the first derived data sets are the same as the corresponding received data sets.

13. The method of claim 11, wherein the received data sets each include a plurality of data items and the first derived data sets are a subset of the data items the corresponding received data sets.

14. The method of claim 11, wherein the writing the first derived data sets into one or more of the memory arrays includes writing individual ones of the first derived data sets into the memory arrays multiple times in differing locations.

15. The method of claim 11, further comprising:
deriving from the received data sets by the control circuitry of a plurality of corresponding second derived data sets;
writing the second derived data sets into one or more of the memory arrays, wherein the first derived data sets are written into the memory arrays oriented along word lines;
maintaining by the control circuitry of a correspondence between the locations of the first and second derived data sets that correspond to the same received data set,
wherein sub-operations performed with the memory circuits use the first and second derived data sets.

16. The method of claim 15, wherein said correspondences is maintained through a mapping formula.

17. The method of claim 15, wherein said correspondences is maintained through a mapping table in memory system.

18. The method of claim 15, wherein the received data sets each include a plurality of data items, the first derived data sets are a first subset of the data items the corresponding received data sets, and the second derived data sets are a second subset of the data items the corresponding received data sets.

19. The method of claim 11, wherein the received instruction are for sub-operations of one or more analytic operations for which one or more additional sub-operations are performed by the server.

20. The method of claim 11, wherein the control circuitry further includes a memory system controller and the received instruction are for sub-operations of one or more analytic operations for which one or more additional sub-operations are performed by the memory system controller.

21. The method of claim 11, wherein the operations assigned to be performed within the memory circuits include one or more of: a search function; a match function; determination of a maximum; determination of a minimum; a greater than operation; a less than operation; an addition operation; and a subtraction operation.

22. The method of claim 11, wherein the operations assigned to be performed on the control circuitry include one or more of: a sort operation; a merge operation; an addition operation; a subtraction operation; a division operation; and an exponential operation.

23. The method of claim 11, wherein the control circuitry includes multiple memory controllers each controlling an associated set of one or more associated memory circuits, and wherein a plurality of the sub-operations are distributed across a plurality of the memory controller and the corresponding associated memory arrays.

24. The method of claim 23, wherein the plurality of the memory controllers issue parallel command sequences to the corresponding associated memory arrays to execute the distributed sub-operations in parallel.

25. The method of claim 24, wherein the parallel command sequences correspond to different analytic jobs.

26. The method of claim 11, further comprising:
transposing the first derived data sets from a word line orientation to a bit line orientation prior to said writing the first derived data sets into one or more of the memory arrays.

27. The method of claim 26, wherein the determination of the content of the first derived data sets and the transposing thereof is dependent on the received instructions.

28. The method of claim 11, wherein the memory system performs the analytics based upon firmware on the control circuitry.

29. The method of claim 11, wherein the control circuitry is optimized to perform a selected set of analytic operations.

30. The method of claim 11, wherein one or more of the sub-operations to be performed with the memory circuits are performed in parallel with one or more of the sub-operations to be performed on the control circuitry.

31. The method of claim 30, wherein the control circuitry performs a counting operation concurrently with one or more sensing operations being performed on the memory circuits.

32. The method of claim 11, wherein the control circuitry includes a plurality of memory controllers and an interface controller, wherein the interface controller coordinates the merging of results of sub-operations received from the memory controllers.

33. The method of claim 11, wherein the control circuitry includes a plurality of memory controllers and an interface controller, wherein the interface controller transfers out to the server results of sub-operations received from the memory controllers for merging on the server.

34. The method of claim 11, wherein while executing the analytics, the control circuitry suspends data maintenance operations for the memory system.

35. The method of claim 1, wherein the memory arrays are of a 3D-type architecture.

36. The method of claim 11, wherein the memory arrays are of a 3D-type architecture.