# Patent

## Title
Pixel driving method, pixel driving device and liquid crystal display using thereof

## Abstract

The present invention provides a pixel driving method for a liquid crystal display. The pixel includes a storage capacitor and a liquid crystal capacitor. The pixel driving method includes steps of: providing a common voltage signal to a liquid crystal capacitor, and providing a bias signal to a storage capacitor wherein the bias signal is synchronized with the common voltage signal and the amplitude of the bias signal is larger than that of the common voltage signal.

## Background
FIELD OF THE INVENTION
The present invention relates to a pixel driving method and a liquid crystal display using thereof, and more particularly to a LCD panel with a capacitor voltage modulating function.
BACKGROUND OF THE INVENTION
LCD panels, especially small and middle LCD panels, S/M LCD panels, for mobile and multimedia applications, are being developed ambitiously. To meet the demands of high-end mobile devices including functions such as cellular phone, digital camera, music player, GPS, mobile TV and so on, the development of S/M LCD panels with higher resolution, higher image quality, low power consumption and cost competitiveness is inevitable.
Please refer to FIG. 1(a), Vcom modulation is widely applied in S/M LCD panels. The driving of Vcom modulation can reduce the output voltage range of a source driver so as to save the source driver cost. However, it still causes the gray level inconsistent and then leads to the flick and the low transmittance when the TFT of a pixel unit is turned off and common voltage changes. This problem is attributed to the charge distribution on the pixel unit, which is disturbed by the voltage change of Vcom. To avoid the gray level being inconsistent, a storage capacitor Cst is configured in the common structure. That is, the Cst of the pixel unit on common structure is comprised of a common line and a pixel electrode disposed on a array substrate, wherein the common line and the common electrode are connected to the same voltage source, so that both the voltages of the common line and the common electrode are modulated to balance the charge distribution in the pixel unit.
Please refer to FIG. 1(b), which illustrates the layout of the storage capacitor Cst on common structure. The pixel unit 1 includes data lines 11 & 12, gate lines 13 & 14, a TFT 15, a common line 16, and a pixel electrode 17. The pixel electrode 17 covers the common line 16 to form the Cst, as shown the cross-section view along the dotted line a to a′. The Vcom modulation requires the Cst on common structure to avoid the gray level inconsistency when the TFT turns off and common voltage changes.
However, if a pixel includes some significant parasitic capacitances, although it has the Cst on common structure, the gray level also appears to be inconsistent. On the other word, the storage capacitor Cst in the common structure doesn't solve this problem completely. In many high-end applications such as HAR design, In-Cell Touch panel and so on, the significant parasitic capacitance is indispensable.
Please refer to FIG. 2, which is a circuit diagram showing a pixel unit of an In-Cell Touch panel according to the prior art. Touch sensors or photo sensors (not shown) are regularly disposed in the cell of the In-Cell touch panel. Moreover, readout lines connected to the sensors transmit the touch signals to a readout circuit. The pixel unit 2 includes a TFT 20, a liquid crystal capacitor CLC, and a storage capacitor CST. The G(Gate) electrode of TFT 10 is electrically connected to the gate line Gaten, the D(Drain) electrode is electrically connected to the data line Datam, and the S(Source) electrode is electrically connected to one end of respective the liquid crystal capacitor CLC and the storage capacitor CST. The other ends of respective the liquid crystal capacitor CLC and the storage capacitor CST are connected to the common voltage source. Owing to the existence of the read-out line of an In-Cell touch panel for In-Cell touch signal, a parasitic capacitor Cread-out is formed in the pixel unit as FIG. 2 shows. For example, the parasitic capacitor Cread-out formed between the pixel electrode and the readout line leads to the inconsistent gray level when the TFT 20 is turned off and Vcom changes.
Either the In-Cell touch panel or the HAR designed panel meet significant parasitic capacitance causing gray level inconsistent. Please refer to FIG. 3, which is a schematic diagram showing the structure of a high aperture ratio (HAR) pixel unit according to the prior art. The HAR pixel unit 3 includes a pixel electrode 30, a first data line 31, a second data line 32, a first gate line 33, and a second gate line 24. The pixel electrode 30 is designed to partially cover the adjacent data lines 31 & 32 and gate lines 33 & 34 so that the black matrix (BM)(not shown) widths are shrunk, therefore the high aperture ratio is increased, as FIG. 3 shows. It is noted that the capacitance formed between the pixel electrode 20 and the data line 31 is Cd1, the capacitance formed between the pixel electrode 30 and the data line 32 is Cd2, the capacitance formed between the pixel electrode 30 and the gate line 33 is Cg1, and the capacitance formed between the pixel electrode 30 and the gate line 34 is Cg2. The cross-section view along the dotted line a to a′ is, for example, also shown in FIG. 3.
As FIG. 3 shows, the capacitance formed between the pixel electrode 30 and the gate line 33 due to the partial covering thereof is Cg1. The area generated from the pixel electrode 30 covering the gate line 33 leads to one of the aforementioned parasitic capacitance, which causes the inconsistent gray level when the TFT 35 (shown in FIG. 2) of the pixel unit 3 is turned off and Vcom changes.
Please refer to FIG. 3(a), which is an equivalent circuit diagram showing the structure of the HAR pixel unit according to FIG. 3. The HAR pixel unit 3 includes a TFT 30, a liquid crystal capacitor Clc, a storage capacitor Cst, a Gate line 1, a Gate line 2, a Data line 1, and a Data line 2. The G(gate) electrode of the TFT 30 is electrically connected to the Gate line 1, the D(drain) electrode of the TFT 30 is electrically connected to the Data line 1, and the S(source) electrode of the TFT 30 is electrically connected to one end of the liquid crystal capacitor Clc and one end of the storage capacitor Cst. The other end of the storage capacitor Cst is connected to the common line and that of the liquid crystal capacitor Clc is connected to the common electrode of a color filter (CF) (not shown). Both the common line and the common electrode are electrically connected to a common voltage source. Similarly, the capacitance formed between the pixel electrode and the Data line 1 is Cd1, the capacitance formed between the pixel electrode and the Data line 2 is Cd2, the capacitance formed between the pixel electrode and the Gate line 1 is Cg1, and the capacitance formed between the pixel electrode and the Gate line 2 is Cg2. One ends of Cd2, Cd1, Cg2, Cg1, Cst, and CLC are all electrically connected to a node P, and the node P electrode connected to the S(source) electrode of the TFT 30. That is, the total parasitic capacitance, Cb, of the HAR pixel unit 3 is comprised of Cd1, Cd2, Cg1, and Cg2. That is,

Cb=Cg1+Cg2+Cd1+Cd2 

Please refer to FIG. 3(b), which is a waveform diagram showing the waveforms of the Vcom signal and the Gate signal of the HAR pixel unit in FIG. 3(a) according to the prior art. The waveform above shows the waveforms of the Vcom signal and the Gate signal in the even frame and the waveform below shows those in the odd frame. During the periods of gate signal impulses, the TFT becomes conductive between S(source) terminal and D(drain) terminal because of the inversion layer in the amorphous silicon layer induced by gate signal impulses, and the voltage at node P in FIG. 3(a) is charged and discharged to the data signal voltages in the even frame and in the odd frame respectively. After the gate signal impulses, the TFT becomes isolated between S(source) terminal and D(drain) terminal because the low gate voltage dispels the inversion layer in the amorphous silicon layer. Therefore, the pixel electrode becomes floating and the voltage at the node P is synchronously varied with the Vcom signal. Because the parasitic capacitances exist, the change quantity (ΔVp) of node P voltage shown in the black horizontal line is smaller than that (ΔVcom) of Vcom modulated voltage, which causes the voltage difference between the node P and common voltage source is not fixed, leading to the transmittance loss and gray level inconsistent. That is, with the existence of the total parasitic capacitance Cb, the peak ΔVp is always smaller than the ΔVcom. Since the total parasitic capacitance Cb shares the charge pumped by the Vcom voltage in the pixel electrode, the gray level of the HAR pixel unit 3 thus becomes inconsistent. The traditional method to solve this problem is to enlarge the size of the storage capacitor Cst. However, the aperture ratio will be decreased undesirably.
Similarly, FIG. 3(b) also showing the waveform of the In-Cell touch panel, and please refer to FIG. 2 which is an equivalent circuit diagram showing the pixel structure of the In-Cell touch panel. The In-Cell touch panel pixel 2 includes a TFT 20, a liquid crystal capacitor Clc, a storage capacitor Cst, a Gate line n, a Gate line n−1, a Data line n, and a readout line. The G(gate) electrode of the TFT 20 is electrically connected to the Gate line n, the D(drain) electrode of the TFT 20 is electrically connected to the Data line n, and the S((source) electrode of the TFT 20 is electrically connected to one end of liquid crystal capacitor Clc and that of the storage capacitor Cst. The other end of the storage capacitor Cst is connected to the common line and that of the crystal capacitor Clc is connected to the common electrode of a color filter (CF) (not shown). Both the common line and the common electrode are electrically connected to a common voltage source. In the In-Cell touch panel, there is a readout capacitor Cread-out, a parasitic capacitance caused by readout line, of which one end is electrically connected to the S(source) electrode of the TFT 20, and the other end of the Cread-out is connected to the readout line. The one end of Cread-out, Cst, and CLC are all electrically connected to a node P, and the node P electrode connected to the S(source) electrode of the TFT 20. Therefore, the main parasitic capacitance in the pixel structure of the In-Cell touch panel is Cread-out.
Please refer to FIG. 3(b), which is a waveform diagram showing the waveforms of the Vcom signal and the Gate signal of the In-Cell touch panel pixel unit in FIG. 2 according to the prior art. The waveform above shows the waveforms of the Vcom signal and the Gate signal in the even frame and the waveform below shows those in the odd frame. During the periods of gate signal impulses, the TFT 20 becomes conductive between S(source) terminal and D(drain) terminal because of the inversion layer in the amorphous silicon layer induced by gate signal impulses, and the node P in FIG. 2 is charged and discharged to the data signal voltages in the even frame and in the odd frame respectively.
After the gate signal impulses, the TFT 20 becomes isolated between S(source) terminal and D(drain) terminal because the low gate voltage dispels the inversion layer in the amorphous silicon layer. Therefore, the pixel electrode becomes floating and the voltage at the node P is synchronously varied With the Vcom signal. Because the parasitic capacitances exist, the change quantity (ΔVp) of node P voltage shown in the black horizontal line is smaller than that (ΔVcom) of Vcom modulated voltage, which causes the voltage difference between the node P and common voltage source is not fixed, leading to the transmittance loss and gray level inconsistent. That is, with the existence of the total parasitic capacitance Cread-out, the peak ΔVp is always smaller than the ΔVcom. Since the total parasitic capacitance Cread-out shares the charge pumped by the Vcom voltage in the pixel electrode, the gray level of the In-Cell touch panel thus becomes inconsistent.
SUMMARY OF THE INVENTION
According to the foregoing object of the present invention, a pixel driving method for a liquid crystal display is provided. The pixel includes a storage capacitor and a liquid crystal capacitor. The pixel driving method includes steps of: providing a common voltage signal to a liquid crystal capacitor, and providing a bias signal to a storage capacitor. The bias signal is synchronized with the common voltage signal and the amplitude of the bias signal is larger than that of the common voltage signal.
According to the foregoing object of the present invention, a liquid crystal display including a plurality of pixels is provided. Each of the pixel includes a storage capacitor having a first terminal connected electrically to a bias signal and a second terminal, and a liquid crystal capacitor having a first terminal connected electrically to the second terminal of the storage capacitor and a second terminal connected electrically to a common voltage signal. The bias signal is synchronized with the common voltage signal and an amplitude of the bias signal is larger than that of the common voltage signal.
According to the foregoing object of the present invention, a pixel driving device for a liquid crystal display is provided. The pixel includes a storage capacitor and a liquid crystal capacitor. The pixel driving device includes means for providing a common voltage signal to the liquid crystal capacitor, and means for providing a bias signal to the storage capacitor. The bias signal is synchronized with the common voltage signal and an amplitude of the bias signal is larger than that of the common voltage signal.
According to the foregoing object of the present invention, a liquid crystal display including a plurality of pixels is provided. Each of the pixel includes a storage capacitor having a first terminal connected electrically to a bias signal and a second terminal, a first capacitor having a first terminal connected electrically to a first line and a second terminal, and a liquid crystal capacitor having a first terminal connected electrically to the second terminal of the storage capacitor and the third capacitor, and a second terminal connected electrically to a common voltage signal. The bias signal is synchronized with the common voltage signal and amplitude of the bias signal is larger than that of the common voltage signal.
Preferably, the liquid crystal display is an In-Cell Touch panel.
Preferably, the liquid crystal display is a high aperture ratio (HAR) pixel panel.
Preferably, the pixel further includes a switching element having a control terminal connected electrically to a first gate line, a first terminal connected electrically to a first data line, and a second terminal connected electrically to the storage capacitor and the liquid crystal capacitor.
Preferably, there is a capacitor between a pixel electrode and a readout line.
Preferably, there is an overlap portion between a pixel electrode and a readout line.
Preferably, there is an overlap portion between a pixel electrode and the gate line and the data line.
The foregoing and other features and advantages of the present invention will be more clearly understood through the following descriptions with reference to the drawings, wherein:



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1(a) is a diagram showing a Vcom modulation driving curve according to the prior art;
FIG. 1(b) is a schematic diagram showing the structure of the layout of the Cst on common structure according to the prior art;
FIG. 2 is a circuit diagram showing a pixel unit of a In-Cell Touch panel according to the prior art;
FIG. 3 is a schematic diagram showing the structure of a high aperture ratio (HAR) pixel unit according to the prior art;
FIG. 3(a) is a circuit diagram showing the structure of another HAR pixel unit according to the prior art;
FIG. 3(b) is a waveform diagram showing the waveforms of the Vcom signal and the Gate signal of the HAR pixel unit in FIG. 3(a) according to the prior art;
FIG. 4 is a circuit diagram showing a pixel unit of an In-Cell Touch panel according to one embodiment of the present invention;
FIG. 5 is a circuit diagram showing the structure of a HAR pixel unit according to the present invention;
FIG. 6 is a waveform diagram showing the bias signal and the common voltage signal of the HAR pixel unit 5 in FIG. 5; and
FIG. 7 is a circuit diagram showing a pixel unit of an In-Cell Touch panel according to another embodiment of the present invention.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for the purposes of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.
Please refer to FIG. 4, which is a circuit diagram showing a pixel unit of an In-Cell Touch panel according to one embodiment of the present invention. The pixel unit 4 includes a TFT 40, a liquid crystal capacitor CLC, whose structure is comprised of a pixel electrode and a common electrode of a color filter (not shown) to sandwich a liquid crystal layer, and a storage capacitor CST. The TFT 40 is electrically connected to the first gate line Gaten with its Gate terminal, electrically connected to the first data line Datam with its Drain terminal, and electrically connected to the pixel electrode of the liquid crystal capacitor CLC and the first terminal of the storage capacitor CST with its Source terminal. A parasitic capacitor Cread-out is further electrically connected between the pixel electrode and the read-out line.
According to the pixel driving method of the present invention, instead of the common voltage source electrically connected to the liquid crystal capacitor CLC and the storage capacitor Cst, a common voltage source, which supplies a common voltage signal, electrically connected to the liquid crystal capacitor CLC, and a bias voltage source, which supplies a bias voltage signal, electrically connected to the first terminal of the storage capacitor CST.
Please refer to FIG. 6, which is a waveform diagram showing the bias signal and the common voltage signal of an In-Cell Touch panel pixel unit in FIG. 4. It is clear from FIG. 6 that the bias signal is synchronized with the common voltage signal, and the amplitude of the bias signal is larger than that of the common voltage signal. Therefore, the ΔVp can be determined by the following equation.

ΔVp=[(CLC)/(Cst+CLC+Cread-out)]·ΔVcom+[(Cst)/(Cst+CLC+Cread-out)]·ΔVbias 

It is expected that ΔVp=ΔVcom, we can obtain

ΔVbias=[(Cst+Cread-out)/Cst]·ΔVcom 

It is apparent that ΔVbias is independent on the liquid crystal capacitor CLC. That is, the specific amplitude of the bias signal is independent on the varied capacitance of the liquid crystal capacitor CLC, which means the compensation adopted in the present invention is always consistent at any gray levels. Therefore, with this implementation, the inconsistent gray level can be avoided.
Similarly, the same pixel driving method can also be applied to the structure of the high aperture ratio (HAR) pixel unit 3 shown in FIG. 3, where there exists at least one overlap portion between the pixel electrode and the gate lines 33 & 34 and the data lines 31 & 32 to cause the above-mentioned effects.
Please refer to FIG. 5, which is a circuit diagram showing the structure of a HAR pixel unit according to the present invention. The HAR pixel unit 5 includes a TFT 50, a liquid crystal capacitor Clc, a storage capacitor Cst, a Gate line 1, a Gate line 2, a Data line 1, and a Data line 2. The TFT 50 is electrically connected to the Gate line 1, the Data line 1, and one end of the liquid crystal capacitor CLC and the storage capacitor Cst.
According to the pixel driving method of the present invention, instead of the common voltage source, which supplies a common voltage signal, and connected to the storage capacitor Cst, the other end of the storage capacitor Cst is connected to a Bias voltage source for obtaining a bias signal and that of the liquid crystal capacitor Clc is connected to the common voltage source for obtaining a common voltage signal. Besides, similar to the prior art, the capacitance formed between the pixel electrode and the Data line 1 is Cd1, the capacitance formed between the pixel electrode and the Data line 2 is Cd2, the capacitance formed between the pixel electrode and the Gate line 1 is Cg1, and the capacitance formed between the pixel electrode and the Gate line 2 is Cg2. That is, the total parasitic capacitance, Cb, of the HAR pixel unit 5 is comprised of Cd1, Cd2, Cg1, and Cg2.
Please refer to FIG. 6, which is a waveform diagram showing the bias signal and the common voltage signal of the HAR pixel unit 5 in FIG. 5. It is clear from FIG. 6 that the bias signal is synchronized with the common voltage signal, and the amplitude of the bias signal is larger than that of the common voltage signal. The present pixel driving method is given in detail as follows.
The total parasitic capacitance, Cb, of the HAR pixel unit 5 is comprised of Cd1, Cd2, Cg1, and Cg2. Therefore, the total parasitic capacitance of Cb can be determined by the following equation.

Cb=Cd1+Cd2+Cg1+Cg2   (3)

Base on the conservation of charge, it can be deduced that the relation between ΔVp, the change quantity of node P voltage, and Δ Vcom, the change quantity of modulated Vcom voltage. The ΔVp can be determined by the following equation.

ΔVp=[(Clc)/(Cst+Clc+Cb)]·ΔVcom+[(Cst)/(Cst+Clc+Cb)]·ΔVbias   (4)

It is expected that ΔVp=ΔVcom, so we can obtain

ΔVbias=[(Cst+Cb)/Cst]·ΔVcom   (5)

It is apparent that ΔVbias is independent of the varied capacitance of the liquid crystal capacitor Clc, which means the compensation adopted in the present invention is always consistent at any gray levels. Therefore, with this implementation, the inconsistent gray level can be avoided.
Except for the above-mentioned pixel driving method and the liquid crystal display fabricated thereby, the present invention can further be inferred that a pixel driving device for an LCD is provided. The pixel driving device includes at least means for providing a common voltage signal to a liquid crystal capacitor of the pixel and means for providing a bias signal to a storage capacitor of the pixel, wherein the bias signal is synchronized with the common voltage signal and an amplitude of the bias signal is larger than that of the common voltage signal. As described in the aforementioned embodiments, means for providing the common voltage signal to the liquid crystal capacitor CLC of the pixel is exemplarily a common voltage source, such as a means 71 shown in FIG. 7 and so on. Besides, means for providing a bias signal to a storage capacitor CST of the pixel is exemplarily a bias voltage source, such as a means 72 shown in FIG. 7 and so on. The means for providing the common voltage signal and the means for providing a bias signal can be integrated into a means 73 shown in FIG. 7, which can provide common voltage signal and a bias signal. The means 71, the means 72, and means 73 all can be realized by IC chips or power supply circuits.
The above-mentioned invention not only limited in In-Cell touch panel or HAR designed panel. Any display panel with significant parasitic capacitance can be decreased the gray level inconsistent by the method of this invention.
While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

## Claims

1. A driving method for a pixel unit of a liquid crystal display, the pixel unit comprising a liquid crystal capacitor including a pixel electrode with a pixel electrode voltage and a common electrode and a storage capacitor including a bias electrode and the pixel electrode having a first changing quantity of the pixel electrode voltage, comprising steps of:
providing a common voltage signal, having a second changing quantity of a common voltage, to the common electrode; and
providing a bias signal, having a third changing quantity of a bias voltage determined based on that the first changing quantity is equal to the second changing quantity, to the bias electrode wherein the bias signal is synchronized with the common voltage signal.

2. The driving method according to claim 1, wherein the liquid crystal display is a touch panel comprising a read-out line.

3. The driving method according to claim 1, wherein the pixel unit further comprises a switching element having a control terminal connected electrically to a first gate line, a first terminal connected electrically to a first data line, and a second terminal connected electrically to the pixel electrode.

4. The driving method according to claim 2, wherein there is an overlap portion between the pixel electrode and the readout line.

5. The driving method according to claim 3, wherein there is an overlap portion between a pixel electrode and the first gate line.

6. The driving method according to claim 3, wherein there is an overlap portion between the pixel electrode and the first data line.

7. The driving method according to claim 3, wherein there is an overlap portion between the pixel electrode and a second gate line adjacent to the first gate line.

8. The driving method according to claim 3, wherein there is an overlap portion between the pixel electrode and a second data line adjacent to the first data line.

9. A liquid crystal display comprising a plurality of pixel units, each of the pixel units comprising:
a liquid crystal capacitor having a first terminal with a pixel electrode voltage and a second terminal, wherein the first terminal has a first changing quantity of the pixel electrode voltage, and the second terminal is connected electrically to a common voltage signal having a second changing quantity of a common voltage;
a storage capacitor having a first terminal connected electrically to a bias signal, having a third changing Quantity of a bias voltage determined based on that the first changing quantity is equal to the second changing quantity, and a second terminal connected electrically to the first terminal of the liquid crystal capacitor; and
wherein the bias signal is synchronized with the common voltage signal.

10. The liquid crystal display according to claim 9, wherein the liquid crystal display is a touch panel comprising a read-out line.

11. The liquid crystal display according to claim 9, wherein the pixel unit further comprises a switching element having a control terminal connected electrically to a first gate line, a first terminal connected electrically to a first data line, and a second terminal connected electrically to the second terminal of the storage capacitor and the first terminal of the liquid crystal capacitor.

12. The liquid crystal display according to claim 10, wherein there is a capacitor between a pixel electrode and the read-out line.

13. The liquid crystal display according to claim 11, wherein there is a capacitor between the first terminal of the liquid crystal capacitor and the first gate line.

14. The liquid crystal display according to claim 11, wherein there is a capacitor between the first terminal of the liquid crystal capacitor and the first data line.

15. The liquid crystal display according to claim 11, wherein there is a capacitor between the first terminal of the liquid crystal capacitor and a second gate line.

16. The liquid crystal display according to claim 11, wherein there is a capacitor between the first terminal of the liquid crystal capacitor and a second data line adjacent to the first data line.

17. A driving device for a pixel unit of a liquid crystal display, the pixel unit comprising a parasitic capacitance (Cb), a liquid crystal capacitor (Clc), and a storage capacitor (Cst), comprising:
means for providing a common voltage signal, to the liquid crystal capacitor; and
means for providing a bias signal, to the storage capacitor, wherein the bias signal is synchronized with the common voltage signal, the amplitude of the bias signal (ΔVbias) is larger than that of the common voltage signal (ΔVcom), and a relationship between the bias signal and the common voltage signal is based on ΔVbias=[(Cst+Cb)/Cst]·ΔVcom.

18. The driving device according to claim 17, wherein the liquid crystal display is a touch panel comprising a read-out line.

19. The driving device according to claim 17, wherein the pixel unit further comprises a switching element having a control terminal connected electrically to a first gate line, a first terminal connected electrically to a first data line, and a second terminal connected electrically to the storage capacitor and the liquid crystal capacitor.

20. The driving device according to claim 19, wherein there is an overlap portion between a pixel electrode and the read-out line.

21. The driving method according to claim 19, wherein there is an overlap portion between a pixel electrode and the first gate line.

22. The driving method according to claim 19, wherein there is an overlap portion between a pixel electrode and the first data line.