# Patent

## Title
Semiconductor device with (110)-oriented silicon

## Abstract

A vertical semiconductor device includes a bottom metal layer and a first P-type semiconductor layer overlying the bottom metal layer. The first P-type semiconductor layer is characterized by a surface crystal orientation of (110) and a first conductivity. The first P-type semiconductor layer is heavily doped. The vertical semiconductor device also includes a second P-type semiconductor layer overlying the first P-type semiconductor layer. The second semiconductor layer has a surface crystal orientation of (110) and is characterized by a lower conductivity than the first conductivity. The vertical semiconductor device also has a top metal layer overlying the second P-type semiconductor layer. A current conduction from the top metal layer to the bottom metal layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane.

## Background
CROSS-REFERENCES TO RELATED APPLICATIONS
This application is a division of U.S. application Ser. No. 12/174,030, filed Jul. 16, 2008 which claims the benefit of U.S. Provisional Application No. 60/975,739, filed Sep. 27, 2007, commonly assigned, which are incorporated herein by reference in their entirety for all purposes.


BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor devices, and more particularly to a method and structure for making trench FETs in (110)-oriented silicon.
Conventional semiconductor manufacturing utilizes a number of processes to form semiconductor structures on substrates. In certain devices, the substrate is used as part of the current conduction path. For example, the substrate plays an important role with the solid state switch which is a key semiconductor structure used for discrete device applications and integrated circuits. Solid state switches include, for example, the power metal-oxide-semiconductor field effect transistor (power MOSFET), the insulated-gate bipolar transistor (IGBT), and various types of thyristors. Some of the defining performance characteristics for the power switch are its on-resistance (i.e., drain-to-source on-resistance, RDSon), breakdown voltage, and switching speed.
Generally, the switching speed, on-resistance, breakdown voltage, and power dissipation of a typical MOSFET are influenced by the layout, dimensions, and materials. Industry design practice has sought to keep the on-resistance of the MOSFET as low as possible to lower conducting power loss and increase current densities. For example, in vertical power MOSFETs, the on-resistance is composed of several resistances such as channel resistance, drift region (e.g., epitaxial layer) resistance, and substrate resistance. The on-resistance of such a vertical power MOSFET (as well as other MOSFETs) is directly influenced by the type and dimensions of materials used to form the drain to source conduction path. Therefore, for a vertical power device, such as a power MOSFET, the substrate is a critical performance element.
Even though conventional techniques have been used for making vertical power devices utilizing various substrate materials, there are limitations associated with these conventional techniques. Some of these limitations are discussed in detail below.
Thus, there is a need for improved techniques for making vertical devices having desirable substrate properties while maintaining a simple manufacturing process.
BRIEF SUMMARY OF THE INVENTION
In accordance with embodiments of the invention, various techniques are described for combining higher hole mobility in the (110) P-type material and low resistivity of heavily doped (110) P-type material to improve device properties of P-type vertical semiconductor devices.
According to an embodiment of the invention, a method is provided for forming a semiconductor device on a heavily doped P-type (110) semiconductor layer. The method includes providing a first P-type semiconductor layer, which is characterized by a surface crystal orientation of (110) and a first conductivity, and is heavily doped. The method also includes forming a second P-type semiconductor layer overlying the first P-type semiconductor layer. The second P-type semiconductor layer has a surface crystal orientation of (110) and is characterized by a lower conductivity than the first conductivity. The method further includes forming a top conductor layer overlying the second P-type semiconductor layer, and forming a bottom conductor layer underlying the first P-type semiconductor layer. A current conduction from the top conductor layer to the bottom conductor layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on a (110) crystalline plane.
In one specific embodiment, the method includes providing a first support substrate and forming a P-type heavily doped (110) silicon layer overlying the first support substrate. At least a top layer of the first support substrate is removable by a selective etching process with respect to the P-type heavily doped (110) silicon layer. Then a vertical semiconductor device structure is formed in and over the P-type heavily doped (110) silicon layer. The device structure includes a top metal layer and is characterized by a current conduction on a (110) plane and in a <110> direction. The method includes bonding a second support substrate to the top metal layer and removing the first support substrate using a selective etching process to expose a surface of the P-type heavily doped (110) silicon layer. The method also includes providing a metal layer in contact with the surface of P-type heavily doped (110) silicon layer and removing the second support substrate.
In one embodiment, the first support substrate includes an oxide layer overlying a silicon substrate, which is characterized by (100) crystalline orientation, P-type conductivity, and light doping. In a specific embodiment, the P-type heavily doped (110) silicon layer is formed as follows. A P-type heavily doped (110) silicon layer is formed overlying a first silicon substrate which is a lightly doped P-type (110) substrate. A first oxide layer is formed overlying the P-type heavily doped (110) silicon layer. Hydrogen ions are implanted into the heavily doped (110) silicon layer to form a region therein sufficiently weakened by the hydrogen to allow cleaving the heavily doped (110) silicon layer along the region to form an upper (110) layer and a lower (110) layer. In an embodiment, a second oxide layer is formed overlying the first support silicon substrate. The method includes bonding the first substrate to the first support silicon substrate and cleaving the P-type heavily doped (110) silicon layer along the region leaving the lower layer bonded to the second silicon dioxide layer overlying the first support silicon substrate. The lower (110) layer is characterized by P-type conductivity and heavy doping. In a specific embodiment, the first support substrate is removed by grinding the silicon substrate, etching the remaining silicon substrate using the oxide layer as an etch stop, and etching the oxide layer using the P-type heavily doped (110) silicon layer as an etch stop.
In another embodiment, the first support substrate includes a silicon substrate characterized by (110) crystalline orientation, P-type conductivity, and light doping, and the P-type heavily doped (110) silicon layer is formed using an epitaxial process or an ion implantation process. In a specific embodiment, the first support substrate is removed by grinding the silicon substrate and etching the remaining silicon substrate using the heavily doped P-type silicon as a etch stop. For example, the first support silicon substrate can be removed using a wet etching process including KOH or EDP.
In accordance with another embodiment of the invention, a vertical semiconductor device includes a bottom conductive layer and a first P-type semiconductor layer overlying the bottom conductor layer. The first P-type semiconductor layer is heavily doped and is characterized by a surface crystal orientation of (110) and a first conductivity. The vertical semiconductor device includes a second P-type semiconductor layer having overlying the first P-type semiconductor layer. The second semiconductor layer is also P-type and is characterized by a lower conductivity than the first conductivity. A top metal layer overlies the second P-type semiconductor layer and forms a top contact to the device. In this vertical semiconductor device, a current conduction from the top metal layer to the bottom metal layer and through the second P-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane.
In a specific embodiment of the vertical semiconductor device, the first P-type semiconductor layer is characterized by a doping concentration of 1E17/cm3 or higher. In another embodiment, the first P-type semiconductor layer is characterized by a doping concentration higher than 6E19/cm3.
In a specific embodiment, the vertical semiconductor device includes a trench gate MOSFET which includes a trench extends into the second P-type semiconductor region. A gate dielectric layer lines sidewalls and bottom of the trench. The trench gate MOSFET includes a gate electrode over the gate dielectric in the trench and P-type source regions flanking each side of the gate electrode in the trench. The MOSFET also includes a P-type drift region, an n-type body region extending over the drift region, and P-type source regions in the body region adjacent to the trench.
In another embodiment, the vertical semiconductor device includes a shielded gate trench MOSFET which includes a trench extending into the second semiconductor layer. A shield dielectric lines sidewalls and a bottom surface of the trench. The shielded gate trench MOSFET includes a shield electrode in a lower portion of the trench and is insulated from the second semiconductor layer by the shield dielectric. An inter-electrode dielectric overlies the shield electrode, and a gate dielectric lines upper portions of trench sidewalls. The shielded gate trench MOSFET also includes a gate electrode in an upper portion of the trench over the inter-electrode dielectric. The gate electrode is insulated from the second semiconductor layer by the gate dielectric. In one embodiment, the second semiconductor layer includes a P-type drift region, an n-type body region extending over the drift region, and P-type source regions in the body region adjacent to the trench.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantage of the present invention.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified cross-sectional view diagram illustrating a P-type trench gate MOSFET in accordance with an embodiment of the invention;
FIG. 2 is a simplified cross-sectional view diagram illustrating a P-type shielded gate trench MOSFET in accordance with another embodiment of the invention;
FIGS. 3A and 3B are simplified view diagrams illustrating crystalline orientations in a (110) wafer in accordance with embodiments of the invention;
FIGS. 4A-4F are simplified cross-sectional view diagrams illustrating a simplified process flow for forming a heavily doped P-type (110) oriented substrate structure according to another embodiment of the present invention;
FIGS. 5A-5H are simplified cross-sectional view diagrams illustrating a process flow for forming a vertical device using a heavily doped P-type (110) oriented substrate according to an embodiment of the present invention;
FIG. 6 is a simplified diagram illustrating variations in silicon etch rate as a function of boron concentration according to an embodiment of the present invention; and
FIGS. 7A-7G are simplified cross-sectional view diagrams illustrating another process flow for forming a vertical device using a heavily doped P-type (110) oriented substrate according to an alternative embodiment of the present invention.



DETAILED DESCRIPTION OF THE INVENTION
In accordance with embodiments of the invention, various techniques are described for forming vertical devices using P-type (110) oriented silicon material that provides increased hole mobility in current conduction on a (110) plane and in the <110> direction and heavily doped P-type regions for both reducing substrate resistance and forming a good ohm-contact. In one embodiment, a layer of heavily doped (110) silicon material is formed and then transferred to a support substrate. Following vertical device fabrication, the support substrate is replaced with a metal contact layer to the heavily doped (110) silicon material. In one variation of the invention, a layer of heavily doped (110) silicon material is formed on a lightly doped (110) silicon substrate. After device fabrication, the substrate is removed using a selective etching process after initial mechanical-grinding. Accordingly, embodiments of the invention combine higher hole mobility in the (110) P-type material and low resistivity of heavily doped (110) P-type material to improve device properties of P-type vertical semiconductor devices.
Depending upon the embodiment, the present invention includes various features, which may be used. These features include the following:

    
    
        1. High mobility p-channel device is realized on the (110)/<110> crystallographically configured silicon wafer to achieve the high hole mobility in the inversion layer;
        2. The contribution of the lightly doped (110) silicon substrate to device on-resistance is reduced; and
        3. A (110) oriented silicon-on-metal (SOM) structure allows to substantially improve Rdson without increasing gate charge at the vertical power trench devices.
    
    


The above features may be in one or more of the embodiments to follow. These features are merely examples, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
FIG. 1 is a simplified cross-sectional view diagram illustrating a P-type trench gate MOSFET 100 in accordance with an embodiment of the invention. It is to be understood, however, that the principle techniques of the present invention apply to both discrete devices as well as integrated circuits using any processing technology. As with all other figures described herein, it is to be understood that the relative dimensions and sizes of various elements and components depicted in the figures do not exactly reflect actual dimensions and are for illustrative purposes only. As shown, MOSFET 100 includes gate electrodes G that are formed inside trenches 102. The trenches 102 extend from the top surface of an N− well body region 104 terminating in a P-type drift or epitaxial region 106. In one embodiment, the trenches 102 are lined with thin dielectric layers 108 and are substantially covered with conductive material 110, such as doped polysilicon. P-type source regions 112 are formed inside the N− well body region 104 adjacent trenches 102. MOSFET 100 includes a N+ body region 117 formed inside the N− well body region 104. MOSFET 100 includes a metal source layer 116. A drain terminal D for MOSFET 100 is coupled to a metal substrate 118 disposed on a P-type heavily doped silicon layer 114. The epitaxial layer 106 and body region 104 form a semiconductor structure layer 107 disposed on the heavily doped P-type silicon layer 114.
FIG. 2 is a simplified cross-sectional view diagram illustrating a P-type shielded gate trench MOSFET 200 in accordance with an embodiment of the invention. As shown, MOSFET 200 includes gate electrodes G that are formed inside trenches 202. The trenches 202 extend from the top surface of an N− well body region 204 terminating in a P-type drift or epitaxial region 206. In one embodiment, the upper portions of trenches 202 are lined with thin gate dielectric layers 208 and are substantially covered with conductive material 210, such as doped polysilicon, which form the gate electrodes G. Shielded gate electrodes 211, made of conductive material such as doped polysilicon, are insulated from lower portions of the trenches 202 with shield dielectric layers 209. P-type source regions 212 are formed inside the N− well body region 204 adjacent trenches 202. MOSFET 200 includes a N+ body region 217 formed inside the N− well body region 204. MOSFET 200 includes a metal source layer 216. A drain terminal D for MOSFET 200 is coupled to a metal substrate 218 disposed on a P-type heavily doped silicon layer 214. The epitaxial layer 206 and body region 204 form a semiconductor structure layer 207 disposed on the heavily doped P-type silicon layer 214.
A focus for trench MOSFET technology development is to reduce both on-resistance (Rdson) and gate charge, especially gate-to-drain charge (Qgd). For example, Rdson can be reduced with increasing trench density by reducing pitch. This approach, however, often leads to higher Qgd simultaneously. It also can increase difficulty in contact formation for both the heavy body region and source region. This pitch miniaturization also can lead to higher leakage failure rate due to the defect generated by heavy body process.
According to one embodiment of the invention, a method is provided to fabricate p-channel trench MOSFET device on (110)-oriented silicon wafers with flat (notch) in crystallographic <110> direction to reduce the channel resistance. It is known that the hole mobility in the inversion layer can be more than doubled on silicon (110) plane in <110> direction ((110)/<110>) than on (100) plane in <100> direction ((100)/<100>). A relationship between hole mobility and channel resistance can be expressed in the following equation.




  
    R
    ch
  
  =
  
    L
    
      Z
      ⁢
      
        
      
      ⁢
      
        μ
        p
      
      ⁢
      
        
          C
          ox
        
        ⁡
        
          (
          
            
              V
              G
            
            -
            
              V
              T
            
          
          )
        
      
    
  




where L is the channel length, Z is the channel width, Cox is the gate oxide capacitance per unit area, VG is the gate voltage, μp is the hole mobility in channel region, and VT is the threshold voltage. The p-channel devices built on (110)/<110> crystallographically configured wafers thus have much reduced the Rch due to improved μp.

As shown in FIG. 3A, the (110)/<110> configuration can be realized by using (110)-oriented silicon wafers with flat (notch) parallel to the <110> crystallographic direction. As shown in FIG. 3B, the vertical trenches on this type of wafers have both trench bottom and side wall on (110) planes and the direction of current flow from the trench top to the trench bottom (channel direction) is in the <110> direction.
An obstacle in applying the (110)/<110> wafers for power trench MOSFET devices is growing heavily boron doped (110) oriented Czochralski (CZ) silicon wafers. Due to very small boron segregation coefficient on (110) oriented silicon crystal, boron incorporation is very limited. The resistivity of such ingot is in the range of tens Ω-cm. To build the vertical power trench device, it is necessary to have a heavily boron doped (110) oriented substrate and a technology to reduce the substrate contribution to the device on-resistance. According to one embodiment, the present invention provides a method for making p-channel trench MOSFET devices on a (110)-oriented silicon substrate with reduced the channel resistance. The invention also provides a method for reducing drain resistance with heavily doped (110)-oriented silicon substrate.
A process flow for forming a power device using a heavily doped P-type (110) substrate structure according to an exemplary embodiment of the invention is outlined next. An epi layer with a resistivity less than 100 mΩ-cm (dopant concentration >1×1017 cm−3) and a thickness less than 3.0 μm is grown on the lightly doped (110) orientation silicon substrate. Then a thermal silicon dioxide layer with a thickness of 400 ̃500 Å is grown on the top of the epi layer. Hydrogen ions/molecules are implanted through the silicon dioxide layer at a dose of 3×1016 cm−2 and energy of 60-170 KeV. For ease of reference, this wafer is called the seed wafer hereafter. The seed wafer is then bonded to another silicon wafer (support substrate) which is topped with a thermal silicon dioxide layer of 1000-2500 Å in thickness, using wafer direct bonding technique performed at room temperature. The bonded wafer pair is then subjected to the two-step low temperature annealing procedure. The first anneal at 150-300° C. for 10-20 hours is used for the fusion bond pre-strengthening, and the second anneal at 450° C. for 45 minutes serves for the separation of the heavily boron doped (110)-layer of the seed wafer along the cleaving plane defined by the hydrogen implantation energy. The thickness of the transferred heavily boron doped (110)-layer is defined therefore by the energy of the hydrogen implant and range from 0.5 to 1.5 μm in a specific embodiment. A more detailed description is now presented below.
FIGS. 4A-4F are simplified cross-sectional view diagrams illustrating a process flow for forming a heavily doped P-type (110) substrate structure according to an embodiment of the present invention. FIG. 4A illustrates a cross-sectional view of a seed (110) silicon material 402, which may be doped by dopants such as Boron. In a specific example, silicon material 402 may be a lightly doped P-type silicon substrate. A heavily doped P-type epi layer 404 with a resistivity less than 100 mΩ-cm (dopant concentration >1×1017 cm−3) and a thickness less than 3.0 μm is grown on the lightly doped (110) orientation silicon substrate. Alternatively, heavily doped layer 404 may be formed by implanting dopants in silicon material 402. Then a thermal silicon oxide layer 406 with a thickness of 400 ̃500 Å is grown on the top of heavily doped layer 404. Hydrogen ions/molecules are implanted through the silicon dioxide layer at a dose of 3×1016 cm−2 and energy of 60-170 KeV. In one embodiment, the wafer including layers 402, 404, and 406 is referred to as the seed wafer 407 hereafter. In an embodiment, the hydrogen implant creates a hydrogen rich region 405 delineated as the dotted line in the epi layer 404. An exemplary process for doping hydrogen ions into a silicon substrate is disclosed in U.S. Pat. No. 5,374,564, by Bruel, incorporated herein by reference in its entirety.
In one embodiment, the concentration of hydrogen ions is provided at a sufficient depth and energy potential to form a hydrogen rich region, or cleavable region, 405, having an exemplary thickness of between about 1-2 μm. Because of hydrogen embrittlement, the cleavable region 405 lattice is weaker than non-hydrogen doped silicon lattice.
FIG. 4B illustrates a cross-sectional view of one embodiment of a first support substrate 308 accordance with embodiments of the invention. In one embodiment, the first support substrate 308 is a (100) silicon substrate. In another embodiment, the (100) silicon substrate is covered by a silicon dioxide (SiO2) layer 305. The SiO2 layer 305 is used as an etch stop layer and may be virtually any thickness that may be used to advantage. For example, in one embodiment, the SiO2 layer 305 may be about between 1000 and 2500 Å. In another embodiment, the SiO2 layer 305 may be about between 2500 and 4000 Å. The SiO2 layer 305 may be grown or deposited on the support substrate 308 using virtually any SiO2 layer formation process. For example, the SiO2 layer 305 may be grown using a thermal oxidation process.
In FIG. 4C the first support substrate 308 and oxide layer 305 is bonded to seed wafer 407 including layers 402, 404, and 406 as shown in FIG. 4A. In a specific embodiment, oxide layers 305 and 406 are bonded together in the bonding process to form oxide layer 306. The bonding can be carried out using any of a number of bonding techniques. For example, after a wet chemical and de-ionized (DI) water treatment to render the SiO2 layers 305 and 406 with a hydrophilic surface, the SiO2 layer 305 and the seed wafer 407 may be bonded at room temperature using conventional bonding techniques.
In FIG. 4D a cleaving process is performed to divide the epi layer 404 into two separate layers 114A and 114B. The cleaving process leaves a lower layer 114B of heavily doped (110) P-type silicon on the first support substrate 308 and a remaining layer portion 114A of the epi layer on the seed silicon material 402. The cleaving may be carried out using any number of cleaving processes to break the lattice structure of the cleavable region 405. In one embodiment, the cleaving process includes annealing the seed wafer 407 and the initial substrate 308 at a temperature of between 150 and 300° C. for about 5 hours to 10 hours. In another embodiment the cleaving process includes annealing the seed wafer 407 and the first support substrate 308 at a temperature of about 450° C. for about 15 minutes. In a specific embodiment, the bonded wafer pair is subjected to a two-step low temperature annealing procedure. The first anneal at 150-300° C. for 10-20 hours is used for the fusion bond pre-strengthening, and the second anneal at 450° C. for 45 minutes serves for the separation of the heavily boron doped (110)-layer of the seed wafer along the cleaving plane defined by the hydrogen implantation energy. The thickness of the transferred heavily boron doped (110)-layer is defined therefore by energy of the hydrogen implant and range from 0.5 to 1.5 μm in a specific embodiment.
FIGS. 4E and 4F are simplified cross-sectional view diagrams illustrating the two parts formed in the cleaving process described in FIG. 4D. In FIG. 4E a composite material 420 is formed which includes lightly doped P-type (110) silicon wafer 402 and a heavily P-type doped (110) epi layer 114A. In one embodiment, composite material 420 can be used to form another seed wafer, such as seed wafer 407 in FIG. 4A, and used repeatedly in a process as described in FIGS. 4A-4D. FIG. 4F shows a composite material 430, which includes heavily doped P-type (110) layer 114B overlying an oxide layer now labeled 306 which overlies the first support substrate 308. In one embodiment layer 114B has a resistivity of 8 mΩ-cm, which is much lower than that of commercially available (110) silicon wafers. In one embodiment this layer is used in forming a vertical device and provides a good ohm contact for backside meta layer. An example of a method for forming a vertical device is discussed below.
FIGS. 5A-5H are simplified cross-sectional view diagrams illustrating a process flow for forming a vertical device using a heavily doped P-type (110) oriented substrate according to an embodiment of the present invention. FIG. 5A illustrates a cross-sectional view of one embodiment of the semiconductor process structure 430 of FIG. 4F with heavily doped P-type (110) silicon layer 114B over an oxide layer 306 which in turn overlies support layer 308. In one example, support layer 308 may be a lightly doped (100) silicon layer. In a specific embodiment, layer 114B has a doping concentration of 1E17/cm3 or higher. In one embodiment, the structure in FIG. 5A may be formed using a process described in FIGS. 4A-4F. Alternatively, the structure in FIG. 5A may be formed using another method.
In FIG. 5B, a lightly doped P-type (110) epitaxial layer 106 is formed on the doped P-type (110) silicon layer 114B. Optionally, the cleaved doped silicon layer 114B may be pretreated in a CVD chamber to prepare the silicon layer 114B for the epitaxial layer 106 formation. The pretreatment may be used to generate a more uniform surface.
In FIG. 5C, semiconductor devices 702 are formed in and over epitaxial layer 106 and form semiconductor structure layer 107. The formation of the semiconductor structure layer 107 may be done by any conventional semiconductor structure formation techniques. For example, the semiconductor structures 702 may be formed on and/or within the epitaxial layer 106 using conventional semiconductor structure fabrication steps such as layering, patterning, and doping. The semiconductor structures 702 may also be formed on and/or formed integral to the doped silicon layer 114B. In one example, semiconductor structure layer 107 may include trench gate MOSFET structures as discussed above in connection with FIG. 1. In this example, each semiconductor structures 702 is a trench gate MOSFET. In another example, semiconductor structure layer 107 in FIG. 5C may include shielded gate trench MOSFET structures as discussed above in connection with FIG. 2. In this example, each semiconductor structures 702 is a shielded gate trench MOSFET. In one optional operational configuration, for MOSFETs, for example, the metal layer 116 is formed on the semiconductor structures 702. The metal layer 116 may be applied using virtually any process some of which are described herein. In another embodiment, after the formation of the device layer 107, the initial substrate 308, SiO2 layer 306, doped silicon layer 114B, and semiconductor structure layer 107 together form another intermediate semiconductor processing structure 507.
In FIG. 5D a second support substrate 802, for example, a glass wafer, is mounted to metal layer 116 over the semiconductor structure layer 107 to support the semiconductor process structure 507 for processing. For example, second support substrate 802 is mounted to the semiconductor process structures 507 using a UV releasable double sided tape, which provides an adhesive bond sufficient in strength to securely hold the intermediate semiconductor process structure for processing.
In FIG. 5E, the initial support layer 308, for example, a (100) silicon substrate, is thinned by a substrate thinning process. Optionally, in one embodiment, the initial substrate 308 is thinned using a mechanical thinning process such as mechanical polishing/grinding to form a thinner substrate 308A. The initial substrate 308 may be thinned, e.g., to about 8 mils to make it faster to remove with chemicals.
In FIG. 5F the remaining substrate 308A is removed using a substrate etching process. In one process, the substrate 308A is removed by chemically etching the substrate 308A with a chemical etching process using the buried SiO2 layer 306 as an etch stop layer. As the SiO2 layer 306 is configured to stop the chemical etching process, silicon layer 114B and the semiconductor structure layer 107 remain untouched by the chemical used to etch the initial substrate 308A. The chemical etching may be done by any process to remove the initial substrate 308A. For example, the etching process may be done with chemicals such as acid, hydroxides, and the like, that remove the initial substrate 308A, but do not etch the buried SiO2 layer 306. In one process, the chemical etching process to remove the initial substrate 308A may be illustrated with the following chemical formula:

Si+OH−+2H2O→SiO2(OH)2−+H2 

Where SiO2(OH)2− is a soluble complex.

In FIG. 5G the SiO2 layer 306 is removed by an etching process. The buried SiO2 layer 306 may be chemically etched using a solution of HF. In this configuration, the heavily doped (110) silicon layer 114B is used as the etch stop. For example, the SiO2 layer 306 may be etched with a 49 wt % HF solution at room temperature. This particular solution may etch the SiO2 layer 306 at about 2.5 μm/min. The etching process for removing layer 306 can be illustrated with the following chemical equation:

SiO2+6HF→H2SiF6(aq)+2H2O

In FIG. 5H a metal substrate 118 is formed on the doped silicon layer 114B. In one embodiment, the metal substrate 118 may be formed using virtually any process, such as electroplating and/or using deposition processes such as plasma vapor deposition (PVD), chemical vapor deposition (CVD), and the like. In another example, the metal substrate 118 may be electroplated on the doped silicon layer 114B. The metal substrate 118 may include virtually any metal or conductor that may be used to advantage such as copper, aluminum, or alloys such as solder, and the like.
In FIG. 5H, support layer 802 is removed. The support layer 802 may be removed using any number of techniques. For example, the support layer 802 may be removed using an ultra violet light process where the bonding tape is configured to release when exposed to a sufficient amount of UV light for a predetermined duration. Subsequently, the semiconductor process structure 500 in FIG. 5H may be diced into individual devices (dies) in accordance with embodiments of the invention.
As discussed above in connection with FIGS. 4A-4F and FIGS. 5A-5H, the present invention provides a method for fabricating p-channel trench MOSFET device on (110)-oriented silicon material to facilitate hole current conduction in the <110> direction to reduce channel resistance. In a specific embodiment, the vertical trenches on this type of wafers have both trench bottom and side wall on (110) planes and the direction of current flow from the trench top to the trench bottom (channel direction) is in the <110> direction. The method can be used to form a vertical device, such as trench gate MOSFET or shielded gate trench MOSFET, in which a current conduction in the vertical direction is enhanced. For example, in FIG. 5H a current may be conducted between metal layers 116 and 118 and through device layer 107, where device layer 107 may include a trench gate MOSFET or a shielded gate trench MOSFET. In alternative embodiment, device layer 107 may also include other vertical devices such as diodes or IGBTs.
FIG. 6 is a simplified diagram illustrating a relationship between etch rate of a silicon substrate and its boron concentration according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims herein. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. As shown, the etch rate of silicon decreases sharply as its boron concentration is increased above about 1×1019 cm−3. Specifically there is significant etching rate difference between heavily and lightly boron doped silicon substrates with either KOH or ehtylenediamine/pytocatechol/water (EDP). For example, in EDP solution at 81° C., the etching rate at boron concentration <1×1019 cm−3 is about 20 μm/hr, compared to that of 0.1 μm/hr at the boron concentration of 1×1020 cm−3. The etching rate difference can be as large as 200 times. A similar etching rate difference has been observed in KOH chemistry as well. This etching difference will enable the heavily boron doped silicon layer as etching stop. This etch selectivity between lightly doped P-type silicon and heavily doped P-type silicon is used advantageously in a method in an embodiment of the present invention.
FIGS. 7A-7G are simplified cross-sectional view diagrams illustrating another process flow for forming a vertical device using a heavily doped P-type (110) oriented substrate according to an alternative embodiment of the present invention. First, in FIG. 7A, a heavily boron doped (110) layer 114 (with concentration >6×1019 cm−3) is epitaxially grown or formed through boron implant on (110) oriented silicon wafer 708. Merely as an example, an epi process can be carried out at 1060° C. with a B2H6 doping species (mixing with H2 at a concentration of 5000 ppm). Alternatively, heavily doped layer 114 may be formed by boron ion implantation. The implant can be of 60 KeV with a dose of 1×1016 cm−2 for half an hour to create a heavily doped silicon layer. After this process, the desired device epi layer 106 is grown as shown in FIG. 7B. The wafer then undergoes the device fabrication process to build the device. In FIG. 7C device layer 107 and metal layer 116 are formed, which may include trench gate MOSFET or shielded gate trench MOSFET, or other vertical devices, such as described in FIGS. 5A-5H. The finished wafer is then bonded to a support substrate 802, e.g., a glass carrier as shown in FIG. 7D, and ready for substrate transfer.
In FIG. 7E, the majority (e.g. 90%) of support substrate silicon wafer 708 is removed through mechanical grinding and acid etching until certain thickness of lightly doped (110) oriented silicon wafer 708A is left, such as 5 μm. The final 5 μm thick silicon 708A is removed by EDP or KOH. Due to the high selectivity of the EDP/KOH etching, the silicon etching will stop at the heavily doped boron silicon 114. In FIG. 7F, this wafer is then ready for the backside metal deposition 118 and supporting metal transferring by removing the glass substrate 802, resulting in the device structure shown in FIG. 7G. The method include certain processes, such as vertical device fabrication, support layer bonding, metal deposition, etc, similar to corresponding processes described above in connection with FIGS. 5A-5H.
Thus FIGS. 7A-7G are simplified diagrams illustrating an alternative method for forming vertical devices in (110) P-type silicon for enhanced hole mobility which also provides heavily-doped (110) P-type drain regions and metal layers for reducing resistance. As shown, the process is simplified by etch selectivity between heavily doped P-type silicon and lightly doped P-type silicon.
Another challenge in applying the (110)/<110> configured wafers for power trench MOSFET devices is forming high quality gate oxide on (110) plane. An issue is to reduce both fixed oxide charge and interface trap density (Dit) to achieve acceptable threshold voltage and threshold voltage stability. It has been established that the Dit is proportional to the density of available bonds on the surface. Table 1 summarizes the silicon properties of different crystallographic planes. The Dits at (100) and at (111) planes are of 2×1010 and of 2×1011 1/cm2-eV, respectively. The fact that available bonds per unit area on the (110) plane are between (100) and (111) planes indicates that the Dit of (110) plane will be between 2×1010 and 2×1011 1/cm2-eV although no data is available. According to embodiments of the invention, reducing oxide growth rate and adding additional hydrogen annealing can further reduce the Dit and fixed oxide charge and improve gate oxide integrity.







TABLE 1







Physical properties of Silicon













Surface






Density
Available
Dit at mid-gap



Orientation
1/cm2
Bonds 1/cm2
1/cm2-eV







(100)
6.8 × 1014
6.8 × 1014
2 × 1010



(110)
9.6 × 1014
9.6 × 1014



(111)
7.85 × 1014 
11.8 × 1014 
2 × 1011










While the above is a complete description of specific embodiments of the present invention, various modifications, variations, and alternatives may be employed. For example, while the invention is illustrated using vertical MOSFETs, the invention could easily be applied to other structures such as trench gate IGBTs by merely reversing the polarity of the substrate from those shown in FIGS. 1 and 2. Further, the invention is not limited to trench gate structures and may be used in forming other devices such as planar gate vertical MOSFETs, planar gate vertical IGBTs, diodes, and various types of thyristors. Hence, the scope of this invention should not be limited to the embodiments described, but are instead defined by the following claims.

## Claims

1. A vertical semiconductor device, comprising:
a bottom metal layer;
a first P-type semiconductor layer overlying the bottom metal layer, the first P-type semiconductor layer being characterized by a surface crystal orientation of (110) and a first conductivity, the first P-type semiconductor layer being heavily doped;
a second P-type semiconductor layer overlying the first P-type semiconductor layer, the second semiconductor layer having a surface crystal orientation of (110) and being characterized by a lower conductivity than the first conductivity; and
a top metal layer overlying the second P-type semiconductor layer,
wherein a current conduction from the top metal layer to the bottom metal layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane.

2. The vertical semiconductor device of claim 1 wherein the first P-type semiconductor layer is characterized by a doping concentration of 1×1017 cm−3 or higher.

3. The vertical semiconductor device of claim 1 wherein the first P-type semiconductor layer is characterized by a doping concentration higher than 6×1019 cm−3.

4. The vertical semiconductor device of claim 1 wherein a thickness of the first P-type semiconductor layer is between approximately 0.5 μm to approximately 3 μm.

5. The vertical semiconductor device of claim 1 wherein each of the first and second P-type semiconductor layers is an epitaxial layer.

6. The vertical semiconductor device of claim 1 wherein the bottom metal layer has sufficient thickness for supporting the vertical semiconductor device.

7. The vertical semiconductor device of claim 1 wherein the vertical semiconductor device comprises a trench gate P-channel MOSFET, the trench gate MOSFET further comprising:
a trench extending into the second P-type semiconductor region; a gate dielectric layer lining sidewalls and bottom of the trench;
a gate electrode over the gate dielectric in the trench;
P-type source regions flanking each side of the gate electrode in the trench;
a P-type drift region;
an N-type body region extending over the drift region; and
a P-type drain region including at least a portion of the heavily doped first P-type semiconductor layer.

8. The vertical semiconductor device of claim 1 wherein the vertical semiconductor device comprises a P-channel shielded gate trench MOSFET, the shielded gate trench MOSFET further comprising:
a trench extending into the second P-type semiconductor layer;
a shield dielectric lining sidewalls and a bottom surface of the trench;
a shield electrode in a lower portion of the trench, the shield electrode being insulated from the second semiconductor layer by the shield dielectric;
an inter-electrode dielectric overlying the shield electrode;
a gate dielectric lining upper portions of trench sidewalls; and
a gate electrode in an upper portion of the trench over the inter-electrode dielectric, the gate electrode being insulated from the second P-type semiconductor layer by the gate dielectric.

9. The vertical semiconductor device of claim 8 wherein the second P-type semiconductor layer comprises:
a P-type drift region;
an N-type body region extending over the drift region; and
P-type source regions in the body region adjacent to the trench.

10. A vertical trench gate MOSFET device formed in a (110) substrate, comprising:
a bottom metal layer;
a first P-type semiconductor layer overlying the bottom metal layer, the first P-type semiconductor layer being characterized by a surface crystal orientation of (110) and a first conductivity, the first P-type semiconductor layer being heavily doped;
a second P-type semiconductor layer having a surface crystal orientation of (110) and overlying the first P-type semiconductor layer, the second semiconductor layer—being characterized by a lower conductivity than the first conductivity;
an N-type body region in the second P-type semiconductor layer; and
a trench extending through the body region and into a bottom portion of the second P-type semiconductor layer underlying the body region;
a gate dielectric layer lining sidewalls and bottom of the trench;
a gate electrode over the gate dielectric in the trench;
P-type source regions flanking each side of the gate electrode in the trench; and
a top metal layer overlying the second P-type semiconductor layer, the top metal layer being coupled to the source regions and the body region,
wherein a current conduction from the top metal layer to the bottom metal layer and through the second P-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation.

11. The vertical semiconductor device of claim 10 wherein the first P-type semiconductor layer is characterized by a doping concentration of 1×1017 cm−3 or higher.

12. The vertical semiconductor device of claim 10 wherein the first P-type semiconductor layer is characterized by a doping concentration higher than 6×1019 cm−3.

13. The vertical semiconductor device of claim 10 wherein a thickness of the first P-type semiconductor layer is between approximately 0.5 μm to approximately 3 μm.

14. The vertical semiconductor device of claim 10 wherein each of the first and second P-type semiconductor layers is an epitaxial layer.

15. The vertical semiconductor device of claim 10 wherein the bottom metal layer has sufficient thickness for supporting the vertical semiconductor device.

16. A vertical shielded gate trench MOSFET device formed in a (110) substrate, comprising:
a bottom metal layer;
a first P-type semiconductor layer overlying the bottom metal layer, the first P-type semiconductor layer being characterized by a surface crystal orientation of (110) and a first conductivity, the first P-type semiconductor layer being heavily doped;
a second P-type semiconductor layer having a surface crystal orientation of (110) and overlying the first P-type semiconductor layer, the second P-type semiconductor layer being characterized by a lower conductivity than the first conductivity;
an N-type body region in the second P-type semiconductor layer;
a trench extending through the body region and into a bottom portion of the second P-type semiconductor layer underlying the body region;
a shield dielectric lining sidewalls and a bottom surface of the trench, the shield dielectric including a first shield oxide layer;
a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by the shield dielectric;
an inter-electrode dielectric overlying the shield electrode; a gate dielectric lining upper portions of trench sidewalls;
a gate electrode in an upper portion of the trench over the inter-electrode dielectric, the gate electrode being insulated from the semiconductor region by the gate dielectric;
P-type source regions flanking each side of the gate electrode in the trench; and
a top metal layer overlying the second P-type semiconductor layer, the top metal layer being coupled to the source regions and the body region; wherein a current conduction from the top metal layer to the bottom metal layer and through the second P-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and in a (110) crystalline plane.

17. The vertical semiconductor device of claim 16 wherein the first P-type semiconductor layer is characterized by a doping concentration of 1×1017 cm−3 or higher.

18. The vertical semiconductor device of claim 16 wherein the first P-type semiconductor layer is characterized by a doping concentration higher than 6×1019 cm−3.

19. The vertical semiconductor device of claim 16 wherein a thickness of the first P-type semiconductor layer is between approximately 0.5 μm to approximately 3 μm.

20. The vertical semiconductor device of claim 16 wherein each of the first and second P-type semiconductor layers is an epitaxial layer.

21. The vertical semiconductor device of claim 16 wherein the bottom metal layer has sufficient thickness for supporting the vertical semiconductor device.