# Patent

## Title
Application of a meta-viterbi algorithm for communication systems without intersymbol interference

## Abstract

Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the Non-ISI Meta-Viterbi detector performs χ+2t2t add, compare, and select operations.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE
This application is a continuation of U.S. patent application Ser. No. 11/059,875 filed Feb. 17, 2005, now U.S. Pat. No. 7,469,373 which makes reference to:
U.S. application Ser. No. 11/049,769, entitled “META-VITERBI ALGORITHM FOR USE IN COMMUNICATION SYSTEMS”, filed Feb. 3, 2005.
The above stated application is hereby incorporated herein by reference in its entirety.


FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[Not Applicable]
MICROFICHE/COPYRIGHT REFERENCE
[Not Applicable]
BACKGROUND OF THE INVENTION
It is well known that the Viterbi algorithm may be used for the maximum likelihood detection of data. In the absence of intersymbol interference and when using the linear block coding rate (χ−t)/χ, the detection of data may be accomplished by using a Viterbi detector with 2t states. However, when using linear block coding of rate (χ−t)/χ, in which t bits of parity are encoded in a codeword of length χ, the Viterbi algorithm requires performing χ2t (χ times 2t) add, compare, select (ACS) operations. Unfortunately, performing a large number of ACS operations is sub-optimal since the implementation complexity also increases.
The limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
Various aspects of the invention provide a system and/or method for detecting and correcting one or more data bit errors transmitted through a communication channel, wherein the communication channel does not exhibit any intersymbol interference, substantially as shown in and/or described in connection with at least one of the following figures, as set forth more completely in the claims.
These and other advantages, aspects, and novel features of the present invention, as well as details of illustrated embodiments, thereof, will be more fully understood from the following description and drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a functional block diagram of an error detection and correction system that utilizes a conventional Viterbi Algorithm to decode a linear block code transmitted through a communication channel, in the absence of intersymbol interference (ISI).
FIG. 1B is a functional block diagram of a system that utilizes the Meta-Viterbi Algorithm in accordance with an embodiment of the invention.
FIG. 2 is a functional block diagram describing a computational circuitry of a Non-ISI Meta-Viterbi detector that is used in determining a preferred set of error events, in accordance with an embodiment of the invention.
FIG. 3A is a table illustrating the computation of cumulative parity and cumulative weight of a subset of error events (subset of H={e1, e2, . . . , e15}) associated with a four-bit parity codeword, in accordance with an embodiment of the invention.
FIG. 3B is a diagram illustrating the 16 state Meta-Viterbi trellis path taken when the error events chosen correspond to {e3, e7, e10, e15}, as described in relation to FIG. 3A, in accordance with an embodiment of the invention.
FIG. 4 illustrates a portion of a Meta-Viterbi trellis diagram in accordance with an embodiment of the invention.
FIG. 5 is a diagram illustrating the selection of a path having lowest cumulative event weight, when two paths merge in a Meta-Viterbi trellis, in accordance with an embodiment of the invention.
FIG. 6 is a functional block diagram of a Non-ISI Meta-Viterbi detector in accordance with an embodiment of the invention.



DETAILED DESCRIPTION OF THE INVENTION
Various aspects of the invention provide a system and method of detecting and correcting data bit errors that occur when a data stream is transmitted through a communication channel. The data bit errors may be detected and corrected by way of transmitting a sequence of codewords. The codewords may incorporate or encode one or more parity bits into the transmitted data. The codewords are used in the detection and correction process to recover the data transmitted. The method as described herein utilizes what is referred to as a Meta-Viterbi Algorithm for use in communication channels that do not exhibit intersymbol interference (ISI). Hereinafter, this method may be termed or referred to as a Meta-Viterbi Algorithm. The system that performs the detection and correction as described herein may be termed a symbol detector and Non-ISI Meta-Viterbi detector.
In a representative embodiment, the channel may comprise a wireline communications channel. In another representative embodiment, the channel may comprise any communications transmission channel in which ISI is absent. Aspects of the invention provide performance that is equivalent to that provided by using the Viterbi Algorithm with 2t states. However, various aspects of the invention provide a significant reduction in implementation complexity compared with that provided by using the Viterbi Algorithm to detect codewords. When using the Viterbi Algorithm having codeword length χ and t parity bits that results in a linear block coding of rate (χ−t)/χ, maximum likelihood detection requires the use of 2t states run over χ steps. In terms of implementation complexity, the Viterbi algorithm requires performing a total of χ2t (χ multiplied by 2t) add, compare, select (ACS) operations. In contrast, the Meta-Viterbi Algorithm may be performed using only a total of χ+2t2t or χ+22t operations.
Various aspects of the invention implement at least a method and a system of determining an optimum set of one or more error events associated with a parity syndrome of a transmitted codeword. Each transmitted codeword is associated with an optimal set of one or more error events. The set of error events may be used to correct the codeword by way of using its parity syndrome. The optimal set of one or more error events is associated with a minimum cumulative event weight computed by a path formed from the decision branches of a trellis diagram. The path traverses one or more steps corresponding to the error events associated with the codeword. The set of error events may be determined by using the parity syndrome and cumulative parity of the codeword. A path or route is taken over a decision tree or trellis diagram by way of one or more decision branches. The branch taken corresponds to whether a particular error event occurs in a codeword. Each of the one or more paths is associated with an event weight. The cumulative weight may be found by summing the event weights of the branches used to create the path of a codeword. The path with the smallest cumulative weight is chosen as the optimal solution for correcting the codeword. Consequently, the set of error events associated with this path is used to correct the received codeword. The cumulative parity at the last step of the path may coincide with the parity syndrome of the received codeword.
FIG. 1A is a functional block diagram of an error detection and correction system that utilizes a conventional Viterbi Algorithm to decode a linear block code transmitted through a communication channel, in the absence of intersymbol interference (ISI). The system comprises a linear block encoder 104, a noise source 108, and a conventional Viterbi detector 112. As illustrated, a block of bits, ω=(ω1, . . . , ωχ−t) comprising (χ−t) bits is input into a linear block encoder 104 prior to transmission through the communication channel. The linear block encoder 104 outputs a codeword, ζ=(ζ1, . . . , ζχ), that contains a total of χ bits. One may denote a linear operator that generates a parity syndrome for each codeword: Φ:{0,1}χ→{0,1}t. Since the codeword is typically transmitted through a noisy communication channel, a noise source 108 is applied to the communication channel. In a representative embodiment, the noise source 108 may generate independent identically distributed noise into the communication channel. In yet another representative embodiment that is not illustrated, data-dependent noise may be added to the communication channel. In the embodiment illustrated in FIG. 1A, the noise output by the noise source 108 is added to the codeword, ζ, such that a codeword, ξ is input into a conventional Viterbi detector 112. The sequence of codewords received by the Viterbi detector 112 is represented by the variable ξεRχ. The Viterbi detector 112 utilizes 2t states over χ steps in the detection and correction process. The Viterbi detector 112 determines a corrected codeword ν(0), given by the equation:




  
    
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where Ξ={xε{0,1}χ|Φ(x)=0}. In the absence of ISI in the communication channel and with noise that is independent and identically distributed,





  
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FIG. 1B is a functional block diagram of a system that utilizes the Meta-Viterbi Algorithm in accordance with an embodiment of the invention. In a representative embodiment, the system may comprise a wireline data communications channel that corrects one or more data bit errors of one or more codewords by way of utilizing the Meta-Viterbi Algorithm. Of course, the system may comprise any type of communication channel without intersymbol interference. As illustrated, the system comprises a linear block encoder 154, a noise source 158, a symbol detector 162, and a Non-ISI Meta-Viterbi detector 166. Aspects of the invention provide that the system shown in FIG. 1B processes codewords in a more efficient manner by way of adding t bits of redundancy to each codeword, and allowing the Non-ISI Meta-Viterbi detector 166 to process the codewords using 2t states. Linear block coding may be used at the transmitter, for example, to generate codewords having t bits of parity. Compared to the system described in FIG. 1A, the system in FIG. 1B replaces the Viterbi detector with the symbol detector 162 and the Non-ISI Meta-Viterbi detector 166. As illustrated, a block of bits, ω=(ω1, . . . , ωχ−t), containing (χ−t) bits is input into the linear block encoder 154 prior to transmission through the communication channel. The linear block encoder 154 outputs a codeword, ζ=(ζ1, . . . , ζχ), that contains a total of χ bits. One may denote a linear operator that generates a parity syndrome for each codeword: Φ:{0,1}χ→{0,1}t. Since the codeword is typically transmitted through a noisy communication channel, a noise source 158 is applied to the communication channel. In a representative embodiment, the noise source 158 may generate independent identically distributed noise into the communication channel. The noise output by the noise source 158 is added to the codeword, ζ, such that a codeword, ξ is input into the symbol detector 162. The symbol detector 162 provides an output, referred to as a hard decision output that is used by the Non-ISI Meta-Viterbi detector 166, for example. In a representative embodiment, a slicer makes a decision by quantizing a received sample to a particular value. The value provides an estimate of the actual transmitted sample. The hard decision output provided by the symbol detector 162, ν, may be defined by the following equation:




  
    
      
        
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The hard decision output is used by the Non-ISI Meta-Viterbi detector 166 to generate a soft decision output that may be expressed using the following equation:

w(e)=log P(ξ|ν)−log P(ξ|ν+e)

The event weights, w(e), may be determined using the previously defined equation. As discussed later, the soft decision output may be generated by using an event weight processor located within the Non-ISI Meta-Viterbi detector 166. The soft decision output may be expressed as follows: log P(ξi|νi)−log P(ξi| νi), for i=1, . . . , χ, in which νi denotes the complement of the bit νi. In the case of additive white Gaussian noise (AWGN), this soft decision output is equal to −(ξi−νi)2+(ξi− νi)2. The parity syndrome, π=Φ(ν), of the received codeword may be computed by the Non-ISI Meta-Viterbi detector 166. The Non-ISI Meta-Viterbi detector 166 utilizes the hard and soft decision outputs to determine the optimum set of error events for the received codeword. The error events are used by the Non-ISI Meta-Viterbi detector 166 to determine the corrected output, ν(0) using ν. One may define an error event to be a bit sequence of length χ, comprising a single non-zero element such that ν+eε{0,1}χ, in which the operator “+” denotes conventional arithmetic addition. Various aspects of the present invention provide for an error event, comprising a single bit error, to be specified simply by its bit location within the received codeword. The single bit error event may be expressed in terms of a vector and the set of all possible error events may be specified by the variable G*(ν):

G*(ν)={e(D)=±Di|ν+eε{0,1}χ}

The Non-ISI Meta-Viterbi detector 166 determines the probability of an error event occurring by way of computing one or more event weights, w(e). Since aspects of the invention consider a communication channel with no ISI, the weight of an error event is based on soft information (i.e, the soft decision output provided by the event weight processor) at the location of the single bit error. However, for the purposes of explaining the Meta-Viterbi algorithm, it is sufficient to simply assume that some strictly positive function w:G*(ν)→(0, ∞) exists that maps to positive values. The Non-ISI Meta-Viterbi detector 166 determines the set of error events ={e1, e2, . . . , en},⊂G*(ν), such that it corrects the parity syndrome, Φ():=Φ(e1)⊕Φ(e2)⊕ . . . ⊕Φ(en)=π, of the received codeword and has minimum weight,





  
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The Non-ISI Meta-Viterbi detector 166 generates an output that corresponds to the output of a Viterbi detector using 2t states. The output of the Non-ISI Meta-Viterbi detector 166 may be represented by the following equation which indicates that the hard decision output is added to one or more error events to provide a corrected output:




  
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FIG. 2 is a functional block diagram describing a computational circuitry 208 of a Non-ISI Meta-Viterbi detector (e.g., 166 of FIG. 1B) that is used in determining a preferred set of error events, in accordance with an embodiment of the invention. The Non-ISI Meta-Viterbi detector comprises the computational circuitry 208. The computational circuitry 208 determines the error events eε and Φ(e)=π≠0, such that:




  
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As illustrated in FIG. 2, the symbol detector (e.g., slicer) 204 outputs a hard decision output, ν, into the computational circuitry 208. Additionally, the noisy codeword, ξ, is input into the symbol detector 204 and the computational circuitry 208. The computational circuitry 208 determines the preferred error events that have the smallest event weight for each possible parity syndrome, given t parity bits or 2t states. In FIG. 2, the computational circuitry 208 may also record the parity syndrome values associated with one or more codewords. The embodiment of FIG. 2 illustrates how the computational circuitry 208 determines a preferred set of error events when a four-bit parity code is used for each codeword. In this representative embodiment, there is a preferred error event associated with each of the 15 possible syndromes within a codeword. The preferred error events are considered “locally minimized”, since their associated event weight is a minimum value for the associated parity syndrome. Each of the preferred error events comprises an error event step in a trellis diagram. Overall, the various aspects of the present invention may be applied to codewords comprising one or more parity bits. FIG. 2 provides a representative embodiment illustrating the use of a Meta-Viterbi algorithm using codewords having an exemplary four bits of parity.

The preferred set of error events for the kth codeword may be denoted by the following equation:




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The events in H may be ordered in sequence based on the parity syndromes they produce and may be represented by the following equation:

H={e1,e2,e3, . . . ,e2t−1},

where Φ(e1)=(0 . . . 001)ε{0,1}t, Φ(e2)=(0 . . . 0101), Φ(e3)=(0 . . . 011), etc.

The event weights associated with each preferred error event may be ordered according to the parity syndromes produced as follows:

{w(e1),w(e2), . . . ,w(e2t−1)}.

The Meta-Viterbi Algorithm, as executed by the Non-ISI Meta-Viterbi detector, charts various subsets of each of the preferred sets of error events by way of a Meta-Viterbi trellis diagram. As may be visualized using the Meta-Viterbi trellis diagram, every subset of Hk corresponds to a path through the Meta-Viterbi trellis.

FIG. 3A is a table illustrating the computation of cumulative parity and cumulative weight of a subset of error events (subset of H={e1, e2, . . . , e15}) associated with a four-bit parity codeword, in accordance with an embodiment of the invention. The subset of error events comprises {e3, e7, e10, e15}. The exemplary path shown in FIG. 3A corresponds to a sequence of error event steps—“no e1”, “no e2”, “e3”, “no e4”, “no e5”, etc. The Meta-Viterbi path taken corresponds to a series of error event decisions made at each step of the sequence. The second row of the table provides the event parity associated with the error event that is taken. The third row of the table provides the event weight associated with the error event that is taken. The fourth row provides the cumulative parity at each step of the trellis path based on the error events taken. The fifth row provides the cumulative event weight at each step of the 16 state Meta-Viterbi trellis diagram. The Meta-Viterbi trellis comprises 2t states and in this embodiment, t=4. Each event parity corresponds to an associated event weight. By way of using the Meta-Viterbi trellis, the path that provides the smallest cumulative event weight for a codeword is chosen given the codeword's parity syndrome. This path corresponds to an optimal set of error events that corrects the output provided by the symbol detector (e.g., slicer).
FIG. 3B is a diagram illustrating the 16 state Meta-Viterbi trellis path taken when the error events chosen correspond to {e3, e7, e10, e15}, as described in relation to FIG. 3A, in accordance with an embodiment of the invention. Alternatively, the sequence of event choice steps which forms a path through the trellis may be indicated as follows: “No e1, No e2, e3, No e4, No e5, No e6, e7, No e8, No e9, e10, No e11, No e12, No e13, No e14, e15”. The path corresponds to the cumulative parity as displayed by the fourth row of the table illustrated in FIG. 3A. The path shown is only one representative embodiment of a path taken through the 16 state Meta-Viterbi trellis. As illustrated, the path ends with a cumulative parity equal to “0001”. The path through the Meta-Viterbi trellis determines the set of error events that may be used to correct the received codeword generated by the symbol detector. The path taken comprises a path ending with a cumulative parity corresponding to the syndrome of the codeword.
FIG. 4 illustrates a diagram of a Meta-Viterbi trellis diagram in accordance with an embodiment of the invention. As shown, step=0 is the starting point for all paths of a four-bit parity codeword. The various states (or cumulative parity) and associated event weights (or path metrics) are listed for the three steps illustrated in FIG. 4. The following three steps list the states, path memory, and path metric associated with each step of a codeword of a received sequence of codewords, for a 16 state Non-ISI Meta-Viterbi detector:
Step 0:
State (0000): path memory={ }, path metric=0
Other 15 states (0001) through (1111) are invalid
Step 1:
State (0000): path memory={ }, path metric=0
State (0001): path memory={e1}, path metric=w(e1)
Other 14 states are invalid
Step 2:
State (0000): path memory={ }, path metric=0
State (0001): path memory={e1}, path metric=w(e1)
State (0010): path memory={e2}, path metric=w(e2)
State (0011): path memory={e1, e2}, path metric=w(e1)+w(e2)
Other 12 states are invalid
As we progress through the steps, all 16 states become valid and we start performing ACS operations in a similar fashion as may be performed using the Viterbi Algorithm. The ACS operations allow elimination of “non-survivor” paths when determining the path having the least cumulative event weight.
FIG. 5 is a diagram illustrating the selection of a path having lowest cumulative event weight, when two paths merge in a Meta-Viterbi trellis, in accordance with an embodiment of the invention. As may be seen, the cumulative parity is the same for the two paths (1110). However, their associated cumulative weights may differ. For the first path, the cumulative weight is equal to w(e3)+w(e7)+w(e10) while in the second path, the cumulative weight is equal to w(e6)+w(e8). At the merge point illustrated, each respective path has undergone a sequence of different error events. In one instance, the path comprises the error events {e3, e7, e10} while in the other instance, the path comprises the error events {e6, e8}. However, at the end of the path, the two paths meet with the same cumulative parity. The Non-ISI Meta-Viterbi detector performs an add, compare, and select (ACS) operation similar to that performed by the Viterbi Algorithm. This process allows elimination of “non-survivor” paths when determining the path with the lowest path metric or lowest cumulative event weight. The Non-ISI Meta-Viterbi detector may utilize the following pseudo-language sequence of steps which may be used to implement a state machine for performing the Meta-Viterbi Algorithm when constructing a trellis within a codeword:












Meta Viterbi algorithm for: State=r (Step=j)


The predecessor states are









State=r1 (Step=j−1)



State=r2 (Step=j−1)



where r1 = r⊕Φ(ej),r2 = r ,







If neither predecessor is valid, the State=r (Step=j) is declared not valid


If only one predecessor State=r1 (Step=j−1) is valid, set










PathMemory(State=r, Step=j) = {ej} ∪ PathMemory(State=r1, Step=j−1)
(2)



PathMetric(State=r, Step=j) = w(ej) + PathMetric(State=r1, Step=j−1)
(3)







If only one predecessor State=r2 (Step=j−1) is valid, set










PathMemory(State=r, Step=j) = PathMemory(State=r2, Step=j−1)
(4)



PathMetric(State=r, Step=j) = PathMetric(State=r2, Step=j−1)
(5)







If both predecessors are valid perform, compare:









w(ej) + PathMetric(State=r1, Step=j−1) vs. PathMetric(State=r2, Step=j−1)



If the left-hand-side is smaller, perform (2) and (3), otherwise perform







(4) and (5).









As indicated in the pseudo-language above, the Meta-Viterbi algorithm determines the sequence of error events by using the PathMemory variable. The Meta-Viterbi algorithm determines the path metric or cumulative event weight by using the PathMetric variable. When the paths merge, the Meta-Viterbi algorithm performs a comparison between the two path metrics associated with the two paths. It determines the path metric that has the smaller value and subsequently stores the associated sequence of error events and path metric. Since we need to enforce the parity of the codeword, at Step=2t−1 only State=π is valid.

FIG. 6 is a functional block diagram of a Non-ISI Meta-Viterbi detector 604 in accordance with an embodiment of the invention. The Non-ISI Meta-Viterbi detector 604 comprises an event weight processor 608, a computational circuitry 612, a parity syndrome calculator 616, and an error correction circuitry 620. The event weight processor 608 is capable of computing one or more event weights, w(e), of a trellis. As mentioned earlier, the event weight may be computed using the following equation:
w(e)=log P(ξ|ν)−log P(ξ|ν+e). Further, the soft decision output may be expressed as follows:

log P(ξi|νi)−log P(ξi| νi), for i=1, . . . , χ,

in which νi denotes the complement of the bit νi. This equation may be further simplified when the noise introduced by the channel is AWGN. In the case of additive white Gaussian noise (AWGN), this soft decision output is equal to −(ξi−νi)2+(ξi− νi)2. The computational circuitry 612 is capable of computing one or more parameters associated with a Meta-Viterbi trellis. The symbol detector (e.g., slicer) provides hard decision information which is used by the event weight processor 608. The symbol detector also provides the hard decision information used by the parity syndrome calculator 616. The event weight processor 608 uses as inputs, the hard decision output provided by the symbol detector and the one or more noisy received codewords, ξ. The computational circuitry 612 determines the error events that have the smallest event weights for each parity syndrome of a particular received codeword. The parity syndrome calculator 616 computes the parity syndrome values associated with the one or more received codewords. The parity syndrome calculator 616 processes the output provided by the symbol detector and outputs the parity syndrome values to the computational circuitry 612. As illustrated, the computational circuitry 612 receives event weights computed by the event weight processor 608 and the values calculated by the parity syndrome calculator 616. The computational circuitry 612 may determine one or more optimal paths taken using a trellis diagram. One of the one or more optimal paths corresponds to a path having minimum cumulative event weight. The computational circuitry 612 may compute the cumulative parity of the sequence of error events. The computational circuitry 612 may perform one or more ACS operations when determining one or more cumulative event weights of one or more paths in the trellis diagram. The computational circuitry 612 may compute one or more event weights associated with one or more error events of a codeword. Additionally, the computational circuitry 612 may compute one or more cumulative event weights associated with one or more codewords. The error correction circuitry 620 corrects the one or more received codewords by determining the appropriate set of error events to add to the one or more received codewords. The error correction circuitry 620 may utilize the set of error events associated with the optimal path having a minimum cumulative event weight. The event weight processor 608, computational circuitry 612, parity syndrome calculator 616, and error correction circuitry 620 may comprise any type of digital logic circuitry used to implement an appropriate state-machine.

While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

## Claims

1. A method of detecting and correcting data bit errors in one or more received codewords transmitted through a communication channel comprising:
receiving a codeword generated from a block encoder, said codeword affected by noise introduced by said communication channel;
first processing said codeword using a symbol detector;
generating a hard decision output from said symbol detector; and
second processing said hard decision output with said codeword to generate one or more event weights, said one or more event weights used to generate a soft decision output, said hard decision output and said soft decision output used to generate a corrected codeword.

2. The method of claim 1 wherein each of said one or more event weights comprises a soft decision output, w(e), wherein


w(e)=P(ζi|vi)−log P(ζi|vi), for i=1, . . . , χ.

3. The method of claim 1 wherein a linear operator, Φ:{0,1}χ→(0,1)t, computes a parity syndrome value of said hard decision output such that Φ(E):Φ(e1)⊕Φ(e2)⊕ . . . ⊕Φ(en)=π, wherein a sum of said one or more event weights has a minimum value.

4. The method of claim 1 wherein one or more preferred error events are determined for said received codeword such that the following conditions apply:


eεE, and Φ(e)=π≠0, and






  
    e
    =
    
      arg
      ⁢
      
        
      
      ⁢
      
        
          min
          
            x
            ∈
            Ω
          
        
        ⁢
        
          w
          ⁡
          
            (
            x
            )
          
        
      
    
  
  ,




where


Ω={xεG*(v),Φ(x)=π}.

5. The method of claim 1 wherein said second processing comprises: determining a path in a trellis diagram associated with a minimum cumulative event weight using said one or more event weights; and correcting said received codeword using a cumulative parity associated with said path.

6. A method of correcting one or more data bit errors in a received codeword of a communications channel, said method comprising:
determining one or more error events,





  
    e
    =
    
      arg
      ⁢
      
        
      
      ⁢
      
        
          min
          
            x
            ∈
            Ω
          
        
        ⁢
        
          w
          ⁡
          
            (
            x
            )
          
        
      
    
  
  ,




where Ω={xεG*(v),Φ(x)=π} of said received codeword wherein




  v
  =
  
    
      
        
          
            arg
            ⁢
            
              
            
            ⁢
            max
          
          ⁢
          
            
          
        
        
          x
          ∈
          
            
              {
              
                0
                ,
                1
              
              }
            
            χ
          
        
      
      ⁢
      
        
      
      ⁢
      
        w
        ⁡
        
          (
          x
          )
        
      
      ⁢
      
        
      
      ⁢
      log
      ⁢
      
        
      
      ⁢
      
        P
        ⁡
        
          (
          
            ζ
            |
            x
          
          )
        
      
    
    =
    
      
        
          arg
          ⁢
          
            
          
          ⁢
          max
        
        
          x
          ∈
          
            
              {
              
                0
                ,
                1
              
              }
            
            χ
          
        
      
      ⁢
      
        
          ∑
          
            i
            =
            1
          
        
        ⁢
        
          log
          ⁢
          
            
          
          ⁢
          
            P
            ⁡
            
              (
              
                
                  ζ
                  i
                
                |
                
                  x
                  i
                
              
              )
            
          
        
      
    
  




and ζ represents a sequence of noisy received codewords, said one or more error events used to correct said one or more data bit errors using a linear operator that computes one or more parity syndromes of said one or more error events, said linear operator operating on said one or more error events such that Φ(E):Φ(e1)⊕Φ(e2)⊕ . . . ⊕Φ(en)=π;
determining one or more preferred error events associated with said one or more parity syndromes; using said one or more preferred error events to construct a trellis diagram; and selecting a path of said trellis diagram associated with a minimum cumulative event weight.

7. The method of claim 6 wherein said minimum cumulative event weight is equal to the sum of the event weights associated with said path of said trellis diagram, said minimum cumulative event weight defined by the following equation:




  
    w
    ⁡
    
      (
            )
    
  
  :=
  
    
      ∑
      
        e
        ∈
              
    
    ⁢
    
      
        w
        ⁡
        
          (
          e
          )
        
      
      .

8. The method of claim 6 wherein each of said one or more preferred error events corresponds to a parity syndrome whose event weight has minimum value.

9. The method of claim 6 wherein said minimum cumulative event weight is used to correct said received codeword.

10. The method of claim 6 wherein said communications channel incorporates noise that is independent, identically distributed, additive white Gaussian.

11. A system for detecting and correcting data bit errors in one or more received codewords transmitted through a communication channel comprising:
a first detector that processes said one or more received codewords; and
a second detector that processes said one or more received codewords processed by said first detector, said second detector used for computing parity syndromes, associated event weights, and cumulative event weights, and for performing add, compare, and select operations, said second detector generating a preferred set of error events associated with a parity syndrome, said preferred set of error events associated with a minimum cumulative event weight.

12. The system of claim 11 wherein said preferred error events is given by




  H
  =
  
    
      {
      
        
          
            e
            π
          
          ⁢
          
            
          
          ⁢
          for
          ⁢
          
            
          
          ⁢
          
            ∀
            
              π
              ∈
              
                
                  {
                  
                    0
                    ,
                    1
                  
                  }
                
                t
              
            
          
        
        ,
        
          
            
              π
              ≠
              0
            
            |
            
              e
              π
            
          
          =
          
            arg
            ⁢
            
              
            
            ⁢
            
              
                min
                
                  x
                  ∈
                  Ω
                
              
              ⁢
              
                w
                ⁡
                
                  (
                  x
                  )
                
              
            
          
        
        ,
        
          Ω
          =
          
            {
            
              
                x
                ∈
                
                  G
                  *
                  
                    (
                    v
                    )
                  
                
              
              ,
              
                
                  Φ
                  ⁡
                  
                    (
                    x
                    )
                  
                
                =
                π
              
            
            }
          
        
      
      }
    
    .

13. The system of claim 11 wherein said first detector comprises a symbol detector.

14. The system of claim 11 wherein said second detector performs χ+2t2t add, compare, and select operations.

15. The system of claim 11 wherein said second detector comprises: an event weight processor for computing said associated event weights; a computational circuitry for performing said add, compare, and select operations, and for computing said minimum cumulative event weight; a parity syndrome calculator for computing said parity syndromes; and an error correction circuitry used to correct said data bit errors in said one or more received codewords.

16. The system of claim 15 wherein said event weight processor, computational circuitry, parity syndrome calculator, and error correction circuitry are implemented using digital logic circuitry.

17. A system comprising:
one or more circuits operable for, at least:
determining one or more error events of said received codeword, said one or more error events used to correct data bit errors of said received codeword using a linear operator that computes a parity syndrome based on said one or more error events, said linear operator operating on said one or more error events;
determining one or more preferred error events associated with said parity syndrome, said one or more circuits using said one or more preferred error events to construct a trellis diagram;
selecting a path of said trellis diagram associated with a minimum cumulative event weight; and
using said parity syndrome associated with said minimum cumulative event weight to correct said received codeword.

18. The system of claim 17 wherein said minimum cumulative event weight is equal to the sum of the event weights associated with said path of said trellis diagram.

19. The system of claim 17 wherein said received codeword comprises noise that is independent, identically distributed, additive white Gaussian.