# Patent

## Title
Display device and driving method thereof

## Abstract

In an organic light emitting diode display, a plurality of sub-pixels sharing a select scan line that extends in a row direction forms a unit pixel, and the plurality of sub-pixels are arranged in a column direction in the unit pixel. A field is divided into a plurality of subfields, and corresponding one of the plurality of sub-pixels emits light in each of the plurality of subfields.

## Background
CROSS REFERENCE TO RELATED APPLICATION
This divisional patent application claims priority to and the benefit of U.S. application Ser. No. 11/312,016, filed Dec. 19, 2005, now U.S. Pat. No. 7,847,756 which claims priority to and the benefit of Korean Patent Application No. 10-2005-0000759 filed on Jan. 5, 2005 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display device and a driving method thereof, and more particularly, to an organic light emitting diode (OLED) display device and a driving method thereof.
2. Description of the Related Art
In general, the organic light emitting diode display device is a display device for electrically exciting phosphorous organic matter and emitting light. The organic light emitting diode display device drives organic light emission cells arranged in a matrix format to represent images. An organic light emission cell having a diode characteristic is referred to as an organic light emitting diode (OLED) and has a structure including an anode electrode layer, an organic thin film, and a cathode electrode layer. Holes and electrons injected through the anode electrode and the cathode electrode are combined on the organic thin film, and emit light. The organic light emission cell emits different amounts of light according to injected amounts of electrons and holes, that is, depending on the applied current.
In a display device such as the organic light emitting diode display device, a pixel includes a plurality of sub-pixels each of which has one of a plurality of colors (e.g., primary colors of light), and colors are represented through combinations of the colors emitted by the sub-pixels. In general, a pixel includes a sub-pixel for displaying red (R), a sub-pixel for displaying green (G), and a sub-pixel for displaying blue (B), and the colors are displayed by combinations of red, green, and blue (RGB) colors. Generally, the sub-pixels are arranged in an order of R, G, and B along a row direction.
Each sub-pixel in the organic light emitting diode display device includes a driving transistor for driving the organic light emitting diode, a switching transistor, and a capacitor. Also, each sub-pixel has a data line for transmitting (or applying) a data signal, and a power line for transmitting (or applying) a power supply voltage. Therefore, many wires are required for transmitting (or applying) voltages or signals to the transistors and capacitors formed at each pixel. It is difficult to arrange such wires in the pixel, and the aperture ratio corresponding to a light emission area of the pixel is reduced.
SUMMARY OF THE INVENTION
One exemplary embodiment of the present invention provides a display device for improving an aperture ratio.
Another exemplary embodiment of the present invention provides a display device for simplifying the arrangement of wires and elements in unit pixels.
Still another exemplary embodiment of the present invention provides a display device for reducing a number of select scan lines.
Further, another exemplary embodiment of the present invention provides a scan driver for reducing a number of flip-flops.
In one aspect of the present invention, a display device including a plurality of unit pixels, a plurality of data lines, a plurality of select scan lines, a plurality of emit scan lines, and a scan driver is provided. A field is divided into a plurality of subfields. The plurality of unit pixels are arranged in rows and display an image during the field. Each of the unit pixels includes a plurality of light emitting elements arranged in a column direction. The plurality of data lines extend in the column direction, and transmit data signals. The plurality of select scan lines extend in a row direction and transmit select signals, and each of the select scan lines is coupled to a corresponding one of the rows of the unit pixels. The plurality of emit scan lines transmit emission control signals, and each of the emit scan lines is coupled to a corresponding one of the rows of the unit pixels. The scan driver applies the select signals to the select scan lines, and applies the emission control signals to the emit scan lines, in each of the plurality of subfields. At least one of the unit pixels uses a corresponding one of the data signals in response to a first signal of a corresponding one of the select signals, and each of the plurality of light emitting elements of the at least one of the unit pixels emits light in response to an emit signal of a corresponding one of the emission control signals in a corresponding one of the subfields.
In another aspect of the present invention, a display device including a plurality of unit pixels, a plurality of data lines, a plurality of select scan lines, a plurality of emit scan lines, a first scan driver, and a second scan driver is provided. A field is divided into a plurality of subfields. The plurality of unit pixels are arranged in rows and display an image during the field. Each of the unit pixels includes a plurality of light emitting elements arranged in a column direction. The plurality of data lines extend in the column direction and transmit data signals. The plurality of select scan lines extend in a row direction and transmit select signals, and each of the select scan lines is coupled to a corresponding one of the rows of the unit pixels. The plurality of emit scan lines transmit emission control signals, and each of the emit scan lines is coupled to a corresponding one of the rows of the unit pixels. The first scan driver applies the select signals to the select scan lines of a first row group from among the rows of the unit pixels and applies the emission control signals to the emit scan lines of the first row group, in each of the plurality of subfields. The second scan driver applies the select signals to the select scan lines of a second row group from among the rows of the unit pixels and applies the emission control signals to the emit scan lines of the second row group, in each of the plurality of subfields. At least one of the unit pixels uses a corresponding one of the data signals in response to a first signal of a corresponding one of the select signals, and each of the plurality of light emitting elements of the at least one of the unit pixels emits light in response to an emit signal of a corresponding one of the emission control signals in a corresponding one of the subfields.
In still another aspect of the present invention, a pixel circuit driving method of a display device is provided. The display device includes a plurality of data lines that extend in a first direction and transmitting data signals, a plurality of select scan lines that extend in a second direction and transmitting select signals, and a plurality of unit pixels. Each of the unit pixels includes a plurality of sub-pixels. At least one of the select signals is applied to a corresponding one of the plurality of select scan lines in a first subfield of a field, and at least one of the data signals is applied to at least one of the plurality of data lines. A first emission control signal is applied to at least one of the unit pixels to which a corresponding one of the select signals and a corresponding one of the data signals are applied, so that a first sub-pixel of the plurality of sub-pixels emits light. At least one of the select signals is applied to a corresponding one of the plurality of select scan lines in a second subfield of the field, and at least one of the data signals is applied to at least one of the plurality of data lines. A second emission control signal is applied to at least one of the unit pixels to which a corresponding one of the select signals and a corresponding one of the data signals are applied so that a second sub-pixel of the plurality of sub-pixels emits light, and the first and second sub-pixels are arranged in the first direction.
In a further aspect of the present invention, a display device including a display area, a first driver, and a second driver is provided. The display area includes a plurality of data lines that extend in a first direction, a plurality of select scan lines that extend in a second direction, and a plurality of unit pixels. Each of the unit pixels includes a plurality of sub-pixels arranged in the first direction. The first driver sequentially transmits select signals to the plurality of select scan lines in each of a plurality of subfields that form a field, and transmits emission control signals to corresponding at least one of the plurality of sub-pixels in each of the plurality of subfields to emit light in the corresponding at least one of the plurality of sub-pixels. The second driver transmits a data signal to at least one of the data lines of the unit pixels coupled to a corresponding one of the select scan lines to which one of the select signals is applied. The first driver generates the emission control signals respectively corresponding to the plurality of subfields using a first shift signal.



BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the invention, wherein:
FIG. 1 shows a plan view of an organic light emitting diode display device according to a first exemplary embodiment of the present invention;
FIG. 2 shows a simplified circuit diagram of unit pixels of the organic light emitting diode display device shown in FIG. 1;
FIG. 3 shows a signal timing diagram of the organic light emitting display device according to the first exemplary embodiment of the present invention;
FIGS. 4 to 6 respectively show simplified circuit diagrams of unit pixels of organic light emitting diode display devices according to second to fourth exemplary embodiments of the present invention;
FIG. 7 shows a signal timing diagram in the unit pixel of FIG. 6;
FIGS. 8, 11, 13, 15, 17, 19, 21, 23, 24, 26 and 27 respectively show scan drivers in organic light emitting diode display devices according to fifth to fifteenth exemplary embodiments;
FIGS. 9, 12, 14, 16, 18, 20, 22, 25, 28 respectively show signal timing diagrams in the scan drivers of FIGS. 8, 11, 13, 15, 17, 19, 21, 24, 26;
FIG. 10 shows a flip-flop used in a select scan driver of FIG. 8;
FIG. 29 shows a plan view of an organic light emitting diode display device according to a sixteenth exemplary embodiment of the present invention;
FIGS. 30A and 30B respectively show odd row and even row scan drivers in the organic light emitting diode display device according to the sixteenth exemplary embodiment; and
FIG. 31 shows a signal timing diagram of the odd row scan driver of FIG. 30A.



DETAILED DESCRIPTION
In the following detailed description, only certain exemplary embodiments of the present invention are shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
Accordingly, the drawings and description are to be regarded as illustrative in nature, and not restrictive. There may be parts shown in the drawings, or parts not shown in the drawings, that are not discussed in the specification as they are not essential to a complete understanding of the invention. Like reference numerals designate like elements. Phrases such as “one thing is coupled to another” can refer to either “a first one is directly coupled to a second one” or “the first one is coupled to the second one with a third one provided therebetween”.
A display device and a driving method thereof according to exemplary embodiments of the present invention will be described in detail with reference to the drawings, and an organic light emitting diode display device using an organic light emitting diode as a light emitting element will be exemplified and described in the exemplary embodiments.
FIG. 1 shows a plan view of an organic light emitting diode display device according to a first exemplary embodiment of the present invention.
As shown in FIG. 1, the organic light emitting diode display device includes a display area 100 seen as a screen to a user, a scan driver 200, and a data driver 300.
The display area 100 includes a plurality of data lines D1 to Dm, a plurality of select scan lines S1 to Sn, a plurality of emit scan lines Em11 to Em1n and Em21 to Em2n, and a plurality of unit pixels 110. Each unit pixel 110 includes two sub-pixels 111 and 112 which are arranged in a column direction. The data lines D1 to Dm are extended in a column direction and transmit data signals representing images to the corresponding unit pixels. The select scan lines S1 to Sn are extended in a row direction and transmit select signals for selecting corresponding lines to the select scan lines S1 to Sn in order to apply data signals to the unit pixels of the corresponding lines. The emit scan lines Em11 to Em1n and Em21 to Em2n are extended in a row direction and transmit emission control signals for controlling light emission of the respective sub-pixels 111 or 112 to the corresponding unit pixels 110. The unit pixel 110 is defined in an area where the select scan lines S1 to Sn and the data lines D1 to Dm are crossed. The scan lines S1 to Sn are coupled to the sub-pixels 111 and 112 in the respective unit pixels 110.
One field is divided into two subfields, and the scan driver 200 sequentially transmits select signals to the select scan lines S1 to Sn in the respective subfields. The scan driver 200 sequentially transmits emission control signals for controlling light emission of the sub-pixels 111 to the emit scan lines Em11 to Em1n in one subfield, and sequentially transmits emission control signals for controlling light emission of the sub-pixels 112 to the emit scan lines Em21 to Em2n in the other subfield. The data driver 300 applies data signals corresponding to the pixels of lines to which select signals are applied to the data lines D1 to Dm each time the select signals are sequentially applied. In addition, the data driver 300 applies data signals corresponding to the sub-pixels 111 in the one subfield, and applies data signals corresponding to the sub-pixels 112 in the other subfield.
The scan driver 200 and the data driver 300 are coupled to a substrate in which the display area 100 is formed. Alternatively, the scan driver 200 and/or the data driver 300 may be installed directly on the substrate, and they may be substituted with a driving circuit which is formed on the same layer on the substrate as the layer on which scan lines, data lines, and transistors are formed. Alternatively, the scan driver 200 and/or the data driver 300 may be installed in a chip format on a tape carrier package (TCP), a flexible printed circuit (FPC), or a tape automatic bonding unit (TAB) coupled to the substrate.
FIG. 2 shows a simplified circuit diagram of the unit pixels of the organic light emitting diode display device shown in FIG. 1. The three unit pixels 110ij, 110i(j+1), and 110i(j+2) coupled to the scan line Si of the ith row (where ‘i’ is a positive integer less than or equal to ‘n’) and the data lines Dj to Dj+2 of the ith to (j+2)th columns (where ‘j’ is a positive integer less than or equal to ‘m−2’) will be exemplified in FIG. 2. It is assumed that the sub-pixels are arranged in an order of R, G, and B along the row direction, and the same color sub-pixels are arranged along the column direction in FIG. 2.
As shown in FIG. 2, the two sub-pixels 111 and 112 of the one unit pixel 100 are coupled to one of the select scan lines S1 to Sn in common and have a pixel driver 115 in common, and the pixel driver 115 includes a driving transistor M1, a switching transistor M2, and a capacitor C1.
In more detail, the unit pixel 110ij coupled to the ith select scan line Si and the jth data line Dj includes the pixel driver 115, a switching unit, and two organic light emitting diodes OLEDR1 and OLEDR2 that emit red light. The switching unit includes two emission control transistors M3a and M3b to selectively transmit a driving current from the pixel driver 115 to the two organic light emitting diodes OLEDR1 and OLEDR2. In addition, the sub-pixels 111ij and 112ij respectively include the two organic light emitting diodes OLEDR1 and OLEDR2 in the unit pixel 110ij.
The unit pixel 110i(j+1) coupled to the ith select scan line Si and the (j+1)th data line Dj+1, and the unit pixel 110i(j+2) coupled to the ith select scan line Si and the (j+2)th data line Dj+2 have the same structures as the unit pixel 110ij. In addition, the sub-pixels 111i(j+1) and 112i(j+1) respectively include two organic light emitting diodes OLEDG1 and OLEDG2 that emit green light in the unit pixel 110i(j+1), and the sub-pixels 111i(j+2) and 112i(j+2) respectively include two organic light emitting diodes OLEDB1 and OLEDB2 that emit blue light in the unit pixel 110i(j+2).
In the unit pixel 110ij, the driving transistor M1 has a source coupled to a power line for supplying a power supply voltage VDD, and a gate coupled to a drain of the switching transistor M2. The capacitor C1 is coupled between the source and the gate of the driving transistor M1. The switching transistor M2 having a gate coupled to the select scan line Si and a source coupled to the data line Dj, transmits (or applies) the data signal converted to analog voltage (hereinafter, “data voltage”) provided by the data line Dj in response to the select signal provided by the select scan line Si. The driving transistor M1 has a drain coupled to sources of the emission control transistors M3a and M3b, and gates of the emission control transistors M3a and M3b are coupled to the emit scan lines Em1i and Em2i, respectively. Drains of the emission control transistors M3a and M3b are coupled, respectively, to anodes of the organic light emitting diodes OLEDR1 and OLEDR2, and a power supply voltage VSS is applied to cathodes of the organic light emitting diodes OLEDR1 and OLEDR2. The power supply voltage VSS in the first exemplary embodiment is lower than the voltage VDD, and can be a negative voltage or a ground voltage. As shown in FIG. 2, the unit pixels 110i(j+1) and 110i(j+2) have the same connecting structure as the unit pixel 110ij.
In the unit pixel 110ij, the one emit scan line Em1i of the emit scan lines Em1i and Em2i is coupled to the gates of the transistors M3a respectively coupled to the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1, and the other emit scan line Em2i is coupled to the gates of the transistors M3b respectively coupled to the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2.
A low-level emission control signal is applied to the emit scan line Em1i in one subfield of two subfields forming a field, and therefore, the transistor M3a is turned on. Then, a current IOLED as expressed in Equation 1 flows from the transistor M1 to the organic light emitting diode so that the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 emit light corresponding to the magnitude of the current IOLED. A low-level emission control signal is applied to the emit scan line Em2i in the other subfield, and therefore, the transistor M3b is turned on. Then, a current IOLED flows from the transistor M1 to the organic light emitting diode so that the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 emit light.




  
    
      
        
          I
          OLED
        
        =
        
          
            β
            2
          
          ⁢
          
            
              (
              
                
                  
                  
                    V
                    SG
                  
                  
                
                -
                
                  
                  
                    V
                    TH
                  
                  
                
              
              )
            
            2
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
        ⁢
        1
      
    
  




where β is a constant determined by a channel width and a channel length of the transistor M1, VSG is a voltage between the source and the gate of the transistor M1, and VTH is a threshold voltage of the transistor M1.

Referring to FIG. 2, an upper line L1 is formed by the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1, and a lower line L2 is formed by the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2. The organic light emitting diodes of the upper line L1 start emitting light in one subfield of the fields, and the organic light emitting diodes of the lower line L2 start emitting light in the other subfield of the fields.
A driving method of the organic light emitting diode display device according to the first exemplary embodiment of the present invention will be described in detail with reference to FIG. 3. In FIG. 3, the select signal applied to the select scan line Si is depicted as ‘select[i]’, and the emission control signals applied to the emit scan lines Em1i and Em2i are depicted as ‘emit1[i]’ and ‘emit2[i]’, respectively.
As shown in FIG. 3, one field includes two subfields 1F and 2F, and low-level select signals are sequentially applied to the select scan lines S1 to Sn in each subfield 1F or 2F. The two organic light emitting diodes of the unit pixel that share the select scan line emit light during periods corresponding to subfields 1F and 2F, respectively. In FIG. 3, widths of low-level signals (e.g., pulses) of the emission control signals emit1[i] and emit2[i] are the same as periods corresponding to the subfields 1F and 2F, respectively.
In the first subfield 1F, when a low-level select signal select[1] is applied to the select scan line S1 on the first row, data voltages corresponding to the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 of the unit pixels on the first row are applied to the corresponding data lines D1-Dm. A low-level emission control signal emit1[1] is applied to the emit scan line Em11 on the first row, and the emission control transistors M3a of the unit pixels on the first row are turned on. Then, currents corresponding to the data voltages are transmitted to the corresponding organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 from the driving transistors M1 to thus emit light in the upper line L1 on the first row. The light is emitted during the period in which the emission control signal emit1[1] is low-level.
Next, when a low-level select signal select[2] is applied to the select scan line S2 on the second row, data voltages corresponding to the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 of the unit pixels on the second row are applied to the corresponding data lines D1-Dm. A low-level emission control signal emit1[2] is applied to the emit scan line Em12 on the second row, and the emission control transistors M3a of the unit pixels on the second row are turned on. Then, the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 on the upper line L1 of the second row emit light in response to the low-level emission control signal emit1[2]. The light is emitted during the period in which the emission control signal emit1[2] is low-level.
In a like manner, low-level select signals select[1] to select[n] are sequentially applied to the select scan lines S1 to Sn on the first to nth rows in the first subfield 1F. When the low-level select signal select[i] is applied to the select scan line Si on the ith row, the data voltages corresponding to the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 of the unit pixels on the ith row are applied to the corresponding data line D1 to Dm, and a low-level emission control signal emit1[i] is applied to the emit scan line Em1i of the ith row. Then, the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1, which are formed on the upper line L1 of the ith row, emit light during a period corresponding to the width of the low-level emission control signal emit1[i]. 
In the second subfield 2F, a low-level select signal select[1] is applied to the select scan line S1 on the first row, and data voltages corresponding to the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 of the unit pixels on the first row are applied to the corresponding data lines D1-Dm. A low-level emission control signal emit2[1] is applied to the emit scan line Em21 on the first row, and the emission control transistors M3b of the unit pixels on the first row are turned on. Then, the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 on the lower line L2 of the first row emit light during the period in which the emission control signal emit2[1] is low-level.
Next, a low-level select signal select[2] is applied to the select scan line S2 on the second row, and data voltages corresponding to the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 of the unit pixels on the second row are applied to the corresponding data lines D1-Dm. A low-level emission control signal emit2[2] is applied to the emit scan line Em22 on the second row, and the emission control transistors M3b of the unit pixels on the second row are turned on. Then, the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 on the lower line L2 of the second row emit light during the period in which the emission control signal emit2[2] is low-level.
In a like manner, low-level select signals select[1] to select[n] are sequentially applied to the select scan lines S1 to Sn on the first to nth rows in the second subfield 2F. When the low-level select signal select[i] is applied to the select scan line Si on the ith row, the data voltages corresponding to the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 of the unit pixels on the ith row are applied to the corresponding data line D1 to Dm, and a low-level emission control signal emit2[i] is applied to the emit scan line Em2i of the ith row. Then, the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2, which are formed on the lower line L2 of the ith row, emit light in during a period corresponding to the width of the low-level emission control signal emit2[i]. 
As described above, one field is divided into the two subfields, and the subfields are sequentially driven in the organic light emitting diode display device driving method according to the first exemplary embodiment. The organic light emitting diodes formed on the upper line L1 of the each row start emitting light in one subfield, and the organic light emitting diodes formed on the lower line L2 of the each row start emitting light in the other subfield. As a result, the organic light emitting diodes of all sub-pixels formed on 2n lines of n rows can emit light in the one field. In addition, the number of select scan lines and the number of pixel drivers (e.g., the transistors and the capacitors) can be reduced since the two sub-pixels share the select scan line and the pixel driver. As a result, the number of integrated circuits for driving the select scan lines can be reduced, and the elements can be easily arranged in the unit pixel.
Further, the scan driver and the data driver of the interlace scan method may be applicable to those according to the first exemplary embodiment of the present invention because the lower lines L2 are scanned after the upper lines L1 are scanned in the first exemplary embodiment. In addition, the single scan method is applicable to the organic light emitting diode display device in FIG. 3, but the dual scan method may also be applicable to the organic light emitting diode display device according to the first exemplary embodiment by using two scan drivers. Further, another scan method, in which the select scan signals are selectively applied to the plurality of select scan lines, may also be applicable to the organic light emitting diode display device according to the first exemplary embodiment.
Referring back to FIGS. 1 and 2, in the first exemplary embodiment, one sub-pixel 111ij (including the organic light emitting diode OLEDR1) of the unit pixel 110ij is arranged on the upper side of the select scan line Si, and the other sub-pixel 112ij (including the organic light emitting diode OLEDR2) of the unit pixel 110ij is arranged on the lower side of the select scan line Si. Alternatively, as shown in FIG. 4, the two sub-pixels 111ij and 112ij may be arranged on the lower side (or the upper side) of the select scan line Si.
FIG. 4 shows a simplified circuit diagram of unit pixels 110ij′, 110i(j+1)′ and 110i(j+2)′ of an organic light emitting diode display device according to a second exemplary embodiment of the present invention.
As shown in FIG. 4, the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 are arranged below the pixel driver 115 to form the upper line L1′, and the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 are arranged below the upper line L1′ to form the lower line L2′.
However, when the organic light emitting diodes are arranged as shown in FIG. 4, length of a wire for transmitting current from the pixel driver 115 to the organic light emitting diode OLEDR2, OLEDG2 or OLEDB2 is longer than length of a wire for transmitting current from the pixel driver 115 to the organic light emitting diode OLEDR1, OLEDG1 or OLEDB1. Then, the brightness of the upper line L1′ may be different from the brightness of the lower line L2′ by parasitic components present in the wire.
The transistors M1, M2, M3a, and M3b are depicted as PMOS transistors in FIGS. 2 and 4, but another conductive type of transistors may be applicable to the transistors M1, M2, M3a, and M3b. 
In addition, while the two emission control transistors M3a and M3b are respectively controlled by the two emit scan lines Em1i and Em2i in the first and second exemplary embodiments, emission control transistors in other embodiments may be controlled by one emit scan line as shown in FIG. 5.
FIG. 5 shows a simplified circuit diagram of unit pixels 110ij′′, 110i(j+1)′′ and 110i(j+2)′′ of an organic light emitting diode display device according to a third exemplary embodiment of the present invention.
As shown in FIG. 5, the unit pixel 110ij′′ according to the third exemplary embodiment has the same structure as that according to the first exemplary embodiment, except for emission control transistors M3a′ and M3b′ and an emit scan line Emi.
In more detail, an emission control transistor M3a′ has the opposite conductive type to an emission control transistor M3b′, and the emit scan line Emi on ith row is coupled to gates of the two emission control transistors M3a′ and M3b′. In FIG. 5, the emission control transistors M3a′ respectively coupled to the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 of the upper line L1 are depicted as PMOS transistors, and the emission control transistors M3b′ coupled to the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 of the lower line L2 are depicted as NMOS transistors. In addition, an emission control signal applied to the emit scan line Emi has the same signal timing as the emission control signal emit1[i] shown in FIG. 3.
Then, emission timings of the organic light emitting diodes OLEDR1, OLEDG1 and OLEDB1 coupled to the transistors M3a′, which have the same conductive type as the transistors M3a shown in FIG. 2, are the same as those of the first exemplary embodiment. Referring to FIG. 3, since the emission control signal emit2[i] has an inverted waveform of the emission control signal emit1[i], and the transistor M3b′ has the opposite conductive type to the transistor M3b shown in FIG. 2, emission timings of the organic light emitting diodes OLEDR2, OLEDG2 and OLEDB2 coupled to the transistors M3b′ are the same as those of the first exemplary embodiment.
As a result, the number of the emit scan lines Emi according to the third exemplary embodiment can be reduced as compared with those according to the first and second exemplary embodiments.
The two sub-pixels share the select scan line in the first to third exemplary embodiments, but three or more sub-pixels may share the select scan line in other embodiments. Assuming that three sub-pixels (respectively including three organic light emitting diodes) arranged in a column direction share a select scan line, three emission control transistors are coupled to the three organic light emitting diodes, respectively. The three emit scan lines may be respectively coupled to gates of the three emission control transistors, and may respectively transmit (or apply) emission control signals for controlling the three emission control transistors. In addition, one field may be divided into three subfields, and the three emission control transistors may be respectively turned on in the three subfields. Then, one row may be divided into the three lines, and the three lines may emit light in the three subfields, respectively.
The sub-pixels having the same color are coupled to the pixel driver 115 in the first to third exemplary embodiment, but the sub-pixels having different colors may be coupled to the pixel driver 115. For example, R organic light emitting diode may be coupled to the upper side of the pixel driver 115 in the unit pixel 110ij shown in FIG. 2, and G organic light emitting diode may be coupled to the lower side of the pixel driver 115.
However, since the R, G, and B organic light emitting diodes generally require different current ranges for representing gray levels, the driving voltages which are respectively transmitted from the driving transistors to the R, G, and B organic light emitting diodes are set to the different ranges. In order to set the different ranges, the ranges of the data voltages which are transmitted through the data lines to the driving transistors may be set to be different in R, G, and B sub-pixels, or the sizes of the driving transistors may be set to be different in the R, G, and B sub-pixels. However, if the colors represented in the sub-pixels sharing the pixel driver are different, the data voltages corresponding to the sub-pixels having the different colors are respectively transmitted to the data line in the respective subfields. Then, the data voltage of the data driver is difficult to be optimized because the data voltage range of the data driver is not optimized to the sub-pixels having the same color and is optimized to or made suitable for the sub-pixels having different colors.
On the other hand, when the sub-pixels sharing the pixel driver have the same color as shown in FIGS. 2, 4, and 5, each output of the data driver can be optimized to the data voltage corresponding to each color. Accordingly, the data voltage transmitted to the one data line can be set to the voltage range corresponding to the one color, and the desired brightness can be represented in the respective sub-pixels. As a result, a white balance can be realized in the display area.
In addition, the pixel driver using the switching and driving transistors and the capacitor is described in the first to third exemplary embodiments, but the plurality of sub-pixels may share a pixel driver which uses at least one transistor and/or at least one capacitor in addition to the switching and driving transistors to compensate variation of the threshold voltage of the driving transistor or the voltage drop. That is, since the driving current outputted from the pixel driver generally depends on the threshold voltage of the driving transistor in the unit pixel shown in FIG. 2, the driving currents may be different if the threshold voltages of the driving transistors are different. Then, the brightness between the unit pixels may be different. A unit pixel which can compensate for a variation of the threshold voltage of the driving transistor will be described with reference to FIG. 6.
FIG. 6 shows a simplified circuit diagram of a unit pixel of an organic light emitting diode display device according to a fourth exemplary embodiment of the present invention. The unit pixel coupled to the scan line Si of the ith row and the data line Dj will be exemplified in FIG. 6. When referring to the select scan lines, a scan line for transmitting a current select signal will be referred to as a “current select scan line” and a scan line which has transmitted a select signal before the current select signal is transmitted will be referred to as a “previous select scan line.”
As shown in FIG. 6, a pixel driver 115′ of the unit pixel according to the fourth exemplary embodiment further includes a threshold voltage compensator for compensating a threshold voltage of a driving transistor. Hence, the unit pixel of FIG. 6 is different from the unit pixel according to the first exemplary embodiment. The threshold voltage compensator includes two transistors M14 and M15, and a capacitor C12.
In more detail, transistors M11, M12, M13a, and M13b correspond to the transistors M1, M2, M3a, and M3b shown in FIG. 2, respectively, and capacitors C11 and C12 correspond to the capacitor C1 shown in FIG. 2. A first electrode of the capacitor C11 is coupled to a power supply voltage VDD, and a second electrode of the capacitor C11 is coupled to a first electrode of the capacitor C12. A second electrode of the capacitor C12 is coupled to a gate electrode of the driving transistor M11, and the switching transistor M12 is coupled to the first electrode of the capacitor C12. The transistor M14 is coupled between gate and drain electrodes of the transistor M11, and diode-connects the transistor M11 in response to the select signal of the previous select scan line Si−1. The transistor M15 is coupled between the power supply voltage VDD and the first electrode of the capacitor C12, and couples the first electrode of the capacitor C12 to the power supply voltage VDD in response to the select signal of the previous select scan line Si−1.
An operation of the unit pixel 115ij′ shown in FIG. 6 will be described with reference to FIG. 7. In reference to FIG. 7, a first subfield in which the organic light emitting diodes formed on the upper line L1 are emitted by turn-on of the transistors M13a will be described only. Therefore, the emission control signal, which is applied to the emit scan line Em2i and is high-level in the first subfield, is not shown in FIG. 7.
Referring to FIG. 7, the transistors M14 and M15 are turned on during a period in which the select signal select[i−1] of the previous select scan line Si−1 is low-level, and the emission control signal emit1[i]′′ of the emit scan line Em1i is high-level. Then, the transistor M11 is diode-connected while the transistor M13a and M13b are turned off, and a voltage between the gate and source electrodes of the transistor M11 becomes the threshold voltage Vth of the transistor M11. In addition, since the capacitor C12 is coupled between the gate and source electrodes of the transistor M11, a voltage at the gate electrode of the Transistor M11, i.e., the second electrode of the capacitor C12, becomes “VDD+Vth” voltage.
Next, the transistor M12 is turned on and the transistors M14 and M15 are turned off during a period in which the select signal select[i] of the current select scan line Si is low-level, and the emit control signal emit1[i]′′ is high-level. Then, since the data voltage Vdata is applied to the first electrode of the capacitor C12 through the switching transistor M12, a voltage at the second electrode of the capacitor C12 is changed by the variation “Vdata−VDD” of the voltage at the first electrode of the capacitor C12. That is, the voltage at the second electrode of the capacitor C12 becomes “Vdata+Vth” voltage, and therefore, the voltage between the gate and source electrodes of the transistor M11 becomes “Vdata+Vth−VDD” voltage. In addition, the “Vdata+Vth−VDD” voltage is stored in the capacitors C11 and C12.
Next, when the emission control signal becomes low-level, a current IOLED expressed in Equation 2 flows from the transistor M11 to the organic light emitting diode OLEDR1, and then, the organic light emitting diode OLEDR1 emits light.




  
    
      
        
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          OLED
        
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          ⁢
          
            
              (
              
                VDD
                -
                Vdata
              
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            2
          
        
      
    
    
      
        Equation
        ⁢
        
          
        
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        2
      
    
  




In addition, a unit pixel which can compensate the threshold voltage of the driving transistor by adding at least one transistor and/or at least one capacitor to the unit pixel of FIG. 2 may be used instead of the unit pixel shown in FIG. 6.
Further, the low-level period of the emission control signal may be set differently from the period shown in FIG. 3. For example, when the brightness is high, the low-level period of the emission control signal may be set to be shorter than a period corresponding to the subfield. That is, the rising edge of the emission control signal may be set to be later than the rising edge of the select signal, and/or the falling edge of the emission control signal may be set to be faster (or earlier) than the rising edge of the select signal in the next subfield.
The organic light emitting diode display device using the voltage programming method is described in the first to fourth exemplary embodiments, but the above-described exemplary embodiments can be applicable to the organic light emitting diode display device using the current programming method.
Next, scan drivers (e.g., the scan driver 200 of FIG. 1) of organic light emitting diode display devices according to exemplary embodiments of the present invention will be described with reference to FIGS. 8 to 25.
FIG. 8 shows a scan driver 200a in an organic light emitting diode display device according to a fifth exemplary embodiment, FIG. 9 shows a signal timing diagram in the scan driver 200a of FIG. 8, and FIG. 10 shows a flip-flop used in the select scan driver 200a of FIG. 8. An inverted signal of a clock VCLK is depicted as /VCLK in FIG. 8, and is not shown in FIG. 9.
As shown in FIG. 8, the scan driver 200a includes two shift registers 210a and 220a. The shift register 210a includes (n+1) flip-flops FF11 to FF1(n+1) and n NAND gates NAND11 to NAND1n, and the shift register 220a includes n flip-flops FF21 to FF2n and n inverters INV21 to INV2n.
In the shift register 210a, a start signal VSP1 is inputted to the first flip-flop FF11, and an output signal SR1i of the ith flip-flop FF1i is inputted to the (i+1)th flip-flop FF1(i+1). The ith NAND gate NAND1i performs a NAND operation to the output signals SR1i and SR1(i+1) of the two adjacent flip-flops FF1i and FF1(i+1) and outputs a select signal select[i].
In the shift register 220a, a start signal VSP2 is inputted to the first flip-flop FF21, and an output signal of the ith flip-flop FF2i is inputted to the (i+1)th flip-flop FF2(i+1). In addition, the output signal of the ith flip-flop FF2i is the emission control signal emit2[i], and the inverter INV2i inverts the output signal of the ith flip-flop FF2i to output the emission control signal emit1[i]. 
The flip-flops FF1i and FF2i output input signals (in) in response to a high-level clock (clk), and latch and output the input signals (in) of the high-level period of the clock (clk) in response to a low-level clock (clk). That is, the flip-flops FF1i and FF2i output the input signals (in) of the high-level period of the inner clock (clk) during one clock VCLK cycle.
Referring to FIG. 8, the clock /VCLK or VCLK inverted to the clock VCLK or /VCLK, which are used in the flip-flop FF1i, are used in the flip-flops FF1(i+1) adjacent to the flip-flop FF1i. In more detail, the flip-flops FF1i that are located at odd-numbered positions in a longitudinal direction use the clocks VCLK as inner clocks (clk). The flip-flops FF1i that are located at even-numbered positions in the longitudinal direction use the inverted clocks /VCLK as inner clocks (clk). Since the output signal SR1i of the flip-flop FF1i is inputted to the flip-flop FF1(i+1), the output signal SR1(i+1) of the flip-flop FF1(i+1) is shifted from the output signal SR1i of the flip-flop FF1i by a half clock VCLK cycle.
As shown in FIG. 9, the start signal VSP1 has a high-level signal (e.g., high-level pulse) in the high-level period of the one clock VCLK cycle in each of the subfields 1F and 2F, and the flip-flop FF11 outputs the high-level signal during one clock VCLK cycle in each of the subfields 1F and 2F. As a result, the flip-flops FF11 to FF1(n+1) may sequentially output each output signal SR1i by shifting the high-level signal by the half clock VCLK cycle.
The NAND gate NAND1i performs a NAND operation of the output signals SR1i and SR1(i+1) of the flip-flops FF1i and FF1(i+1), and outputs a low-level signal (e.g., low-level pulse) when both output signals SR1i and SR1(i+1) are high-level. Here, since the output signal SR1(i+1) of the flip-flop FF1(i+1) is shifted from the output signal SR1i of the flip-flop FF1i by the half clock VCLK cycle, the output signal select[i] of the NAND gate NAND1i has a low-level signal during a period in which the both output signals SR1i and SR1(i+1) have the high-level signal in common in each of the subfields 1F and 2F. In addition, the output signal select[i+1] of the NAND gate NAND1(i+1) is shifted from the output signal select[i] of the NAND gate NAND1i by half the clock VCLK cycle. Therefore, the shift register 210a may sequentially output each select signal select[i] by shifting the low-level signal by the half clock VCLK cycle.
The flip-flop FF2i of the shift register 220a has the same structure as the flip-flop FF1i of the shift register 210a except for the clocks VCLK and /VCLK. That is, the flip-flops FF2i that are located at odd-numbered positions in the longitudinal direction use the inverted clocks /VCLK as inner clocks (clk), and the flip-flops FF2i that are located at the even-numbered positions use the clocks VCLK as inner clocks (clk). Therefore, the emission control signal emit1[i+1] which is the output signal of the flip-flop FF2(i+1) is shifted from the emission control signal emit1[i], which is the output signal of the flip-flop FF2i, by the half clock VCLK cycle.
In addition, the start signal VSP2 is high-level in the low-level period of all clock VCLK cycles in the subfield 1F and is low-level in the low-level period of all clock VCLK cycles in the subfield 2F. As a result, the emission control signal emit2[1] becomes high-level when the select signal select[1] becomes low-level in the first subfield 1F, and becomes low-level when the select signal select[1] becomes low-level in the second subfield 2F. Therefore, the shift register 220a can sequentially output each emission control signal emit2[i], which becomes low-level together with the select signal select[i] in the second subfield 2F, by shifting the half clock VCLK cycle.
Since the output signal emit1[i] of the inverter INV2i has an inverted waveform of the emission control signal emit2[i], the shift register 220a can sequentially output each emission control signal emit1[i], which becomes low-level together with the select signal select[i] in the first subfield 1F, by shifting the half clock VCLK cycle.
Since the flip-flops FF1i and the flip-flops FF2i have the same structure, a flip-flop of FIG. 10 can be used to represent both the flip-flops FF1i and the flip-flops FF2i. Referring to FIG. 10, the flip-flop (e.g., FF1i) includes a clocked inverter 211, and a latch including an inverter 212 and a clocked inverter 213. The clocked inverter 211 inverts an input signal (in) when the clock (clk) is high-level, and the inverter 212 inverts the output signal (/out) of the clocked inverter 211. When the clock (clk) is low-level, the output of the clocked inverter 211 is blocked, the output signal of the inverter 212 is inputted to the clocked inverter 213, and the output signal (/out) of the clocked inverter 213 is inputted to the inverter 212. As a result, the latch is formed. At this time, the output signal (out) of the inverter 212 is the output signal of the flip-flop, and the input signal (/out) of the inverter 212 is the inverted signal to the output signal (out). Therefore, the flip-flop can output the input signal (in) when the clock (clk) is high-level, and latch and output the input signal (in) in the high-level period of the clock (clk) when the clock (clk) is low-level.
As shown in FIG. 10, the signal (/out) inverted to the output signal (out) is outputted from the flip-flop (e.g., FF2i) of the shift register 220a. Therefore, the inverted output signal (/out) of the flip-flop of FIG. 10 may be used as the emission control signal emit1[i] of the first subfield 1F, and the inverter INV2i can be eliminated in the shift register 220a. In addition, the signal having the high-level signal in the first subfield 1F is used as the start signal VSP2 in FIGS. 8 and 9, but a signal inverted to the start signal VSP2 may be used as the start signal of the shift register 220a. Then, the output signal of the flip-flop becomes the emission control signal emit1[i] of the first subfield 1F, and the output signal of the inverter INV2i becomes the emission control signal emit2[i] of the second subfield 2F.
As described above, the emission control signal emit1[i] or emit2[i] is low-level when the select signal select[i] is low-level in the scan driver 200a. This signal timing can be applicable to the organic light emitting diode display device using the voltage programming method in which the data voltage is transmitted to the data line to be stored in the capacitor. However, in the organic light emitting diode display device using the current programming method, the current from the driving transistor needs to be blocked from the organic light emitting diodes when the data current are programmed to the pixel driver. That is, emission control signals emit1[i]′ and emit2[i]′ should be high-level when the select signal select[i] is low-level. In addition, this signal timing may be applicable to the organic light emitting diode display device using the voltage programming method. These exemplary embodiments will be described with reference to FIGS. 11 and 12.
FIG. 11 shows a scan driver 200b in an organic light emitting diode display device according to a sixth exemplary embodiment, and FIG. 12 shows a signal timing diagram in the scan driver 200b of FIG. 11. The scan driver 200b of FIGS. 11 and 12 use the same clock VCLK as the scan driver 200a shown in FIGS. 8 and 9.
As shown in FIG. 11, the scan driver 200b includes the shift register 210a for outputting the select signal select[i] and a shift register 220b for outputting the emission control signals emit1[i]′ and emit2[i]′. The shift register 220b includes (n+1) flip-flops FF31 to FF3(n+1), n NAND gates NAND31 to NAND3n, and n OR gates OR31 to OR3n. Here, a NAND gate and an inverter may be used instead of the OR gate OR3i.
The clock VCLK is inputted to the flip-flops FF3i, and the NAND gate NAND3i performs a NAND operation between the output signals SR3i and SR3(i+1) of the flip-flops FF3i and FF3(i+1) to output the emission control signal emit1[i]′. The OR gate OR3i performs an OR operation between the output signals SR3i and SR3(i+1) of the flip-flops FF3i and FF3(i+1) to output the emission control signal emit2[i]′. 
As shown in FIG. 12, the start signal VSP2 shown in FIG. 9 is inputted to the flip-flop FF3i. Therefore, the output signal SR3i of the flip-flop FF3i becomes high-level when the select signal select[i] becomes low-level in the first subfield 1F, and becomes low-level when the select signal select[i] becomes low-level in the second subfield 2F. Since the NAND gate NAND3i outputs the low-level signal while both the output signal SR3i and SR3(i+1) of the flip-flops FF3i and FF3(i+1) are high-level, the emission control signal emit1[i]′ becomes low-level when the select signal select[i] becomes high-level in the first subfield 1F. In addition, since the OR gate OR3i outputs the high-level signal while both the output signal SR3i and SR3(i+1) of the flip-flops FF3i and FF3(i+1) are low-level, the emission control signal emit2[i]′ becomes low-level when the select signal select[i] becomes high-level in the second subfield 2F.
As described above, the emission control signals emit1[i]′ and emit2[i]′ are high-level in the sixth exemplary embodiment when the select signal select[i] has the low-level signal. In addition, emission control signals emit1[i]′′ and emit2[i]′′ may be high-level when the previous and current select signals select[i−1] and select[i] have the low-level signals. This exemplary embodiment will be described with reference to FIGS. 13 and 14.
FIG. 13 shows a scan driver 200c in an organic light emitting diode display device according to a seventh exemplary embodiment, and FIG. 14 shows a signal timing diagram of the scan driver 200c shown in FIG. 13. The scan driver 200c of FIGS. 13 and 14 use the same clock VCLK as the scan driver 200a shown in FIGS. 8 and 9.
As shown in FIG. 13, the scan driver 200c includes the shift register 210a for outputting the select signal select[i] and a shift register 220c for outputting the emission control signals emit1[i]′′ and emit2[i]′′. The shift register 220c includes n flip-flops FF41 to FF4n, n inverters INV41 to INV4n, and 2n NOR gates NOR11 to NOR1n, and NOR41 to NOR4n.
The flip-flops FF41 to FF4n and the inverters INV41 to INV4n have the same structure as the flip-flops FF21 to FF2n and the inverters INV21 to INV2n of FIG. 8 except for the clocks VCLK and /VCLK. That is, the flip-flop FF4i uses the clock VCLK or /VCLK inverted to the clock /VCLK or VCLK of the flip-flop FF2i shown in FIG. 8. The NOR gate NOR1i performs a NOR operation between the output signal SR1i of the flip-flop FF1i and the inverted output signal /SR4i of the flip-flop FF4i to output the emission control signal emit1[i]′′ in the first subfield 1F. The NOR gate NOR4i performs a NOR operation between the output signals SR1i and SR4i of the flip-flops FF1i and FF4i to output the emission control signal emit2[i]′′ in the second subfield 2F.
As shown in FIG. 14, a start signal VSP2′ is high-level in the high-level period of the clock VCLK in the first subfield 1F and is low-level in the high-level period of the clock VCLK in the second subfield 2F. As a result, the output signal SR4i of the flip-flop FF4i has the high-level signal during a period corresponding to the first subfield 1F and has the low-level signal during a period corresponding to the second subfield 2F. Therefore, the output signal SR4i of the flip-flop FF4i becomes high-level when the output signal SR1i of the flip-flop FF1i becomes high-level in the first subfield 1F, and becomes low-level when the output signal SR1i of the flip-flop FF1i becomes high-level in the second subfield 2F.
Since the NOR gate NOR1i outputs the low-level signal while both the output signal SR1i of the flip-flop FF1i and the inverted output signal /SR4i of the flip-flop FF4i are low-level, the output signal emit1[i]′′ of the NOR gate NOR1i becomes low-level together with the output signal SR1i in the first subfield 1F and becomes high-level together with the output signal SR1i in the second subfield 2F. Since the NOR gate NOR4i outputs the low-level signal while both the output signals SR1i and SR4i of the flip-flops FF1i and FF4i are low-level, the output signal emit2[i]′′ of the NOR gate NOR4i becomes low-level together with the output signal SR1i in the second subfield 2F and becomes high-level together with the output signal SR1i in the first subfield 1F. Therefore, the emission control signals emit1[i]′′ and emit2[i]′′ are high-level when the previous and current select signals select[i−1] and select[i] have the low-level signals.
In addition, the emission control signals emit1[i]′′ and emit2[i]′′ shown in FIG. 14 may be generated from the scan driver shown in FIG. 11. This exemplary embodiment will be described with reference to FIGS. 15 and 16.
FIG. 15 shows a scan driver 200d in an organic light emitting diode display device according to an eight exemplary embodiment, and FIG. 16 shows a signal timing diagram of the scan driver 200d shown in FIG. 15.
As shown in FIG. 15, the scan driver 200d includes the shift register 210a for outputting the select signal select[i] and a shift register 220d for outputting the emission control signals emit1[i]′′ and emit2[i]′′. The shift register 220d further includes a flip-flop FF30 before the flip-flop FF31, which is different from the shift register 220b of FIG. 11, and a start signal VSP2′′ is inputted to the flip-flop FF30. The flip-flop FF30 receives the clock VCLK as the inner clock (clk).
In the shift register 220d, the ith NAND gate NAND3i performs a NAND operation between the output signals SR3(i−1) and SR3(i+1) of the (i−1)th and (i+1)th flip-flops FF3(i−1) and FF3(i+1) to output the emission control signal emit1[i]′′. The ith OR gate OR3i performs an OR operation between the output signals SR3(i−1) and SR3(i+1) of the (i−1)th and (i+1)th flip-flops FF3(i−1) and FF3(i+1) to output the emission control signal emit2[i]′′. 
Referring to FIG. 16, the start signal VSP2′′ is high-level when the clock VCLK is high-level in the first subfield 1F, and is low-level when the clock VCLK is high-level in the second subfield 2F. Then, the output signal SR3i of the flip-flop FF3i is same as that SR3i shown in FIG. 12. Therefore, the emission control signals emit1[i]′′ and emit2[i]′′ are high-level when the previous and current select signal select[i−1] and select[i] have the low-level signals.
As described above, the select signals and the emission control signals are generated from the two shift registers each including the plurality of flip-flops. Next, exemplary embodiment which may reduce the number of the flip-flops compared to these exemplary embodiments, will be described.
FIG. 17 shows a scan driver 200e in an organic light emitting diode display device according to a ninth exemplary embodiment, and FIG. 18 shows a signal timing diagram of the scan driver 200e shown in FIG. 17. A clock VCLK′ used in the scan driver 200e of FIGS. 17 and 18 has twice the period of the clock VCLK of FIGS. 8 to 16, and the inverted clock /VCLK′ is not shown in FIG. 18.
As shown in FIG. 17, the scan driver 200e includes a shift register 210e for outputting the select signal select[i] and a shift register 220e for outputting the emission control signals emit1[i]′′ and emit2[i]′′. The shift register 210e includes ((n/2)+1) flip-flops FF51 to FF5(n/2+1), n NAND gates NAND51 to NAND5(n/2), and NAND61 to NAND6(n/2), and the shift register 220e includes (n/2) flip-flops FF61 to FF6(n/2), and n OR gates OR51 to OR5(n/2), and OR61 to OR6(n/2) (where ‘n’ is assumed to an even number).
The clocks VCLK′ and /VCLK′ of the flip-flop FF5(j+1) are inverted to the clocks /VCLK′ and VCLK′ of the adjacent flip-flops FF5j in the shift register 210e (where ‘j’ is a positive integer less than or equal to ‘n/2’), and the clock VCLK′ is inputted to the flip-flop FF51 as the inner clock (clk). As shown in FIG. 18, since the start signal VSP1′ has the high-level signal in the high-level period of the one clock VCLK cycle in each of the subfields 1F and 2F, the flip-flops FF51 to FF5(n/2+1) may sequentially output each output signal SR5i by shifting the high-level signal by the half clock VCLK′ cycle. Here, the output signal SR5i has the high-level signal during one clock VCLK′ cycle in each of the subfields 1F and 2F.
The jth NAND gate NAND5j performs a NAND operation of the output signals SR5j and SR5(j+1) of the flip-flops FF5j and FF5(j+1), and the inverted clock /VCLK to output the (2j−1)th select signal select[2j−1]. Therefore, the select signal select[2j−1] has the low-level signal during a low-level period of the clock VCLK of a period in which the both output signals SR5j and SR5(j+1) are high-level. The jth NAND gate NAND6j performs the NAND operation of the output signals SR5j and SR5(j+1) of the flip-flops FF5j and FF5(j+1), and the clock VCLK to output the (2j)th select signal select[2j]. Therefore, the select signal select[2j] has the low-level signal during a high-level period of the clock VCLK of the period in which the both output signals SR5j and SR5(j+1) are high-level.
The clocks VCLK′ and /VCLK′ of the flip-flop FF6(j+1) are inverted to the clocks /VCLK′ and VCLK′ of the adjacent flip-flops FF6j in the shift register 212e, and the inverted clock /VCLK′ is inputted to the flip-flop FF61 as the inner clock (clk). As shown in FIG. 18, since the start signal VSP2′′ has the high-level signal in the first subfield 1F, the flip-flops FF61 to FF6(n/2) may sequentially output each output signal SR6i by shifting the high-level signal by the half clock VCLK′ cycle. Here, the output signal SR6i has the high-level signal during a period corresponding to the first subfield 1F.
The jth OR gate OR5j performs an OR operation of the output signal SR5j of the flip-flop FF5j and the inverted output signal /SR6j of the flip-flop FF6j to output the (2j−1)th and (2j)th emission control signals emit1[2j−1]′′ and emit1[2j]′′ (shown as emit1[2j−1, 2j] in FIG. 17) in the first subfield 1F. Therefore, the emission control signals emit1[2j−1]′′ and emit1[2j]′′ have the low-level signal during a period in which the both output signal SR5j of the flip-flop FF5j and inverted output signal /SR6j of the flip-flop FF6j are low-level. The jth OR gate OR6j performs the OR operation of the output signal SR5j of the flip-flop FF5j and the output signal SR6j of the flip-flop FF6j to output the (2j−1)th and (2j)th emission control signals emit2[2j−1]′′ and emit2[2j]′′ (shown as emit2[2j−1, 2j] in FIG. 17) in the second subfield 2F. Therefore, the emission control signals emit2[2j−1]′′ and emit2[2j]′′ have the low-level signal during a period in which the both output signals SR5j and SR6j of the flip-flops FF5j and FF6j are low-level.
As a result, as shown in FIG. 18, the emission control signals emit1[2j−1]′′ and emit2[2j−1]′′ are high-level when the previous and current select signals select[2j−2] and select[2j−1] have the low-level signals, and the emission control signals emit1[2j]′′ and emit2[2j]′′ are high-level when the previous and current select signals select[2j−1] and select[2j] have the low-level signal.
Next, exemplary embodiments which use one shift register to output the select signals and the emission control signals will be described with reference to FIGS. 19 to 26.
First, a scan driver 200f for outputting the emission control signals emit1[i] and emit2[i] shown in FIG. 9 will be described with reference to FIGS. 19 and 20.
FIG. 19 shows the scan driver 200f in an organic light emitting diode display device according to a tenth exemplary embodiment, and FIG. 20 shows a signal timing diagram of the scan driver 200f shown in FIG. 19.
As shown in FIG. 19, the scan driver 200f includes (n+1) flip-flops FF71 to FF7(n+1), n XNOR gates XNOR71 to XNOR7n, and n inverters INV71 to INV7n, and operates as a shift register. The flip-flops FF71 to FF7(n+1) and the n inverters INV71 to INV7n have the same structure as the flip-flops FF11 to FF1(n+1) and the n inverters INV21 to INV2n shown in FIG. 8. In addition, the flip-flops FF71 to FF7(n+1) use the clock VCLK and the start signal VSP2 shown in FIG. 9.
Therefore, an output signal SR7i of the flip-flop FF7i is same as the emission control signal emit1[i] of the first subfield 1F, and the output signal of the inverter INV7i is same as the emission control signal emit2[i] of the second subfield 2F. In addition, the inverted output signal (/out) of the flip-flop FF7i may be used as the emission control signal emit2[i] instead of the output signal of the inverter INV7i.
The XNOR gate XNOR7i performs XNOR operation between the output signals SR7i and SR7(i+1) of the flip-flops FF7i and FF7(i+1) to output the select signal select[i]. That is, the XNOR gate XNOR7i outputs the low-level select signal select[i] while the output signals SR7i and SR7(i+1) of the flip-flops FF7i and FF7(i+1) have the different levels. Accordingly, the select signal select[i] has the low-level signals during a period corresponding to the half clock VCLK cycle from the falling edge of the output signal SR7i and a period corresponding to the half clock VCLK cycle from the rising edge of the output signal SR7i. As a result, the emission control signals emit1[i] and emit2[i] become low-level together with the select signal select[i] in the first and second subfields 1F and 2F, respectively.
Next, scan drivers 200g and 220h for outputting the emission control signals emit1[i]′ and emit2[i]′ shown in FIG. 12 will be described with reference to FIGS. 21 to 23.
FIG. 21 shows the scan driver 200g in an organic light emitting diode display device according to an eleventh exemplary embodiment, and FIG. 22 shows a signal timing diagram of the scan driver 200g shown in FIG. 21.
As shown in FIG. 21, the scan driver 200g has the same structure as the scan driver 200f of FIG. 19 except that the emission control signals emit1[i]′ and emit2[i]′ are generated from a NAND gate NAND7i and an OR gate OR7i.
In more detail, the ith NAND gate NAND7i performs a NAND operation between the output signals SR7i and SR7(i+1) of the flip-flops FF7i and FF7(i+1) to output the emission control signal emit1[i]′ of the first subfield 1F, and the ith OR gate OR7i performs an OR operation between the output signals SR7i and SR7(i+1) of the flip-flops FF7i and FF7(i+1) to output the emission control signal emit2[i]′ of the second subfield 2F. Then, since the emission control signals emit1[i]′ and emit2[i]′ are at high-level in a period corresponding to the low-level signal of the select signal select[i], the emission control signals emit1[i]′ and emit2[i]′ shown in FIG. 22 can be outputted.
FIG. 23 shows the scan driver 200h in an organic light emitting diode display device according to a twelfth exemplary embodiment.
As shown in FIG. 23, the scan driver 200h has the same structure as the scan driver 200g of FIG. 21 except that the select signal select[i] are generated from a NAND gate NAND8i.
Referring to FIG. 22, the two emission control signal emit1[i]′ and emit2[i]′ have high-levels during a period in which the select signal select[i] has low-level. Therefore, the select signal select[i] can be generated by the NAND operation of the emission control signals emit1[i]′ and emit2[i]′ which is performed by the NAND gate NAN D8i.
Next, a scan driver 200i for outputting the emission control signals emit1[i]′′ and emit2[i]′′ shown in FIG. 14 will be described with reference to FIGS. 24 to 26.
FIG. 24 shows the scan driver 200i in an organic light emitting diode display device according to a thirteenth exemplary embodiment, and FIG. 25 shows a signal timing diagram of the scan driver 200i shown in FIG. 24.
The scan driver 200i of FIG. 24 further includes 2n OR gates OR11 to OR1n and OR21 to OR2n in addition to the elements of the scan driver 200g of FIG. 21, and the flip-flops FF71 to FF7n are not shown in FIG. 24. In addition, the ith OR gates OR1i and OR2i, (i−1)th and ith NAND gates NAND7(i−1) and NAND7i, (i−1)th and ith OR gates OR7(i−1) and OR7i, and ith XNOR gate XNOR7i are shown in FIG. 24. In FIGS. 24 and 25, the signals SR7(i−1), SR7i, and SR7(i+1) respectively correspond to the output signals of the flip-flops FF7(i−1), FF7i, and FF7(i+1), and signals Ai and Ai respectively correspond to the emission control signals emit1[i]′ and emit2[i]′ of the scan driver 200g shown in FIG. 21.
As shown in FIG. 25, the OR gate OR1i performs an OR operation of the signals Ai−1 and Ai to output the emission control signals emit1[i]′′ during a period in which the both signals Ai−1 and Ai are low-level. In addition, the OR gate OR2i performs an OR operation of the signals Bi−1 and Bi to output the emission control signals emit2[i]′′ during a period in which the both signals Bi−1 and Bi are low-level. These emission control signals emit1[i]′′ and emit2[i]′′ are same as those shown in FIG. 14.
In addition, if the output signals Ai−k and Ai+p of the (i−k)th and (i+p)th NAND gates NANDi−k and NANDi+p are inputted to the ith OR gates OR1i and OR2i (where ‘k’ and ‘p’ are respectively positive integers), the low-level periods of the emission control signals emit1[i]′′ and emit2[i]′′ may be controlled by an integral multiple of the half clock VCLK cycle.
FIG. 26 shows a scan driver 200j in an organic light emitting diode display device according to a fourteenth exemplary embodiment.
As shown in FIG. 26, the scan driver 200j includes a NAND gate NAND8i instead of the XNOR gate XNOR7i in the scan driver 200i of FIG. 24. The ith NAND gate NAND8i performs a NAND operation of the output signal Ai of the ith NAND gate NAND7i and the output signal Bi of the ith OR gate OR7i to output the select signal select[i] as described in reference to FIG. 23.
In the above exemplary embodiments, the cases in which the width of the low-level signal of the select signal select[i] is same as the half clock VCLK cycle have been described. That is, the rising edge of the select signal select[i−1] corresponds to the falling edge of the select signal select[i]. In other embodiment, however, the falling edge of the select signal select[i] may be apart from the rising edge of the select signal select[i−1]. That is, the width of the low-level signal of the select signal select[i] may be shorter than the half clock VCLK cycle. One such exemplary embodiment will be described with reference to FIGS. 27 and 28.
FIG. 27 shows a scan driver 200k in an organic light emitting diode display device according to a fifteenth exemplary embodiment, and FIG. 28 shows a signal timing diagram of the scan driver 200k shown in FIG. 27. In FIGS. 27 and 28, the case in which the low-level signal width (e.g., low-level pulse width) of the select signal is reduced in the scan driver 200a of FIGS. 8 and 9 will be described.
As shown in FIGS. 27 and 28, the scan driver 200k has the same structure as the scan driver 200a of FIGS. 8 and 9 except for a clip signal CLIP, and NAND gates NAND11i (i.e., NAND111 to NAND11n), to which the clip signal CLIP is applied in addition to the output signals SR1i and SR1(i+1). The clip signal CLIP has a cycle corresponding to the half clock VCLK cycle, and has the low-level signal whose width is shorter than the half clock VCLK cycle. In addition, the low-level period of the clip signal CLIP includes the falling edge or the rising edge of the clock VCLK.
Then, the NAND gate NAND11i outputs the low-level signal of the select signal select[i]′ (i.e., one of select signals select[1]′ to select[n]′) during a period in which the clip signal CLIP is high-level. That is, the falling edge of the select signal select[i]′ is apart from the rising edge of the select signal select[i−1]′ by the low-level signal width (e.g., low-level pulse width) of the clip signal CLIP.
The principles of the exemplary embodiment described in FIGS. 27 and 28 may also be applicable to the other exemplary embodiments described above.
In addition, the scan driver may be divided into a scan driver for driving the unit pixels formed on the odd row (hereinafter, “an odd row scan driver”) and a scan driver for driving the unit pixels formed on the even row (hereinafter, “an even row scan driver”). This exemplary embodiment will be described with reference to FIGS. 29 to 31.
FIG. 29 shows a plan view of an organic light emitting diode display device according to a sixteenth exemplary embodiment of the present invention, FIGS. 30A and 30B respectively show odd row and even row scan drivers 201 and 202 in the organic light emitting diode display device according to the sixteenth exemplary embodiment, and FIG. 31 shows a signal timing diagram of the odd row scan driver 201 shown in FIG. 30A.
As shown in FIG. 29, the organic light emitting diode display device according to the sixteenth exemplary embodiment has the same structure as that of FIG. 1 except for the scan drivers 201 and 202.
The odd row scan driver 201 is formed on one side of the display area 100, and sequentially transmits the select signals select[2j−1] to the odd-numbered select scan lines S2j−1 (where T is a positive integer less than or equal to n/2). The even row scan driver 202 is formed on the other side of the display area 100, and sequentially transmits the select signals select[2j] to the even-numbered select scan lines S2j. In addition, the odd row scan driver 201 sequentially transmits emission control signals emit1[2j−1]′′ to the odd-numbered emit scan lines Em1(2j−1) in the first subfield 1F, and sequentially transmits emission control signals emit2[2j−1]′′ to the odd-numbered emit scan lines Em2(2j−1) in the second subfield 2F. The even row scan driver 202 sequentially transmits emission control signals emit1[2j]′′ to the even-numbered emit scan lines Em1(2j) in the first subfield 1F, and sequentially transmits emission control signals emit2[2j]′′ to the even-numbered emit scan lines Em2(2j) in the second subfield 2F.
Referring to FIG. 30A, the odd row scan driver 201 has a structure in which NAND gates NAND61 to NAND6(n/2) for even-numbered select signals are eliminated from the scan driver 200e shown in FIG. 17. In more detail, the odd row scan driver 201 includes a shift register 211 for outputting the odd-numbered select signals select[2j−1] and a shift register 221 for outputting the odd-numbered emission control signals emit1[2j−1]′′ and emit2[2j−1]′′. The shift register 211 includes ((n/2)+1) flip-flops FF81, FF83, . . . , FF8(n+1), and (n/2) NAND gates NAND91, NAND93, . . . , NAND9(n−1), and the shift register 221 includes (n/2) flip-flops FF91, FF93, . . . , FF9(n−1), and n OR gates OR81, OR83, OR8(n−1), and OR91, OR93, . . . , OR9(n−1).
Referring to FIG. 30B, the even row scan driver 202 has a structure in which the NAND gates NAND51 to NAND5(n/2) for odd-numbered select signals are eliminated from the scan driver 200e shown in FIG. 17. In more detail, the even row scan driver 202 includes a shift register 212 for outputting the even-numbered select signal select[2j] and a shift register 222 for outputting the even-numbered emission control signals emit1[2j]′′ and emit2[2j]′′. The shift register 212 includes ((n/2)+1) flip-flops FF82, FF84, . . . , FF8(n+2), and (n/2) NAND gates NAND92, NAND94, . . . , NAND9n, and the shift register 212 includes (n/2) flip-flops FF92, FF94, . . . , FF9n, and n OR gates OR82, OR84, . . . , OR8n, and OR92, OR94, . . . , OR9n.
Referring to FIGS. 30A, 30B and 31, the start signal VSP1′ shown in FIG. 18 is inputted to the flip-flops FF81 and FF82, and the start signal VSP2′′ shown in FIG. 18 is inputted to the flip-flops FF91 and FF92. The NAND gate NAND9(2j−1) of the scan driver 201 performs a NAND operation of the output signals SR8(2j−1) and SR8(2j+1) of the flip-flops FF8(2j−1) and FF8(2j+1) and the clock VCLK to output the (2j−1)th select signal select[2j−1]. In addition, the NAND gate NAND9(2j) of the scan driver 202 performs a NAND operation of the output signals SR8(2j) and SR8(2j+2) of the flip-flops FF8(2j) and FF8(2j+2) and the inverted clock /VCLK to output the (2j)th select signal select[2j]. 
In the scan driver 201, the OR gate OR8(2j−1) performs an OR operation of the output signal SR8(2j−1) of the flip-flop FF8(2j−1) and the inverted output signal /SR9(2j−1) of the flip-flop FF9(2j−1) to output the (2j−1)th emission control signal emit1[2j−1]′′, and the OR gate OR9(2j−1) performs an OR operation of the output signals SR8(2j−1) and SR9(2j−1) of the flip-flops FF8(2j−1) and FF9(2j−1) to output the (2j−1)th emission control signal emit2[2j−1]′′. In the scan driver 202, the OR gate OR8(2j) performs an OR operation of the output signal SR8(2j) of the flip-flop FF8(2j) and the inverted output signal /SR9(2j) of the flip-flop FF9(2j) to output the (2j)th emission control signal emit1[2j]′′, and the OR gate OR9(2j) performs an OR operation of the output signals SR8(2j) and SR9(2j) of the flip-flops FF8(2j) and FF9(2j) to output the (2j)th emission control signal emit2[2j]′′. 
The principles of the exemplary embodiment described in FIGS. 29 to 31 may also be applicable to the other exemplary embodiments described above.
In the above exemplary embodiments, the cases in which the select signals and the emission control signals provided by the scan driver are directly applied to the select scan lines and the emit scan lines have been shown. In other embodiments, however, one or more buffers may be formed between the display area 100 and the scan driver 200 (or the scan drivers 201 and 202). In addition, one or more level shifters which change the levels of the select signals and the emission control signals may also be formed between the display area 100 and the scan driver 200 (or the scan drivers 201 and 202).
According to the exemplary embodiments of the present invention, the plurality of sub-pixels share the select scan line and the pixel driver in the unit pixel. As a result, the sub-pixels can be easily arranged in the unit pixel, and the aperture ratio of the unit pixel can be improved. In addition, since the number of the select scan lines is reduced compared to that of the number of the row lines, the number of the output terminals and the dimension of the scan driver can be reduced. Further, since the dimension of the scan driver is reduced, the non-emission area can be reduced when the scan driver and the unit pixels are formed on the same substrate.
According to the other exemplary embodiments of the present invention, the number of the flip-flops can be reduced in the scan driver for outputting the select signals and the emission control signals of the first and second subfields.
While this invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims and their equivalents.

## Claims

1. A pixel circuit driving method of a display device including a plurality of data lines extending in a first direction and for transmitting data signals, a plurality of select scan lines extending in a second direction and for transmitting a plurality of select signals, and a plurality of unit pixels, each of the unit pixels including a plurality of sub-pixels, the pixel circuit driving method comprising:
applying at least one of the select signals to a corresponding one of the plurality of select scan lines in a first subfield of a field, and applying at least one of the data signals to at least one of the plurality of data lines;
applying a first emission control signal to at least one of the unit pixels to which a corresponding one of the select signals and a corresponding one of the data signals are applied, to emit light in a first sub-pixel of the plurality of sub-pixels;
applying at least one of the select signals to a corresponding one of the plurality of select scan lines in a second subfield of the field, and applying at least one of the data signals to at least one of the plurality of data lines; and
applying a second emission control signal to at least one of the unit pixels to which a corresponding one of the select signals and a corresponding one of the data signals are applied, to emit light in a second sub-pixel of the plurality of sub-pixels, the first and second sub-pixels being arranged in the first direction,
wherein the first subfield and the second subfield constitute a plurality of subfields.

2. The pixel circuit driving method of claim 1, wherein each of the plurality of sub-pixels includes at least one light emitting element, and
wherein each of the plurality of unit pixels comprises:
a pixel driver
for storing a corresponding one of the data signals in response to a first signal of a corresponding one of the select signals in each of the plurality of subfields, and
for outputting a driving current corresponding to the corresponding one of the data signals; and

a plurality of switches, each of the plurality of switches being coupled to the pixel driver and a corresponding one of the plurality of sub-pixels.

3. The pixel circuit driving method of claim 2, wherein the plurality of switches include;
a first switch being turned on in response to a second signal of the first emission control signal; and
a second switch being turned on in response to a third signal of the second emission control signal.

4. The pixel circuit driving method of claim 3, further comprising:
shifting at least one of first shift signals having a fourth signal in each of the plurality of subfields by a first period to sequentially output a plurality of the first shift signals; and
generating the first signal of at least one of the select signals during at least a part of a period in which the fourth signal of one of the first shift signals at least partly overlaps with the fourth signal of another one of the first shift signals.

5. The pixel circuit driving method of claim 4, further comprising:
shifting at least one of second shift signals having a fifth signal and a sixth signal in the field by the first period to sequentially output a plurality of the second shift signals;
generating the second signal of the first emission control signal in response to the fifth signal of a corresponding one of the second shift signals; and
generating the third signal of the second emission control signal in response to the sixth signal of a corresponding one of the second shift signals.

6. The pixel circuit driving method of claim 4, further comprising:
shifting at least one of second shift signals having a fifth signal and a sixth signal in the field by the first period to sequentially output a plurality of the second shift signals;
generating the second signal of the first emission control signal during a period in which the fifth signal of one of the second shift signals at least partly overlaps with the fifth signal of another one of the second shift signals; and
generating the third signal of the second emission control signal during a period in which the sixth signal of one of the second shift signals at least partly overlaps with the sixth signal of another one of the second shift signals.

7. The pixel circuit driving method of claim 3, further comprising:
shifting at least one of first shift signals having a fourth signal and a fifth signal in the field by a first period to sequentially output a plurality of the first shift signals; and
generating the first signal of at least one of the select signals during at least a part of a period in which two of the first shift signals shifted from each other by the first period have different signals.

8. The pixel circuit driving method of claim 7, further comprising:
generating the second signal of the first emission control signal in response to the fourth signal of a corresponding one of the first shift signals; and
generating the third signal of the second emission control signal in response to the fifth signal of a corresponding one of the first shift signals.

9. The pixel circuit driving method of claim 7, further comprising:
generating the second signal of the first emission control signal during a period in which the fourth signal of one of the first shift signals at least partly overlaps with the fourth signal of another one of the first shift signals; and
generating the third signal of the second emission control signal during a period in which the fifth signal of one of the first shift signals at least partly overlaps with the fifth signal of another one of the first shift signals.

10. The pixel circuit driving method of claim 3, further comprising:
shifting at least one of first shift signals having a fourth signal and a fifth signal in the field by a first period to sequentially output a plurality of the first shift signals;
generating the second signal of the first emission control signal during a period in which the fourth signal of one of the first shift signals at least partly overlaps with the fourth signal of another one of the first shift signals;
generating the third signal of the second emission control signal during a period in which the fifth signal of one of the first shift signals at least partly overlaps with the fifth signal of another one of the first shift signals; and
generating the first signal of a corresponding one of the select signals during at least a part of a period in which the first emission control signal does not have the second signal and the second emission control signal does not have the third signal.

11. The pixel circuit driving method of claim 3, further comprising:
shifting at least one of first shift signals having a fourth signal and a fifth signal in the field by a first period to sequentially output a plurality of the first shift signals;
generating a sixth signal of at least one of second shift signals during a period in which the fourth signal of one of the first shift signals at least partly overlaps with the fourth signal of another one of the first shift signals;
generating a seventh signal of at least one of third shift signals during a period in which the fifth signal of one of the first shift signals at least partly overlaps with the fifth signal of another one of the first shift signals;
generating the second signal of the first emission control signal during a period in which the sixth signal of one of the second shift signals at least partly overlaps with the sixth signal of another one of the second shift signals; and
generating the third signal of the second emission control signal during a period in which the seventh signal of one of the third shift signals at least partly overlaps with the seventh signal of another one of the third shift signals.

12. The pixel circuit driving method of claim 11, further comprising:
generating the first signal of at least one of the select signals during at least a part of a period in which two of the first shift signals shifted from each other by the first period have different signals.

13. The pixel circuit driving method of claim 11, further comprising:
generating the first signal of at least one of the select signals during at least a part of a period in which a corresponding one of the second shift signals does not have the sixth signal and a corresponding one of the third shift signals does not have the seventh signal.

14. The pixel circuit driving method of claim 3,
wherein the plurality of select signals comprise:
a plurality of first select signals applied to a first group of the select scan lines including odd-numbered select scan lines; and
a plurality of second select signals applied to a second group of the select scan lines including even-numbered select scan lines,

wherein at least one of the first select signals is shifted by a first period from another one of the first select signals,
wherein at least one of the second select signals is shifted by the first period from another one of the second select signals, and
wherein the at least one of the second select signals is shifted by a second period corresponding to one-half of the first period from the at least one of the first select signals.

15. The pixel circuit driving method of claim 14, further comprising:
outputting a first shift signal having a fourth signal and a fifth signal in turn with a cycle of the first period;
shifting at least one of second shift signals having a sixth signal in each of the plurality of subfields by the first period to sequentially output a plurality of the second shift signals;
generating the first signal of at least one of the first select signals during at least a part of a period in which the sixth signal of one of the second shift signals at least partly overlaps with the sixth signal of another one of the second shift signals and the first shift signal has the fourth signal; and
generating the first signal of at least one of the second select signals during at least a part of a period in which the sixth signal of one of the second shift signals at least partly overlaps with the sixth signal of another one of the second shift signals and the first shift signal has the fifth signal.

16. The pixel circuit driving method of claim 15, further comprising:
shifting at least one of third shift signals having a seventh signal and an eighth signal in the field by the first period to sequentially output a plurality of the third shift signals;
generating the second signal of the first emission control signal during a period in which a corresponding one of the third shift signals has the seventh signal and a corresponding one of the second shift signals does not have the sixth signal; and
generating the third signal of the second emission control signal during a period in which a corresponding one of the third shift signals has the eighth signal and a corresponding one of the second shift signals does not have the sixth signal,
wherein same said first and second emission control signals are applied to one of the unit pixels to which one of the first select signals is applied and to one of the unit pixels to which one of the second select signals is applied.

17. The pixel circuit driving method of claim 14, wherein
at least one of the first select signals is inputted to a first terminal of a corresponding one of the select scan lines, and
at least one of the second select signals is inputted to a second terminal of a corresponding one of the select scan lines.

18. The pixel circuit driving method of claim 1, wherein each of the plurality of sub-pixels comprises an organic light emitting diode.