US 2023/0060711 Al

n-type GaN nanofin core 107, and including GaN; optional
source contact 122 disposed on n-type GaN nanofin core 107
and p-type nanofin shell 114 and in electrical communica-
tion with n-type source 112, such that n-type source 112 is
interposed between source contact 122 and n-type channel
110; gate contact 118 disposed on p-type nanofin shell 114
and in electrical communication with p-type nanofin shell
114, such that p-type nanofin shell 114 is interposed between
gate contact 118 and n-type channel 110, and gate contact
118 is interposed between source contact 122 and drain
contact 124; and drain contact 124 disposed on n-type drift
layer 108, such that drain contact 124 is in electrical
communication via ohmic contact with n-type drift layer
108; turning on core-shell nanofin vertical switch 100 by:
receiving, by gate contact 118, a gate voltage that is positive
with respect to a ground potential; accumulating electron
charge carriers in n-type GaN nanofin core 107 in response
to receiving the gate voltage; flowing electrical current
between source contact 122 and drain contact 124 in
response to accumulating electron charge carriers; and turn-
ing off core-shell nanofin vertical switch 100 by: receiving,
by gate contact 118, the gate voltage that is at ground
potential or negative with respect to a ground potential;
depleting the electron charge carriers from n-type GaN
nanofin core 107 in response to receiving the gate voltage at
ground potential or negative with respect to a ground
potential; and terminating flow of electrical current between
source contact 122 and drain contact 124 in response to
depleting the electron charge carriers.

[0059] In an embodiment, the process for high-voltage
switching includes placing source contact 122 and drain
contact 124 in electrical communication and receiving the
electrical current at source contact 122 in response to turning
on core-shell nanofin vertical switch 100; and electrically
isolating source contact 122 and drain contact 124 in
response to turning off core-shell nanofin vertical switch
100.

[0060] In an embodiment, a potential difference between
source contact 122 and the drain contact 124 after core-shell
nanofin vertical switch 100 is subjected to turning is from 1
V to 1500 V, and core-shell nanofin vertical switch 100 is
configured so that, without electrical breakdown or damage,
core-shell nanofin vertical switch 100 withstands the poten-
tial difference between source contact 122 and drain contact
124 from 0 V to 1500 V.

[0061] In an embodiment, the process for high-voltage
switching includes connecting an electrical load in electrical
‘ication with source contact 122, so that the electri-
in electrical communication with drain contact
124 and receives the electrical current from source contact
122 in response to turning on core-shell nanofin vertical
switch 100; and electrically isolated from drain contact 124
in response to turning off core-shell nanofin vertical switch
100.

[0062] The process for high-voltage switching can include
connecting a load or power-converter circuit to the source
contact, wherein the load or power-converter circuit can
include an electrical motor or DC-DC power converter.
[0063] The process for high-voltage switching can include
modulating the gate contact 118 voltage to energize a load
or circuit and with an intentional actuation response.
[0064] Core-shell nanofin vertical switch 100 and pro-
cesses disclosed herein have numerous beneficial uses.
Advantageously, core-shell nanofin vertical switch 100

Mar. 2, 2023

overcomes limitations and technical deficiencies of conven-
tional devices and conventional processes. Core-shell
nanofin vertical switch 100 and processes herein provide
high-quality selective area growth of GaN nanofin cores and
core-shell p-n junction nanofins using the selective area
growth, Moreover, core-shell nanofin vertical switch 100
includes an electrically functional core-shell p-n junction
with low-leakage, diode-like current-voltage characteristics
using the core-shell selective area growth.

[0065] The articles and processes herein are illustrated
further by the following Examples, which are non-limiting.
EXAMPLES
Example 1

[0066] By simulation, core-shell nanofin vertical switch
100 had a breakdown voltage greater than 1000 V, e.g., 1.5
KV, a threshold turn-on voltage of 2.5 V for normally-off
operation, or an on-state resistance, eg. of 0.18
mohm*cm*2. Simulations for electrical properties of core-
shell nanofin vertical switch 100 are shown in FIG. 5 and
FIG. 6.

[0067] The simulation was used to partially optimize the
core-shell nanofin dimensions, doping concentrations, and
p-shell Al content. As a result, the optimized structure had
various physical attributes. The GaN nanofin core had a
width of 160 nm and a height of 6 um. The n-type doping in
the nanofin core was 1E17 cm*? in the superjunction drift
layer and 5E16 cm”? in the channel region. The p-type shell
was 70 nm thick and had a doping concentration of SE17
cm” in the channel region and 1E17 cm-? in the superjunc-
tion drift region. The Al mole fraction of the p-type shell
layer was 0.15.

Example 2

[0068] Semiconductor device modeling showed that using
an Al,Ga,,.N shell with Al mole fraction x decreased
leakage current flowing through the gate contact. This
allows higher gate biases to enhance the channel conduc-
tance and drain current without causing the gate p-n junction
to become forward biased. Simulations showed that Al mole
fraction x=0.1-0.2 produced reduction of the parasitic gate
leakage current, as shown in FIG. 7.

[0069] While one or more embodiments have been shown
and described, modifications and substitutions may be made
thereto without departing from the spirit and scope of the
invention. Accordingly, it is to be understood that the present
invention has been described by way of illustrations and not
limitation. Embodiments herein can be used independently
or can be combined.

[0070] All ranges disclosed herein are inclusive of the
endpoints, and the endpoints are independently combinable
with each other. The ranges are continuous and thus contain
every value and subset thereof in the range. Unless other-
wise stated or contextually inapplicable, all percentages,
when expressing a quantity, are in mole fractions. The suffix
(s) as used herein is intended to include both the singular and
the plural of the term that it modifies, thereby including at
least one of that term (e.g., the colorant(s) includes at least
one colorants). Option, optional, or optionally means that
the subsequently described event or circumstance can or
cannot occur, and that the description includes instances
where the event occurs and instances where it does not. As



Patent Application Publication Mar. 2, 2023 Sheet 4 of 7 US 2023/0060711 Al

i. Providing a substrate 102 for epitaxial growth and device fabrication

|

ii, growing a suitable buffer layer 104 to seed subsequent GaN
nanostructure growth

J

iii. depositing and patterning a growth mask 106

iv. growing an n-type GaN nanofin core (108,110,112) at sufficiently high
temperature fo produce only vertical growth and a subsequent p-type
nanofin shell 114 at sufficiently low temperature so to produce growth on
nanofin core sidewalls as part ofa single, uninterrupted epitaxial growth

1

v. etching the nanofin shell 114 to expose the nanofin core source contact
region 112 and planarizing the GaN nanofin core-shell structure by filing
with dielectric material 116

J

vi. etching the dielectric fill to expose the p-contact gate region 110 of the
nanofin shell 114

I

vil. depositing and patterning the gate contact metal 118

i

vill, planarizing the gate contact metal by filing with dielectric material 120
+

ix. etching the dielectric fill to expose the source contact region 112

i

x. depositing and patterning the source metal electrode 122

4

xi. depositing and patterning the drain metal electrode 124 on the substrate
back surface

FIG. 4


US 2023/0060711 Al

of lateral p-n junctions that are hard to produce in GaN
because ion implantation and diffusion doping are not effec-
tive in this material system. Instead, etching and epitaxial
regrowth are used to produce lateral p-n junctions in vertical
GaN transistors. This approach suffers greatly from unin-
tentional contamination of the regrowth interface and device
active area during regrowth, which leads to high electrical
leakage currents, low-voltage breakdown, and difficulties in
engineering the space-charge regions of the p-n junctions.
The core-shell nanofin vertical switch 100 and process for
making the core-shell nanofin vertical switch 100 described
herein overcome these technical shortcomings of conven-
tional technology.

[0015] It has been discovered that a core-shell nanofin
vertical switch 100 described herein provides switching at
high source-to-drain voltages (e.g., greater than 1 kV) at a
low on-state resistance (e.g., less than 0.2 mohm*cm”2) and
with normally-off (enhancement-mode) operation. The core-
shell nanofin vertical switch 100 can be used for high-
efliciency semiconductor power electronics, such as a power
converter or motor driver, e.g., for an electric vehicle.
[0016] Core-shell nanofin vertical switch 100 performs
high-voltage switching. In an embodiment, with reference to
FIG. 1, FIG. 2, and FIG. 3, core-shell nanofin vertical switch
100 includes: n-type GaN nanofin core 107 including: n-type
drift layer 108 arranged at drain terminus 103 of n-type GaN
nanofin core 107 and including GaN; n-type channel 110
disposed on n-type drift layer 108 and including GaN; and
n-type source 112 disposed on n-type channel layer 110,
arranged at source terminus 101, and including GaN, such
that n-type channel 110 is interposed between n-type source
112 and n-type drift layer 108; p-type nanofin shell 114
disposed on n-type GaN nanofin core 107, surrounding
n-type GaN nanofin core 107 at interface surface 105 of
n-type GaN nanofin core 107, and including GaN; source
contact 122 disposed on n-type GaN nanofin core 107 and
p-type nanofin shell 114 and in electrical communication
with n-type source 112, such that n-type source 112 is
interposed between source contact 122 and n-type channel
110; and gate contact 118 disposed on p-type nanofin shell
114 and in electrical communication with p-type nanofin
shell 114, such that p-type nanofin shell 114 is interposed
between gate contact 118 and n-type channel 110, and gate
contact 118 is interposed between source contact 122 and
drain contact 124,

[0017] Core shell nanofin vertical switch 100 can be used
asa digital switch or as an analog switch, wherein core shell
nanofin vertical switch 100 can operate as an on/off switch
for electrical isolation or conduction, or wherein core shell
nanofin vertical switch 100 can operate as an analog device
to provide continuity in varying an amount of electrical
current being supplied by core shell nanofin vertical switch
100, e.g., to modulate electrical current such as providing
modulated current to a motor.

[0018] In an embodiment, core-shell nanofin vertical
switch 100 includes substrate 102 disposed on n-type drift
layer 108 proximate to drain terminus 103 and distal to
source terminus 101, such that n-type drift layer 108 is
interposed between substrate 102 and n-type channel 110,
and n-type drift layer 108 and p-type nanofin shell 114
longitudinally extend away from substrate 102 toward
source terminus 101.

[0019] In an embodiment, core-shell nanofin vertical
switch 100 includes buffer layer 104 disposed on n-type drift

Mar. 2, 2023

layer 108 proximate to drain terminus 103 and distal to
source terminus 101, such that he buffer layer 104 is
interposed between substrate 102 and n-type drift layer 108.
In an embodiment, buffer layer 104 provides a crystallo-
graphic template for epitaxial growth of n-type drift layer
108.

[0020] In an embodiment, core-shell nanofin vertical
switch 100 includes growth mask 106 disposed on buffer
layer 104, such that growth mask 106 is interposed between
buffer layer 104 and p-type nanofin shell 114. In an embodi-
ment, growth mask 106 electrically isolates buffer layer 104
and p-type nanofin shell 114.

[0021] In an embodiment, core-shell nanofin vertical
switch 100 includes gate-drain dielectric fill 116 disposed on
p-type nanofin shell 114 and interposed between growth
mask 106 and gate contact 118. In an embodiment, gate-
drain dielectric fill 116 electrically isolates gate contact 118
and buffer layer 104.

[0022] In an embodiment, core-shell nanofin vertical
switch 100 includes source-gate dielectric fill 120 disposed
on gate contact 118, such that source-gate dielectric fill 120
is interposed between source contact 122 and gate contact
118. In an embodiment, source-gate dielectric fill 120 elec-
trically isolates gate contact 118 and source contact 122.

[0023] In an embodiment, core-shell nanofin vertical
switch 100 includes drain contact 124 disposed on substrate
102, such that substrate 102 is interposed between drain
contact 124 and n-type drift layer 108. In an embodiment,
drain contact 124 is in electrical communication via ohmic
contact with substrate 102 and n-type drift layer 108.
[0024] In an embodiment, source contact 122 is absent in
core-shell nanofin vertical switch 100, and core-shell
nanofin vertical switch 100 is a diode. In this configuration,
core-shell nanofin vertical switch 100 can be used for
rectification.

[0025] In an embodiment, core-shell nanofin vertical
switch 100 includes source contact 122, and core-shell
nanofin vertical switch 100 is a transistor. Accordingly,
core-shell nanofin vertical switch 100 is a three-terminal,
gallium-nitride transistor that controls electrical power.

[0026] It is contemplated that core-shell nanofin vertical
switch 100 has a fin-based geometry and can be made by
epitaxial growth that produces core-shell GaN nanostruc-
tures. N-type GaN nanofin core 107 can be grown under
conditions that only produces growth in a longitudinal
direction (also referred to as vertical growth) of n-type GaN
nanofin core 107 with respect to substrate 102. Such growth
can occur via a process described in U.S. Pat. No. 9,460,921,
which is incorporated by reference herein in its entirety.
P-type nanofin shell 114 is grown under conditions that
produce uniform deposition on the sidewalls of n-type GaN
nanofin core 107 at interface surface 105. The resulting
-n junction at interfa 05 at the top
section of the fin proximate to source terminus 101 is a
junction field effect transistor (FET), wherein the gate
contact voltage is used to deplete or accumulate charge
carriers in the n-type transistor channel, which produces the
switching action of the transistor. Moreover, the arrange-
ment of the components of n-type GaN nanofin core 107 and
p-type nanofin shell 114 are configured as compatible with
superjunction formation in which the doping in n-type GaN
nanofin core 107 and p-type nanofin shell 114 are charge-
balanced with opposite doping types (n-type vs. p-type).



US 2023/0060711 Al

Mar. 2, 2023 Sheet 6 of 7

tion Publication

Patent Applica

3 —

(wary) WeEsND B21S-HO

Drain Voltage (V)

FIG. 6


Patent Application Publication Mar. 2, 2023 Sheet 5 of 7 US 2023/0060711 Al

<>
=
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1 i ’ T T T f

<> ~ oo
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¥ ¥ E3

rm
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Drain Current (A/com* )
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Gate Voltage (V)

FIG. 5


US 2023/0060711 Al

CORE-SHELL NANOFIN VERTICAL
SWITCH AND HIGH-VOLTAGE SWITCHING

CROSS REFERENCE TO RELATED
APPLICATIONS

[0001] This application claims the benefit of U.S. Provi-
sional Patent Application Ser. No. 63/236,897 (filed Aug. 25,
2021), which is herein incorporated by reference in its
entirety.

STATEMENT REGARDING FEDERALLY,
SPONSORED RESEARCH

[0002] This invention was made with United States Gov-
ernment support from the National Institute of Standards and
‘Technology (NIST), an agency of the United States Depart-
ment of Commerce. The Government has certain rights in
this invention.

BRIEF DESCRIPTION

[0003] Disclosed is a core-shell nanofin vertical switch for
high-voltage switching, the core-shell nanofin vertical
switch comprising: an n-type GaN nanofin core comprising
an n-type drift layer arranged at a drain terminus of the
n-type GaN nanofin core and comprising GaN; an n-type
channel disposed on the n-type drift layer and comprising
GaN; and an n-type source disposed on the n-type channel
layer, arranged at a source terminus, and comprising GaN,
such that the n-type channel is interposed between the n-type
source and the n-type drift layer; a p-type nanofin shell
disposed on the n-type GaN nanofin core, surrounding the
n-type GaN nanofin core at an interface surface of the n-type
GaN nanofin core, and comprising GaN; an optional source
contact disposed on the n-type GaN nanofin core and the
p-type nanofin shell and in electrical communication with
the n-type source, such that the n-type source is interposed
between the source contact and the n-type channel; and a
gate contact disposed on the p-type nanofin shell and in
electrical communication with the p-type nanofin shell, such
that the p-type nanofin shell is interposed between the gate
contact and the n-type channel, and the gate contact is
interposed between the source contact and a drain contact.
[0004] Disclosed is a process for high-voltage switching
with a core-shell nanofin vertical switch, the process com-
prising: receiving, by a drain contact of a core-shell nanofin
vertical switch, a drain voltage, the core-shell nanofin ver-
tical switch comprising: an n-type GaN nanofin core com-
prising: an n-type drift layer arranged at a drain terminus of
the n-type GaN nanofin core and comprising GaN; an n-type
channel disposed on the n-type drift layer and comprising
GaN; and an n-type source disposed on the n-type channel
layer, arranged at a source terminus, and comprising GaN,
such that the n-type channel is interposed between the n-type
source and the n-type drift layer; a p-type nanofin shell
disposed on the n-type GaN nanofin core, surrounding the
n-type GaN nanofin core at an interface surface of the n-type
GaN nanofin core, and comprising GaN; an optional source
contact disposed on the n-type GaN nanofin core and the
p-type nanofin shell and in electrical communication with
the n-type source, such that the n-type source is interposed
between the source contact and the n-type channel; a gate
contact disposed on the p-type nanofin shell and in electrical
communication with the p-type nanofin shell, such that the
p-type nanofin shell is interposed between the gate contact

Mar. 2, 2023

and the n-type channel, and the gate contact is interposed
between the source contact and the drain contact; and the
drain contact disposed on the n-type drift layer, such that the
drain contact is in electrical communication via ohmic
contact with the n-type drift layer; turning on the core-shell
nanofin vertical switch by: receiving, by the gate contact, a
gate voltage that is positive with respect to a ground poten-
tial; accumulating electron charge carriers in the n-type GaN
nanofin core in response to receiving the gate voltage:
flowing electrical current between the source contact and the
drain contact in response to accumulating electron charge
carriers; turning off the core-shell nanofin vertical switch by:
receiving, by the gate contact, the gate voltage that is at
ground potential or negative with respect to a ground
potential; depleting the electron charge carriers from the
n-type GaN nanofin core in response to receiving the gate
voltage at ground potential or negative with respect to a
ground potential; and terminating flow of electrical current
between the source contact and the drain contact in response
to depleting the electron charge carriers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The following description cannot be considered
limiting in any way. Various objectives, features, and advan-
tages of the disclosed subject matter can be more fully
appreciated with reference to the following detailed descrip-
tion of the disclosed subject matter when considered in
connection with the following drawings, in which like
reference numerals identify like elements.

[0006] FIG. 1 shows a core-shell nanofin vertical switch,
according to some embodiments.

[0007] FIG. 2 shows: (A) a perspective view of a core-
shell nanofin vertical switch; and (B) electrical connections
for a plurality of core-shell nanofin vertical switches,
according to some embodiments.

[0008] FIG. 3 shows formation of a core-shell nanofin
vertical switch, according to some embodiments.

[0009] FIG. 4 shows a flowchart for making a core-shell
nanofin vertical switch, according to some embodiments.
[0010] FIG. 5 shows a graph of drain current versus gate
voltage for a core-shell nanofin vertical switch, according to
some embodiments.

[0011] FIG. 6 shows a graph of off-state current versus
drain voltage for a core-shell nanofin vertical switch, accord-
ing to some embodiments.

[0012] FIG. 7 shows a graph of current versus gate bias for
a core-shell nanofin vertical switch, according to some
embodiments.

DETAILED DESCRIPTION,

[0013] A detailed description of one or more embodiments
is presented herein by way of exemplification and not
limitation.

[0014] There is a need for a semiconductor transistor that
can handle a large voltage (c.g., greater than I kV) with a
low resistive loss. Such a transistor can be used in power
electronics such as converters or motor drivers. Gallium.
nitride has materials properties that include high electron
mobility and a large breakdown field that make it a candidate
for high-power transistors. However, it is difficult to make
GaN transistors with a vertical architecture for use in power
electronics devices, where current flows normal to the wafer
surface. Vertical transistor architectures involve fabrication


as) United States
a2) Patent Application Publication co) Pub. No.: US 2023/0060711 Al

US 2023006071 1A1

Bertness et al. (43) Pub. Date: Mar. 2, 2023
(54) CORE-SHELL NANOFIN VERTICAL HOLL 29/20 (2006.01)
SWITCH AND HIGH-VOLTAGE SWITCHING HOLL 29/205 (2006.01)
HOLL 29/66 (2006.01)
(71) Applicant: Government of the United States of (52) US. CL
America, as represented by the CPC HOLL 29/7788 (2013.01); HO3K 17/6871
Secretary of Commerce, Gaithersburg, (2013.01); HOIL 29/0634 (2013.01); HOLL
MD (US) 29/2003 (2013.01); HOIL 29/205 (2013.01);
HOLL 29/6462 (2013.01)
(72) Inventors: Kristine Ann Bertness, Boulder, CO
(US); Matthew David Brubaker, . .
Louisville, CO (US); Patrick John 67) ABSTRACT
Fay, Granger, IN (US) ‘A core-shell nanofin vertical switch performs high-voltage
(21) Appl. No.: 17/821,977 switching and includes: an n-type GaN nanofin core includ-
ing: an n-type drift layer; an n-type channel; and an n-type
(22) Filed: Aug. 24, 2022 source; a p-type nanofin shell surrounding the n-type GaN
nanofin core at an interface surface of the n-type GaN
Related U.S. Application Data nanofin core, and comprising GaN; an optional source
: . contact disposed on the n-type GaN nanofin core and the
(60) Provisional application No. 63/236,897, filed on Aug. type nanofin shell and in electrical communication with
25, 2021. the n-type source, such that the n-type source is interposed
Publication Classification between the source contact and the n-type channel; and a
° gate contact disposed on the p-type nanofin shell and in
(51) Int. Cl. electrical communication with the p-type nanofin shell, such
HOLL 29/778 (2006.01) that the p-type nanofin shell is interposed between the gate
HO3K 17/687 (2006.01) contact and the n-type channel, and the gate contact is
HOLL 29/06 (2006.01) interposed between the source contact and a drain contact.
100

longitudinal
Zz

y transverse



US 2023/0060711 Al

a lower growth temperature), wherein growth occurs in both
the vertical (i.e., longitudinal) and horizontal (i.c., lateral or
transverse) directions. P-type doping can occur by including
magnesium during GaN growth. P-type nanofin shell 114
can include aluminum to form the wide-bandgap ternary
compound AlGaN to decrease gate leakage current and to
increase the on-state gate voltage of core-shell nanofin
vertical switch 100. P-type doping in AIGaN can occur by
including magnesium or beryllium during AlGaN growth.

[0038] In an embodiment, p-type nanofin shell 114 con-
sists essentially of aluminum, gallium, and nitrogen. In an
embodiment, the aluminum, gallium, and nitrogen of p-type
nanofin shell 114 includes AlxGal-xN, wherein x is a
nonnegative real number from 0 to 1.0.

[0039] N-type drift layer 108, n-type channel 110, n-type
source 112, and p-type nanofin shell 114 in combination
provide a core-shell GaN nanofin vertical switch. In an
embodiment, with reference to FIG. 2, a plurality of indi-
vidual core-shell GaN nanofin vertical switches (100.1,
100.2, ... , 100.n) can be disposed on substrate 102 and
operated in parallel to obtain device operation at higher
electrical currents.

[0040] Gate-drain dielectric fill 116 is interposed between
gate contact 118 and p-type nanofin shell 114 to provide
electrical isolation and mechanical support between gate
contact 118, buffer layer 104, and proximate core-shell GaN
nanofin vertical switches (e.g., 100.2, etc.) in array of such
switches, Gate-drain dielectric fill 116 or source-gate dielec-
tric fill 120 can electrically insulating, have high electrical
breakdown endurance, and have good mechanical or thermal
stability. Exemplary dielectric material for gate-drain dielec-
tric fill 116 or source-gate dielectric fill 120 includes ben-
zocyclobutene (BCB), silicon dioxide, silicon nitride, and
the like, which can be selectively etched and planarized
using reactive ion etching (eg., with SF,/O,). A material
with high thermal conductivity such as diamond can be used
as a dielectric material.

[0041] Gate contact 118 is in electrical communication
with p-type nanofin shell 114 that is in electrical commu-
nication with n-type channel 110. Gate contact 118 can be a
global gate contact for a plurality of individual core-shell
GaN nanofin vertical switches arranged in an array. Gate
contact can be an electrically conductive metal layer formed
(e.g., by deposition) on p-type nanofin shell 114. P-contacts
to GaN and AlGaN can include nickel or gold for ohmic
contact. It is contemplated that non-ohmic contacts can be
used for gate contact 118.

[0042] Source-gate dielectric fill 120 provides electrical
isolation between gate contact 118 and source contact 122
and can include a suitable dielectric material or this purpose.
[0043] Source contact 122 makes ohmic electrical contact
with n-type source 112 and can be an electrically conductive
metal layer deposited on n-type source 112. N-contacts to
GaN can include titanium/aluminum metallization for ohmic
contact. Low-resistance, ohmic-contact is made by source
contact 122 to the n-type source 112. Such metallization can
be non-ohmic with respect to p-type nanofin shell 114 and
electrical current from the source contact metal flows only
into n-type source 112. In some embodiments, p-type
nanofin shell 114 can be absent proximate to source contact
122.

[0044] Drain contact 124 makes ohmic electrical contact
to substrate 102 and electrical contact to n-type GaN nanofin
core 107 via substrate 102 and buffer layer 104, Drain

Mar. 2, 2023

contact 124 can be an electrically conductive metal layer
deposited on substrate 102 to provide a low-resistance,
ohmic-contact. Drain contact 124 can made proximate to
buffer layer 104 in a region not covered by core-shell
nanofin vertical switches 100.

[0045] Core-shell nanofin vertical switch 100 can be made
in various ways. It should be appreciated that core-shell
nanofin vertical switch 100 includes a number of compo-
nents, wherein such components can be interconnected and
placed in electrical communication or electrical isolation. It
should be appreciated that core-shell nanofin vertical switch
100 can be disposed in a terrestrial environment or space
environment. Elements of core-shell nanofin vertical switch
100 can be formed from materials such as silicon, silicon
nitride, sapphire, and the like although other suitable mate-
rials can be used. Accordingly, core-shell nanofin vertical
switch 100 can be made by additive or subtractive manu-
facturing. In an embodiment, elements of core-shell nanofin
vertical switch 100 are selectively etched to remove various
different materials using different etchants and photolitho-
graphic masks and procedures. In some embodiments, vari-
ous layers thus formed can be subjected to joining by
bonding to form core-shell nanofin vertical switch 100.
[0046] In an embodiment, with reference FIG. 3 and FIG.
4, a process for making core-shell nanofin vertical switch
100 includes: (i) providing substrate 102 to be subjected to
forming (e.g... epitaxial growth) switch elements thereon; (ii)
optionally forming buffer layer 104 as a seed for forming
GaN nanostructure (optional, based on substrate 102); (iii)
forming and patterning growth mask 106; (iv) forming
n-type GaN nanofin core 107 by forming n-type drift layer
108 on substrate 102, n-type channel 110 on n-type drift
layer 108, and n-type source 112 on n-type channel 110;
optionally modulating n-type doping concentration along
n-type drift layer 108 on substrate 102, n-type channel 110
on n-type drift layer 108, and n-type source 112; optionally
forming undoped nanofin shell on n-type GaN nanofin core
107; and forming p-type nanofin shell 114 on n-type GaN
nanofin core 107, such that forming n-type GaN nanofin core
107 and p-type nanofin shell 114 can occur in an uninter-
rupted epitaxial growth; (v) planarizing n-type GaN nanofin
core 107 and p-type nanofin shell 114 (also referred to as the
GaN nanofin core-shell structure) by forming dielectric
material as gate-drain dielectric fill 116 at shell fin surface
109; (vi) etching gate-drain dielectric fill 116 to expose a
portion of p-type nanofin shell 114 disposed at n-type
channel 110; (vii) forming and patterning gate contact 118
on the exposed portion of p-type nanofin shell 114 disposed
at n-type channel 110; (viii) planarizing gate contact 118 by
forming source-gate dielectric fill 120 on gate contact 118;
(ix) etching source-gate dielectric fill 120 at source terminus
101 so that source-gate dielectric fill 120 exposes a portion
of p-type nanofin shell 114 and n-type source 112 at source
terminus 101; (x) forming and patterning source contact 122
‘on the exposed portion of p-type nanofin shell 114 and
n-type source 112 at source terminus 101; and (xi) forming
and patterning drain contact 124 on substrate 102 such that
substrate 102 is interposed between drain contact 124 and
n-type drift layer 108 to form core-shell nanofin vertical
switch 100, core-shell nanofin vertical switch 100 e.g., as
shown in FIG. 1 and FIG. 2.

[0047] In an embodiment, n-type drift layer 108, n-type
channel 110, n-type source 112, and p-type nanofin shell 114
are formed via continuous growth. This continuous core-



US 2023/0060711 Al

This superjunction can withstand high source-drain voltages
without electrical breakdown.

[0027] It should be appreciated that core-shell nanofin
vertical switch 100 can have elements present and arranged
to provide a JFET or superjunction. However, while the
superjunction is an advantageous and useful subcomponent,
such is optional for operation of core-shell nanofin vertical
switch 100 as a transistor or the clean interfaces of the
core-shell structure (provided by n-type GaN nanofin core
107 and p-type nanofin shell 114).

[0028] In an embodiment, with reference to FIG. 2, core-
shell nanofin vertical switch 100 includes a plurality of
switches (100.1, 100.2,..., 100.7, wherein n is an arbitrary
positive non-zero integer that indexes the number of such
switches). The switches can be arranged in an array of
regular or irregular spacing or patterns. An exemplary
arrangement is a linear array or two-dimensional array of
switches that can be individually and selectively addressed
and independently or synchronously switched together.
[0029] Core-shell nanofin vertical switch 100 includes
various elements and components that can be, e.g., micro-
fabricated. Elements of core-shell nanofin vertical switch
100 can be various sizes. Elements of core-shell nanofin
vertical switch 100 can be made of a material that is
physically or chemically resilient in an environment in
which core-shell nanofin vertical switch 100 is disposed
without impairing high-voltage switching of core-shell
nanofin vertical switch 100. Exemplary materials include
semiconductor, electrically conductive, and dielectric mate-
rials, dopants, and the like. The elements of n-type GaN
nanofin core 107 can be made of the same or different
material.

[0030] Substrate 102 provides a structure upon which
other elements of core-shell nanofin vertical switch 100 can
be formed. Substrate 102 is electrically conductive to con-
duct electrical current between buffer layer 104 and drain
contact 124. Exemplary materials for substrate include semi-
conductor materials such as highly doped silicon, silicon
carbide, or sapphire.

[0031] Buffer layer 104 is formed on substrate 102 and
provides a crystallographic template for epitaxial growth of
n-type GaN nanofin core 108. Buffer layer 104 can be
electrically conductive to communicate electrical current
between n-type GaN nanofin core 108 and substrate 102
Buffer layer 104 can be a planar AIN/GaN layer, where the
AIN layer (¢.g., from about 1 nm to 40 nm thick) provides
crystallographic alignment to substrate 102, and GaN (e.g..
about 300 nm thick) provides an electrically conductive
crystal template for GaN nanostructure growth.

[0032] Growth mask 106 is formed and patterned on
buffer layer 104 and includes a portion that delineates a
footprint of GaN nanofin core 108 during epitaxial growth.
Growth mask 106 can include a dielectric material to
electrically isolate buffer layer 104 from GaN nanofin shell
114. The dielectric material can be, ¢.g., silicon nitride (e.g.,
from about 25 nm to 70 nm thick) or silicon dioxide. Growth
mask 106 can be formed via deposition, including low-
pressure chemical vapor deposition (LPCVD), plasma-en-
hanced chemical vapor deposition (PECVD), and the like.
‘An opening in a portion of growth mask 106 can be formed
by electron-beam lithography or could or by any lithography
that can make a linewidth that can be, e.g., less than 200 nm.
Such processing can include extreme ultraviolet (EUV)
irradiation, nanoimprinting, and the like.

Mar. 2, 2023

[0033] N-type drift layer 108 can be grown in the pat-
termed mask opening of growth mask 106. It should be
appreciated that n-type drift layer 108 and p-type nanofin
shell 114 provide a p-n junction. Advantageously, the super-
junction drift layer 108 supports high voltage between
source contact 122 and drain contact 124 without electrical
breakdown. The n-type doping concentration can be selected
to enhance superjunction charge balance in n-type drift layer
108. In an embodiment, n-type drift layer 108 consists
essentially of GaN. In an embodiment, n-type drift layer 108
can include dopants disposed in GaN.

[0034] N-type channel 110 can be grown on and with the
same footprint as n-type drift layer 108 to form a p-n
junction with p-type nanofin shell 114. N-type channel 110
‘and p-type nanofin shell 114 can provide a junction field
effect transistor (IFET) that provides switching of electrical
current between source contact 122 and drain contact 124 as
controlled by gate voltage applied to gate contact 118. The
n-type doping concentration of n-type channel 110 can be
selected to enhance switching of n-type channel 110. In an
embodiment n-type channel 110 consists essentially of GaN.
In an embodiment, n-type channel 110 can include dopants
disposed in GaN.

[0035] N-type source 112 can be grown on and with the
same footprint as n-type channel 110. N-type source 112 can
be highly doped with n-type dopant to enhance conductivity
to source contact 122. In an embodiment, n-type source 112
consists essentially of GaN. In an embodiment, n-type
source 112 can include dopants disposed in GaN.

[0036] N-type GaN nanofin core 107 includes n-type drift
layer 108, n-type channel 110, and n-type source 112. N-type
GaN nanofin core 107 can be formed, e.g., grown by
selective area epitaxy, e.g., at a selected growth temperature,
with vertical GaN growth in the opening of growth mask
106, which can provide a constant width along the fin
structure. In this manner, GaN for n-type GaN nanofin core
107 is not growth on an upper surface of growth mask 106.
Plasma-assisted molecular beam epitaxy can be used
although viable techniques can be used such as metal-
organic vapor phase epitaxy (MOVPE or MOCVD) or
hydride vapor phase epitaxy (HVPE). N-type doping occurs
by supplying silicon, germanium, or oxygen during growth
and can be varied during growth of n-type GaN nanofin core
107 to produce different doping concentrations in n-type
drift layer 108, n-type channel 110, or n-type source 112
The nanofins can be grown so as to obtain a select crystal-
lographic orientation such as m-plane (10-10) or a-plane
(11-20) sidewalls. The nanofins can be grown in the N-polar
[000-1] or Ga-polar [0001] orientations.

[0037] P-type nanofin shell 114 can be formed, e.g., grown
conformally, on n-type GaN nanofin core 107 including
exposed surfaces of n-type drift layer 108, n-type channel
110, and n-type source 112 at interface surface 105. P-type
nanofin shell 114 and n-type channel 110 provide a p-n
junction field effect transistor that switches electrical current
between source contact 122 and drain contact 124 as con-
trolled by gate voltage received by gate contact 118. P-type
nanofin shell 114 can include of a wider bandgap AlGaN to
reduce leakage current between gate contact 118 and source
contact 122. This increases the on-state gate voltage of the
p-n junction field effect transistor and reduces the on-state
resistance. It is contemplated that p-type nanofin shell 114 is
grown over n-type GaN nanofin core 107 (108,110,112) as
a continuation of the growth process and at conditions (e.g.



Patent Application Publication Mar. 2, 2023 Sheet 7 of 7 US 2023/0060711 Al

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US 2023/0060711 Al

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Mar. 2, 2023 Sheet 3 of 7

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US 2023/0060711 Al

used herein, combination is inclusive of blends, mixtures,
alloys, reaction products, collection of elements, and the
like.
[0071] As used herein, a combination thereof refers to a
combination comprising at least one of the named constitu-
ents, components, compounds, or elements, optionally
together with one or more of the same class of constituents,
components, compounds, or elements.
[0072] All references are incorporated herein by reference.
[0073] The use of the terms “a,” “an,” and “the” and
similar referents in the context of describing the invention
(especially in the context of the following claims) are to be
construed to cover both the singular and the plural, unless
otherwise indicated herein or clearly contradicted by con-
text. It can further be noted that the terms first, second,
primary, secondary, and the like herein do not denote any
order, quantity, or importance, but rather are used to distin-
guish one element from another. It will also be understood
that, although the terms first, second, etc. are, in some
instances, used herein to describe various elements, these
elements should not be limited by these terms. For example,
a first current could be termed a second current, and,
similarly, a second current could be termed a first current,
without departing from the scope of the various described
embodiments. The first current and the second current are
both currents, but they are not the same condition unless
explicitly stated as such.
[0074] The modifier about used in connection with a
quantity is inclusive of the stated value and has the meaning
dictated by the context (e.g., it includes the degree of error
associated with measurement of the particular quantity). The
conjunction or is used to link objects of a list or alternatives
and is not disjunctive; rather the elements can be used
separately or can be combined together under appropriate
circumstances.
What is claimed is:
1. A core-shell nanofin vertical switch for high-voltage
switching, the core-shell nanofin vertical switch comprising:
an n-type GaN nanofin core comprising:
an n-type drift layer arranged at a drain terminus of the
n-type GaN nanofin core and comprising GaN;
an n-type channel disposed on the n-type drift layer and
comprising GaN; and
an n-type source disposed on the n-type drift layer,
arranged at a source terminus, and comprising GaN,
such that the n-type channel is interposed between
the n-type source and the n-type drift layer;
p-type nanofin shell disposed on the n-type GaN nanofin
core, surrounding the n-type GaN nanofin core at an
interface surface of the n-type GaN nanofin core, and
comprising GaN:
an optional source contact disposed on the n-type GaN
nanofin core and the p-type nanofin shell and in elec-
trical communication with the n-type source, such that
the n-type source is interposed between the source
contact and the n-type channel; and
‘a gate contact disposed on the p-type nanofin shell and in
electrical communication with the p-type nanofin shell,
such that the p-type nanofin shell is interposed between
the gate contact and the n-type channel, and the gate
contact is interposed between the source contact and a
drain contact.

Mar. 2, 2023

2. The core-shell nanofin vertical switch of claim 1,
wherein the source contact is present, and the core-shell
nanofin vertical switch is a transistor.

3. The core-shell nanofin vertical switch of claim 1,
wherein the source contact is absent, and the core-shell
nanofin vertical switch is a diode.

4. The core-shell nanofin vertical switch of claim 1,
further comprising a substrate disposed on the n-type drift
layer proximate to the drain terminus and distal to the source
terminus, such that the n-type drift layer is interposed
between the substrate and the n-type channel, and the n-type
drift layer and the p-type nanofin shell longitudinally extend
away from the substrate toward the source terminus.

5. The core-shell nanofin vertical switch of claim 4,
further comprising a buffer layer disposed on the n-type drift
layer proximate to the drain terminus and distal to the source
terminus, such that the bufler layer is interposed between the
substrate and the n-type drift layer.

6. The core-shell nanofin vertical switch of claim 5,
wherein the buffer layer provides a crystallographic template
for epitaxial growth of the n-type drift layer.

7. The core-shell nanofin vertical switch of claim 5,
further comprising a growth mask disposed on the buffer
layer, such that the growth mask is interposed between the
buller layer and the p-type nanofin shell

8. The core-shell nanofin vertical switch of claim 7,
wherein the growth mask electrically isolates the buffer
layer and the p-type nanofin shell.

9. The core-shell nanofin vertical switch of claim 7,
further comprising a gate-drain dielectric fill disposed on the
p-type nanofin shell and interposed between the growth
mask and the gate contact.

10. The core-shell nanofin vertical switch of claim 9,
wherein the gate-drain dielectric fill electrically isolates the
gate contact and the buffer layer.

11. The core-shell nanofin vertical switch of claim 6,
further comprising a source-gate dielectric fill disposed on
the gate contact, such that the source-gate dielectric fill is
interposed between the source contact and the gate contact.

12. The core-shell nanofin vertical switch of claim 11,
wherein the source-gate dielectric fill electrically isolates the
gate contact and the source contact.

13. The core-shell nanofin vertical switch of claim 4,
further comprising a drain contact disposed on the substrate,
such that the substrate is interposed between the drain
contact and the n-type drift layer.

14. The core-shell nanofin vertical switch of claim 13,
wherein the drain contact is in electrical communication via
ohmic contact with the substrate and the n-type drift layer.

15. The core-shell nanofin vertical switch of claim 1,
wherein the n-type drift layer consists essentially of GaN.

16. The core-shell nanofin vertical switch of claim 1,
wherein the n-type channel consists essentially of GaN.

17. The core-shell nanofin vertical switch of claim 1.
wherein the n-type source consists essentially of GaN.

18. The core-shell nanofin vertical switch of claim 1,
wherein the p-type nanofin shell consists essentially of
aluminum, gallium, and nitrogen.

19. The core-shell nanofin vertical switch of claim 1,
wherein the aluminum, gallium, and nitrogen of the p-type
nanofin shell comprises Al,Ga,_,N, wherein x is a nonnega-
tive real number from 0 to 1.0.

20. A process for high-voltage switching with a core-shell
nanofin vertical switch, the process comprising:



Patent Application Publication Mar. 2, 2023 Sheet 2 of 7 US 2023/0060711 Al

{A) 100
Ce me 2 a ‘ source (S)

gate (G)
drain (D)
longitudinal
lateral %
transverse
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source (load) gate (control signal)

drain (supply)

FIG. 2


Patent Application Publication Mar. 2, 2023 Sheet 1 of 7 US 2023/0060711 Al

100
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105
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109
longitudinal

z iA

L. transverse

FIG. 1


US 2023/0060711 Al

shell growth avoids defects and impurities that can occur
during other etch-and-regrowth based device architectures
or formation processes. These deleterious etch-and regrowth
processes incorporate parasitic defects and impurities in the
device active region and adversely affect transistor perfor-
mance. The process for making core-shell nanofin vertical
switch 100 includes bottom-up growth of GaN nanostruc-
tures (107, 114) that also produces nearly defect-free GaN
fins, regardless of the growth substrate and makes structures
that are not limited by the defect structure. This provides a
cost advantage because GaN nanofins can be made on
inexpensive substrates (e.g., silicon) that may not be suitable
for producing high-quality epitaxial structures by conven-
tional planar growth techniques.

[0048] The process for making core-shell nanofin vertical
switch 100 provides a vertical gallium-nitride-based switch
(e.g. a diode or transistor) with core-shell structure that does
not involve selective area regrowth at the p-n junction and
avoids performance-reducing contamination in the device
active area.

[0049] In making core-shell nanofin vertical switch 100,
growing n-type GaN nanofin core 107 occurs at tempera-
tures sufliciently high to produce only vertical growth (with
optional modulation of n-type doping concentration along
nanofin height to form drift 108, channel 110, and source
contact 112 regions) and subsequently growing a p-type
nanofin shell 114 (with optional Al mole fraction) at sufli-
ciently low temperatures to produce growth on nanofin core
sidewalls. The process can include growth of an undoped or
lightly n-doped nanofin shell between the n-type core and
p-type shell as part the single, uninterrupted epitaxial growth
of n-type GaN nanofin core 107 and p-type nanofin shell
114.

[0050] The process for making core-shell nanofin vertical
switch 100 can includes various conditions and steps
described in U.S. Pat. No. 9,460,921, which is incorporated.
by reference herein in its entirety.

[0051] In making core-shell nanofin vertical switch 100,
providing substrate 102 involves using a substrate with
suitable crystal structure to be a template for epitaxial GaN
growth. Exemplary substrates include silicon, silicon car-
bide, silicon-on-insulator, bulk GaN, and sapphire. Substrate
102 can be electrically conductive to communicate electrical
current through substrate 102. When substrate 102 is not
electrically conductive, current flows through electrically
conductive buffer layer 104 to a drain contact located on a
portion of buffer 104 surface that is free of core-shell nanofin
vertical switches 100.

[0052] Growing of a buffer layer provides a crystallo-
graphic template for subsequently grown GaN nanofins.
Buffer layers can include a thin AIN layer (e.g., from 1 nm
to 40 nm thick) to improve orientation of epitaxial material
to the substrate and a thicker (e.g., about 350 nm thick) GaN
layer that allows for homoepitaxial growth of GaN nanofins
‘As a result, the buffer layer is electrically conducting to
communicate electrical current in the longitudinal (ic.,
vertical) direction and lateral direction.

[0053] Depositing a patterned growth mask defines the
footprint of the GaN nanofins. The growth mask is a
dielectric and can be silicon nitride or silicon dioxide, The
growth mask can be electrically insulating and can have a
eg., of about 70 nm. The growth mask can be a
single material or a combination of dielectric layers (c.g... a
silicon dioxide/silicon nitride stack).

Mar. 2, 2023

[0054] Growing an n-type GaN nanofin core by a selective
area epitaxy growth can occur via molecular beam epitaxy,
metal-organic vapor phase epitaxy, metal organic chemical
vapor deposition, or hydride vapor phase epitaxy. In this
step, the GaN epitaxy is carried out at a high growth
temperature, wherein GaN growth on the mask surface is
inhibited, and the GaN growing in the patterned nanofin
mask opening occurs only in the vertical direction. N-type
doping levels can be modulated during core growth to
produce distinct drift, channel, and source contact regions.
The n-type dopant can be silicon or germanium or oxygen.
The nanofin can be oriented to produce (10-10) m-planes or
(11-20) a-planes. The fin growth direction can be in the
[000-1] N-polar or [0001] Ga-polar directions.

[0055] Growing p-type nanofin shell 114 occurs as part of
uninterrupted epitaxial growth subsequent to formation of
n-type GaN nanofin core 107. The substrate is not removed
from the growth reactor between the core and shell steps of
the growth process. The growth of the shell phase proceeds
at a temperature low enough to grow p-type GaN on the
n-type core 107 sidewalls at interface surface 105, creating
acore-shell p-n junction. This eliminates contamination that
can occur in conventional etch-and-regrowth fin-based pro-
cessing. Such also is consistent with formation of lateral p-n
junctions for a superjunction drift layer. P-type nanofin shell
114 can be AlGaN to reduce gate leakage current and
increase the allowable on-state gate voltage of core-shell
nanofin vertical switch 100. A lightly-doped n-type or
undoped shell can be grown between n-type GaN nanofin
core 107 and p-type nanofin shell 114.

[0056] As a result of making core-shell nanofin vertical
switch 100 in accordance with the above process, the p-n
junction core-shell nanofin (107, 114) is formed with epi-
taxial structure in vertical configuration with a superjunction
drift layer 108.

[0057] In an embodiment, core-shell nanofin vertical
switch 100 is prepared according to the following. To
provide a low-cost silicon wafer and grow an AIN (5
nm)/GaN (350 nm) buffer layer, a 70 nm thick silicon nitride
growth mask is patterned by electron beam lithography to
form mask openings of ~160 nmx5000 nm that form the
footprint of the n-type GaN nanofins. The GaN nanofin
n-type cores are then grown by molecular beam epitaxy at a
growth temperature exceeding 850° C. and to a height of
5000 nm. Without removing the wafer from the growth
reactor, the growth temperature is lowered to 700° C. to
grow a 70 nm thick p-type shell as part of a continuous
core-shell growth.

[0058] Core-shell nanofin vertical switch 100 has numer-
ous advantageous and unexpected benefits and uses. In an
embodiment, a process for high-voltage switching with
core-shell nanofin vertical switch 100 includes: receiving,
by drain contact 124 of core-shell nanofin vertical switch
100, drain voltage, the core-shell nanofin vertical switch 100
including: n-type GaN nanofin core 107 including: n-type
drift layer 108 arranged at drain terminus 103 of n-type GaN
nanofin core 107 and including GaN: n-type channel 110
disposed on n-type drift layer 108 and including GaN; and
n-type source 112 disposed on n-type channel layer 110,
arranged at source terminus 101, and including GaN, such
that n-type channel 110 is interposed between n-type source
112 and n-type drift layer 108; p-type nanofin shell 114
disposed on n-type GaN nanofin core 107, surrounding
n-type GaN nanofin core 107 at interface surface 105 of



US 2023/0060711 Al

, by a drain contact of a core-shell nanofin
vertical switch, a drain voltage, the core-shell nanofin
vertical switch comprising
an n-type GaN nanofin core comprising:

an n-type drift layer arranged at a drain terminus of
the n-type GaN nanofin core and comprising GaN;

an n-type channel disposed on the n-type drift layer
and comprising GaN; and

an n-type source disposed on the n-type drift layer,
arranged at a source terminus, and comprising
GaN, such that the n-type channel is interposed
between the n-type source and the n-type drift
layer;

a p-type nanofin shell disposed on the n-type GaN
nanofin core, surrounding the n-type GaN nanofin
core at an interface surface of the n-type GaN
nanofin core, and comprising GaN;

an optional source contact disposed on the n-type GaN
nanofin core and the p-type nanofin shell and in
electrical communication with the n-type source,
such that the n-type source is interposed between the
source contact and the n-type channel;

a gate contact disposed on the p-type nanofin shell and
in electrical communication with the p-type nanofin
shell, such that the p-type nanofin shell is interposed
between the gate contact and the n-type channel, and
the gate contact is interposed between the source
contact and the drain contact; and

the drain contact disposed on the n-type drift layer, such
that the drain contact is in electrical communication
via ohmic contact with the n-type drift layer;
turning on the core-shell nanofin vertical switch by:
receiving, by the gate contact, a gate voltage that is
positive with respect to a ground potential;

accumulating electron charge carriers in the n-type
GaN nanofin core in response to receiving the gate
voltage;

flowing electrical current between the source contact
and the drain contact in response to accumulating
electron charge carriers; and

Mar. 2, 2023

turning off the core-shell nanofin vertical switch by:

receiving, by the gate contact, the gate voltage that is at
‘ground potential or negative with respect to a ground
potential;

depleting the electron charge carriers from the n-type
GaN nanofin core in response to receiving the gate
voltage at ground potential or negative with respect
to a ground potential; and

terminating flow of electrical current between the
source contact and the drain contact in response to
depleting the electron charge carriers.

21. The process for high-voltage switching of claim 20,
farther comprising:

placing the source contact and the drain contact in elec-

trical communication and receiving the electrical cur-
rent at the source contact in response to turing on the
core-shell nanofin vertical switch; and

electrically isolating the source contact and the drain

contact in response to turning off the core-shell nanofin
vertical switch.

22. The process for high-voltage switching of claim 20,
wherein a potential difference between the source contact
and the drain contact after the core-shell nanofin vertical
switch is subjected to turning is from 1 V to at least 1500 V,
and the core-shell nanofin vertical switch is configured so
that, without electrical breakdown or damage, the core-shell
nanofin vertical switch withstands the potential difference
between the source contact and the drain contact from 0 V
to at least 1500 V.

23. The process for high-voltage switching of claim 20,
further comprising:

connecting an electrical load in electrical communication

with the source contact, so that the electrical load is:

in electrical communication with the drain contact and
receives the electrical current from the source con-
tact in response to turning on the core-shell nanofin
vertical switch; and

electrically isolated from the drain contact in response
to turning off the core-shell nanofin vertical switch.

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