NIST & SRC Nanoelectronics Research 

Partnership for InnovationDr. Jeff WelserDirector, SRC Nanoelectronics Research InitiativeIBM Almaden Research CenterOctober, 2008
Semiconductor Research Corporation: Collaboratively Sponsored University R

 The Semiconductor Industry Association (SIA) members ha

collaboration among industry, government and academia imeans of advancing university research capabilities

 Strong university research is critical to maintain technology 

 Research in new concepts, breakthrough ideas and solu

which no currently known solutions exist

 Development of talent pool of scientists and engineers

 Semiconductor Research Corporation (SRC) has been estab

collaboratively sponsored university research

 Manages full spectrum of research related to CMOS and 

 Awarded the 2005 National Medal of Technology

 “For building the world’s largest and most successful university

research force to support the ... semiconductor industry ...”
SRC Global Research Collabor

Pre-competitive 

Research

Pre-competitive

Longer Range

Research

C

GRC

–

Global 

Research 

Collaboration

FCRP 

–

Focus 

Center 

Research 

Progra

NRI 

–

Nanoelectronics 

Research Initiat
Scaling Drives the Industry

Smaller features Æ Better performance & 

More apps Æ Larger marke
CMOS Power Issue:Active vs. Passive Power

1 0

0.001

0.01

0.1

1

10

100

1000

Gate Len

Active Power

1994 

S

G

D

Power components:

 Active power Passive power

• Gate leakage• Source - Drain leakage

Polysilicon Gate 10S Tox=11A

S

G

D

Silicon (SOI) Gate Oxide

Power Density (W/cm

2

)

Gate Leng

Air Cooling limit
Implications for Nanoelectronics 

 Circuit heat generation is the main limi

scaling of device speed and switch circu

 Scaling to molecular dimensions may not yie

increases

 We will be forced to trade-off between speed an

 Optimal dimensions for electronic switches s

between 5 and 50 nm

 Likely achievable with Si – easily within the scop

projections

 Going to other materials for FETs will likely a

“one-time” percentage gains

3⁄4 Need a new device mechanism or computa

to enable a new scaling path
Has This Ever Happened Befo

Year of Announcement

1950 1960 1970 1980 1990 2

02468

101214

Bipolar

C

Start of

Water Cooling

 2005 ~ 2015: New technology enhancements

 Continued CMOS shrinking, multi-core chips, 3

new memory devices, etc.

 > 2015? : New device? 

Æ NRI’s Goal

Module Heat Flux(watts/cm2)
NRI Mission Statement

 NRI Mission: Demonstrate novel computing d

replacing the CMOS FET as a logic switch in ttimeframe.

 These devices should show significant advan

FETs in power, performance, density, and/or cosemiconductor industry to extend the historic

performance trends for information technolo

 To meet these goals, NRI pursues five researc

on discovering and demonstrating new devices for doing computation.

 Finally, it is desirable that these technologies be 

integrating with CMOS, to allow exploitation complementary functionality in heterogeneous senable a smooth transition to a new scaling pat
NRI Primary Research Vect

 NEW DEVICE

Device with alternativestate vector

 NEW WAYS TO CONNECT

DEVICESNon-charge data transfer

 NEW METHODS FOR 

COMPUTATIONNon-equilibrium systems

 NEW METHODS TO MANAGE

HEATNanoscale phonon engineering

 NEW METHODS OF FABRICATION

Directed self-assembly devices

A

B

C

Out
Nanoelectronics Research Initiative 

2001-2004: Defining Research Needs

 ITRS-Emerging Research Device Technical Working Group NSF-SRC Ind-Academia-Govt “Silicon Nanoelectronics and Bey

 SIA Technology Strategy Committee workshops

3⁄4Defined 13 Research Vectors for finding the “nex3⁄4SIA Board passes resolution for formation of NRI

March 2005: Six Companies sign NRI ParticipatiSep 2005: First NRI and NRI-NSF Solicitations reJan 2006: Research Programs startedSep 2007: NIST joins NRINRI partnership model highlighted in as sidebar 

Nanotechnology Initiative (NNI) Strategic Plan (
NRI-NSF Interaction:Co-funding Projects at NSF Centers

Columbia NSEC 2006: Non-equilibrium Quantum Coherent Dev

2008: Novel Device Arch. based on Quantum T

UCSB MRSEC (Stanford, U Mass) 2006: Development of Next Generation DeviceHarvard NSEC 2006: Ultrasmall Nanowire and Oxide Switches 2008: Tunable Ultra-fast Conductance SwitchinU. Arkansas/U. Oklahoma MRSEC 2006: Nanoferroelectric Random Access MemoPurdue NCN 2006, 2007: Exploratory Theory, Modeling, and 

2008: Experimental Realization of Low-power T

UVA MRSEC (Notre Dame, UCSB)

2006: Directed Assembly of Epi SemiconductoSwitches; 2007: Coherent Spin Dynamics in SiTowards a Coherent or Quantum Spin Switch

U. Nebraska MRSEC 2007: Multiferroic Interfaces: New Paradigms foYale MRSEC 2007: Design and Fab of Magnetic-based DeviMaryland MRSEC (UT Austin) 2007: Pseudospintronics 2008: Controlling the Electronic Properties of GCornell NSEC 2007: Controlled Orbital Hybridization in the CNStanford NSEC (UT Austin) 2008: Ultra-Low Power Pseudospintronic SwitcCaltech MRSEC 2008: Graphene Atomic Switches for Ultracomp
NRI-NIST Interaction:Full Partners in NRI Centers

 Leveraging industry, university, and both state & fed 

and driving university nanoelectronics infrastructure

INSTITUTE FOR NANOELECTRONICS INSTITUTE FOR NANOELECTRONICSDISCOVERY AND EXPLORATION DISCOVERY AND EXPLORATION

WINWestern Institute of Nanoelectronics

INDEXInstitute for Nanoelectronics Discovery & Exploration

SWANSouthWest Academy Nanoelectronics

UCLA, UCSB, UCIrvine, Berkeley, Stanford, U Denver, Iowa, Portland State

SUNY-Albany, GIT, RPI, Harvard, MIT, Purdue, Yale, Columbia, Caltech, NCSU, UVA

UT-Austin, UT-Dallas, A&M, Rice, ASU, Notre Dame, Maryland, NCSUIllinois-UC

Theme 1: Spin devicesTheme 2: Spin circuitsTheme 3: Benchmarks 

& metrics

Theme 4: Spin 

Metrology

Task I: Novel state-variable 

devices

Task II: Fabrication & SelfassemblyTask III: Modeling & ArchTask IV: Theory & SimTask V: RoadmapTask VI: Metrology

Task 1: Logic devices w

new state-varia

Task 2: Materials & struTask 3: Nanoscale ther

management

Task 4: Interconnect & Task 5: Nanoscale 

characterization
NRI Funded Universities

UC Los AngelesUC BerkeleyUC IrvineUC Santa BarbaraStanfordU DenverPortland StateU Iowa

Notre Dame PurdueIllinois-UC Penn StateMichigan UT-Dallas

UT-Austin Rice Texas A&MUT-Dallas ASU Notre DameU. Maryland NCSU Illinois UC

SUPuCaYa

Over 30 Universities in 20 State
SRC NRI Management Structu

NRI Centers: WIN / INDEX / SWAN / MIND

Industry

Assignees

Theme 1 : 

*******

Project 1Project 2

.......

Theme 2 : 

*******

Project 1Project 2

.......

Theme N : 

PI Leader

Project 1Project 2

.......

NSF C

NSECs / M

NRI P

Industr

Liaiso

Team

NRI P

Industr

Liaiso

Team

SRC NRI Governing Council

SRC NRI Director: Jeff Welser

SRC NRI TPG (Ind / Gov Reps)

Center Executive Committee:• Lead University Professors•SRC NRI Director•TPG representatives

NIST

Interaction

David Seiler Alt: Jason Boehm

Stephen KnightAlt: Yaw Obeng
NRI Funding Model

$2.75M

per 

year

NIST

$5M

per 

year 

Industry 

Partners

~$15M 

per

year/

States

RegGovCon•Gra•Tax

Inc

S

Bus

Dev

com

University-Based Research

Research Results

•INDEX: Institute for NanolectronicsDiscovery and Exploration•MIND: Midwest Institute for Nanoelectronics Discovery•SWAN: South West Academy of Nanoelectronics•WIN: Western Institute of Nanoelectronics
NRI Center Example

Five fully-integrated and synergistic research tasks for magnetic and molecular device paradigms

To discover and demonstrinnovations that surmount limits that will impede the hprogress of US Semicon

INDEX

First Pha(Novel Coand Task and F
NRI Center Example 

National synergistic network of centralized core fabricfacilities at UAlbany supporting tasks of all INDEX pacomprehensive array of design and fabrication nodes at 

Harvard CNS 

CNSE’s Albany 

NanoTech

GIT MIRC/NRC
INSTITUTE FOR NANOELECTRONICS INSTITUTE FOR NANOELECTRONICSDISCOVERY AND EXPLORATION DISCOVERY AND EXPLORATION

Quantum Dot Devices

Oktyabrsky et al (UAlbany) 

Ballistic Sp

Labella et al 

Post CMOS Switches

S pump S→T

A B

Z

A

B

Z

Molecular Excitons 

Spintronics

Baldo et al (MIT)

Logical Switches based on Complex Oxides

Ahn et al (Yale)

-100 -50 0 50 100

0.00.51.01.5

Field (Oe)

GMR (%)

NiFe6/Cu6/Co8

2 μm, 200 nm

S2

S2R

S1

S3

Multi bits logic

Magnetoelectronic Devices

Ross et al (MIT)

Reconfigurable One-Dimensional (1D) 

Switch (R1DS)

Ji Ung Lee (UAlbany)

Graphene ba

Charles 

Quantum Dot Modeling

Shur et al (RPI) 
NIST – INDEX Projects

PI Project Karl Berggren 

He Ion Microscope 

Alain Diebold

Optical measurement of Phonons in Graphene and their connection to electron mean free path

Robert Geer Nanoscale electrical measurements and SPM of GraphenJulia Greer Graphene mechanical properties Phillip First Atomic-scale electrical metrologies specifically for 

graphene

Philip Kim Studying quantum Hall effect in graphene as a resistanc

standard
Research Progress

 Key vision for NRI: Creating a goal-oriented, basic science  No new device yet, but research results indicate strong pr

three key areas to achieve this:

 Studying new science phenomena with device potentia

• Pseudospintronics for giant “electro-resistance”• Digital Ballistic Anisotropic Magneto-Resistance (BAMR)

 Linking scientists to engineers, to focus research on th

(E.g. logic gates, room temp operation, power dissipation, co

• Spin wave logic devices and circuits “roadmap”• NOR-gate based on molecular excitons

3⁄4Linking work across groups / universities / centers to m

• Study of graphene electronic and spintronic properties• Spin Hall effect experiments and modeling

 Points to initial success in focusing the science towards sw

 Get the right information early to direct research on m From industry member at INDEX review (9/08): “NRI e

we learned more about graphene for device applicationthan we would normally learn in 5 or 10 years in the b

research model.”
Industry Support of NIST’s Involv

 “NIST joining NRI enabled the recent expansion of the program, an

convincing the NRI industry members to extend their commitments beyond 2008, so this partnership has already resulted in increased 

-- Jeffrey Welser, Director of the Nanoelectronics Research 

 “There is tremendous interest in every part of the world to win the 

reap the economic rewards that will go with it. For America to win, collaboration between government, higher education and industry. type of collaboration is the important work going on in the Nanoele

at more than 30 universities with funding and participation from NIsemiconductor and research institutions.”

--John E. Kelly III, IBM Senior Vice President and Director o

 “The research results from this new initiative will enable the semico

Moore's Law -- the 40-year-old prediction that the industry can doutransistors it places on a computer chip every couple of years -- far when the potential limits of the current industry technology may be 

-- Larry Sumney, President and CEO of the Semiconductor 

 “The Nanoelectronics Research Initiative (NRI) and the regional res

what can be done when industry, government and academia work tlikely to pay substantial dividends in the future. Leading-edge univeproved to be powerful magnets for investment by technology comphigh-tech ecosystem for high-value jobs in the future.” 

-- George Scalise, President of the Semiconductor Industry 
NRI Technical Directions

 Grow NRI as a strategic goal-oriented, basic-scienc

 Expanded focus on specific key areas in the first thre

• Devices with alternate state variables – emphasis on ne• Device-to-device communication of alternate state varia• Non-equilibrium computation systems

 Expanded focus on combining these 3 vectors for log

implementations

• Still want more ideas on novel computational architectu

 Expanded modeling to extrapolate both device and c

potential characteristics

• Increased focus on nano-metrology to link theory to ex

 Create set of benchmarks / report card to assess de

new technologies compared to “ultimate CMOS”

 Tailor assessment appropriately for stage of research

gate” evaluation

• New phenomena: operation temperature, on/off ratio, • More advanced device ideas: speed, area, gain, commu

 Benchmarking working group led by MIND center sta
Continuous Research to Product E

Research Focus “Thousand Flowers Bloom” (2005-2010)

 Projects: Many, moderate size, new science/technology ideas

 Results: Science, new materials/structures knowledge, initial d

for early introduction of spin-off technologies and product inn

 “Cultivating Flowers” (2010 and beyond)

 Projects: Expanded work on 2-3 promising devices/architectu

 Results: Prove-out technologies before transfer to advanced R

more rapid uptake of technologies into products

Program Management Continue to organize work into multi-university centers

 Maintain balance between sufficient autonomy for new idea g

towards a practical device – strong interaction with industry a

 Continue to partner with states to expand existing centers 

 Target states with nanotechnology infrastructure initiatives an

 Expand program with Federal and state partners in three a

 Expand direct Fed-Ind partnership on post-CMOS nanoelectro Expand Fed and state investements in nanoelectronics infrast

 Expand interaction with national labs and encourage funding 
From Vacuum Tubes to DiodeThe cost of Inventing the Transistor

Semiconductor 

Research

$5B 

U.S. Air Force

RADAR

Program

$25 B

National Defense Research Council

Bell LabsRadiation LabGeneral ElectricSylvania Electric Sperry Research Labs Eagle Picher, Westinghouse

Purdue UU PennsylvaniaRochester UCatholic UOhio State U

1907 G.W. Pickard obtained a patent on the use of silicon in rectifying diodes.

$20M

Bell Labs.

Solid 

State 

Physics

Program

Ralph Cavin and Victor Zhirnov, Semico

1940 1945

Discovery Era

1907

Prehistoric Era

(2004 Dollars)
Summary 

 Power will continue as the principal scaling issue a

 CMOS will continue to scale over at least the next de

on utilizing increasing transistor density over increas

 Continuing the trend of increased function / dollar 

maintaining the exponential growth of our IT-base

 The country/state/companies that find the “next swi

dominate the Nanoelectronics Era the way the U.S. Microelectronics Era for the past half century

 Similar to the vacuum tube to transistor transition 

Industry – government – academia partnership is 

 Funding and focusing basic research at universities a

find a new device to scale beyond CMOS by 2020

 Building up nanoelectronics infrastructure leadership  Training the next generation of science & engineerin Rapidly commercializing new technology as it is disc
NRI Goal: Continue the Curve 

$1000 Buys:

1900 1920 1940 1960

IE-5

IntegratedCircuit

DiscreteTransistor

VacuumTube

ElectroMechanical

Mechanical

1980 

IE+12

Computations per secondIE+9 IE+6 IE+3 IE+0 IE-3
Questions? More Informatio

Jeff Welser, Director

jeff.welser@src.org

Allison Hilbert, Executive Ass

allison.hilbert@src.org

NRI Annual Review: Dec. 1-2, 2008,