The Open-Source SDR LTE Platform for Public Safety R&D

Paul Sutton

Software Radio Systems

www.softwareradiosystems.com
2

DISCLAIMER

This presentation was produced by guest speaker(s) 

and presented at the National Institute of Standards 

and Technology’s 2019 Public Safety Broadband 

Stakeholder Meeting. The contents of this 

presentation do not necessarily reflect the views or 

policies of the National Institute of Standards and 

Technology or the U.S. Government.

Posted with permission
• A reference implementation of key LTE features for first responders. 

• Enabling, supporting and growing the public safety broadband development ecosystem. 

• Providing a commercialization path for public safety LTE using proven business models.

• Building upon the proven srsLTE suite of open-source libraries, tools and applications.

An open-source end-to-end LTE network for public safety research & development. 

OpenFirst
• Technology

• Requirements

• Approach

• Status & Features

• Impact

Outline
RF Front-End

Baseband

Processor

Technology – Software Radio
RF Front-End

Baseband

Processor

Technology – Software Radio
Ease of use / Ease 

of programming 

new capabilities

Requirements
Ease of use / Ease 

of programming 

new capabilities

Requirements

Clarity and 

completeness of 

documentation 
Ease of use / Ease 

of programming 

new capabilities

Requirements

Clarity and 

completeness of 

documentation 

Long-term 

sustainability / 

Development 

ecosystem
Ease of use / Ease 

of programming 

new capabilities

Requirements

Clarity and 

completeness of 

documentation 

Long-term 

sustainability / 

Development 

ecosystem

Availability for 

follow-on research / 

Potential for 

commercialization
Ease of use / Ease 

of programming 

new capabilities

Requirements

Clarity and 

completeness of 

documentation 

Long-term 

sustainability / 

Development 

ecosystem

Availability for 

follow-on research / 

Potential for 

commercialization

Sufficiently 

complete 

implementation / 

Interoperability
Ease of use / Ease 

of programming 

new capabilities

Requirements

Clarity and 

completeness of 

documentation 

Long-term 

sustainability / 

Development 

ecosystem

Availability for 

follow-on research / 

Potential for 

commercialization

Sufficiently 

complete 

implementation / 

Interoperability

Sufficient set of 

components
Ease of use / Ease 

of programming 

new capabilities

Requirements

Clarity and 

completeness of 

documentation 

Long-term 

sustainability / 

Development 

ecosystem

Availability for 

follow-on research / 

Potential for 

commercialization

Sufficiently 

complete 

implementation / 

Interoperability

Sufficient set of 

components

Performance 

comparable to likely 

operational 

implementations
Ease of use / Ease 

of programming 

new capabilities

Requirements

Clarity and 

completeness of 

documentation 

Long-term 

sustainability / 

Development 

ecosystem

Availability for 

follow-on research / 

Potential for 

commercialization

Sufficiently 

complete 

implementation / 

Interoperability

Sufficient set of 

components

Performance 

comparable to likely 

operational 

implementations

Network scale
Clarity and 

completeness of 

documentation 

Ease of use / 

Ease of 

programming 

new capabilities

Long-term 

sustainability / 

Development 

ecosystem

Availability for 

follow-on research 

/ Potential for 

commercialization

Sufficiently 

complete 

implementation / 

Interoperability

Sufficient set of 

components

Performance 

comparable to 

likely operational 

implementations

Network scale

Path towards 

operational 

implementation

Requirements
Roadmap
Justin Tallon

Senior Engineer

Paul Sutton

Director

Ismael Gomez

Director

Linda Doyle

Director

Andre Puschmann

Senior Engineer

Xavier Arteaga

Senior Engineer

Francisco Paisana

Senior Engineer

Pedro Alvarez

Senior Engineer

SRS Team

Oriol Font-Bach

Senior Engineer

Pavel Harbanau

Senior Engineer
• GNU Affero General Public 

License (AGPLv3)

• Ensuring dissemination of the 

technology

• Maximizing usability

• Promoting sustainability

• Safeguarding availability

www.github.com/srslte

Open Source
Proven Development Models, Languages, Tools
OS Integration

launchpad.net/~srslte
Clean Modular Architecture
Clean Modular Architecture
Active Community
Active Community
Active Community
Sustainable Business Model
Baseline End-to-End System
Current Status
Baseline End-to-End System

RF Front-End

Baseband

Processor
Baseline End-to-End System

Console Applications
Baseline End-to-End System

Real-Time Metrics
Baseline End-to-End System

Detailed Log Files
Baseline End-to-End System

Wireshark Packet Captures
Impact
Impact
Impact
Impact
Impact
Impact
Impact
Impact
Impact

https://www.linkedin.com/pulse/impact-open-source-mobile-security-research-roger-piqueras-jover/

https://sites.google.com/view/ltefuzz

https://alter-attack.net/
Impact

https://www.linkedin.com/pulse/impact-open-source-mobile-security-research-roger-piqueras-jover/

https://sites.google.com/view/ltefuzz

https://alter-attack.net/
Impact

https://www.linkedin.com/pulse/impact-open-source-mobile-security-research-roger-piqueras-jover/

https://sites.google.com/view/ltefuzz

https://alter-attack.net/
Impact

https://www.linkedin.com/pulse/impact-open-source-mobile-security-research-roger-piqueras-jover/

https://sites.google.com/view/ltefuzz

https://alter-attack.net/
Impact

https://www.linkedin.com/pulse/reflection-history-cellular-security-research-outlook-piqueras-jover/

“Currently srsLTE is by far the best and most 

widely used – both in academia and industry 

– tool for LTE security research”
Impact
Impact
Impact
Impact
Impact

• Target SDR platforms: MPSoC (FPGA + multi-core CPU(s)) – FPGA is a co-processor to accelerate selected DSP functions

• Combination of custom HDL code + 3rd party IP cores (e.g., turbo-decoder)

– srsLTE code will need to be (minimally) adapted (i.e., FPGA integration) 

• Design goal: portable design – Support different platforms with minimal/no changes to the code

• Starting point: Xilinx Ultrascale+ & AD FMCOMMS4 – FPGA is also implementing timestamping (e.g., AD936x chips)

Xilinx ZCU102 eval board with ZU9EG 

Ultrascale+ MPSoC

Analog Devices AD-FMCOMMS4-EBZ FMC 

Board with AD9364
Impact

eNB:

● USRP B200 mini: RF front-end

● Intel NUC: srs eNB application (unmodified)

UE:

● AD FMCOMMS4: RF front-end

● Xilinx Ultrascale+:

○ FPGA: custom timestamping, interfacing of CPU and RF chip

○ ARM: srs UE application (integrated with the FPGA design)

Come back for the 

Next 

Session BACK AT

3:30 PM

78

#PSCR2019