National Institute of Standards and Technology | U.S. Department of Commerce 1

CHIPS R&D Update

February 14, 2024

Eric K. Lin

Deputy Director, CHIPS R&D Office
National Institute of Standards and Technology | U.S. Department of Commerce 2

Two component programs to:

1. Attract large-scale

investments in advanced

technologies such as leading-edge 

logic and memory, and advanced 

packaging

2. Incentivize expansion 

of manufacturing capacity 

for mature and other types of 

semiconductors

$39 billion

for incentives

Plus CHIPS initiatives 

from other agencies, 

including DOD, State, 

NSF, and Treasury

Four integrated programs to:

1. Conduct research and prototyping of 

advanced semiconductor technology

2. Strengthen semiconductor advanced 

packaging, assembly, and test

3. Enable advances in measurement 

science, standards, material 

characterization, instrumentation, 

testing, and manufacturing

$11 billion

for R&D

Workforce Initiatives

CHIPS for America
National Institute of Standards and Technology | U.S. Department of Commerce 3

Vision for Success

U.S. Technology 

Leadership

Robust Semiconductor 

Workforce

Accelerated Ideas 

to Market

The United States establishes 

the capacity to invent, develop, 

prototype, and deploy the 

foundational semiconductor 

technologies of the future.

Inventors, designers, researchers, 

developers, engineers, 

technicians, and staff meet 

evolving domestic government and 

commercial-sector needs.

The best ideas achieve 

commercial scale as quickly 

and cost effectively as 

possible.
National Institute of Standards and Technology | U.S. Department of Commerce 4

Manufacturing USA 

Institute

Metrology National 

Semiconductor 

Technology Center

National Advanced 

Packaging 

Manufacturing 

Program

CHIPS R&D Programs

Workforce Initiatives
National Institute of Standards and Technology | U.S. Department of Commerce 5

National Institute of Standards and Technology | U.S. Department of Commerce 5

CHIPS R&D Timeline

NSTC

NAPMP

Manufacturing 

USA institute(s)

Metrology

FALL 2023 WINTER 23/24

Establish NSTC

NAPMP vision and 

strategy

Announce selected 

topic(s)

Standards Standards Summit

Spring 2024

Natcast.org / CEO Membership / Programs

Notice of Intent Notice of Funding Opp

(~$300M)

Notice of Intent Notice of Funding Opp (min. 

$200M)

• Digital Twin Data

• Chiplets

• Digital Twin Data

• Supply Chain Trust Data

3 Grand Challenges Funded Communities of Practice
National Institute of Standards and Technology | U.S. Department of Commerce 6

Updates

• National Semiconductor Technology Center Consortium 

• Feb 9, 2024

• Signing ceremony at White House Executive Office Bldg.

• Commerce, Energy, Defense, NSF, Natcast

• Natcast CEO, Deirdre Hanford

• HBCU CHIPS Network kick-off (Feb 8, 2024)

• At Department of Commerce

• Inside CHIPS Metrology (Jan 16, 2024)

• National Advanced Packaging Manufacturing Program Vision

• Nov 27, 2023

• Building the U.S. Semiconductor Workforce (Nov 15, 2023)
National Institute of Standards and Technology | U.S. Department of Commerce 7

NAPMP will develop critical and relevant innovations for advanced packaging technologies and accelerate their 

scaled transition to U.S. manufacturing entities

Mission

The National Advanced Packaging Manufacturing Program will drive U.S. leadership in advanced packaging and 

provide the technology needed for packaging manufacturing in the United States.

Vision

• Within the decade NAPMP funded activities, coupled with CHIPS manufacturing incentives, will establish a 

vibrant, self-sustaining, profitable, high-volume, onshore packaging industry where advanced node chips 

manufactured in the USA are packaged in the USA.

• We expect the technology developed to be leveraged in new applications and market sectors

Outcomes

NAPMP Vision, Mission, and Outcomes
National Institute of Standards and Technology | U.S. Department of Commerce 8

Substrates & materials are the 

platform for heterogeneous 

integration of dielets

Equipment, tools & processes are needed to 

pattern substrates and assemble dielets and 

passivate assemblies

The chiplet ecosystem is crucial for any 

implementation of advanced packaging

Automated design for test, repair, 

security, and reliability; substrate 

and process dependent 

Thermal management and efficient 

power delivery are critical needs 

Photonics and connectors allow 

the assembly to interact with the 

outside world 

The APPF provides a test bed for integration 

of the different investment areas and also 

functions as a piloting and prototyping facility

NAPMP Priority Research Investment Areas

APPF: advanced packaging piloting facility
National Institute of Standards and Technology | U.S. Department of Commerce 9

CHIPS Manufacturing USA 

Institute

• Establish one Institute with the potential for significant impact on 

semiconductor manufacturing

• Topic = Digital twins

• For general planning, minimum expected NIST commitment 

~$200 million over a five-year period

• Anticipate a greater than 1:1 cost share

• Analysis of RFI responses, industry feedback, listening sessions 

across 15+ engagements, and technology opportunities across 

the CHIPS R&D portfolio.
National Institute of Standards and Technology | U.S. Department of Commerce 10

Vision

Enable seamless integration of 

digital twin models into the U.S. 

semiconductor manufacturing, 

advanced packaging, and 

assembly industries, enabling 

rapid adoption of innovations and 

enhancing domestic 

competitiveness for decades.

Mission

Foster a collaborative 

environment within the domestic 

semiconductor industry, enabled 

by the world’s first shared

semiconductor Digital Twin 

process validation facility, 

industry-relevant research 

projects, and digital-twin 

supported workforce training.

Digital Twin Institute
National Institute of Standards and Technology | U.S. Department of Commerce 11

Digital Twin Institute Objectives

Reduce the time and cost for chip development and 

manufacturing

Accelerate the adoption of semiconductor manufacturing 

innovations

Increase access to semiconductor manufacturing training 

through the adoption of digital twin-enabled tools

Expand access to digital twin tools, solutions and 

frameworks 
National Institute of Standards and Technology | U.S. Department of Commerce 12

Deliver technical 

solutions, de-risk 

new tools, and 

conduct data 

analysis

Develop and test 

education & workforce 

development tools 

enabled by digital twins

Digital Twin Institute Approach

A physical 

facility and 

digital 

framework, 

integrated 

with industryled research 

projects

Expected activities:

• Baseline facility testbed

• Digital emulation hardware

• Core technical & operations staff

Competitively fund industry-led technical 

and workforce development projects 2

Create a shared 

marketplace of 

digital twin models

4

Data analysis tools DT+ Full process flows

1 Establish a shared physical facility

Digital framework for 

interoperable data and 

models

3