# Patent

## Title
Bandgap reference circuits

## Abstract

Bandgap reference circuits capable operating in low voltage environments. In the bandgap reference circuit, a current generation circuit generates an output current obtained by combining a first current, a second current and a third current. The first current is converted from a first voltage and a first forward voltage of a first constant voltage generation element. The second current and the third current are both converted from a voltage difference between the first forward voltage and a second forward voltage of the second constant voltage generation element. A current-to-voltage generator converts the output current to an output voltage.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/737315, filed Nov. 16, 2005, and entitled “Low-voltage bandgap voltage reference circuit”.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to reference circuits, and in particular to bandgap reference circuits capable of operating in low voltage environments while generating output with a nearly-zero temperature coefficient.
2. Description of the Related Art
Analog circuits incorporate voltage and current reference circuits extensively. Such reference circuits are DC quantities that exhibit little dependence on supply and process parameters and a well-defined dependence on the temperature. For example, bandgap reference circuits are probably the most popular high performance reference circuits, with the principle thereof to implement components having characteristics of positive temperature coefficient and negative temperature coefficient and add the voltages or current of these components in a predetermined proportion to generate a value independent of temperature, such value output as a reference. The conventional bandgap reference circuits use bipolar technology to create a stable low reference voltage at around 1.25V which is almost equal to the silicon energy gap measured in electron volts. However, in modem deep-submicron technology, a voltage of around 1V is preferred. As such, the conventional bandgap reference circuits are inadequate for current requirements.
BRIEF SUMMARY OF THE INVENTION
A detailed description is given in the following embodiments with reference to the accompanying drawings.
Embodiments of bandgap reference circuits are provided, in which a current generation circuit generates an output current, obtained by combining a first current, a second current and a third current. The first current is converted from a first voltage and a first forward voltage of a first constant voltage generation element. The second current and the third current are both converted from a voltage difference between the first forward voltage and a second forward voltage of the second constant voltage generation element. A current-to-voltage generator converts the output current to an output voltage.
The invention provides another embodiment of bandgap reference circuits, in which a current mirror comprises a control terminal, a first output terminal and a second output terminal, an operational amplifier comprises an output terminal coupled to the control terminal of the current mirror, and first and second input terminals. A first resistor is coupled between the first output terminal of the current mirror and the first input terminal of the operational amplifier. A second resistor is coupled between the first output terminal of the current mirror and the second input terminal of the operational amplifier, and a third resistor comprises a first terminal coupled to the first input terminal of the operational amplifier, and a second terminal. A first transistor is coupled between the second terminal of the third resistor and a ground voltage, and a second transistor is coupled between the ground voltage and the second input terminal of the operational amplifier. A fourth resistor is coupled between the ground voltage and the second output terminal of the current mirror.
The invention provides another embodiment of bandgap reference circuits, in which a current mirror comprises a control terminal, a first output terminal and a second output terminal, and an operational amplifier comprises an output terminal coupled to the control terminal of the current mirror, and first and second input terminals. A first resistor is coupled between the first output terminal of the current mirror and the first input terminal of the operational amplifier. A second resistor is coupled between the first output terminal of the current mirror and the second input terminal of the operational amplifier, and a third resistor comprising a first terminal coupled to the first input terminal of the operational amplifier, and a second terminal. A first transistor is coupled between the second terminal of the third resistor and a ground voltage, and a second transistor is coupled between the ground voltage and the second input terminal of the operational amplifier. A fourth resistor is coupled between the first output terminal and the second output terminal of the current mirror.
The invention provides another embodiment of bandgap reference circuits, in which a first MOS transistor is coupled between a power voltage and a first node, a second MOS transistor is coupled between the power voltage and an output terminal, and an operational amplifier comprises an output terminal coupled to the first and the second MOS transistors. A first resistor is coupled between the first node and the operational amplifier, a second resistor is coupled between the first node and the operational amplifier, and a third resistor is coupled to the first node and the operational amplifier. A first transistor is coupled between the third resistor and a ground voltage, a second transistor is coupled between the ground voltage and the second resistor, a fourth resistor is coupled to the first node; and a fifth resistor is coupled between the output terminal and the ground voltage.
The invention provides another embodiment of bandgap reference circuits, in which a current mirror produces a first current mirror output and a second current mirror output through a first output terminal and a second output terminal respectively, in response to a control signal. The first current mirror output comprises first and second current with negative temperature coefficient and a third current with positive temperature coefficient. A first resistor is coupled between the first output terminal and a first node to receive the first current, and a second resistor is coupled between the first output terminal and a second node to receive the second current. An operational amplifier is coupled to the first node and the second node to generate the control signal to control the current mirror according to voltages on the first and the second nodes. A third resistor comprises a first terminal coupled to the first input terminal of the operational amplifier, and a second terminal, and a first transistor is coupled between the second terminal of the third resistor and a ground voltage. A second transistor is coupled between the ground voltage and the second node, and a fourth resistor is coupled to the first output terminal to receive the third current.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 shows an embodiment of a bandgap reference circuit; and
FIG. 2 shows another embodiment of a bandgap reference circuit.



DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 shows an embodiment of a bandgap reference circuit. As shown, a bandgap reference circuit 100A comprises a current generation circuit 10A and a current-to-voltage generator 20. The current generation circuit 10A generates two identical output currents I4a and I4b, and the current I4b is obtained by combining currents I1, I2 and I3 since the currents I4a and I4b are identical. The current-to-voltage generator 20 generates an output voltage Vref according to the current I4b generated by the current generation circuit 10A.
The current generation circuit 10A comprises a current mirror CM, an operating amplifier OP, resistors R1, R2a, R2b and R3, and two bipolar transistors Q1 and Q2, in which the current mirror CM comprises two PMOS transistors MP1 and MP2 and the resistors R2a and R2b have the same resistance. For example, the transistors MP1 and MP2 are the same size, and the emitter area of the transistor Q1 can be N times that of the transistor Q2, in which N>1. The current-to-voltage generator 20 can be a resistor, a resistive element, a passive element or combinations thereof. In this case, the current-to-voltage generator 20 comprises a resistor R4.
The transistor MP1 comprises a first terminal coupled to a power voltage Vcc, a second terminal coupled to a node N1, and a control terminal coupled to the transistor MP2. The transistor MP2 comprises a first terminal coupled to the power voltage Vcc, a control terminal coupled to the control terminal of the transistor MP1 and a second terminal coupled to the resistor R4. The resistor R3 is coupled between the node N1 and a ground voltage GND, the resistor R2a is coupled between the nodes N1 and N2, the resistor R2b is coupled between the nodes N1 and N3, and the resistor R1 is coupled between the node N2 and the transistor Q1.
The operational amplifier comprises a first terminal coupled to the node N2 and a second terminal coupled to the node N3, and an output terminal coupled to the control terminals of the transistors MP1 and MP2 in the current mirror CM. The operational amplifier OP outputs a control signal to control the current mirror CM according to the voltages at the nodes N2 and N3.
The transistor Q1 comprises an emitter coupled to the resistor R1 and a collector coupled to the ground voltage GND and a base coupled to the transistor Q2. The transistor Q2 comprises an emitter coupled to the node N3 and a collector coupled to the ground voltage GND and a base coupled to the base of the transistor Q1. In this case, the bases of the transistor Q1 and Q2 are coupled to the ground voltage GND. Namely, the transistors Q1 and Q2 are diode-connected transistors.
If the base current is neglected, the emitter-base voltage VEB of a forward active operation diode can be expressed as:




  
    V
    EB
  
  =
  
    
      
        k
        ⁢
        
          
        
        ⁢
        T
      
      q
    
    ⁢
    
      ln
      ⁡
      
        (
        
          
            I
            C
          
          
            I
            S
          
        
        )
      
    
  




Wherein k is Boltzmannis constant (1.38×10−23 J/K), q is the electronic charge (1.6×10−29C), T is temperature, Ic is the collator current, and Is is the saturation current.
When the input voltages V1 and V2 of the operational amplifier OP are matched and the size of the transistor Q1 is N times that of the transistor Q2, the emitter-base voltage difference between the transistors Q1 and Q2, ΔVEB, becomes:




  
    Δ
    ⁢
    
      
    
    ⁢
    
      V
      EB
    
  
  =
  
    
      
        V
        
          EB
          ⁢
          
            
          
          ⁢
          2
        
      
      -
      
        V
        
          EB
          ⁢
          
            
          
          ⁢
          1
        
      
    
    =
    
      
        
          k
          ⁢
          
            
          
          ⁢
          T
        
        q
      
      ⁢
      ln
      ⁢
      
        
      
      ⁢
      N
    
  




Wherein VEB1 is the emitter-base voltage of the transistor Q1, and VEB2 is the emitter-base voltage of the transistor Q2.
Because the input voltages V1 and V2 are matched by the operational amplifier OP, the voltages V1 and V2 can be expressed as:



  
    
      V
      ⁢
      
        
      
      ⁢
      1
    
    =
    
      
        V
        ⁢
        
          
        
        ⁢
        2
      
      =
      
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            V
            
              EB
              ⁢
              
                
              
              ⁢
              1
            
          
          +
          
            I
            ⁢
            
              
            
            ⁢
            1
            ×
            R
            ⁢
            
              
            
            ⁢
            1
          
        
      
    
  




  
    
      I
      ⁢
      
        
      
      ⁢
      1
      ×
      R
      ⁢
      
        
      
      ⁢
      1
    
    =
    
      
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            2
          
        
        -
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            1
          
        
      
      =
      
        
          
            k
            ⁢
            
              
            
            ⁢
            T
          
          q
        
        ⁢
        ln
        ⁢
        
          
        
        ⁢
        N
      
    
  



Thus, the current I1 through the resistors R2a and R1 can be expressed as:




  
    
      I
      ⁢
      
        
      
      ⁢
      1
    
    =
    
      
        
          V
          T
        
        
          R
          ⁢
          
            
          
          ⁢
          1
        
      
      ⁢
      ln
      ⁢
      
        
      
      ⁢
      N
    
  
  ,




wherein thermal voltage





  
    V
    T
  
  =
  
    
      
        k
        ⁢
        
          
        
        ⁢
        T
      
      q
    
    .
  




Because the resistors R2a and R2b are identical and the input voltages V1 and V2 are matched by the operational amplifier OP, the current I2 can be the same as the current I1.
Accordingly,




  
    
      I
      ⁢
      
        
      
      ⁢
      1
    
    =
    
      
        I
        ⁢
        
          
        
        ⁢
        2
      
      =
      
        
          
            V
            T
          
          
            R
            ⁢
            
              
            
            ⁢
            1
          
        
        ⁢
        ln
        ⁢
        
          
        
        ⁢
        N
      
    
  
  ,




since the thermal voltage VT has a positive temperature coefficient of 0.085 mV/° C., the currents I1 and I2 have positive temperature coefficient.

Thus, voltage V3 at the node N1 can be expressed as:

V3=I3×R3=I1×(R1+R2a)+VEB1=I2×R2b+V EB2

Hence, the current 13 can be expressed as:




  
    I
    ⁢
    
      
    
    ⁢
    3
  
  =
  
    
      1
      
        R
        ⁢
        
          
        
        ⁢
        3
      
    
    ⁡
    
      [
      
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            2
          
        
        +
        
          (
          
            
              
                
                  V
                  T
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                N
              
              
                R
                ⁢
                
                  
                
                ⁢
                1
              
            
            ×
            R
            ⁢
            
              
            
            ⁢
            2
            ⁢
            b
          
          )
        
      
      ]
    
  




Because the emitter-base voltage VEB of transistors has a negative temperature coefficient of −2 mV/° C., the current I3 has a negative temperature coefficient.
As the transistors MP1 and MP2 in the current mirror CM are identical, the current I4b is the same as the current I4a, and can be expressed as:




  
    I
    ⁢
    
      
    
    ⁢
    4
    ⁢
    a
  
  =
  
    
      I
      ⁢
      
        
      
      ⁢
      4
      ⁢
      b
    
    =
    
      
        
          I
          ⁢
          
            
          
          ⁢
          1
        
        +
        
          I
          ⁢
          
            
          
          ⁢
          2
        
        +
        
          I
          ⁢
          
            
          
          ⁢
          3
        
      
      =
      
        
          
            2
            ⁢
            
              
            
            ⁢
            I
            ⁢
            
              
            
            ⁢
            1
          
          +
          
            I
            ⁢
            
              
            
            ⁢
            3
          
        
        =
        
          
            
              (
              
                
                  2
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    b
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    1
                    ×
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              )
            
            ×
            
              V
              T
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            N
          
          +
          
            
              V
              
                EB
                ⁢
                
                  
                
                ⁢
                2
              
            
            
              R
              ⁢
              
                
              
              ⁢
              3
            
          
        
      
    
  




Hence, if a proper ratio of resistances of the resistors R1, R2a, R2b and R3 is selected, the current I4a will have a nearly-zero temperature coefficient and low sensitivity to temperature. Namely, each current mirror output (currents I4a and I4b) of the current mirror CM will have a nearly-zero temperature coefficient and low sensitivity to temperature.
Accordingly, the output voltage of the bandgap reference circuit 100A can be expressed as:




  
    V
    ref
  
  =
  
    
      I
      ⁢
      
        
      
      ⁢
      4
      ⁢
      b
      ×
      R
      ⁢
      
        
      
      ⁢
      4
    
    =
    
      
        
          (
          
            
              
                2
                ⁢
                
                  
                
                ⁢
                R
                ⁢
                
                  
                
                ⁢
                4
              
              
                R
                ⁢
                
                  
                
                ⁢
                1
              
            
            +
            
              
                R
                ⁢
                
                  
                
                ⁢
                2
                ⁢
                b
                ×
                R
                ⁢
                
                  
                
                ⁢
                4
              
              
                R
                ⁢
                
                  
                
                ⁢
                1
                ×
                R
                ⁢
                
                  
                
                ⁢
                3
              
            
          
          )
        
        ×
        
          V
          T
        
        ⁢
        ln
        ⁢
        
          
        
        ⁢
        N
      
      +
      
        
          
            R
            ⁢
            
              
            
            ⁢
            4
          
          
            R
            ⁢
            
              
            
            ⁢
            3
          
        
        ×
        
          V
          
            EB
            ⁢
            
              
            
            ⁢
            2
          
        
      
    
  




It should be noted that, the resistors R2a and R2b prevents the input terminal of the operational amplifier OP from connecting directly, ensuring the operational amplifier OP can be operated normally. Without the resistor R3, the output voltage Vref of the bandgap reference circuit is limited to 1.25V, which cannot be operated in low voltage environments, in order to obtain a nearly-zero temperature coefficient. Thus, the resistor R3 is used to induce the current I3 with negative temperature coefficient to overcome such limitation, and if a proper ratio of resistances of the resistors R1, R2a, R2b, R3 and R4 is selected, the output voltage Vref will have low sensitivity to temperature and can be operated in low voltage environments.
FIG. 2 shows another embodiment of a bandgap reference circuit. As shown, the bandgap reference circuit 100B is similar to the circuit 100A shown in FIG. 1 except for the resistor R3. The resistor R3 is coupled between the node N1 and the resistor R4 rather than the ground voltage GND.
Similarly, currents I1 and I2 are equal and can be expressed as:




  
    I
    ⁢
    
      
    
    ⁢
    1
  
  =
  
    
      I
      ⁢
      
        
      
      ⁢
      2
    
    =
    
      
        
          V
          T
        
        
          R
          ⁢
          
            
          
          ⁢
          1
        
      
      ⁢
      ln
      ⁢
      
        
      
      ⁢
      N
    
  




The voltage V3 at the node N1 and the output voltage Vref can be expressed as:




  
    
      
        
          V
          ⁢
          
            
          
          ⁢
          3
        
        =
        
          
            
              
                
                  V
                  T
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                N
              
              
                R
                ⁢
                
                  
                
                ⁢
                1
              
            
            ×
            R
            ⁢
            
              
            
            ⁢
            2
            ⁢
            b
          
          +
          
            V
            
              EB
              ⁢
              
                
              
              ⁢
              2
            
          
        
      
    
  
  
    
      
        Vref
        =
        
          R
          ⁢
          
            
          
          ⁢
          4
          ×
          
            [
            
              
                (
                
                  
                    
                      V
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                    -
                    Vref
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                )
              
              +
              
                2
                ⁢
                I
                ⁢
                
                  
                
                ⁢
                2
              
              +
              
                (
                
                  
                    
                      V
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                    -
                    Vref
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                )
              
            
            ]
          
        
      
    
  
  
    
      
        =
        
          R
          ⁢
          
            
          
          ⁢
          4
          ×
          
            (
            
              
                
                  2
                  ⁢
                  V
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              -
              
                
                  2
                  ⁢
                  Vref
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              +
              
                2
                ⁢
                I
                ⁢
                
                  
                
                ⁢
                2
              
            
            )
          
        
      
    
  
  
    
      
        =
        
          
            1
            
              (
              
                1
                +
                
                  
                    2
                    ⁢
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
              
              )
            
          
          ⁡
          
            [
            
              
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                ⁢
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
              +
              
                
                  (
                  
                    
                      
                        2
                        ⁢
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        2
                        ×
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        4
                      
                      
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        1
                        ×
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                    
                    +
                    
                      
                        2
                        ⁢
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        4
                      
                      
                        R
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                  
                  )
                
                ⁢
                
                  V
                  T
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                N
              
            
            ]
          
        
      
    
  




Because the emitter-base voltage VEB of transistors has a negative temperature coefficient of −2 mV/° C., the current I3 has a negative temperature coefficient. Hence, if a proper ratio of resistances of the resistors R1, R2a, R2b, R3 and R4 is selected, the output voltage Vref will have low sensitivity to temperature and can be operated in low voltage environments. Similarly, if a proper ratio of resistances of the resistors R1, R2a, R2b, R3 and R4 is selected, the output voltage Vref will have low sensitivity to temperature, the currents I4a and I4b can also have low sensitivity to temperature, and the description thereof is omitted for simplification.
The bandgap reference circuits 100A and 100B of the invention can act as a necessary functional block for the operation of mixed-mode and analog integrated circuits (ICs), such as data converters, phase lock-loop (PLL), oscillators, power management circuits, dynamic random access memory (DRAM), flash memory, and much more. For example, the bandgap reference circuit 100A provides the current I4b or the output voltage Vref to a core circuit, and the core circuit executes functions thereof accordingly.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

## Claims

1. A bandgap reference circuit, comprising:
a current mirror comprising a control terminal, a first output terminal and a second output terminal;
an operational amplifier comprising an output terminal coupled to the control terminal of the current mirror, and first and second input terminals;
a first resistor coupled between the first output terminal of the current mirror and the first input terminal of the operational amplifier;
a second resistor coupled between the first output terminal of the current mirror and the second input terminal of the operational amplifier;
a third resistor comprising a first terminal coupled to the first input terminal of the operational amplifier, and a second terminal;
a first transistor coupled between the second terminal of the third resistor and a ground voltage;
a second transistor coupled between the ground voltage and the second input terminal of the operational amplifier; and
a fourth resistor coupled between the first output terminal and the second output terminal of the current mirror.

2. The bandgap reference circuit as claimed in claim 1, further comprising a fifth resistor coupled between the ground voltage and the second output terminal of the current mirror.

3. The bandgap reference circuit as claimed in claim 2, wherein the current mirror comprises:
a first MOS transistor comprising a first terminal coupled to a power voltage, a control terminal coupled to the output terminal of the operational amplifier, and a second terminal coupled to the first, the second and the fourth resistors; and
a second MOS transistor comprising a first terminal coupled to the power voltage, a control terminal coupled to the output terminal of the operational amplifier, and a second terminal coupled to the fourth and the fifth resistors.

4. The bandgap reference circuit as claimed in claim 3, wherein the first resistor is identical to the second resistor.

5. The bandgap reference circuit as claimed in claim 4, wherein the first and second transistors are diode-connected bipolar transistors.

6. A bandgap reference circuit, comprising:
a first MOS transistor coupled between a power voltage and a first node;
a second MOS transistor coupled between the power voltage and an output terminal;
an operational amplifier comprising an output terminal coupled to the first and the second MOS transistors;
a first resistor coupled between the first node and the operational amplifier;
a second resistor coupled between the first node and the operational amplifier;
a third resistor coupled to the first resistor and the operational amplifier;
a first transistor coupled between the third resistor and a ground voltage;
a second transistor coupled between the ground voltage and the second resistor;
a fourth resistor coupled to the first node and coupled between the first MOS transistor and the second MOS transistor; and
a fifth resistor coupled between the output terminal and the ground voltage.

7. A bandgap reference circuit, comprising:
a current mirror, in response to a control signal, producing a first current mirror output and a second current mirror output through a first output terminal and a second output terminal respectively, wherein the first current mirror output comprises first and second currents with positive temperature coefficient and a third current with negative temperature coefficient;
a first resistor coupled between the first output terminal and a first node, receiving the first current;
a second resistor coupled between the first output terminal and a second node, receiving the second current;
an operational amplifier coupled to the first node and the second node, generating the control signal to control the current mirror according to voltages on the first and second nodes;
a third resistor comprising a first terminal coupled to the first input terminal of the operational amplifier, and a second terminal;
a first transistor coupled between the second terminal of the third resistor and a ground voltage;
a second transistor coupled between the ground voltage and the second node; and
a fourth resistor coupled between the first output terminal and the second output terminal of the current mirror, receiving the third current.

8. The bandgap reference circuit as claimed in claim 7, further comprising a fifth resistor coupled between the ground voltage and the second output terminal of the current mirror, receiving the second current mirror output and generating an output voltage.

9. A bandgap reference circuit, comprising:
a current generation circuit, generating an output current obtained by combining a first current, a second current and a third current, wherein the first current is converted from a first voltage and a first forward voltage of a first constant voltage generation element, and the second current and the third current are both converted from a voltage difference between the first forward voltage and a second forward voltage of the second constant voltage generation element; and
a current-to-voltage generator, converting the output current to an output voltage, wherein the current generation circuit comprises: a first transistor, comprising a first terminal coupled to a power voltage, a second terminal coupled to the current-to-voltage generator, and a gate terminal:
a second transistor comprising a first terminal coupled to the power voltage, a gate terminal coupled to a gate terminal of the first transistor, and a second terminal coupled to a first node:
a first resistor coupled between the first node and the second terminal of the current-to-voltage generator:
a second resistor coupled between the first node and a second node:
a third resistor coupled between the first node and a third node:
an operational amplifier coupled to the second node and the third node. generating the control signal to control the first and the second transistors according to voltages on the second and the third nodes:
a fourth resistor comprising a first terminal coupled to the second node, and a second terminal:
a third transistor coupled between the second node and the ground voltage, comprising a control terminal coupled to the ground voltage: and
a fourth transistor coupled between the third node and the ground voltage, comprising a control terminal coupled to the ground voltage.

10. The bandgap reference circuit as claimed in claim 9, wherein the first and the second constant voltage elements each comprise a diode-connected element.