# Patent

## Title
Wide-temperature integrated operational amplifier

## Abstract

The present invention relates to a reference current circuit. The reference circuit comprises a low-level current bias circuit, a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT), and a MOSFET-based constant-IC regulator circuit. The MOSFET-based constant-IC regulator circuit includes a constant-IC input and constant-IC output. The constant-IC input is electrically connected with the VPTAT generator such that the voltage proportional-to-absolute temperature is the input into the constant-IC regulator circuit. Thus the constant-IC output maintains the constant-IC ratio across any temperature range.

## Background
PRIORITY CLAIM
The present application is a non-provisional patent application, claiming the benefit of priority of U.S. Provisional Application No. 60/748,360, filed on Dec. 7, 2005 entitled “A Wide Temperature Integrated Operational Amplifier.”


STATEMENT OF GOVERNMENT INTEREST
The invention described herein was made in the performance of work under a NASA contract and is subject to the provisions of Public Law 96-517 (35 USC 202) in which the Contractor has elected to retain title.


BACKGROUND
(1) Field of the Invention
The present invention relates to integrated operational amplifiers and, more particularly, to analog, wide temperature range, quad operational-amplifiers.
(2) Background of the Invention
Electronic devices permeate the modern world. They are used in everything from appliances to computers to state-of-the-art scientific apparatuses. Given the broad range of applications and, accordingly, the broad range of environments in which modern electronics are required to reliably operate, means for hardening electronic devices against extreme environmental variables.
Perhaps the harshest environment in which modem electronics are required to operate is outer space. In a typical space application, when a circuit is exposed to direct sunlight, its temperature can rise to over 120° C., higher than the boiling temperature of water on Earth. In the absence of sunlight, the vacuum of space can rapidly cool the same circuit to 180° C. below zero, a temperature nearly cold enough to make liquid Nitrogen on Earth.
Modern integrated circuit elements require current references to accomplish proper circuit element biasing. If the same circuits are to operate in extreme temperatures, these circuits require current references that stay nearly constant over the required operating range, otherwise circuit performance will change when integrated transistors become improperly biased.
In the best-case scenario, improper biasing causes changes in the transistors' inversion levels, electron and hole mobilities, and thermal voltage levels. These changes drastically alter the performance characteristics of transistors and typically render a circuit useless unless care has been taken to compensate for such changes. In the worst-case scenario, changes in the current reference lead to overvoltage or voltage surges in the circuit, causing irreversible failure of the device; the mechanisms for such non-reversible failure are typically hot carrier injection and breakdown of oxide layers due to high gate-to-source voltages.
In the past, attempts to make current references that are resistant to such temperature effects have primarily used one of two transistor integration techniques: the first is the constant transconductance method and the second is the constant current method.
The constant transconductance method minimizes variations in small-signal performance parameters, such as bandwidth, when temperatures change. However, the reduction of temperature sensitivity to small-signal parameters leads to increased temperature sensitivity in large-signal parameters, such as slew rate.
As an alternative to the constant transconductance method, the constant current method has been used. The constant current method minimizes variations in large-signal parameters at the expense of small-signal parameters.
In general, it is desirable to simultaneously minimize variations in both small-signal parameters and large-signal parameters with respect to temperature, and neither of the above-described methods can achieve simultaneous minimization of both small-signal and large-signal parameter variations with temperature.
Another extreme environmental variable to which circuits can be exposed is radiation. Radiation degrades transistor performance by knocking atoms out of lattice sites, which cause defects, and scattering electrons and holes out of regions to which they would otherwise be bound. Both processes drastically change the functionality and characteristics of transistors.
Transistors can be exposed to radiation in many different environments, non-limiting examples of which include instrumentation for nuclear reactors, modern laboratory environments in which radioisotopes or cosmic background radiation are studied, and outer space.
Typical metal-on-silicon (MOS) components do not withstand radiation, making the devices unreliable in applications in which they are exposed to radiation. However, several modern technologies, for example silicon-on-insulator (SOI) MOS components, are more resistant to radiation damage than typical bulk MOS devices. SOI MOS devices, as an example, are surrounded by insulator layers, non-limiting examples of which are silicon nitride and silicon oxynitride, that shield the silicon and metals from radiation.
Finally, as discussed above, overvoltage can typically cause non-reversible damage to integrated circuit components. Exacerbating such problems is the recent move of the state-of-the-art from 5 Volt transistors to 3.3 Volt transistors. If new circuits using the 3.3 Volt technology are to be integrated with old circuits and power supplies using the 5 Volt technology, steps must be taken to ensure that overvoltage events do not destroy circuits.
SUMMARY OF THE INVENTION
The present invention relates to a reference current circuit. The reference circuit comprises a low-level current bias circuit, a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT), and a MOSFET-based constant-IC regulator circuit. The MOSFET-based constant-IC regulator circuit includes a constant-IC input and constant-IC output. The constant-IC input is electrically connected with the VPTAT generator such that the voltage proportional-to-absolute temperature is the input into the constant-IC regulator circuit. Thus the constant-IC output maintains the constant-IC ratio across any temperature range.
In yet another aspect, the reference current circuit further comprises a bias current distribution circuit. The bias current distribution circuit itself comprises a bias current circuit, a bias current output electrically connected to the bias current circuit, a current reference input electrically connected to the bias current circuit, and a power input electrically connected to the bias current circuit. The current reference input is electrically connected with the current reference circuit via the constant-IC output, with the bias current distribution circuit generating an output bias current in response to the constant-IC output. Thus the output bias current is used to bias a load circuit such that the performance characteristics over a wide temperature range are minimized.
In yet another aspect, the reference current further comprises a startup circuit electrically connected to the reference circuit. If the startup reference current is larger than the output current of the constant-IC regulator, current is injected into the bias circuitry of the VPTAT generator and the constant-IC regulator to facilitate startup of the current reference.
In yet another aspect, the reference current circuit further comprises a common-mode feedback (CMFB) circuit electrically connected with the input of the reference circuit. In this way, the CMFB circuit prevents VPTAT from floating.
The present invention also relates to a self-biased operational amplifier. The self-biased operational amplifier comprises a current reference circuit. This current reference circuit itself includes the following circuit elements: a low-level current bias circuit; a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT); a MOSFET-based constant-IC regulator circuit including a constant-IC input and constant-IC output, the constant-IC input is electrically connected with the VPTAT generator such that the voltage proportional to absolute temperature is the input into the constant-IC regulator circuit; a bias current distribution circuit that comprises a bias current circuit, a bias current output electrically connected to the bias current circuit, and a current reference input electrically connected to the bias current circuit; and a power input electrically connected to the bias current circuit, the current reference input is electrically connected with the current reference circuit via the constant-IC output, with the bias current distribution circuit generating an output bias current in response to the constant-IC output; a current reference input electrically connected with the current reference circuit via the constant-IC output, the bias current distribution circuit acting to generate an output bias current in response to the constant-IC output; an input stage electrically connected with a reference voltage VREF to set the common-mode level, the input stage further including an input circuit, a non-inverting input, an inverting input, an output, and a current bias input, the current bias input electrically connected with the bias current output; an output stage including an output circuit, a non-inverting input electrically connected with the output circuit, an inverting input electrically connected with the output circuit, an output electrically connected with the output circuit, and a current bias input electrically connected with the output circuit, the current bias input further electrically connected with the bias current output. Thus the output bias current biases the pre-amp and output driver of the load circuit to stabilize the small signal and large signal characteristics.
In yet another aspect, the self-biased operational amplifier further comprises the following elements: a first universal power pad VDD and a second universal power pad VSS; a tail current steering device electrically connected with VDD and VSS; a complementary input pair electrically connected in parallel with the tail current steering device via VDD and VSS; a regulated folded cascode electrically connected in parallel with the tail current steering device via VDD and VSS; and a common-mode feedback circuit electrically connected in parallel with the tail current steering device via VDD and VSS. Thus the fully differential input stage allows for a controlled output level for small-signal inputs and a clamp-able output signal when slewing or performing other large-signal functions.
In yet another aspect, the self-biased operational amplifier has a reference circuit that further includes a power control electrically connected with the current distribution circuit for operating the load circuit in either a full power mode or half power mode. Switching to half power mode is accomplished by halving the bias current fed into a load circuit component from the current reference.
In yet another aspect, the self-biased operational amplifier further comprises a power control electrically connected with the bias distribution cell. The power control's purpose is to convert a 0-V or NC (no connection) state or 5-V logic level to a signal to drive the bias current distribution cell.
In yet another aspect, the self-biased operational amplifier's power control operates the load circuit in either a full-power mode or half-power mode. Thus switching to half-power mode is accomplished by halving the bias current fed into a load circuit component from the current reference.
In yet another aspect, the self-biased operational amplifier's output of the input stage further comprises a regulated folded cascode circuit. The regulated folded-cascode structure provides high output resistance and therefore high gain for the first stage.
In yet another aspect, the self-biased operational amplifier further comprises a frequency compensation network electrically connected between the output of the output stage and the input of the output stage. The frequency compensation network comprises a Miller capacitor electrically connected with the frequency compensation network, a matching capacitor, and an array of MOSFETs electrically connected to each other. whereby the compensation network utilizes Miller compensation with right-half plane zero compensation.
The present invention also relates to another self-biased operational amplifier. This self-biased operational amplifier comprises a current reference circuit including: a low level current bias circuit; a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT); and a MOSFET-based constant-IC regulator circuit including a constant-IC input and constant-IC output. The constant-IC input is electrically connected with the VPTAT generator such that the voltage proportional to absolute temperature is the input into the constant-IC regulator circuit. The self-biased operational amplifier also comprises a bias current distribution circuit including: a bias current output, a current reference input, and a power input. The current reference input is electrically connected with the current reference circuit via the constant-IC output. The bias current distribution circuit acts to generate an output bias current in response to the constant-IC output. The self-biased operational amplifier also comprises an input stage electrically connected with a reference voltage VREF to set the common-mode output level. The input stage itself includes the following: a non-inverting input, a inverting input, a output, and a current bias input. The current bias input is electrically connected with the bias current output. The self-biased operational amplifier also comprises an output stage including a non-inverting input, an inverting input, an output, and a current bias input. The current bias input is electrically connected with the bias current output. The self-biased operational amplifier also includes a regulated-ohmic cascode structure to bias the gates of the cascode transistors in the output branch if the amplifier is operated by a power supply voltage which exceeds that of the technology by as much as 50% of the maximum voltage rating. Thus the output bias current is used to bias the pre-amp and output driver of the load circuit to stabilize small signal and large signal characteristics when the power supply voltage is as much as 50% higher than that normally allowed by the technology.
In yet another aspect, the self-biased operational amplifier has a frequency compensation network which is electrically connected between the output of the output stage and the inputs of the output stage. The frequency compensation network itself comprises: a Miller capacitor electrically connected with the frequency compensation network; a matching capacitor; and an array of MOSFETs electrically connected to each other. Thus the compensation network utilizes Miller compensation with right-half-plane zero-compensation.
In yet another aspect, the self-biased operational amplifier's fully-differential input stage further comprises: a first universal power pad VDD and a second universal power pad VSS; a tail current steering device electrically connected with VDD and VSS; a tail current steering device electrically connected with VDD and VSS; a complementary input pair electrically connected in parallel with the tail current steering device via VDD and VSS; a regulated folded cascode electrically connected in parallel with the tail current steering device via VDD and VSS; and a common-mode feedback circuit electrically connected in parallel with the tail current steering device via VDD and VSS. Thus the fully differential input stage allows for a relatively controlled output level for small-signal inputs, and a clamp-able output signal when slewing or performing other large-signal functions.
In yet another aspect, the self-biased operational amplifier has a reference circuit that further includes a power control for operating the load circuit in either a full power mode or half power mode. Thus switching to half power mode is accomplished by halving the bias current fed into a load circuit component from the current reference.



BRIEF DESCRIPTION OF THE DRAWINGS
The objects, features and advantages of the present invention will be apparent from the following detailed descriptions of the various aspects of the invention in conjunction with reference to the following drawings, where:
FIG. 1 is a illustration of a operational amplifier top-level diagram;
FIG. 2 is a graph contrasting the magnitude of parameter variation between the constant inverse coefficient current bias versus temperature versus temperature exponent;
FIG. 3 is a block diagram of the constant inverse coefficient reference circuit;
FIG. 4 is a illustration of the simplified current reference schematic;
FIG. 5 is a illustration of a complete current reference circuit;
FIG. 6a is a illustration of a power control cell;
FIG. 6b is a schematic of a current mirror acting as a current distribution cell that distributes the master reference current to the pre-amp and output stages of a operational amplifier;
FIG. 7 is a schematic of a frequency compensation network.



DETAILED DESCRIPTION
The present invention relates to a circuit and method for biasing electronic devices. The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.
Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.
Before describing the invention in detail, first an introduction provides the reader with a general understanding of the present invention. Next, details of the present invention are provided to give an understanding of the specific aspects. Finally, a summary is provided as a synopsis of the present invention.
(1) Introduction
The present invention has three “principal” aspects. The first is a reference current circuit. The reference current circuit generates a constant inversion current or constant-IC current which is defined by the relationship of a MOSFET gM/ID ratio. The second principal aspect is a bias current distribution circuit. The bias distribution circuit serves to receive and redistribute a constant-IC current received from the current reference circuit to a load circuit that may be biased. The third principle aspect of the invention is a user controlled power control electrically connected with the bias distribution cell in order to manipulate and enhance functionality of the bias distribution cell. This system may be incorporated into a wide variety of biased devices where small- and large-signals must be simultaneously optimized. This system also may be applied to biased devices where a designer wishes to minimize changes in performance of a biased device over a broad temperature range.
The present invention uses a current reference 100 assisted by a bias current distribution circuit 102 to bias a multitude of devices in which it is desirable to simultaneously optimize small- and large-signal characteristics by biasing an electronic device using a constant-IC current defined by the gM/ID relationship. One such device is depicted in FIG. 1 in which a top-level diagram of an operational amplifier 10 is presented. The operational amplifier 10 is comprised of a fully-differential input stage 106, single-ended output stage 108, current reference circuit 100, bias current distribution circuit 102, a power control circuit 104, and a compensation network 110.
In the general case it is often desirable to simultaneously minimize variations in both small- and large-signal performance. To accomplish this, a constant Inversion Coefficient (IC) current reference may be incorporated into a design as the optimum current reference (bias) for achieving this tradeoff. The gM/ID,or constant-IC current, is well suited for biasing a multitude of circuits including CMOS analog circuits. In contrast to previous biasing techniques, such as the constant current and constant (transductance) gM, the constant-IC current biasing technique minimizes fluctuations in addition to operating across broad temperature ranges. An example of the magnitude of change of the large- and small-signal variations for the three types of current references is shown in FIG. 2.
The present invention teaches to a constant-IC biasing circuit for biasing a variety of circuits in order to provide the best possible simultaneous small- and large-signal characteristic performance of a circuit. The present invention further acts to minimize performance variation, and although the benefits of constant-IC biasing are disclosed as they relate to a operation amplifier biased by a constant-IC current across a temperature range of operation of −180° C. to 120° C., further applications for constant-IC current biasing will be readily recognized by those having average skill in the art.
(5) Details of the Invention
One of the limitations of biased circuits is the inability to optimize the performance of small-scale signals such as bandwidth, and large-scale signal variations such as slew rate. Constant-IC biasing is a tradeoff between the large-signal stability provided by the constant current reference 100, and the small-signal stability provided by the constant gM reference 314. A simplified schematic for the current reference 100 is shown in FIG. 4. The basic design theory of the constant-IC current reference 100 is shown in FIG. 3. In order to calculate the constant-IC current reference, a simplified current reference circuit is shown in FIG. 4. The reference 100 operates by creating a proportional-to-absolute temperature (PTAT) voltage that is fed into a gM/ID regulator circuit 100, the output current 132 of which maintains the MOSFET gM/ID ratio, and therefore the inversion coefficient (gM/ID), across temperature. The first two branches of the current reference shown in FIG. 4 make up a simple low-level (low current) current generator 400 that biases M32 402 and M33 404. This small current ensures that M32 402 and M33 404 are biased in weak inversion, in order to create the PTAT voltage.
The drain current equation for a MOSFET in weak inversion is given as:




  
    
      I
      D
    
    =
    
      
        I
        S
      
      ⁢
      
        exp
        ⁡
        
          (
          
            
              
                V
                GS
              
              -
              
                V
                T
              
            
            
              nU
              T
            
          
          )
        
      
    
  
  ,




where IS is the saturation current, UT the thermal voltage, VT the threshold voltage, and n the subthreshold slope parameter. From this the expression for VGS is derived as:




  
    
      V
      GS
    
    =
    
      
        
          ln
          ⁡
          
            (
            
              
                I
                D
              
              
                I
                S
              
            
            )
          
        
        ⁢
        
          nU
          T
        
      
      +
      
        V
        T
      
    
  
  ,




The PTAT voltage is measured from the source of M32 402 to the source of M33 404. Here again, thanks to PDSOI, body effect is eliminated in M32 and M33. M32 and M33 are also matched in layout. Taking the voltage from the source of M32 to source of M33 to be VREF (not to be confused with VREF of the compensation network 110 shown in FIG. 7), the PTAT voltage can be calculated as:




  
    
      
        
          
            V
            REF
          
          =
          
            
              V
              
                GS
                ,
                
                  M
                  ⁢
                  
                    
                  
                  ⁢
                  32
                
              
            
            -
            
              V
              
                GS
                ,
                
                  M
                  ⁢
                  
                    
                  
                  ⁢
                  33
                
              
            
          
        
        ,
      
    
    
      
        
      
    
  
  
    
      
        
          
            V
            REF
          
          =
          
            
              
                ln
                ⁡
                
                  (
                  
                    
                      I
                      D
                    
                    
                      I
                      
                        S
                        ,
                        
                          M
                          ⁢
                          
                            
                          
                          ⁢
                          32
                        
                      
                    
                  
                  )
                
              
              ⁢
              
                nU
                T
              
            
            +
            
              V
              T
            
            -
            
              ⌊
              
                
                  
                    ln
                    ⁡
                    
                      (
                      
                        
                          I
                          D
                        
                        
                          I
                          
                            S
                            ,
                            
                              M
                              ⁢
                              
                                
                              
                              ⁢
                              32
                            
                          
                        
                      
                      )
                    
                  
                  ⁢
                  
                    nU
                    T
                  
                
                +
                
                  V
                  T
                
              
              ⌋
            
          
        
        ,
        and
      
    
    
      
        
      
    
  
  
    
      
        
          
            V
            REF
          
          =
          
            
              
                nU
                T
              
              ⁢
              ln
              ⁢
              
                ⌊
                
                  
                    (
                    
                      
                        I
                        D
                      
                      
                        I
                        
                          S
                          ,
                          
                            M
                            ⁢
                            
                              
                            
                            ⁢
                            32
                          
                        
                      
                    
                    )
                  
                  ⁢
                  
                    (
                    
                      
                        I
                        
                          S
                          ,
                          
                            M
                            ⁢
                            
                              
                            
                            ⁢
                            33
                          
                        
                      
                      
                        I
                        D
                      
                    
                    )
                  
                
                ⌋
              
            
            =
            
              
                nU
                T
              
              ⁢
              
                ln
                ⁡
                
                  (
                  
                    
                      I
                      
                        S
                        ,
                        
                          M
                          ⁢
                          
                            
                          
                          ⁢
                          33
                        
                      
                    
                    
                      I
                      
                        S
                        ,
                        
                          M
                          ⁢
                          
                            
                          
                          ⁢
                          32
                        
                      
                    
                  
                  )
                
              
            
          
        
        ,
      
    
    
      
        
      
    
  




Selecting M33 to have an aspect ratio k times greater than M32,

IS,M33=kIS,M32, and

VREF=nUTln(k).

Since thermal voltage (UT) is equal to kT/q (where k is Boltzmann's constant), the only undefined variables are temperature and the subthreshold slope parameter, n. Neglecting the small variance in n, this makes the voltage VREF dependent upon changes in temperature, and therefore a PTAT voltage.
VREF becomes the input to the gM/ID regulator. A block diagram of which is given in FIG. 3. The current IOUT 304 is defined as:

IOUT=gmVREF,

and ITAIL 306 and ID 308 are defined as:

ITAIL=mIOUT, and





  
    
      I
      D
    
    =
    
      
        I
        TAIL
      
      2
    
  
  ,




respectively

where ITAIL 306 biases the transconductor block 308, implemented using an NMOS input pair (M46 406, M47 408 in FIG. 4). Solving for the constant-IC gM/ID, during balanced (quiescent) operation,



  
    
      
        I
        OUT
      
      =
      
        
          I
          D
        
        ⁡
        
          (
          
            2
            m
          
          )
        
      
    
    ,
    
      

    
    ⁢
    
      
        
          g
          m
        
        ⁢
        
          V
          REF
        
      
      =
      
        
          I
          D
        
        ⁡
        
          (
          
            2
            m
          
          )
        
      
    
    ,
    and
  




  
    
      
        g
        m
      
      
        I
        D
      
    
    =
    
      
        1
        
          V
          REF
        
      
      ⁢
      
        
          (
          
            2
            m
          
          )
        
        .
      
    
  



Taking the definition of EKV for gM/ID and equating it to the gM/ID from our circuit,




  
    
      
        g
        m
      
      
        I
        D
      
    
    ⁢
    
      (
      
        ckt
        .
      
      )
    
  
  =
  
    
      
        
          1
          
            V
            REF
          
        
        ⁢
        
          (
          
            2
            m
          
          )
        
      
      ⇔
      
        
          
            g
            m
          
          
            I
            D
          
        
        ⁢
        
          (
          EKV
          )
        
      
    
    =
    
      
        
          1
          
            nU
            T
          
        
        ⁡
        
          [
          
            1
            
              
                
                  IC
                  +
                  0.25
                
              
              +
              0.5
            
          
          ]
        
      
      .
    
  




The inversion coefficient can then be found




  
    
      ⇒
      
        
          
            IC
            +
            0.25
          
        
        +
        0.5
      
    
    =
    
      
        (
        
          
            V
            REF
          
          
            nU
            T
          
        
        )
      
      ⁢
      
        (
        
          m
          2
        
        )
      
    
  
  ,
  
    

  
  ⁢
  
    
      ⇒
      
        IC
        +
        0.25
      
    
    =
    
      
        [
        
          
            (
            
              
                α
                ⨯
                m
              
              2
            
            )
          
          -
          0.5
        
        ]
      
      2
    
  
  ,
  
    α
    =
    
      (
      
        
          V
          REF
        
        
          nU
          T
        
      
      )
    
  
  ,
  
    

  
  ⁢
  
    
      ⇒
      
        IC
        +
        0.25
      
    
    =
    
      
        [
        
          
            (
            
              
                α
                ⨯
                m
              
              2
            
            )
          
          -
          0.5
        
        ]
      
      2
    
  
  ,
  
    α
    =
    
      (
      
        
          V
          REF
        
        
          nU
          T
        
      
      )
    
  
  ,
  
    
      and
      ⁢
      
        

      
      ⇒
      IC
    
    =
    
      
        
          (
          
            
              α
              ⨯
              m
            
            2
          
          )
        
        2
      
      -
      
        
          (
          
            
              α
              ⨯
              m
            
            2
          
          )
        
        .
      
    
  




Now substituting




  α
  =
  
    
      
        (
        
          
            V
            REF
          
          
            nU
            T
          
        
        )
      
      ⇒
      
        
          
            nU
            T
          
          ⁢
          
            ln
            ⁡
            
              (
              k
              )
            
          
        
        
          nU
          T
        
      
      ⇒
      
        ln
        ⁡
        
          (
          k
          )
        
      
      ⁢
      
        

      
      ⇒
      IC
    
    =
    
      
        
          (
          
            
              
                ln
                ⁡
                
                  (
                  k
                  )
                
              
              ⨯
              m
            
            2
          
          )
        
        2
      
      -
      
        
          (
          
            
              
                ln
                ⁡
                
                  (
                  k
                  )
                
              
              ⨯
              m
            
            2
          
          )
        
        .
      
    
  




The inversion coefficient is therefore dependent on only the aspect ratio (k) of the PTAT voltage generator, M32 402 and M33 404, and the gM/ID current mirror ratio m set by devices M53 412 and M51 410. This shows that the current reference 100 generates a bias condition such that the MOSFET inversion coefficient is independent of temperature.
The complete current reference, including startup circuitry and protection devices, is shown in FIG. 5. Numerous cascode devices are added for static voltage protection. Additional VPTAT generating MOSFETs are placed in series to create a larger VREF voltage for better accuracy. M43 and M43B form a feedback loop that prevents the reference voltage, VREF, from floating toward the power rails and causing biasing problems within the gM/ID regulator.
Referring to FIG. 5, a complete constant current reference 100, including startup circuitry 500, a low-level current bias 502, a VPTAT generator 504, and a simple Common-Mode Feedback (CMFB) device are shown electrically connected with each other.
Referring to FIG. 6a, example circuitry for a power control cell 104 is provided. Although the power control cell 104 may be configured to allow for a user-defined power control setting, as shown in FIG. 6a, the power control circuit 600 is designed to convert a 0-V/NC or 5-V logic level to a signal used to drive the bias current distribution cell 102. The power control cell 104 may also be configured to enable a user to alternate the operation of a load circuit in either a low-power mode or full-power mode. Switching to half-power mode is accomplished by halving the bias current 122 fed into the amplifier's components 118 and 122 from the bias circuitry 102.
If left floating, the input control signal VCONTROL 602 is pulled low by resistor R2 604. This causes M4 606, M5 608, and M6 610 to be shut off. In turn, M12612 is activated, which pulls the output VSWITCH 614 up to a first universal power-pad VDD 616. This high output level is used to signal the half power mode. However, if VCONTROL 602 is pulled high, M1 618, M2 620, and M3 622 are shut off, pulling down M11's 624 gate such that M11 624 shorts the output VSWITCH 614 to VMIDAUX 628. VMIDAUX 628 is a VMID 638 voltage generated by a duplicated VMID 632 cell. This serves to isolate V 628 from the system-wide VMID 638.
This output signal VSWITCH 614 is connected to a current bias circuit 660 that splits the output of the current reference and feeds it into the necessary branches of the operational amplifier. This circuitry is shown in FIG. 6b. VSWITCH 614, coming from a power control 104, is either at a high voltage level, universal power-pad VDD 616, or at VMID 638. If it is high, M7 640 is turned off, in turn shutting off M8 642 and M9 644. This is considered ‘half power’ mode as only half of the ‘full power’ current is being fed into the amplifier. If VSWITCH 614 is at the VMID 638 voltage level, M7 640 is on, mirroring the current from the M1 6, M2, and M3 branch, placing the amplifier (not shown) in ‘full power’ mode. The gates of the cascode current mirror devices M12 642, M14 644, and M16 646 are tied to VMID 638 to prevent SOA violations over PVT.
An input stage differential paired with an example of a dynamic protection device is shown in FIG. 7. This protection is required to shield the input pairs, as well as the current steering devices. As the common-mode input voltage approaches the universal-power-pad VSS 648, the VDG on the NMOS input pair will approach roughly VDD-VSG,P. In the same way, if the common-mode level goes high, the PMOS input pair will experience excessive VGD. Actively biased cascode devices are added to prevent this. However, they must be biased in such a way as not to clamp the amplifiers ICMR at high common-mode voltages, and must prevent low common-mode voltages from creating an SOA violation.
Attached herewith, and incorporated herein in its entirety, is Appendix A, “DESIGN OF A 5-V COMPATIBLE RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIER IN 3.3-V SOI CMOS FOR WIDE TEMPERATURE RANGE OPERATION.”

## Claims

1. A reference current circuit comprising:
a low-level current bias circuit;
a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT) electrically connected to the low-level current bias circuit; and
a MOSFET-based constant inversion coefficient (IC) regulator circuit including a constant-IC input and constant-IC output, the constant-IC input electrically connected with the VPTAT generator such that the voltage proportional-to-absolute temperature is the input into the constant-IC regulator circuit;
whereby the constant-IC output maintains a constant IC current.

2. A reference current circuit as set forth in claim 1, wherein the reference circuit further comprising a bias current distribution circuit, the bias current distribution circuit comprising:
a bias current circuit;
a bias current output electrically connected to the bias current circuit;
a current reference input electrically connected to the bias current circuit; and
a power input electrically connected to the bias current circuit, where the current reference input is electrically connected with the current reference circuit via the constant-IC output, with the bias current distribution circuit generating an output bias current in response to the constant-IC output;
whereby the output bias current is used to bias a load circuit such that the performance characteristics over a wide temperature range are minimized.

3. A reference current circuit as set forth in claim 2, further comprising a startup circuit electrically connected to the reference circuit such that if the startup reference current is larger than the output current of the constant-IC regulator, current is injected into the bias circuitry of the VPTAT generator and the constant-IC regulator to facilitate startup of the current reference.

4. A reference current circuit as set forth in claim 2, further comprising a common-mode feedback (CMFB) circuit electrically connected with the input of the reference circuit whereby the CMFB circuit prevents VPTAT from floating.

5. A self-biased operational amplifier comprising:
a current reference circuit including:
a low-level current bias circuit;
a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT) electrically connected to the low-level current bias circuit;
a MOSFET-based constant-IC regulator circuit including a constant-IC input and constant-IC output, the constant-IC input electrically connected with the VPTAT generator such that the voltage proportional to absolute temperature is the input into the constant-IC regulator circuit;

a bias current distribution circuit comprising:
a bias current circuit;
a bias current output electrically connected to the bias current circuit;
a current reference input electrically connected to the bias current circuit; and
a power input electrically connected to the bias current circuit, where the current reference input is electrically connected with the current reference circuit via the constant-IC output, with the bias current distribution circuit generating an output bias current in response to the constant-IC output;
an input stage electrically connected with a reference voltage VREF to set the common-mode level, the input stage further including:
an input circuit, a non-inverting input, a inverting input, a output, and a current bias input, the current bias input electrically connected with the bias current output; and
an output stage including an output circuit, a non-inverting input electrically connected with the output circuit, an inverting input electrically connected with the output circuit, an output electrically connected with the output circuit, and a current bias input electrically connected with the output circuit, the current bias input further electrically connected with the bias current output;
whereby the output bias current biases the pre-amp and output driver of the load circuit to stabilize the small signal and large signal characteristics.

6. A self-biased operational amplifier as set forth in claim 5, wherein the input stage further comprises:
a first universal power pad VDD and a second universal power pad Vss;
a tail current steering device electrically connected with VDD and Vss;
a complementary input pair electrically connected in parallel with the tail current steering device via VDD and Vss;
a regulated folded cascode electrically connected in parallel with the tail current steering device via VDD and Vss; and
a common-mode feedback circuit electrically connected in parallel with the tail current steering device via VDD and Vss;
whereby the fully differential input stage allows for a controlled output level for small-signal inputs, and a clamp-able output signal when slewing.

7. A self-biased operational amplifier as set forth in claim 6, wherein the reference circuit further includes a power control electrically connected with the current distribution circuit for operating the load circuit in either a full power mode or half power mode whereby switching to half power mode is accomplished by halving the bias current fed into a load circuit component from the current reference.

8. A self-biased operational amplifier as set forth in claim 5, wherein the operational amplifier further comprises a power control electrically connected with the bias distribution cell, the power control to convert a 0-V or NC (no connection) state or 5-V logic level to a signal to drive the bias current distribution cell.

9. A self-biased operational amplifier as set forth in claim 8, wherein the power control operates the load circuit in either a full-power mode or half-power mode whereby switching to half-power mode is accomplished by halving the bias current fed into a load circuit component from the current reference.

10. A self-biased operational amplifier as set forth in claim 5, wherein the output of the input stage further comprises a regulated folded cascode circuit, the regulated folded-cascode structure provides high output resistance and therefore high gain for the first stage.

11. A self-biased operational amplifier as set forth in claim 5, wherein the self-biased operational amplifier further comprises a frequency compensation network electrically connected between the output of the output stage and the input of the output stage, the frequency compensation network comprising:
a Miller capacitor electrically connected with the frequency compensation network;
a matching capacitor; and
an array of MOSFETs electrically connected to each other;
whereby the compensation network utilizes Miller compensation with right-half plane zero compensation.

12. A self-biased operational amplifier comprising:
a current reference circuit including:
a low level current bias circuit;
a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT) electrically connected to the low level current bias circuit; and
a MOSFET-based constant-IC regulator circuit including a constant IC input and constant-IC output, the constant-IC input electrically connected with the VPTAT generator such that the voltage proportional to absolute temperature is the input into the constant-IC regulator circuit;
a bias current distribution circuit including:
a bias current output;
a current reference input; and
a power input, the current reference input is electrically connected with the current reference circuit via the constant-IC output, the bias current distribution circuit acting to generate an output bias current in response to the constant-IC output; and
an input stage electrically connected with a reference voltage VREF to set the common-mode output level, the input stage further including:
a non-inverting input, an inverting input, an output, and an current bias input, the current bias input electrically connected with the bias current output;
an output stage including a non-inverting input, an inverting input, an output, an output branch comprising a cascode structure, and a current bias input, the current bias input electrically connected with the bias current output; and
a regulated-ohmic cascode structure to bias the cascode structure in the output branch;
whereby the output bias current is used to bias the input stage and output driver of the load circuit.

13. A self-biased operational amplifier as set forth in claim 12, wherein a frequency compensation network is electrically connected between the output of the output stage and the inputs of the output stage, the frequency compensation network comprising:
a Miller capacitor electrically connected with the frequency compensation network;
a matching capacitor; and
an array of MOSFETs electrically connected to each other;
whereby the compensation network utilizes Miller compensation with right-half-plane zero-compensation.

14. A self-biased operational amplifier as set forth in claim 13, wherein the input stage further comprises:
a first universal power pad VDD and a second universal power pad Vss;
a tail current steering device electrically connected with VDD and Vss;
a complementary input pair electrically connected in parallel with the tail current steering device via VDD and Vss;
a regulated folded cascode electrically connected in parallel with the tail current steering device via VDD and Vss; and
a common-mode feedback circuitry electrically connected in parallel with the tail current steering device via VDD and Vss;
whereby the fully differential input stage allows for a relatively controlled output level for small-signal inputs, and a clamp-able output signal when slewing (large-signal).

15. A self-biased operational amplifier as set forth in claim 12, wherein the reference circuit further includes a power control for operating the load circuit in either a full power mode or half power mode whereby switching to half power mode is accomplished by halving the bias current fed into a load circuit component from the current reference.

16. A reference current circuit comprising:
a master current reference circuit including:
a bias current output;
a current reference input;
a constant-IC output;
a bias current distribution circuit;
a power input, the current reference input is electrically connected with the current reference circuit via the constant-IC output, the bias current distribution circuit acting to generate an output bias current in response to the constant-IC output;

a bias current distribution cell including:
a low level current bias circuit;
a voltage proportional-to-absolute temperature generator for creating a proportional-to-absolute temperature voltage (VPTAT) electrically connected to the low level current bias circuit; and
a MOSFET-based constant-IC regulator circuit including a constant IC input and constant-IC output, the constant-IC input electrically connected with the VPTAT generator such that the voltage proportional-to-absolute temperature is the input into the constant-IC regulator circuit; and

a power control electrically connected with the bias distribution cell, the power control able to convert a 0-V/NC or 5-V logic level to a signal used to drive the bias current distribution cell;
whereby the output bias current may be used to bias a load circuit such that the performance characteristics over a wide temperature range are stabilized in response to the power control signal.

17. A reference current circuit as set forth in claim 16, further comprising a startup circuit electrically connected to the reference circuit such that if the startup reference current is larger than the output current of the constant-IC regulator, current is injected into the bias circuitry of the VPTAT generator and the constant-IC regulator to facilitate startup of the current reference.

18. A reference current circuit as set forth in claim 16, further comprising a common-mode feedback (CMFB) circuit electrically connected with the input of the reference circuit whereby the CMFB circuit prevents VPTAT from floating.