# Patent

## Title
Bandgap reference voltage circuit

## Abstract

A reference voltage circuit includes first circuitry that generates a thermal voltage that is approximately proportional to absolute temperature, a first voltage multiplier, second circuitry that generates an inverse thermal voltage that is approximately inversely proportional to absolute temperature, a second voltage multiplier and a summer. The first voltage multiplier multiplies the thermal voltage to obtain a first multiplied voltage. The multiplied voltage is not equal to the thermal voltage. The second voltage multiplier multiplies the inverse thermal voltage to obtain a second multiplied voltage. The summer sums the first multiplied voltage with the second multiplied voltage to obtain a reference voltage.

## Background
BACKGROUND
A bandgap reference voltage circuit provides an output reference that is insensitive to temperature, supply voltage and process variations. Bandgap reference voltage circuits are used in a wide variety of electronic circuits, such as wireless communication devices, memory devices, voltage regulators, filters, analog-to-digital converters, digital-to-analog converters and so on.
There are a variety of ways to generate a bandgap reference voltage that, in general, fall into two main categories. The first category is current mode generation of a bandgap reference voltage. The second category is voltage mode generation of a bandgap reference voltage.
In current mode generation of a bandgap reference voltage, current from a first current source that has a positive temperature coefficient is summed with current from a second current source that has a corresponding negative temperature coefficient to produce an output current. A bandgap reference voltage (VREF) is achieved by passing the output current through a resistance. The use of corresponding positive and negative temperature coefficients in the first and second current sources results in the effects of temperature being canceled out, thus stabilizing the bandgap reference voltage (VREF). For examples of bandgap reference voltage circuits that use current mode generation, see U.S. Pat. No. 5,666,046 and United States Patent Application number 2004/0155700A1.
In voltage mode generation of a bandgap reference voltage, a base-emitter voltage (VBE) is generated from a bipolar transistor having a negative coefficient. A thermal voltage (Vt) is generated that is proportional-to-absolute-temperature (PTAT). The thermal voltage (Vt) has a positive coefficient at room temperature. The thermal voltage is equal to the expression kT/q where k is Boltzmann's constant, T is absolute temperature, and q is the elementary electron charge constant. Neither k nor q is temperature-dependent, and the result is that thermal voltage (Vt) is directly proportional-to-absolute-temperature (PTAT). The thermal voltage (Vt) is multiplied by a constant (K) and summed with the voltage (VBE). The result is a reference voltage (VREF) that is described by Equation 1 below:

VREF=VBE+KVt  EQUATION 1

For examples of voltage mode generation of a bandgap reference voltage, see for example, U.S. Pat. No. 4,849,684 and U.S. Pat. No. 5,900,773.
Current mode generation of a bandgap reference voltage has the ability to achieve a bandgap reference as low as approximately 1 volt. Additionally, current mode generation of a bandgap reference voltage can produce a programmable bandgap reference voltage as the output current has zero temperature coefficient. However, current mode generation of a bandgap reference voltage typically requires one or more relatively large resistors, which can result in a large chip size.
Voltage mode generation of a bandgap reference voltage requires smaller total resistance than current mode generation of a bandgap reference voltage, but typically cannot be used for generating a bandgap reference voltage less than about 1.2 volts. Also, using the voltage mode generation of a bandgap reference voltage, the resulting bandgap reference voltage typically is 1.2 volts or a positive integer multiple of 1.2 volts.
SUMMARY OF THE DISCLOSURE
In accordance with an embodiment of the present invention, a reference voltage circuit includes first circuitry that generates a thermal voltage that is approximately proportional to absolute temperature, a first voltage multiplier, second circuitry that generates an inverse thermal voltage that is approximately inversely proportional to absolute temperature, a second voltage multiplier and a summer. The first voltage multiplier multiplies the thermal voltage to obtain a first multiplied voltage. The multiplied voltage is not equal to the thermal voltage. The second voltage multiplier multiplies the inverse thermal voltage to obtain a second multiplied voltage. The summer sums the first multiplied voltage with the second multiplied voltage to obtain a reference voltage.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a block diagram of a circuit that generates a bandgap reference voltage in accordance with another embodiment of the present invention.
FIG. 2, FIG. 3, FIG. 4, FIG. 5 and FIG. 6 show circuit level diagrams of circuits that generate a bandgap reference voltage in accordance with embodiments of the present invention.



DESCRIPTION OF THE EMBODIMENTS
FIG. 1 shows a block diagram of a circuit that generates a bandgap reference voltage (VREF) on an output 22. A base-emitter voltage (VBE) at a location 18 is generated by a diode 12. Diode 12 is connected to a current source 13 and source-to-source voltage (VSS) 11. For example, diode 12 is implemented by a bipolar transistor having a negative temperature coefficient of approximately −2.2 millivolts per degree centigrade (mV/° C.). Base-emitter voltage (VBE) is multiplied by a voltage multiplier 14 with multiplier having a constant value Q. Voltage multiplier 14 produces a signal with multiplied voltage (QVBE) at a location 19.
A voltage generator 15 generates, at a location 20, a thermal voltage (Vt) that is proportional-to-absolute-temperature (PTAT). The thermal voltage (Vt) has a positive coefficient of, for example, +0.085 mV/° C. at room temperature. The thermal voltage is equal to the expression kT/q where k is Boltzmann's constant, T is absolute temperature, and q is the elementary electron charge constant. Neither k nor q is temperature-dependent, and the result is that thermal voltage (Vt) is directly proportional-to-absolute-temperature (PTAT). Thermal voltage (Vt) is multiplied by a voltage multiplier 16 that has a constant value K. Voltage multiplier 16 produces a signal with multiplied voltage (KVt) at a location 21. A voltage sum 17 sums the voltages of the signals at location 19 and location 21 and produces bandgap reference voltage (VREF) on output 22. Bandgap reference voltage (VREF) can be described as set out by Equation 2 below:

VREF=QVBE+KVt  EQUATION 2

The constant value Q can be a fractional or an integer value. When Q is greater than 1, this results in bandgap reference voltage (VREF) being higher than the typical bandgap voltage of 1.2 volts (V). When Q is lower than 1, this results in bandgap reference voltage (VREF) being lower than the typical bandgap voltage of 1.2V. Selection of an appropriate value of Q allows any programmable reference voltage within the circuit range to be achieved. Minimum bandgap reference voltage (VREF) is, for example, about 1 volt.
Differentiating with respect to temperature and using the temperature coefficients for VBE and Vt leads to a set value of K and Q that should theoretically give zero temperature dependence. That is, bandgap reference voltage (VREF) has a zero first order temperature coefficient.
While herein, a base-emitter voltage (VBE) is used as an example of a voltage that is inverse to PTAT, the present invention works equally well when another type of voltage source that is inverse to PTAT is used instead of a base-emitter voltage (VBE). For example, a voltage source that is inverse to PTAT can be generated by a diode or another type of circuitry.
FIG. 2 is a circuit level diagram of a bandgap reference voltage circuit 200 that generates a bandgap reference voltage (VREF) at a location 201, in accordance with the model shown in FIG. 1. A power supply (VCC) voltage 202 and a ground (VSS) voltage 203 are shown. Bandgap reference voltage circuit 200 includes a PTAT current source through circuit 300, a VBE current source circuit 400 and a sum circuit 500.
PTAT current source through circuit 300 includes a pnp bipolar transistor 301, a pnp bipolar transistor 302, an n-channel field effect transistor (FET) 321, an n-channel FET 322, a p-channel FET 331, a p-channel FET 332, a p-channel FET 333 and a resistor 311, connected as shown. VBE current source circuit 400 includes a pnp bipolar transistor 402, an n-channel FET 421, an n-channel FET 422, a p-channel FET 431, a p-channel FET 432, a p-channel FET 433 and a resistor 411, connected as shown. Sum circuit 500 includes a resistor 501, a resistor 502 and a node 510. Locations of a current IPT1, a current IPT2 a current IPT3, a current IBE1 a current IBE2, a current IBE3 are as shown. V311 is the voltage that occurs across resistance 311. The thermal voltage (Vt) is the fractional of the voltage V311. Base emitter voltage (VBE) is the voltage that occurs across resistance 411.
To achieve the PTAT current (IPT3), the thermal voltage Vt is generated across the resistor 311 using FETs 331, 332, 321 and 322 together with pn transistor diodes 301 and 302. FET 331, FET 332, FET 321 and FET 322 function as current mirrors. FET 331 and FET 332 are the same size. Likewise, FET 321, and FET 322 are the same size. This insures that current IPT1 is equal to current IPT2. The emitter area (A301) of PNP bipolar transistor 301 is scaled relative to the emitter area (A302), of PNP bipolar transistor 302. The scaling factor is designated by the variable “x” shown on FIG. 2. The relationship between the emitter areas of PNP bipolar transistors 301 and 302 is given by Equation 3 below:

A301=x*A302  EQUATION 3

For example, bipolar transistor 301 and bipolar transistor 302 are fabricated in near proximity to each other and are well-matched so that bipolar transistor 301 and bipolar transistor 302 operate at the same emitter current. The difference (ΔVBE) in their base-to-emitter voltage is given by Equation 4 below:

ΔVBE=V311=(k*T/q)*In(x)  EQUATION 4

The current IPT1 is also dependent on absolute temperature as demonstrated by Equation 5 below:

IPT1=IPT2=ΔVBE/R311=V311/R311=Vt*In(x)/R311  EQUATION 5

In Equation 4, V311 is the voltage dropped across resistor 311, the thermal voltage Vt is equal to (k*T/q) which is a fractional of V311 and R311 is the resistance of resistor 311.

Since FET 331, FET 332 and FET 333 form current mirrors, the current IPT3 is a multiple of IPT1. The size of FET 333 is M times the size of FET 331 (and M times the size of FET 332), which results in the current being magnified by a factor of M. Since IPT3/IPT1=M, this results in Equation 6 below:

IPT3=M*IPT1  EQUATION 6

Within VBE current source circuit 400, FET 431 and FET 432 are the same size. Likewise, FET 421 and FET 422 are the same size. Thus, current IBE1 and IBE2 are the same value. The values are given by Equation 7 below:

IBE1=IBE2=VBE402/R411  EQUATION 7

In Equation 7, R411 represents the resistance of resistor 411 and VBE402 represents the base-emitter voltage drop across transistor 402.
Since FET 431, FET 432 and FET 433 form current mirrors, the current IBE3 is a multiple of IBE1. FET 433 is N times the size of FET 431 and of FET 432, as represented by N shown on FIG. 2. This results in Equation 8 below:

IBE3=N*IBE1  EQUATION 8

Current IBE3 flows in to resistor 501 to generate part of the voltage drop across 501. The part of the voltage drop across 501 generated by IBE3 is represented by VBE—REF, as further described by Equation 9 below:

VREF—BE=IBE3*R501=N*IBE1*R501=N*VBE402*R501/R411=Q*VBE402  EQUATION 9

In Equation 9, Q=N*R501/R411 and R501 represents the resistance of resistor 501. By appropriately choosing the value of N, R501 and R411, the value of Q can be higher than one or lower than one.
The currents IPT3 and IBE3 are summed at node 510. The reference voltage VREF at node 201 can be generated as shown by Equations 10 below:




  
    
      
        
          
            
              
                V
                REF
              
              =
              
              ⁢
              
                
                  
                    I
                    
                      PT
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  *
                  
                    R
                    502
                  
                
                +
                
                  
                    (
                    
                      
                        I
                        
                          PT
                          ⁢
                          
                            
                          
                          ⁢
                          3
                        
                      
                      +
                      
                        I
                        
                          BE
                          ⁢
                          
                            
                          
                          ⁢
                          3
                        
                      
                    
                    )
                  
                  *
                  
                    R
                    501
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    I
                    
                      PT
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  *
                  
                    (
                    
                      
                        R
                        502
                      
                      +
                      
                        R
                        501
                      
                    
                    )
                  
                
                +
                
                  
                    I
                    
                      BE
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  *
                  
                    R
                    501
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  M
                  *
                  
                    I
                    
                      PT
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  *
                  
                    (
                    
                      
                        R
                        502
                      
                      +
                      
                        R
                        501
                      
                    
                    )
                  
                
                +
                
                  N
                  *
                  
                    I
                    
                      BE
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  *
                  
                    R
                    501
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  M
                  *
                  
                    V
                    t
                  
                  *
                  I
                  ⁢
                  
                    
                  
                  ⁢
                  
                    n
                    ⁡
                    
                      (
                      x
                      )
                    
                  
                  *
                  
                    
                      (
                      
                        
                          R
                          502
                        
                        +
                        
                          R
                          501
                        
                      
                      )
                    
                    /
                    
                      R
                      311
                    
                  
                
                +
                
                  N
                  *
                
              
            
          
        
        
          
            
              
              ⁢
              
                
                  V
                  
                    BE
                    ⁢
                    
                      
                    
                    ⁢
                    402
                  
                
                *
                
                  
                    R
                    501
                  
                  /
                  
                    R
                    411
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  K
                  *
                  
                    V
                    t
                  
                
                +
                
                  Q
                  *
                  
                    V
                    
                      BE
                      ⁢
                      
                        
                      
                      ⁢
                      402
                    
                  
                
              
            
          
        
      
    
    
      
        EQUATIONS
        ⁢
        
          
        
        ⁢
        10
      
    
  




    
    
        where K=M*In(x)*(R502+R501)/R311 Q=N*R501/R411 
    
    


In Equations 10, R502 represents the resistance of resistor 502. With proper selection of values of K and Q the reference voltage VREF can be of any desired voltage within the range of the circuit. Further VREF is a first order temperature compensated reference voltage. Depending on the Q value, the VREF can be higher or lower than the typical bandgap voltage, 1.2V. If the value for Q is higher than 1, then VREF can be higher than 1.2V. If the value for Q is lower than 1, then the reference voltage is lower than 1.2V. The selection of K, that is, the selection of M and R502, depends on the value of Q, because K is used to compensate the negative temperature coefficient of the voltage VBE402.
For example, for a Chartered Semiconductor Manufacturing (CSM) 0.35 micrometer (μm) process where VCC=3 volts, x=8, M=N=1, R311=20 kilohm, R411=90 Kilohm, R501=36 kilohm and R502=37 kilohm it is possible to achieve VREF of approximately 0.5 volts that is almost independent of temperature. Likewise, for a CSM 0.35 μm process when VCC=3 volts, x=8, M=N=1, R311=20 kilohm, R411=40 Kilohm, R501=48 kilohm and R502=161 kilohm it is possible to achieve VREF of approximately 1.5 volts that is almost independent of temperature.
In another embodiment of the present invention, FET pair 321 and 322, and FET pair 421 and 422 can be replaced by operational amplifiers. An advantage of using operation amplifiers is that it can improve power supply voltage rejection ratio (PSRR) performance. An example circuit is shown in FIG. 3.
FIG. 3 is a circuit level diagram of a bandgap reference voltage circuit 1200 that generates a bandgap reference voltage (VREF) at a location 1201, in accordance with the model shown in FIG. 1. A VCC voltage 1202 and a ground voltage 1203 are shown. Bandgap reference voltage circuit 1200 includes a PTAT current source through circuit 1300, a VBE current source circuit 1400 and a sum circuit 1500.
PTAT current source through circuit 1300 includes a pnp bipolar transistor 1301, a pnp bipolar transistor 1302, an operational amplifier 1351, a p-channel FET 1331, a p-channel FET 1332, a p-channel FET 1333 and a resistor 1311, connected as shown. VBE current source circuit 1400 includes a pnp bipolar transistor 1402, an operational amplifier 1451, a p-channel FET 1431, a p-channel FET 1432, a p-channel FET 1433 and a resistor 1411, connected as shown. Sum circuit 1500 includes a resistor 1501, a resistor 1502 and a node 1510. Locations of a current IPT1, a current IPT2, a current IPT3, a current IBE1, a current IBE2, a current IBE3, x, M and N are as shown. V1311 is the voltage that occurs across resistance 1311, the thermal voltage Vt is equal to (k*T/q) which is a fractional of V1311. Base emitter voltage (VBE1402) is the voltage that occurs across resistance 1411.
In another embodiment of the present invention, pnp bipolar transistor 1402 can be eliminated and the base emitter voltage across pnp bipolar transistor 1302 can be used in place of the base emitter voltage across pnp bipolar transistor 1302. This is illustrated by FIG. 4.
FIG. 4 is a circuit level diagram of a bandgap reference voltage circuit 2200 that generates a bandgap reference voltage (VREF) at a location 2201, in accordance with the model shown in FIG. 1. A VCC voltage 2202 and a ground voltage 2203 are shown. Bandgap reference voltage circuit 2200 includes a PTAT current source through circuit 2300, a VBE current source circuit 2400 and a sum circuit 2500.
PTAT current source through circuit 2300 includes a pnp bipolar transistor 2301, a pnp bipolar transistor 2302, an operational amplifier 2351, a p-channel FET 2331, a p-channel FET 2332, a p-channel FET 2333 and a resistor 2311, connected as shown. VBE current source circuit 2400 includes an operational amplifier 2451, a p-channel FET 2431, a p-channel FET 2433 and a resistor 2411, connected as shown. Sum circuit 2500 includes a resistor 2501, a resistor 2502 and a node 2510. Locations of current IPT1, a current IPT2, a current IPT3, a current IBE1, a current IBE3, x, M and N are as shown. V2311 is the voltage that occurs across resistance 2311, the thermal voltage Vt is equal to (k*T/q) which is a fractional of V2311. Base emitter voltage (VBE2302) is the voltage that occurs across resistance 2411.
In another embodiment of the present invention multiple reference voltages can be generated. Each reference voltage can have a different voltage level and all can be independent of temperature. This is illustrated by FIG. 5.
FIG. 5 is a circuit level diagram of a bandgap reference voltage circuit 3200 that generates a bandgap reference voltage (VREF) at a location 3201, in accordance with the model shown in FIG. 1. Bandgap reference voltage circuit 3200 also generates a bandgap reference voltage (V REF) at a location 3211 and a bandgap reference voltage (VREF2) at a location 3221. A VCC voltage 3202 and a ground voltage 3203 are shown. Bandgap reference voltage circuit 3200 includes a PTAT current source through circuit 3300, a VBE current source circuit 3400 and a sum circuit 3500.
PTAT current source through circuit 3300 includes a pnp bipolar transistor 3301, a pnp bipolar transistor 3302, an n-channel FET 3321, an n-channel FET 3322, a p-channel FET 3331, a p-channel FET 3332, a p-channel FET 3333, a p-channel FET 3334, a p-channel FET 3335 and a resistor 3311, connected as shown. VBE current source circuit 3400 includes a pnp bipolar transistor 3402, an n-channel FET 3421, an n-channel FET 3422, a p-channel FET 3431, a p-channel FET 3432, a p-channel FET 3433, a p-channel FET 3434, a p-channel FET 3435 and a resistor 3411, connected as shown. Sum circuit 3500 includes a resistor 3501, a resistor 3502, a resistor 3503, a resistor 3504, a resistor 3505, a resistor 3506, a node 3510, a node 3511 and a node 3512. Locations of a current IPT1, a current IPT2, a current IPT3, a current IPT4, a current IPT5, a current IBE1, a current IBE2, a current IBE3, a current IBE4 a current IBE5 x, M, M1, M2, N, N1 and N2, are as shown. V3311 is the voltage that occurs across resistance 3311, the thermal voltage Vt is equal to (k*T/q) which is a fractional of V3311. Base emitter voltage (VBE3402) is the voltage that occurs across resistance 3411.
By appropriately selecting values of M, M1, M2, N, N1, N2, and the values of resistors 3501, 3502, 3503, 3504, 3505 and 3506, resulting in different values for K and Q, different voltage references for VREF, VREF1, VREF2 can be generated. In alternative embodiments (not shown), operational amplifiers can be used to replace the n-channel FETs shown in FIG. 5, similar to how operational amplifiers are used in FIGS. 3 and 4, to achieve good PSRR performance.
In the circuits shown in FIGS. 2 through 5, the voltage VBE is converted into a corresponding current before, using a resistor, it is converted back to a voltage. It is also possible to directly add part of the voltage VBE into the bandgap reference voltage (VREF) through different circuit topographies. For example, FIG. 6 below shows an example of this.
FIG. 6 is a circuit level diagram of a bandgap reference voltage circuit 4200 that generates a bandgap reference voltage (VREF) at a location 4201, in accordance with the model shown in FIG. 1. A VCC voltage 4202 and a ground voltage 4203 are shown. Bandgap reference voltage circuit 4200 includes a PTAT current source through circuit 4300, a VBE current source circuit 4400 and a sum circuit 4500.
PTAT current source through circuit 4300 includes a pnp bipolar transistor 4301, a pnp bipolar transistor 4302, an operational amplifier 4351, a p-channel FET 4331, a p-channel FET 4332, a p-channel FET 4333 and a resistor 4311, connected as shown. VBE current source circuit 4400 includes an operational amplifier 4451, an operational amplifier 4452, a resistor 4412, a resistor 4413, a resistor 4414 and a resistor 4415, connected as shown. Sum circuit 4500 includes a resistor 4502 and a node 4510. Locations of current IPT1, a current IPT2 and a current IPT3, a current IBE1, a current IBE3, x and M are as shown. V4311 is the voltage that occurs across resistance 4311, the thermal voltage Vt is equal to (k*T/q) which is a fractional of V4311. Base emitter voltage (VBE) is the voltage (VBE4302) that occurs across pnp bipolar transistor 4302. As shown in FIG. 6, the voltage between node 4510 and ground 4203 is equal to Q*VBE4302.
For FIG. 6, the bandgap reference voltage (VREF) is given by Equations 11, below:




  
    
      
        
          
            
              
                V
                REF
              
              =
              
              ⁢
              
                
                  
                    I
                    
                      PT
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  *
                  
                    R
                    4502
                  
                
                +
                
                  Q
                  *
                  
                    V
                    
                      BE
                      ⁢
                      
                        
                      
                      ⁢
                      4302
                    
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  M
                  *
                  
                    V
                    t
                  
                  *
                  
                    
                      R
                      4502
                    
                    /
                    
                      R
                      4311
                    
                  
                
                +
                
                  Q
                  *
                  
                    V
                    
                      BE
                      ⁢
                      
                        
                      
                      ⁢
                      4302
                    
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  K
                  *
                  
                    V
                    t
                  
                
                +
                
                  Q
                  *
                  
                    V
                    
                      BE
                      ⁢
                      
                        
                      
                      ⁢
                      4302
                    
                  
                
              
            
          
        
      
    
    
      
        EQUATIONS
        ⁢
        
          
        
        ⁢
        11
      
    
  




    
    
        where Q=[R4413/(R4412+R4413)]*[1+R4415/R4414] K=M*R4502/R4311 
    
    


The foregoing discussion discloses and describes merely exemplary methods and embodiments of the present invention. As will be understood by those familiar with the art, the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

## Claims

1. A reference voltage circuit, comprising:
a first means for generating a thermal voltage and multiplying the thermal voltage to obtain a first multiplied voltage, the multiplied voltage not being equal to the thermal voltage, wherein the thermal voltage is approximately proportional to absolute temperature, wherein the first means includes:
a first field effect transistor (FET) having a source, a gate and a drain, the source of the first FET being connected to a power supply for the reference voltage circuit and the gate of the first FET being connected to the drain of the first FET,
a second FET having a source, a gate and a drain, the source of the second FET being connected to the power supply, and the gate of the second FET being connected to the gate of the first FET,
a third FET having a source, a gate and a drain, the source of the third FET being connected to the power supply, and the gate of the third FET being connected to the gate of the first FET,
a fourth FET having a source, a gate and a drain, the drain of the fourth FET being connected to the drain of the first FET and the gate of the fourth FET being connected to the drain of the fourth FET,
a fifth FET having a source, a gate and a drain, the drain of the fifth FET being connected to the drain of the second FET and the gate of the fifth FET being connected to the drain of the second FET,
a first bipolar transistor having an emitter, a collector and a base, the base and the collector of the first bipolar transistor being connected to a ground for the reference voltage circuit,
a second bipolar transistor having an emitter, a collector and a base, the base and the collector of the second bipolar transistor being connected to the ground, and the emitter for the second bipolar transistor being connected to the source of the fifth FET, and
a first resistor connected between the source of the fourth FET and the emitter or the first bipolar transistor;

a second means for generating an inverse thermal voltage that is approximately inversely proportional to absolute temperature and multiplying the inverse thermal voltage to obtain a second multiplied voltage, wherein the second means includes:
a sixth FET having a source, a gate and a drain, the source of the sixth FET being connected to the power supply,
a seventh FET having a source, a gate and a drain, the source of the seventh FET being connected to the power supply, and the gate of the seventh FET being connected to the gate of the sixth FET,
an eighth FET having a source, a gate and a drain, the source of the eighth FET being connected to the power supply, and the gate of the eighth FET being connected to the gate of the sixth FET,
a ninth FET having a source, a gate and a drain, the drain of the ninth FET being connected to the drain of the sixth FET, and the gate of the ninth FET being connected to the drain of the ninth FET,
a tenth FET having a source, a gate and a drain, the drain of the tenth FET being connected to the drain of the seventh FET, and the gate of the tenth FET being connected to the drain of the ninth FET,
a third bipolar transistor having an emitter, a collector and a base, the base and the collector of the third bipolar transistor being connected to the ground, and the emitter for the third bipolar transistor being connected to the source of the ninth FET, and
a second resistor connected between the source of the tenth FET and the ground; and,

a third means for summing the first multiplied voltage with the second multiplied voltage to obtain a reference voltage, wherein the third means includes:
a third resistor connected between the drain of the eighth FET and the ground, and
a fourth resistor connected between the drain of the third FET and the drain of the eighth FET.

2. A reference voltage circuit as in claim 1:
wherein the first means additionally includes:
an eleventh FET having a source, a gate and a drain, the source of the eleventh FET being connected to the power supply, and the gate of the eleventh FET being connected to the gate of the first FET, and
a twelfth FET having a source, a gate and a drain, the source of the twelfth FET being connected to the power supply, and the gate of the twelfth FET being connected to the gate of the first FET;

wherein the second means additionally includes:
a thirteenth FET having a source, a gate and a drain, the source of the thirteenth FET being connected to the power supply, and the gate of the thirteenth FET being connected to the gate of the sixth FET, and
a fourteenth FET having a source, a gate and a drain, the source of the fourteenth FET being connected to the power supply, and the gate of the fourteenth FET being connected to the gate of the sixth FET; and,

wherein the third means additionally includes:
a fifth resistor connected between the drain of the thirteenth FET and the ground,
a sixth resistor connected between the drain of the eleventh FET and the drain of the thirteenth FET,
a seventh resistor connected between the drain of the fourteenth FET and the ground, and
a eighth resistor connected between the drain of the twelfth FET and the drain of the fourteenth FET.

3. A reference voltage circuit, comprising:
a first means for generating a thermal voltage and multiplying the thermal voltage to obtain a first multiplied voltage, the multiplied voltage not being equal to the thermal voltage, wherein the thermal voltage is approximately proportional to absolute temperature, wherein the first means includes:
a first field effect transistor (FET) having a source, a gate and a drain, the source of the first FET being connected to a power supply for the reference voltage circuit,
a second FET having a source, a gate and a drain, the source of the second FET being connected to the power supply, and the gate of the second FET being connected to the gate of the first FET,
a third FET having a source, a gate and a drain, the source of the third FET being connected to the power supply, and the gate of the third FET being connected to the gate of the first FET,
a first bipolar transistor having an emitter, a collector and a base, the base and the collector of the first bipolar transistor being connected to a ground for the reference voltage circuit,
a second bipolar transistor having an emitter, a collector and a base, the base and the collector of the second bipolar transistor being connected to the ground, and the emitter for the second bipolar transistor being connected to the drain of the second FET,
a first resistor connected between the drain of the first FET and the emitter or the first bipolar transistor, and
a first operational amplifier (OP AMP) having a negative input, a positive input and an output, the negative input of the first OP AMP being connected to the drain of the first FET, the positive input of the first OP AMP being connected to the drain of the second FET and the output of the first OP AMP being connected to the gate of the first FET;

a second means for generating an inverse thermal voltage that is approximately inversely proportional to absolute temperature and multiplying the inverse thermal voltage to obtain a second multiplied voltage, wherein the second means includes:
a fourth FET having a source, a gate and a drain, the source of the fourth FET being connected to the power supply,
a fifth FET having a source, a gate and a drain, the source of the fifth FET being connected to the power supply, and the gate of the fifth FET being connected to the gate of the fourth FET,
a sixth FET having a source, a gate and a drain, the source of the sixth FET being connected to the power supply, and the gate of the sixth FET being connected to the gate of the fourth FET,
a third bipolar transistor having an emitter, a collector and a base, the base and the collector of the third bipolar transistor being connected to the ground, and the emitter for the third bipolar transistor being connected to the drain of the fifth FET,
a second resistor connected between the drain of the sixth FET and the ground, and
a second OP AMP having a negative input, a positive input and an output, the negative input of the second OP AMP being connected to the drain of the sixth FET, the positive input of the second OP AMP being connected to the drain of the fifth FET and the output of the second OP AMP being connected to the gate of the sixth FET; and,

a third means for summing the first multiplied voltage with the second multiplied voltage to obtain a reference voltage, wherein the third means includes:
a third resistor connected between the drain of the fourth FET and the ground, and
a fourth resistor connected between the drain of the third FET and the drain of the fourth FET.

4. A reference voltage circuit, comprising:
a first means for generating a thermal voltage and multiplying the thermal voltage to obtain a first multiplied voltage, the multiplied voltage not being equal to the thermal voltage, wherein the thermal voltage is approximately proportional to absolute temperature, wherein the first means includes:
a first field effect transistor (FET) having a source, a gate and a drain, the source of the first FET being connected to a power supply for the reference voltage circuit,
a second FET having a source, a gate and a drain, the source of the second FET being connected to the power supply, and the gate of the second FET being connected to the gate of the first FET,
a third FET having a source, a gate and a drain, the source of the third FET being connected to the power supply, and the gate of the third FET being connected to the gate of the first FET,
a first bipolar transistor having an emitter, a collector and a base, the base and the collector of the first bipolar transistor being connected to a ground for the reference voltage circuit,
a second bipolar transistor having an emitter, a collector and a base, the base and the collector of the second bipolar transistor being connected to the ground, and the emitter for the second bipolar transistor being connected to the drain of the second FET,
a first resistor connected between the drain of the first FET and the emitter of the first bipolar transistor, and
a first operational amplifier (OP AMP) having a negative input, a positive input and an output, the negative input of the first OP AMP being connected to the drain of the first FET, the positive input of the first OP AMP being connected to the drain of the second FET and the output of the first OP AMP being connected to the gate of the first FET;

a second means for generating an inverse thermal voltage that is approximately inversely proportional to absolute temperature and multiplying the inverse thermal voltage to obtain a second multiplied voltage, wherein the second means includes:
a fourth FET having a source, a gate and a drain, the source of the fourth FET being connected to the power supply,
a fifth FET having a source, a gate and a drain, the source of the fifth FET being connected to the power supply, and the gate of the fifth FET being connected to the gate of the fourth FET,
a second resistor connected between the drain of the fourth FET and the ground, and
a second OP AMP having a negative input, a positive input and an output, the negative input of the second OP AMP being connected to the drain of the second FET, the positive input of the second OP AMP being connected to the drain of the fourth FET and the output of the second OP AMP being connected to the gate of the fourth FET; and,

a third means for summing the first multiplied voltage with the second multiplied voltage to obtain a reference voltage, wherein the third means includes:
a third resistor connected between the drain of the fifth FET and the ground, and
a fourth resistor connected between the drain of the third FET and the drain of the fifth FET.

5. A reference voltage circuit, comprising:
a first means for generating a thermal voltage and multiplying the thermal voltage to obtain a first multiplied voltage, the multiplied voltage not being equal to the thermal voltage, wherein the thermal voltage is approximately proportional to absolute temperature, wherein the first means includes:
a first field effect transistor (FET) having a source, a gate and a drain, the source of the first FET being connected to a power supply for the reference voltage circuit,
a second FET having a source, a gate and a drain, the source of the second FET being connected to the power supply, and the gate of the second FET being connected to the gate of the first FET,
a third FET having a source, a gate and a drain, the source of the third FET being connected to the power supply, and the gate of the third FET being connected to the gate of the first FET,
a first bipolar transistor having an emitter, a collector and a base, the base and the collector of the first bipolar transistor being connected to a ground for the reference voltage circuit,
a second bipolar transistor having an emitter, a collector and a base, the base and the collector of the second bipolar transistor being connected to the ground, and the emitter for the second bipolar transistor being connected to the drain of the second FET,
a first resistor connected between the drain of the first FET and the emitter or the first bipolar transistor, and
a first operational amplifier (OP AMP) having a negative input, a positive input and an output, the negative input of the first OP AMP being connected to the drain of the first FET, the positive input of the first OP AMP being connected to the drain of the second FET and the output of the first OP AMP being connected to the gate of the first FET;

a second means for generating an inverse thermal voltage that is approximately inversely proportional to absolute temperature and multiplying the inverse thermal voltage to obtain a second multiplied voltage, wherein the second means includes:
a second OP AMP having a negative input, a positive input and an output, the positive input of the second OP AMP being connected to the drain of the second FET and the negative input of the second OP AMP being connected to the output of the second OP AMP,
a third OP AMP having a negative input, a positive input and an output,
a second resistor connected between the output of the second OP AMP and the positive input of the third OP AMP,
a third resistor connected between the positive input of the third OP AMP and the ground,
a fourth resistor connected between the output of the third OP AMP and the negative input of the third OP AMP, and
a fifth resistor connected between the negative input of the third OP AMP and the ground; and,

a third means for summing the first multiplied voltage with the second multiplied voltage to obtain a reference voltage, wherein the third means includes:
a sixth resistor connected between the drain of the third FET and the output of the third OP AMP.

6. A reference voltage circuit, comprising:
a proportional-to-absolute-temperature (PTAT) current source circuit configured to output a PTAT current (IPAT);
a base-emitter current source circuit configured to output an IBE current, the base-emitter current source circuit having a current mirror configuration comprising a pair of transistors operable to propagate an IBE1 current through a VBE resistor coupled to one of a source or a drain of one of the pair of transistors; and
a sum circuit comprising a first resistor (R1)coupled to a second resistor (R2) with a summing node N located at the junction of the first and the second resistors, wherein a distal end of the first resistor (R1)is coupled to the PTAT current source circuit for propagating the PTAT current through the first and the second resistors, and wherein the summing node N is coupled to the base-emitter current source circuit for propagating the IBE current through the second resistor (R2), thereby providing for a summing of the IBE current and the PTAT current through the second resistor (R2) and generation of a reference voltage (VREF) at the summing node N, the reference voltage (VREF) defined by a first equation VREF=IPAT*R1+(IPAT+IBE)*R2 and further defined by a constant (Q) that is directly proportional to a ratio of the second resistor (R2) to the VBE resistor.

7. The reference voltage circuit as in claim 6 wherein the resistance values of the VBE resistor and the second resistor (R2) are selected to generate a desired reference voltage (VREF).

8. The reference voltage circuit as in claim 6, wherein the base-emitter current source circuit further comprises an output transistor having a size parameter N that is selected for generating the IBE current as a multiple of the IBE1 current and defined by a second equation IBE=N*IBE1.

9. The reference voltage circuit as in claim 6, wherein the ratio of the second resistor (R2) to the VBE resistor is selected for setting Q to a value less than one.

10. The reference voltage circuit as in claim 6, wherein the ratio of the second resistor (R2) to the VBE resistor is selected for setting Q to a value greater than one.

11. The reference voltage circuit as in claim 6, wherein the pair of transistors is a pair of N-channel FETs.

12. The reference voltage circuit as in claim 6, wherein the pair of transistors is a pair of P-channel FETs.