# Patent

## Title
Pulse width modulation controller of DC-DC converter

## Abstract

A DC-DC converter including a Pulse Width Modulation (PWM) controller for converting an input voltage into an output voltage is provided. The PWM controller includes a first comparator, receiving a compensated error signal and a ramp signal, wherein when the compensated error signal exceeds the ramp signal, the first comparator generates a trigger signal. The PWM controller further includes a PWM generator coupled to the first comparator, providing a timing signal according to the trigger signal to control the operation of the DC-DC converter.

## Background
This application is a Continuation of U.S. patent application Ser. No. 13/759,640, filed Feb. 5, 2013, and entitled “DC-DC Converter,” now U.S. Pat. No. 8,624,574 which is a continuation of U.S. patent application Ser. No. 12/536,086, filed Aug. 5, 2009, and entitled “DC-DC Converter with a Constant On-Time Pulse Width Modulation Controller”, which is now U.S. Pat. No. 8,395,367, issued Mar. 12, 2013, the entireties of which are incorporated by reference herein.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a controller of a DC-DC converter, and more particularly to a DC-DC converter with a constant on time (COT) pulse width modulation (PWM) controller.
2. Description of the Related Art
DC-DC converters are widely used for various electronic devices. A constant on-time (COT) voltage regulator is one type of DC-DC converter. In general, a COT voltage regulator may turn on a main switch during a fixed period when a feedback voltage is smaller than a reference voltage, and the COT voltage regulator may adjust a turn off period of the main switch so that a steady output voltage may be provided. An output capacitor with a high equivalent series resistance (ESR) disposed in parallel with a load is necessary for a conventional COT voltage regulator, so that a steady output voltage may be provided. However, although a high ESR may help to provide system stability, for a COT voltage regulator, probability of output ripples increase due to the high ESR, which negatively influence the output voltage and power conversion efficiency of the COT voltage regulator.
U.S. Pat. No. 6,583,610 discloses a voltage regulator which operates in ripple-mode and comprises a virtual ripple generator. The virtual ripple generator provides a regulator feedback signal that includes a generated ripple component as a composite signal. The composite signal is generated according to an actual output signal and a ripple signal synchronized to switching cycles of the voltage regulator. Thus, the regulation feedback signal reflects the DC value of the output signal and is responsive to transient changes in the output signal level.
BRIEF SUMMARY OF THE INVENTION
DC-DC converters are provided. An exemplary embodiment of the DC-DC converter for converting an input voltage into an output voltage is provided. The DC-DC converter comprises an input node for receiving the input voltage, an output node for providing the output voltage to a load, an inductor coupled between the output node and a first node, a first transistor coupled between the input node and the first node, a second transistor coupled between the first node and a ground, and a Pulse Width Modulation (PWM) controller. The PWM controller comprises an error amplifier, a first comparator, a PWM generator, and a ramp generator. The error amplifier receives a reference voltage and the output voltage to generate an error signal according to a difference between the reference voltage and the output voltage. The first comparator compares the error signal with a ramp signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input voltage and the output voltage. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage. The PWM controller provides the PWM signal to control the first transistor and the second transistor, so as to convert the input voltage into the output voltage.
Furthermore, another exemplary embodiment of a DC-DC converter for converting an input voltage into an output voltage is provided. The DC-DC converter comprises an input node for receiving the input voltage, an output node for providing the output voltage to a load, an inductor coupled between the output node and a first node, a first transistor coupled between the input node and the first node, a second transistor coupled between the first node and a ground, and a PWM controller. The PWM controller comprises an error amplifier, a sense unit, a compensation unit, a first comparator, a PWM generator, and a ramp generator. The error amplifier receives a reference voltage and the output voltage to generate an error signal according to a difference between the reference voltage and the output voltage. The sense unit senses the inductor to generate a sense current. The compensation unit generates a compensation signal according to the error signal and the sense current. The first comparator compares the compensation signal with a ramp signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input voltage and the output voltage. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage. The PWM controller provides the PWM signal to control the first transistor and the second transistor, so as to convert the input voltage into the output voltage.
Moreover, another exemplary embodiment of a DC-DC converter for converting an input voltage into an output voltage is provided. The DC-DC converter comprises an input node for receiving the input voltage, an output node for providing the output voltage to a load, an inductor coupled between the output node and a first node, a first transistor coupled between the input node and the first node, a second transistor coupled between the first node and a ground, and a PWM controller. The PWM controller comprises an error amplifier, a sense unit, a compensation unit, a first comparator, a PWM generator, and a ramp generator. The error amplifier receives a reference voltage and the output voltage to generate an error signal according to a difference between the reference voltage and the output voltage. The sense unit generates a sense current corresponding to a loading of the load. The compensation unit generates a compensation signal according to the sense current and a ramp signal. The first comparator compares the compensation signal with error signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input voltage and the output voltage. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage. The PWM controller provides the PWM signal to control the first transistor and the second transistor, so as to convert the input voltage into the output voltage.
A detailed description is given in the following embodiments with reference to the accompanying drawings.



BRIEF DESCRIPTION OF DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 shows a DC-DC converter according to an embodiment of the invention;
FIG. 2 shows a waveform diagram illustrating the relationship between the PWM signal SPWM and a current IL flowing through the inductor L of FIG. 1;
FIG. 3A shows a PWM generator according to an embodiment of the invention;
FIG. 3B shows a waveform diagram of the signals in the PWM generator of FIG. 3A;
FIG. 4A shows a ramp generator according to an embodiment of the invention;
FIG. 4B shows a waveform diagram of the signals in the ramp generator of FIG. 4A;
FIG. 5 shows an example illustrating a waveform diagram of the signals of the DC-DC converter of FIG. 1;
FIG. 6 shows another example illustrating a waveform diagram of the signals of the DC-DC converter of FIG. 1;
FIG. 7 shows a DC-DC converter according to another embodiment of the invention.
FIG. 8 shows a DC-DC converter according to another embodiment of the invention;
FIG. 9 shows a DC-DC converter according to another embodiment of the invention; and
FIG. 10 shows a DC-DC converter according to another embodiment of the invention.



DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 1 shows a DC-DC converter 100 according to an embodiment of the invention. The DC-DC converter 100 converts an input voltage VIN received from an input node Nin into an output voltage VOUT. The DC-DC converter 100 comprises two transistors MU and ML, an inductor L, a control unit 110 and a PWM controller 120. The transistor MU is coupled between the input node Nin and a node N1, and the transistor ML is coupled between the node N1 and a ground GND. In this embodiment, the transistors MU and ML are N-type transistors which function as the switches. The control unit 110 receives a pulse width modulation (PWM) signal SPWM provided by the PWM controller 120 and controls the transistors MU and ML to switch on or off according to the PWM signal SPWM. The inductor L is coupled between the node N1, and an output node Nout, wherein the output voltage VOUT is outputted to a load 180 via the output node Nout. Furthermore, an output capacitor C1 with a lower equivalent series resistance (ESR) is coupled between the Nout and the ground GND, and a resistor Resr represents an ESR of the output capacitor C 1.
As shown in FIG. 1, the PWM controller 120 comprises a ramp generator 130, a PWM generator 140, a compensation unit 150, an error amplifier 160 and a comparator 170. The error amplifier 160 receives a reference voltage YREF and the output voltage VOUT to generate an error signal VERR according to a difference between the reference voltage VREF and the output voltage VOUT. The compensation unit 150 coupled between an output terminal of the error amplifier 160 and the comparator 170 is used to compensate the error signal VERR, and the compensation unit 150 comprises a resistor 152 coupled to the output terminal of the error amplifier 160 and a capacitor 154 coupled between the resistor 152 and the ground GND. After the error signal VERR is compensated, the comparator 170 compares the error signal VERR with a ramp signal SRAMP provided by the ramp generator 130 to generate a trigger signal STR. The PWM generator 140 generates the PWM signal SPWM according to the trigger signal STR, the input voltage VIN and the output voltage YOUT. The ramp generator 130 generates the ramp signal SRAMP according to the PWM signal SPWM, the input voltage YIN and the output voltage YOUT.
FIG. 2 shows a waveform diagram illustrating the relationship between the PWM signal SPWM and a current IL flowing through the inductor L of FIG. 1. Referring to FIG. 1 and FIG. 2 together, during a period Ton (i.e. a turn-on time of the PWM signal), the PWM signal SPWM controls the transistor MU to turn on and controls the transistor ML to turn off. During a period Toff (i.e. a turn-off time of the PWM signal), the PWM signal SPWM controls the transistor MU to turn off and controls the transistor ML to turn on. As shown in FIG. 2, the current IL has a minimum current value Imin (ex. Imin=O) at time tI, and then the current IL starts to increase and reaches a maximum current value Imax at time t2, wherein Imax=2×Iavg and Iavg represents an average current value of the current IL. Next, the current IL starts to decrease and reaches the minimum current value Imin at time t3. A rising slope SI of the current IL may be given by the following Equation (1):




  
    
      
        
          S
          ⁢
          
            
          
          ⁢
          1
        
        =
        
          
            
              
                V
                IN
              
              -
              
                V
                OUT
              
            
            L
          
          =
          
            
              
                2
                ×
                
                  I
                  avg
                
              
              
                T
                on
              
            
            .
          
        
      
    
    
      
        (
        1
        )
      
    
  




According to the Equation (1), the period Ton may be given by the following Equation (2):





  
    
      
        
          T
          on
        
        =
        
          
            
              2
              ×
              
                I
                avg
              
              ×
              L
            
            
              
                V
                IN
              
              -
              
                V
                OUT
              
            
          
          .
        
      
    
    
      
        (
        2
        )
      
    
  




In addition, a falling slope S2 of the current IL may be given by the following Equation (3):





  
    
      
        
          
          
            S
            ⁢
            
              
            
            ⁢
            2
          
          
        
        =
        
          
            
              V
              OUT
            
            L
          
          =
          
            
              
                2
                ×
                
                  I
                  avg
                
              
              
                T
                off
              
            
            .
          
        
      
    
    
      
        (
        3
        )
      
    
  




According to the Equation (3), the period Toff may be given by the following Equation (4):





  
    
      
        
          T
          off
        
        =
        
          
            
              2
              ×
              
                I
                avg
              
              ×
              L
            
            
              V
              OUT
            
          
          .
        
      
    
    
      
        (
        4
        )
      
    
  




Therefore, according to the Equations (2) and (4), a period T and a frequency FSW of the PWM signal SPWM may be given by the following Equations (5) and (6), respectively:





  
    
      
        
          T
          =
          
            
              
                T
                on
              
              +
              
                T
                off
              
            
            =
            
              2
              ×
              
                I
                avg
              
              ×
              
                L
                ⁡
                
                  (
                  
                    
                      1
                      
                        
                          V
                          IN
                        
                        -
                        
                          V
                          OUT
                        
                      
                    
                    +
                    
                      1
                      
                        V
                        OUT
                      
                    
                  
                  )
                
              
            
          
        
        ;
        and
      
    
    
      
        (
        5
        )
      
    
  
  
    
      
        
          F
          SW
        
        =
        
          
            1
            T
          
          =
          
            
              1
              
                2
                ×
                
                  I
                  avg
                
                ×
                L
              
            
            ×
            
              
                
                  
                    (
                    
                      
                        V
                        IN
                      
                      -
                      
                        V
                        OUT
                      
                    
                    )
                  
                  ×
                  
                    V
                    OUT
                  
                
                
                  V
                  IN
                
              
              .
            
          
        
      
    
    
      
        (
        6
        )
      
    
  




Suppose that the period Ton has a relationship with a ratio of the output voltage VOUT to the input voltage VIN, i.e.




  
    
      T
      on
    
    =
    
      RCK
      ⁡
      
        (
        
          
            V
            OUT
          
          
            V
            IN
          
        
        )
      
    
  
  ,




wherein the parameters R, C and K are constant. Therefore, the period Ton may be rewritten as the following Equation (7) to obtain the following Equation (8):





  
    
      
        
          
            T
            on
          
          =
          
            
              RCK
              ⁡
              
                (
                
                  
                    V
                    OUT
                  
                  
                    V
                    IN
                  
                
                )
              
            
            =
            
              
                2
                ×
                
                  I
                  avg
                
                ×
                L
              
              
                
                  V
                  IN
                
                -
                
                  V
                  OUT
                
              
            
          
        
        ;
        and
      
    
    
      
        (
        7
        )
      
    
  
  
    
      
        
          2
          ×
          
            I
            avg
          
          ×
          L
        
        =
        
          
            RCK
            ⁡
            
              (
              
                
                  V
                  OUT
                
                
                  V
                  IN
                
              
              )
            
          
          ⁢
          
            
              (
              
                
                  V
                  IN
                
                -
                
                  V
                  OUT
                
              
              )
            
            .
          
        
      
    
    
      
        (
        8
        )
      
    
  




According to the Equation (8), the period Toff may be rewritten as the following Equation (9):





  
    
      
        
          T
          off
        
        =
        
          
            
              2
              ×
              
                I
                avg
              
              ×
              L
            
            
              V
              OUT
            
          
          =
          
            
              RCK
              ⁡
              
                (
                
                  
                    
                      V
                      IN
                    
                    -
                    
                      V
                      OUT
                    
                  
                  
                    V
                    IN
                  
                
                )
              
            
            .
          
        
      
    
    
      
        (
        9
        )
      
    
  




Thus, according to the Equations (7) and (9), the period T of the PWM signal SPWM may be rewritten as the following Equation (10):





  
    
      
         
        
          
            
              
                T
                =
                
                ⁢
                
                  Ton
                  +
                  Toff
                
              
            
          
          
            
              
                =
                
                ⁢
                
                  
                    
                      RCK
                      ⁡
                      
                        (
                        
                          
                            V
                            OUT
                          
                          
                            V
                            IN
                          
                        
                        )
                      
                    
                    +
                    
                      RCK
                      ⁡
                      
                        (
                        
                          
                            
                              V
                              IN
                            
                            -
                            
                              V
                              OUT
                            
                          
                          
                            V
                            IN
                          
                        
                        )
                      
                    
                  
                  =
                  
                    RCK
                    .
                  
                
              
            
          
        
      
    
    
      
        (
        10
        )
      
    
  




Due to the parameters R, C and K being constant, the period T of the PWM signal SPWM is fixed.

FIG. 3A shows a PWM generator 300 according to an embodiment of the invention. The PWM generator 300 comprises an amplifier 310, a current generating unit 320, a comparator 330, a transistor MI, a resistor RRT and a capacitor CON. The amplifier 310 has an inverting input terminal coupled to a node N2, a non-inverting input terminal for receiving a voltage V1 and an output terminal coupled to a gate of the transistor M1, wherein the voltage V1 is a voltage in proportion to the input voltage VIN, i.e. VI=KI×VIN. The current generating unit 320 is used as an example for description, and does not limit the invention. For example, the current generating unit 320 may be a current mirror circuit. When the trigger signal STR is triggered, a current I1 provided by the current generating unit 320 may flow through the transistor MI and the resistor RRT, wherein a current value of the current I1 is determined according to the voltage V1 and the resistor RRT, ex. I1=VI/RRT=KI×VIN/RRT. Simultaneously, the capacitor CON is charged by a current I2 provided by the current generating unit 320 when the trigger signal STR is triggered. In one embodiment, a current value of the current I2 is equal to that of the current I1, ex. I2=K1×VIN/RRT. In another embodiment, the current I2 is a current in proportion to the current I1.
FIG. 3B shows a waveform diagram of the signals in the PWM generator 300 of FIG. 3A. Referring to FIG. 3A and FIG. 3B together, a voltage V c represents a voltage across the capacitor CON. The comparator 330 is used to compare the voltage VC with a voltage V2, wherein the voltage V2 is a voltage in proportion to the output voltage VOUT, i.e. V2=K2×VOUT. When the voltage VC is smaller than the voltage V2, an active state of the PWM signal SPWM is asserted, i.e. the period Ton. On the contrary, when the voltage VC is larger than the voltage V2, an inactive state of the PWM signal SPWM is asserted, i.e. the period Toff. Therefore, the period Ton and the period Toff may be given by the following Equations (11) and (12), respectively:




  
    
      
        
          
            T
            on
          
          =
          
            
              
                
                  C
                  ON
                
                
                  I
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
              
              ⁢
              dV
              ⁢
              
                
              
              ⁢
              2
            
            =
            
              
                R
                RT
              
              ⁢
              
                
                  C
                  on
                
                ⁡
                
                  (
                  
                    
                      K
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                    
                      K
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  )
                
              
              ⁢
              
                
                  V
                  OUT
                
                
                  V
                  IN
                
              
            
          
        
        ;
        and
      
    
    
      
        (
        11
        )
      
    
  
  
    
      
        Toff
        =
        
          
            R
            RT
          
          ⁢
          
            
              C
              on
            
            ⁡
            
              (
              
                
                  K
                  ⁢
                  
                    
                  
                  ⁢
                  2
                
                
                  K
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
              )
            
          
          ⁢
          
            
              
                
                  V
                  IN
                
                -
                
                  V
                  OUT
                
              
              
                V
                IN
              
            
            .
          
        
      
    
    
      
        (
        12
        )
      
    
  




Due to the resistor RRT, the capacitor CON and the parameters K1 and K2 being constant, the period Ton and the period Toff are determined according to the input voltage VIN and the output voltage VOUT.

FIG. 4A shows a ramp generator 400 according to an embodiment of the invention. The ramp generator 400 comprises an amplifier 410, two transistors M2 and M3, a capacitor COFF and a current source 420. The amplifier 410 has an inverting input terminal coupled to the transistor M2, a non-inverting input terminal for receiving a voltage V3 and an output terminal coupled to the inverting input terminal, wherein the voltage V3 is a voltage in proportion to a difference between the input voltage VIN and the output voltage VOUT, i.e. V3=K3×K1×(VIN−VOUT). The transistor M2 is coupled between the output terminal of the amplifier 410 and a node N3, and the transistor M3 is coupled between the node N3 and the current source 420, wherein the ramp signal SRAMP is a voltage at the node N3. The transistors M2 and M3 are controlled by the PWM signal SPWM and a signal SBPWM, respectively, wherein the signal SBPWM is a reversed signal for the PWM signal SPWM. Therefore, the transistor M2 is turned on and the transistor M3 is turned off when an active state of the PWM signal SPWM is asserted, and the transistor M2 is turned off and the transistor M3 is turned on when an inactive state of the PWM signal SPWM is asserted.
FIG. 4B shows a waveform diagram of the signals in the ramp generator 400 of FIG. 4A. Referring to FIG. 4A and FIG. 4B together, the ramp signal SRAMP represents the voltage of the node N3, i.e. a voltage across the capacitor COFF. When an active state of the PWM signal SPWM is asserted, the transistor M2 is turned on and the transistor M3 is turned off, such that the capacitor COFF is charged by the amplifier 410 via the transistor M2, and then the voltage across the capacitor COFF is charged to a voltage level of the voltage V3. On the contrary, when an inactive state of the PWM signal SPWM is asserted, the transistor M2 is turned off and the transistor M3 is turned on, such that the capacitor COFF is discharged by the current source 420 via the transistor M3, and then the voltage across the capacitor COFF is decreased until a subsequent active state of the PWM signal SPWM is asserted. In the embodiment, the current source 420 may sink a current I3 from the node N3 to the ground GND to decrease the ramp signal SRAMP, wherein the current I3 corresponds to the input voltage VIN. The current source 420 is used as an example, and does not limit the invention. In one embodiment, a current value of the current I3 is equal to that of the current I1 of the PWM generator 300 in FIG. 3A, ex. I3=KI×VIN/RRT. In another embodiment, the current I3 is a current in proportion to the current I1. Therefore, a voltage variation dVRAMP of the ramp signal SRAMP during the period Toff may be given by the following Equation (13):




  
    
      
         
        
          
            
              
                
                  dV
                  RAMP
                
                =
                
                ⁢
                
                  
                    I
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  
                    
                      C
                      OFF
                    
                    ⁢
                    dT
                  
                
              
            
          
          
            
              
                =
                
                ⁢
                
                  
                    
                      K
                      ⁢
                      
                        
                      
                      ⁢
                      1
                      ×
                      
                        V
                        IN
                      
                    
                    
                      
                        R
                        RT
                      
                      ×
                      
                        C
                        OFF
                      
                    
                  
                  ⁢
                  
                    T
                    off
                  
                
              
            
          
          
            
              
                =
                
                ⁢
                
                  
                    
                      K
                      ⁢
                      
                        
                      
                      ⁢
                      1
                      ×
                      
                        V
                        IN
                      
                    
                    
                      
                        R
                        RT
                      
                      ×
                      
                        C
                        OFF
                      
                    
                  
                  ×
                  
                    R
                    RT
                  
                  ⁢
                  
                    
                      C
                      ON
                    
                    ⁡
                    
                      (
                      
                        
                          K
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                        
                          K
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      )
                    
                  
                  ⁢
                  
                    
                      
                        V
                        IN
                      
                      -
                      
                        V
                        OUT
                      
                    
                    
                      V
                      IN
                    
                  
                
              
            
          
          
            
              
                
                  =
                  
                  ⁢
                  
                    
                      K
                      ⁢
                      
                        
                      
                      ⁢
                      2
                      ⁢
                      
                        (
                        
                          
                            C
                            ON
                          
                          
                            C
                            OFF
                          
                        
                        )
                      
                      ⁢
                      
                        (
                        
                          
                            V
                            IN
                          
                          -
                          
                            V
                            OUT
                          
                        
                        )
                      
                    
                    =
                    
                      
                        V
                        ⁢
                        
                          
                        
                        ⁢
                        3
                      
                      -
                      
                        V
                        steady
                      
                    
                  
                
                ,
              
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




wherein a voltage level Vsteady represents an ideal steady voltage level of the error signal VERR in FIG. 1. Therefore, according to the Equation (13), the voltage level Vsteady of the error signal VERR may be given by the following Equation (14):





  
    
      
         
        
          
            
              
                
                  V
                  steady
                
                =
                
                ⁢
                
                  
                    V
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                  -
                  
                    K
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      (
                      
                        
                          C
                          ON
                        
                        
                          C
                          OFF
                        
                      
                      )
                    
                    ⁢
                    
                      (
                      
                        
                          V
                          IN
                        
                        -
                        
                          V
                          OUT
                        
                      
                      )
                    
                  
                
              
            
          
          
            
              
                =
                
                ⁢
                
                  
                    K
                    ⁢
                    
                      
                    
                    ⁢
                    3
                    ×
                    K
                    ⁢
                    
                      
                    
                    ⁢
                    1
                    ⁢
                    
                      (
                      
                        
                          V
                          IN
                        
                        -
                        
                          V
                          OUT
                        
                      
                      )
                    
                  
                  -
                  
                    K
                    ⁢
                    
                      
                    
                    ⁢
                    2
                    ⁢
                    
                      (
                      
                        
                          C
                          ON
                        
                        
                          C
                          OFF
                        
                      
                      )
                    
                    ⁢
                    
                      (
                      
                        
                          V
                          IN
                        
                        -
                        
                          V
                          OUT
                        
                      
                      )
                    
                  
                
              
            
          
          
            
              
                =
                
                ⁢
                
                  
                    (
                    
                      
                        (
                        
                          K
                          ⁢
                          
                            
                          
                          ⁢
                          3
                          ×
                          K
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                        )
                      
                      -
                      
                        K
                        ⁢
                        
                          
                        
                        ⁢
                        2
                        ⁢
                        
                          (
                          
                            
                              C
                              ON
                            
                            
                              C
                              OFF
                            
                          
                          )
                        
                      
                    
                    )
                  
                  ⁢
                  
                    
                      (
                      
                        
                          V
                          IN
                        
                        -
                        
                          V
                          OUT
                        
                      
                      )
                    
                    .
                  
                
              
            
          
        
      
    
    
      
        (
        14
        )
      
    
  




By choosing the parameters K1, K2 and K3 and the capacitors CON and COFF appropriately, the error signal VERR is designed to operate at a direct current (DC) operation voltage level, i.e. the ideal steady voltage level Vsteady.

Referring to FIG. 1, a fine adjustment of the error signal VERR is automatically performed for a feedback loop of the DC-DC converter 100 according to the determined DC operation voltage level of the error signal VERR, so as to determine a time period that the trigger signal STR is triggered for every period T of the PWM signal SPWM, thus obtaining a pseudo fix frequency PWM controller.
FIG. 5 shows an example illustrating a waveform diagram of the signals of the DC-DC converter 100 of FIG. 1. By using the error amplifier 160 to generate the error signal VERR and comparing the error signal VERR with the ramp signal SRAMP to adjust a duty cycle of the PWM signal SPWM, an included angle θ between the error signal VERR and the ramp signal SRAMP is large at time t4 and sufficient to avoid noise interference, thus increasing a signal to noise ratio (SNR) thereof. FIG. 6 shows another example illustrating a waveform diagram of the signals of the DC-DC converter 100 of FIG. 1. Referring to FIG. 6 and FIG. 1 together, the period TH represents that the load 180 has a higher loading, and the period TL represents that the load 180 has a lower loading. In addition, the load 180 is changed from the lower to higher loading at time t5 and changed from the higher to lower loading at time t6. When the loading of the load 180 is changed, the comparator 170 may immediately adjust the time period that the trigger signal STR is triggered by comparing the ramp signal SRAMP and the error signal VERR. Therefore, the DC-DC converter 100 may promptly provide the output voltage VOUT in response to the loading of the load 180, thereby increasing system stability.
FIG. 7 shows a DC-DC converter 700 according to another embodiment of the invention. The DC-DC converter 700 is applied to a capacitor C2 with a smaller or zero ESR. Compared with the PWM controller 120 of FIG. 1, a PWM controller 720 of the DCDC converter 700 further comprises a sense unit 730 for sensing a current flowing through the inductor L to generate a sense current Isense to a compensation unit 710, wherein the sense current Isense corresponds to the loading of the load 180. The compensation unit 710 comprises a resistor 712, a capacitor 714, a resistor Rcomp coupled between the error amplifier 160 and the comparator 170, and a current source 716 for sinking a current I4 from the resistor Rcomp to the ground GND. In one embodiment, the current I4 is a current in proportion to the sense current Isense. The current source 716 is used as an example, and does not limit the invention. In the embodiment, a current value of the current I4 is equal to that of the sense current Isense. Therefore, a voltage across the resistor Rcomp is determined according to the sense current Isense and a resistance of the resistor Rcomp. The compensation unit 710 receives the error signal VERR and generates a compensation signal VCOMP to the comparator 170 according to the error signal VERR and the voltage across the resistor Rcomp, such that the comparator 170 of the PWM controller 720 may compare the compensation signal VCOMP with the ramp signal SRAMP provided by the ramp generator 130 to generate the trigger signal STR. The compensation signal VCOMP comprises a feedback signal from the output voltage VOUT associated with a feedback signal from the current flowing through the inductor L, thus avoiding harmonic oscillation and assuring that the output voltage VOUT is stabilized when the capacitor C2 with a smaller ESR. In addition, by adjusting the resistor Rcomp or detecting a gain of the sense current Isense, a gain of a current loop component is adjusted to increase system stability.
FIG. 8 shows a DC-DC converter 800 according to another embodiment of the invention. Compared with the DC-DC converter 700 of FIG. 7, the sense unit 730 of the DC-DC converter 800 is coupled to a node between the transistor MU and the transistor ML, and senses a current flowing through the transistor ML to generate the sense current Isense. Similarly, the sense current Isense provided by the sense unit 830 corresponds to the loading of the load 180.
FIG. 9 shows a DC-DC converter 900 according to another embodiment of the invention. Compared with the DC-DC converter 700 of FIG. 7, the DC-DC converter 900 further comprises a resistor Rsense coupled between the transistor ML and the ground GND. Furthermore, the sense unit 730 of the DC-DC converter 900 is coupled to the resistor Rsense, and senses a current flowing through the resistor Rsense to generate the sense current Isense. Similarly, the sense current Isense provided by the sense unit 930 corresponds to the loading of the load 180.
FIG. 10 shows a DC-DC converter 1000 according to another embodiment of the invention. In a PWM controller 1020 of the DC-DC converter 1000, the comparator 170 compares the error signal VERR with a compensation signal Vcomp provided by a compensation unit 1010 to generate the trigger signal STR. In the embodiment, the sense unit 730 senses a current flowing through the inductor L to generate the sense current Isense, wherein the sense current Isense corresponds to the loading of the load 180. In one embodiment, the sense unit 730 may sense a current flowing through the transistor ML to generate the sense current Isense. In another embodiment, the DC-DC converter 1000 further comprises a resistor coupled between the transistor ML and the ground GND, e.g. the resistor Rsense of FIG. 9, and the sense unit 730 may sense a current flowing through the resistor to generate the sense current Isense. The compensation unit 1010 comprises the resistor 712, the capacitor 714, a resistor Rcomp coupled between the sense unit 730 and the ramp generator 130, and a current source 716 for sinking a current I4 from the resistor Rcomp to the ground GND. Therefore, the compensation unit 1010 generates the compensation signal VCOMP to the comparator 170 according to the sense current Isense, a voltage across the resistor Rcomp and the ramp signal SRAMP. Similarly, the compensation signal VCOMP comprises a feedback signal from the output voltage VOUT associated with a feedback signal from the current flowing through the inductor L, thus avoiding harmonic oscillation and assuring that the output voltage VOUT is stabilized when the capacitor C2 with a smaller ESR. In addition, by adjusting the resistor Rcomp or detecting a gain of the sense current Isense, a gain of a current loop component is adjusted to increase system stability.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.

## Claims

1. A Pulse Width Modulation (PWM) controller of a DC-DC converter, comprising:
a first comparator, receiving a compensated error signal and a ramp signal, wherein when the compensated error signal exceeds the ramp signal, the first comparator generates a trigger signal;
a PWM generator coupled to the first comparator, providing a timing signal according to the trigger signal to control the operation of the DC-DC converter; and
a compensation unit, compensating an error signal and causing an included angle between the compensated error signal and the ramp signal to increase.

2. The PWM controller as claimed in claim 1, further comprising an error signal generator and a compensation unit, wherein the compensation unit is coupled between an output of the error signal generator and a ground, and the compensated error signal is provided by the compensation unit.

3. The PWM controller as claimed in claim 1, wherein the compensated error signal is provided by an error signal generator and a compensation unit coupled to an output of the error signal generator.

4. The PWM controller as claimed in claim 3, wherein the error signal generator receives a reference voltage and a feedback voltage corresponding to an output voltage of the DC-DC converter to provide an error signal, and the compensation unit provides the compensated error signal according to the error signal.

5. The PWM controller of a DC-DC converter as claimed in claim 1, further comprising:
a sense unit, generating a sense current corresponding to an output current of the DC-DC converter;
wherein the compensation unit is coupled to the sense unit, and provides the compensated error signal according to the error signal and the sense current.

6. The PWM controller of a DC-DC converter as claimed in claim 5, wherein the compensation unit further comprises a first resistor and a first capacitor, wherein the first capacitor is coupled to the first resistor in series.

7. The PWM controller of a DC-DC converter as claimed in claim 6, wherein the compensation unit further comprises:
a second resistor coupled between the sense unit and a ramp generator,
wherein a voltage across the second resistor corresponds to the sense current, and the compensated error signal is generated according to the sense current, the ramp signal and the voltage across the second resistor.

8. A Pulse Width Modulation (PWM) controller of a DC-DC converter, comprising:
a sense unit, generating a sensing signal corresponding to an output current of the DC-DC converter;
a compensation unit coupled to the sense unit, generating a compensated signal according to the sensing signal and a ramp signal;
a first comparator, receiving the compensated signal and an error signal, wherein when the error signal exceeds the compensated signal, the first comparator generates a trigger signal;
a PWM generator coupled to the first comparator, providing a timing signal according to the trigger signal; and
a ramp generator coupled to the PWM generator, generating the ramp signal according to the timing signal.

9. A Pulse Width Modulation (PWM) controller of a DC-DC converter, comprising:
a sense unit, generating a sensing signal corresponding to an output current of the DC-DC converter;
a compensation unit coupled to the sense unit, compensating one of an error signal and a ramp signal to generate a compensated signal according to the sensing signal;
a first comparator coupled to the compensation unit, generating a trigger signal according to the compensated signal and another of the error signal and the ramp signal; and
a PWM generator coupled to the first comparator, providing a timing signal according to the trigger signal,
wherein the compensation unit comprises:
a resistor coupled between the sense unit and the first comparator; and
a current source coupled between the resistor and a ground, sinking a current corresponding to the sensing signal from the resistor to the ground.

10. The PWM controller of a DC-DC converter as claimed in claim 9, wherein the PWM controller is coupled to a first switch and a second switch, a node is between the first switch and the second switch, and an output inductor is coupled to the node, the timing signal is used for controlling the operation of the first switch and the second switch.

11. The PWM controller of a DC-DC converter as claimed in claim 10, wherein the sense unit is coupled to the node to generate the sensing signal.

12. The PWM controller of a DC-DC converter as claimed in claim 9, wherein the sensing signal is an inductor current.

13. The PWM controller of a DC-DC converter as claimed in claim 9, wherein when the error signal is compensated by the compensation unit and the compensated signal exceeds the ramp signal, the first comparator generates the trigger signal.

14. The PWM controller of a DC-DC converter as claimed in claim 9, wherein when the ramp signal is compensated by the compensation unit and the error signal exceeds the compensated signal, the first comparator generates the trigger signal.