# Patent

## Title
Dopant etch selectivity control

## Abstract

Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.

## Background
CROSS-REFERENCES TO RELATED APPLICATIONS
This application claims the benefit of U.S. Prov. Pat. App. No. 61/917,251 filed Dec. 17, 2013, and titled “DOPANT ETCH SELECTIVITY CONTROL” by Purayath et al., which is hereby incorporated herein in its entirety by reference for all purposes.


FIELD
Embodiments of the invention relate to etch selectivity control using dopants.
BACKGROUND
Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process which etches one material faster than another helping e.g. a pattern transfer process proceed. Such an etch process is said to be selective of the first material. As a result of the diversity of materials, circuits and processes, etch processes have been developed that selectively remove one or more of a broad range of materials. Until recently, however, there are few options for selectively etching silicon using gas phase reactants.
Dry etch processes are often desirable for selectively removing material from semiconductor substrates. The desirability stems from the ability to gently remove material from miniature structures with minimal physical disturbance. Dry etch processes also allow the etch rate to be abruptly stopped by removing the gas phase reagents. Some dry-etch processes involve the exposure of a substrate to remote plasma by-products formed from one or more precursors. For example, remote plasma generation of nitrogen trifluoride in combination with ion suppression techniques enables silicon to be selectively removed from a patterned substrate when the plasma effluents are flowed into the substrate processing region.
Methods are needed to broaden the utility of remote silicon etch processes.
SUMMARY
Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion in embodiments. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices. A fluorine-containing precursor is excited in a remote plasma to form plasma effluents which are passed through an ion suppressor plate into a substrate processing region where they selectively etch the substrate. The etch selectivity of silicon relative to silicon of another dopant is enabled by inclusion of an ion suppressor plate to ensure a low electron temperature in the substrate processing region.
Embodiments of the invention include methods of etching a substrate. The methods include transferring the substrate into a substrate processing region of a substrate processing chamber. The methods further include flowing a fluorine-containing precursor into a remote plasma region fluidly coupled to the substrate processing region while forming a plasma in the remote plasma region to produce plasma effluents. The methods further include flowing the plasma effluents into the substrate processing region housing the substrate. The plasma effluents flow into the substrate processing region through perforations in an ion suppression element disposed between the remote plasma region and the substrate processing region. The methods further include etching an n-type silicon portion faster than a p-type silicon portion by flowing the plasma effluents into the substrate processing region. The substrate comprises the n-type silicon portion and the p-type silicon portion.
Embodiments of the invention include methods of etching a patterned substrate. The methods include transferring the patterned substrate into a substrate processing region of a substrate processing chamber wherein the patterned substrate comprises polysilicon, a gate oxide and an active area of single crystal silicon. The polysilicon is above the gate oxide which is above the active area of single crystal silicon. The methods further include flowing a fluorine-containing precursor into a remote plasma region fluidly coupled to the substrate processing region while forming a plasma in the remote plasma region to produce plasma effluents. The methods further include flowing the plasma effluents into the substrate processing region housing the substrate. The plasma effluents flow into the substrate processing region through perforations in an ion suppression element disposed between the remote plasma region and the substrate processing region. The methods further include etching the polysilicon and the active area of single crystal silicon. The polysilicon is etched at greater than twice the rate of the active area of single crystal silicon by flowing the plasma effluents into the substrate processing region.
Additional embodiments and features are set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the specification or may be learned by the practice of the disclosed embodiments. The features and advantages of the disclosed embodiments may be realized and attained by means of the instrumentalities, combinations, and methods described in the specification.



DESCRIPTION OF THE DRAWINGS
A further understanding of the nature and advantages of the disclosed embodiments may be realized by reference to the remaining portions of the specification and the drawings.
FIG. 1 is a flow chart of a selective etch process according to embodiments.
FIG. 2 is a sequence of cross sectional views showing three stages during the formation of a flash memory cell according to embodiments.
FIG. 3 is a chart of etch rates of doped silicon samples according to embodiments.
FIG. 4A shows a substrate processing chamber according to embodiments of the invention.
FIG. 4B shows a showerhead of a substrate processing chamber according to embodiments of the invention.
FIG. 5 shows a substrate processing system according to embodiments of the invention.



In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
DETAILED DESCRIPTION
Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion in embodiments. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices. A fluorine-containing precursor is excited in a remote plasma to form plasma effluents which are passed through an ion suppressor plate into a substrate processing region where they selectively etch the substrate. The etch selectivity of silicon relative to silicon of another dopant is enabled by inclusion of an ion suppressor plate to ensure a low electron temperature in the substrate processing region.
In order to better understand and appreciate the invention, reference is now made to FIG. 1 which is a flow chart of a selective etch process 100 according to embodiments. A substrate (which may be patterned) is transferred into a substrate processing region in operation 110. The substrate may have multiple exposed portions of silicon in the form of polysilicon or single crystal silicon domains. Two or more of these domains may have differing dopant characteristics, for example, a single crystal silicon domain may be n-type and a polycrystalline silicon (polysilicon) domain may be p-type.
Nitrogen trifluoride is flowed into a remote plasma region and a remote plasma power is applied (operation 120) to form plasma effluents. The remote plasma region is separated from the substrate processing region by a nickel-plated perforated plate configured to neutralize ions while retaining reactive radicals during passage. Plasma effluents are neutralized while passing through the perforated plate and then flowed into the substrate processing region (operation 125). The nickel-plated perforated plate may be referred to herein as an ion suppression element or an ion suppressor. Other sources of fluorine may be used to augment or replace the nitrogen trifluoride. In general, a fluorine-containing precursor may be flowed into the remote plasma region and the fluorine-containing precursor may include one or more of atomic fluorine, diatomic fluorine, boron trifluoride, chlorine trifluoride, nitrogen trifluoride, perfluorinated hydrocarbons, sulfur hexafluoride and xenon difluoride. Phosphorus-doped silicon on the patterned substrate is selectively etched relative to boron-doped silicon (operation 130). The reactive chemical species and any process effluents are removed from the substrate processing region and then the substrate is removed from the substrate processing region (operation 145).
The remote plasma region is located within a compartment within the substrate processing chamber between the electrode and the perforated plate. The remote plasma region may is fluidly coupled to the substrate processing region by way of perforations in perforated plate. The hardware just described (and elaborated on in the equipment section) may also be used in all processes discussed herein. The perforated plate may be the showerhead described herein or it may be the ion suppression element according to embodiments. The perforated plate may also describe the combination of an ion suppression element and a showerhead.
Generally speaking, selective etching operation 130 may remove n-type silicon from an n-type silicon portion faster than p-type silicon from a p-type silicon portion. The etch selectivity (n-type silicon:p-type silicon) may also be greater than or about 1.5:1, greater than or about 2:1, greater than or about 2.5:1 or preferably greater than or about 3:1 according to embodiments. With respect to silicon oxide, the etch selectivity (n-type or p-type silicon:silicon oxide) may also be greater than or about 500:1, greater than or about 1000:1, greater than or about 1500:1 or preferably greater than or about 2000:1 in embodiments.
The method also includes applying energy to the fluorine-containing precursor in the remote plasma region to generate the plasma effluents in operation 120. The plasma may be generated using RF frequencies such as 13.56 MHz applied using capacitively-coupled power according to embodiments. The remote plasma source power may be between about 10 watts and about 3000 watts, between about 20 watts and about 2000 watts, between about 30 watts and about 1000 watts in embodiments.
In all embodiments described herein which use a remote plasma, the term “plasma-free” may be used to describe the substrate processing region during application of no or essentially no plasma power. A plasma-free substrate processing region may be used during selective etching method 100 in embodiments.
In embodiments, the fluorine-containing precursor (e.g. NF3) is supplied at a flow rate of between about 5 sccm and about 500 sccm, between about 10 sccm and about 300 sccm, between about 25 sccm and about 200 sccm, between about 50 sccm and about 150 sccm or between about 75 sccm and about 125 sccm. The inclusion of hydrogen (e.g. H2) in the remote plasma region was found to reduce the etch selectivity. The remote plasma region and/or the substrate processing region are essentially devoid of hydrogen according to embodiments. The temperature of the substrate for all embodiments described herein may be greater than 0° C. during the etch process. The substrate temperature may be greater than or about −20° C. and less than or about 300° C. The pressure in the substrate processing region may be similar to the pressure in the remote plasma region during substrate processing method 300. The pressure within the substrate processing region may be below or about 10 Torr, below or about 5 Torr, below or about 3 Torr, below or about 2 Torr, below or about 1 Torr or below or about 750 mTorr according to embodiments. In order to ensure adequate etch rate, the pressure may be above or about 0.05 Torr, above or about 0.1 Torr, above or about 0.2 Torr or above or about 0.4 Torr in embodiments. Any of the upper limits on pressure may be combined with lower limits according to embodiments.
In each remote plasmas described herein, the flows of the precursors into the remote plasma region may further include one or more relatively inert gases such as He, N2, Ar. The inert gas can be used to improve plasma stability, ease plasma initiation, and improve process uniformity. Argon is helpful, as an additive, to promote the formation of a stable plasma. Process uniformity is generally increased when helium is included. These additives are present in embodiments throughout this specification. Flow rates and ratios of the different gases may be used to control etch rates and etch selectivity.
In embodiments, an ion suppressor as described in the exemplary equipment section may be used to provide radical and/or neutral species for selectively etching substrates. The ion suppressor may also be referred to as an ion suppression element. In embodiments, for example, the ion suppressor is used to filter fluorine-containing plasma effluents to selectively etch silicon. The ion suppressor may be included in each exemplary process described herein. Using the plasma effluents, an etch rate selectivity of a selected material to a wide variety of materials may be achieved.
The ion suppressor may be used to provide a reactive gas having a higher concentration of radicals than ions. The ion suppressor functions to dramatically reduce or substantially eliminate ionically charged species traveling from the plasma generation region to the substrate. The electron temperature may be measured using a Langmuir probe in the substrate processing region during excitation of a plasma in the remote plasma region on the other side of the ion suppressor. In embodiments, the electron temperature may be less than 0.5 eV, less than 0.45 eV, less than 0.4 eV, or less than 0.35 eV. These extremely low values for the electron temperature are enabled by the presence of the showerhead and/or the ion suppressor positioned between the substrate processing region and the remote plasma region. Uncharged neutral and radical species may pass through the openings in the ion suppressor to react at the substrate. Because most of the charged particles of a plasma are filtered or removed by the ion suppressor, the substrate is not necessarily biased during the etch process. Such a process using radicals and other neutral species can reduce plasma damage compared to conventional plasma etch processes that include sputtering and bombardment. The ion suppressor helps control the concentration of ionic species in the reaction region at a level that assists the process. Embodiments of the present invention are also advantageous over conventional wet etch processes where surface tension of liquids can cause bending and peeling of small features. Ions may erode the desirable gate oxide 230 so the ion suppressor is included to prevent such erosion. A lack of bias power also protects gate oxide 230 from erosion. A lack of ions during selective etching operation 130 may avoid the accumulation of trapped ions in other ways as well in embodiments.
FIG. 2 is a sequence of cross sectional views 200 showing three stages during an exemplary application of selective etch processes disclosed herein according to embodiments. The exemplary application involves formation of a flash memory cell. The upper left cross sectional view shows two active areas (AA) formed from n-type single crystal silicon 220-1. A gap is formed between two active areas, which are the portions near the top of n-type single crystal silicon 220-1. “Top” and “Up” will be used herein to describe portions/directions perpendicularly distal from the substrate plane and further away from the center of mass of the substrate in the perpendicular direction. Gate oxide 230 (e.g. high quality silicon oxide) is positioned above n-type single crystal silicon 220-1 and p-type polysilicon 240-1 is positioned above gate oxide 230. The gate oxide may be thermal silicon oxide produced by exposing single-crystal silicon to an oxygen source. Hardmask 250 is positioned above p-type polysilicon 240-1. An addressing conducting line (e.g. a wordline) 260 is ultimately formed between the two stacks of material just described and shown in the upper left cross sectional view FIG. 2.
The flash memory cell shown in the upper left cross sectional view of FIG. 2 shows p-type polysilicon 240-1 and n-type single crystal silicon 220-1 having left and right vertical walls which occupy the same plane near gate oxide 230. The active area of n-type single crystal silicon 220-1 and/or polysilicon 240-1 may be exposed on two opposing sides during etching according to embodiments. During operation of the completed device, a large voltage (e.g. 10's of volts) is applied between wordline 260 and n-type single crystal silicon 220-1 when writing data to a cell. The closest separation between wordline 260 and n-type single crystal silicon 220-1 may be as small as 15 nm. In embodiments, conducting wordline 260 may extend to within 20 nm of the active area of single crystal and wordline 260 may be configured to apply charge to the polysilicon by tunneling electrons only through gate oxide 230. Repeated writing of data to the memory cells can accumulate trapped charges in the dielectric material which separates wordline 260 and n-type single crystal silicon 220-1. The trapped charges (as well as other defects) may occur near the active area of n-type single crystal silicon 220-1 and are a leading cause of device failure. Device lifetime may be reduced from above ten thousand write cycles to less than two thousand write cycles by trapped charges. Failure is made more likely by the existence of a direct path between wordline 260 and n-type single crystal silicon 220-1. One way to improve device longevity is to recess the sides of n-type single crystal silicon such that gate oxide 230 and, especially, p-type polysilicon 240-1 possess an “overhang” which blocks a direct “line-of-sight” path between wordline 260 and a nearby corner of n-type single crystal silicon 220-2. Etch processes, up until now, have removed polysilicon faster than single crystal silicon, which makes device failure even more likely.
The middle schematic of FIG. 2 shows a device following selective etch process 100 according to embodiments. Etch process 100 removes n-type silicon at over three times the rate of p-type silicon which more than compensates for the ordinarily slower etch rate of single crystal silicon. n-type single crystal silicon 220-2 is narrower than p-type polysilicon 240-2 after selective etch process 100 is performed on the stack of layers shown in the upper left schematic. The lower right schematic of FIG. 2 shows the same stack of layers after a gapfill dielectric is applied (not shown) and wordline 260 is inserted. Now that n-type single crystal silicon is recessed relative to p-type polysilicon, the electric field lines between wordline 260 and the active areas of n-type single crystal silicon 220-2 must curve which discourages the accumulation of device-compromising defects during operation of the completed device.
The active areas of n-type single crystal silicon 220-2 may be etched at least twice the etch rate of the p-type polysilicon 240-2 during etch process 100 in embodiments. The width of p-type polysilicon 240-2 may be larger than the width of n-type single crystal silicon 220-2 according to embodiments. In semiconductor industry terminology, this configuration may be referred to as having a “negative offset”. Analogously, a “positive offset” may be used to refer to a device having a narrower p-type polysilicon 240 than n-type single crystal silicon 220. The selective etch processes described herein may result in flash memory devices having a negative offset rather than the more typical positive offsets achieved in the past. An overhang as small as one or two nanometers may be helpful in extending the longevity of completed flash memory devices. According to embodiments, the width of p-type polysilicon 240-2 may be larger than the width of n-type single crystal silicon 220-2 by at least 1 nm (0.5 nm overhang), at least 2 nm (1 nm overhang) or at least 4 nm (2 nm overhang) according to embodiments.
Similarly, an overhang of gate oxide 230 relative to n-type single crystal silicon 220-2 may be beneficial for reducing an instance of device degradation by charge accumulation. A gate oxide 230 overhang as small as one or two nanometers may be helpful in extending the longevity of completed flash memory devices. According to embodiments, the width of gate oxide 230 may be larger than the width of n-type single crystal silicon 220-2 by at least 1 nm (0.5 nm overhang), at least 2 nm (1 nm overhang) or at least 4 nm (2 nm overhang) according to embodiments.
FIG. 3 is a chart of intrinsic and doped silicon etch rates 300 according to embodiments. Etch rates are charted for intrinsic silicon, phosphorus-doped silicon and boron-doped silicon having a selection of dopant concentrations. Adding phosphorus increases the etch rate of the etch processes disclosed herein, whereas adding boron decreases the etch rate. In addition, increasing the dopant concentration of boron appears to result in a monotonic decrease in etch rate of silicon. In general, n-type silicon described herein may have a dopant concentration greater than or about 1012 cm−3, greater than or about 1014 cm−3, greater than or about 1015 cm−3 or greater than or about 1016 cm−3 according to embodiments. Similarly, p-type silicon may have a dopant concentration greater than or about 1012 cm−3, greater than or about 1014 cm−3, greater than or about 1015 cm−3 or greater than or about 1016 cm−3 according to embodiments.
The examples described focus on an n-type single crystal silicon and p-type polysilicon. In general, the methods described herein may also be used for any two silicon portions including any combination of single crystal silicon, polysilicon and amorphous silicon. For example, the selective etching methods described may be used to selectively etch n-type polysilicon relative to p-type single crystal silicon or to selectively etch n-type single crystal silicon relative to p-type single crystal silicon according to embodiments.
Additional process parameters are disclosed in the course of describing an exemplary processing chamber and system.
Exemplary Processing System
Processing chambers that may implement embodiments of the present invention may be included within processing platforms such as the CENTURA® and PRODUCER® systems, available from Applied Materials, Inc. of Santa Clara, Calif.
FIG. 4A is a substrate processing chamber 1001 according to embodiments. A remote plasma system 1010 may process a fluorine-containing precursor which then travels through a gas inlet assembly 1011. Two distinct gas supply channels are visible within the gas inlet assembly 1011. A first channel 1012 carries a gas that passes through the remote plasma system 1010 (RPS), while a second channel 1013 bypasses the remote plasma system 1010. Either channel may be used for the fluorine-containing precursor in embodiments. On the other hand, the first channel 1012 may be used for the process gas and the second channel 1013 may be used for a treatment gas. The lid (or conductive top portion) 1021 and a perforated partition 1053 are shown with an insulating ring 1024 in between, which allows a unipolar oscillating voltage to be applied to the lid 1021 relative to perforated partition 1053. The unipolar oscillating voltage strikes a plasma in chamber plasma region 1020. The process gas may travel through first channel 1012 into chamber plasma region 1020 and may be excited by a plasma in chamber plasma region 1020 alone or in combination with remote plasma system 1010. If the process gas (the fluorine-containing precursor) flows through second channel 1013, then only the chamber plasma region 1020 is used for excitation. The combination of chamber plasma region 1020 and/or remote plasma system 1010 may be referred to as a remote plasma region herein. The perforated partition (also referred to as a showerhead) 1053 separates chamber plasma region 1020 from a substrate processing region 1070 beneath showerhead 1053. Showerhead 1053 allows a plasma present in chamber plasma region 1020 to avoid directly exciting gases in substrate processing region 1070, while still allowing excited species to travel from chamber plasma region 1020 into substrate processing region 1070.
Showerhead 1053 is positioned between chamber plasma region 1020 and substrate processing region 1070 and allows plasma effluents (excited derivatives of precursors or other gases) created within remote plasma system 1010 and/or chamber plasma region 1020 to pass through a plurality of through-holes 1056 that traverse the thickness of the plate. The showerhead 1053 also has one or more hollow volumes 1051 which can be filled with a precursor in the form of a vapor or gas (such as the fluorine-containing precursor) and pass through blind-holes 1055 into substrate processing region 1070 but not directly into chamber plasma region 1020. Showerhead 1053 is thicker than the length of the smallest diameter 1050 of the through-holes 1056 in embodiments. To maintain a significant concentration of excited species penetrating from chamber plasma region 1020 to substrate processing region 1070, the length 1026 of the smallest diameter 1050 of the through-holes may be restricted by forming larger diameter portions of through-holes 1056 part way through the showerhead 1053. The length of the smallest diameter 1050 of the through-holes 1056 may be the same order of magnitude as the smallest diameter of the through-holes 1056 or less in embodiments. Showerhead 1053 may be referred to as a dual-channel showerhead, a dual-zone showerhead, a multi-channel showerhead or a multi-zone showerhead to convey the existence of through-holes and blind-holes for introducing precursors.
Showerhead 1053 may be configured to serve the purpose of an ion suppressor as shown in FIG. 4A. Alternatively, a separate processing chamber element may be included (not shown) which suppresses the ion concentration traveling into substrate processing region 1070. Lid 1021 and showerhead 1053 may function as a first electrode and second electrode, respectively, so that lid 1021 and showerhead 1053 may receive different electric voltages. In these configurations, unipolar oscillating electrical power may be applied to lid 1021, showerhead 1053, or both. For example, electrical power may be applied to lid 1021 while showerhead 1053 (and/or an ion suppressor) is grounded. The substrate processing system may include a unipolar oscillating voltage generator that provides electrical power to the lid 1021 or showerhead 1053 while the other is grounded. The voltage applied to lid 1021 may facilitate a uniform distribution of plasma (i.e., reduce localized plasma) within chamber plasma region 1020. To enable the formation of a plasma in chamber plasma region 1020, insulating ring 1024 may electrically insulate lid 1021 from showerhead 1053. Insulating ring 1024 may be made from a ceramic and may have a high breakdown voltage to avoid sparking Portions of substrate processing chamber 1001 near the capacitively-coupled plasma components just described may further include a cooling unit (not shown) that includes one or more cooling fluid channels to cool surfaces exposed to the plasma with a circulating coolant (e.g., water).
In the embodiment shown, showerhead 1053 may distribute (via through-holes 1056) process gases which contain fluorine, hydrogen and/or plasma effluents of such process gases upon excitation by a plasma in chamber plasma region 1020. In embodiments, the process gas introduced into the remote plasma system 1010 and/or chamber plasma region 1020 may contain fluorine. The process gas may also include a carrier gas such as helium, argon, nitrogen (N2), etc. Plasma effluents may include ionized or neutral derivatives of the process gas and may also be referred to herein as radical-fluorine referring to the atomic constituent of the process gas introduced.
Through-holes 1056 are configured to suppress the migration of ionically-charged species out of the chamber plasma region 1020 while allowing uncharged neutral or radical species to pass through showerhead 1053 into substrate processing region 1070. These uncharged species may include highly reactive species that are transported with less-reactive carrier gas by through-holes 1056. As noted above, the migration of ionic species by through-holes 1056 may be reduced, and in some instances completely suppressed. Controlling the amount of ionic species passing through showerhead 1053 provides increased control over the gas mixture brought into contact with the underlying wafer substrate, which in turn increases control of the deposition and/or etch characteristics of the gas mixture. For example, adjustments in the ion concentration of the gas mixture can alter the etch selectivity (e.g., the silicon:silicon nitride etch rate ratio).
In embodiments, the number of through-holes 1056 may be between about 60 and about 2000. Through-holes 1056 may have a variety of shapes but are most easily made round. The smallest diameter 1050 of through-holes 1056 may be between about 0.5 mm and about 20 mm or between about 1 mm and about 6 mm in embodiments. There is also latitude in choosing the cross-sectional shape of through-holes, which may be made conical, cylindrical or combinations of the two shapes. The number of blind-holes 1055 used to introduce unexcited precursors into substrate processing region 1070 may be between about 100 and about 5000 or between about 500 and about 2000 in different embodiments. The diameter of the blind-holes 1055 may be between about 0.1 mm and about 2 mm.
Through-holes 1056 may be configured to control the passage of the plasma-activated gas (i.e., the ionic, radical, and/or neutral species) through showerhead 1053. For example, the aspect ratio of the holes (i.e., the hole diameter to length) and/or the geometry of the holes may be controlled so that the flow of ionically-charged species in the activated gas passing through showerhead 1053 is reduced. Through-holes 1056 in showerhead 1053 may include a tapered portion that faces chamber plasma region 1020, and a cylindrical portion that faces substrate processing region 1070. The cylindrical portion may be proportioned and dimensioned to control the flow of ionic species passing into substrate processing region 1070. An adjustable electrical bias may also be applied to showerhead 1053 as an additional means to control the flow of ionic species through showerhead 1053.
Alternatively, through-holes 1056 may have a smaller inner diameter (ID) toward the top surface of showerhead 1053 and a larger ID toward the bottom surface. In addition, the bottom edge of through-holes 1056 may be chamfered to help evenly distribute the plasma effluents in substrate processing region 1070 as the plasma effluents exit the showerhead and promote even distribution of the plasma effluents and precursor gases. The smaller ID may be placed at a variety of locations along through-holes 1056 and still allow showerhead 1053 to reduce the ion density within substrate processing region 1070. The reduction in ion density results from an increase in the number of collisions with walls prior to entry into substrate processing region 1070. Each collision increases the probability that an ion is neutralized by the acquisition or loss of an electron from the wall. Generally speaking, the smaller ID of through-holes 1056 may be between about 0.2 mm and about 20 mm. In other embodiments, the smaller ID may be between about 1 mm and 6 mm or between about 0.2 mm and about 5 mm. Further, aspect ratios of the through-holes 1056 (i.e., the smaller ID to hole length) may be approximately 1 to 20. The smaller ID of the through-holes may be the minimum ID found along the length of the through-holes. The cross-sectional shape of through-holes 1056 may be generally cylindrical, conical, or any combination thereof.
FIG. 4B is a bottom view of a showerhead 1053 for use with a processing chamber according to embodiments. Showerhead 1053 corresponds with the showerhead shown in FIG. 4A. Through-holes 1056 are depicted with a larger inner-diameter (ID) on the bottom of showerhead 1053 and a smaller ID at the top. Blind-holes 1055 are distributed substantially evenly over the surface of the showerhead, even amongst the through-holes 1056 which helps to provide more even mixing than other embodiments described herein.
An exemplary patterned substrate may be supported by a pedestal (not shown) within substrate processing region 1070 when fluorine-containing plasma effluents arrive through through-holes 1056 in showerhead 1053. Though substrate processing region 1070 may be equipped to support a plasma for other processes such as curing, no plasma is present during the etching of patterned substrate, in embodiments.
A plasma may be ignited either in chamber plasma region 1020 above showerhead 1053 or substrate processing region 1070 below showerhead 1053. A plasma is present in chamber plasma region 1020 to produce the radical-fluorine from an inflow of the fluorine-containing precursor. A unipolar oscillating voltage (shifted or otherwise transformed to generally confine to one polarity) is applied between the conductive top portion (lid 1021) of the processing chamber and showerhead 1053 to ignite a plasma in chamber plasma region 1020 during deposition. The unipolar oscillating voltage applied to lid 1021 is shifted such to not center about the potential of showerhead 1053. A unipolar oscillating voltage power supply generates a unipolar oscillating frequency of less than or about 1,000 kHz, less than or about 500 kHz, less than or about 300 kHz or between 1 kHz and 200 kHz according to embodiments.
The top plasma may be left at low or no power when the bottom plasma in the substrate processing region 1070 is turned on to either cure a film or clean the interior surfaces bordering substrate processing region 1070. A plasma in substrate processing region 1070 is ignited by applying the unipolar oscillating voltage between showerhead 1053 and the pedestal or bottom of the chamber. A cleaning gas may be introduced into substrate processing region 1070 while the plasma is present.
The pedestal may have a heat exchange channel through which a heat exchange fluid flows to control the temperature of the substrate. This configuration allows the substrate temperature to be cooled or heated to maintain relatively low temperatures (from room temperature through about 120° C.). The heat exchange fluid may comprise ethylene glycol and water. The wafer support platter of the pedestal (preferably aluminum, ceramic, or a combination thereof) may also be resistively heated to achieve relatively high temperatures (from about 120° C. through about 1100° C.) using an embedded single-loop embedded heater element configured to make two full turns in the form of parallel concentric circles. An outer portion of the heater element may run adjacent to a perimeter of the support platter, while an inner portion runs on the path of a concentric circle having a smaller radius. The wiring to the heater element passes through the stem of the pedestal.
The chamber plasma region and/or a region in a remote plasma system may be referred to as a remote plasma region. In embodiments, the radical precursors (e.g. radical-fluorine) are formed in the remote plasma region and travel into the substrate processing region where they may individually react with chamber walls or the substrate surface. Plasma power may essentially be applied only to the remote plasma region, in embodiments, to ensure that the radical-fluorine (which may also be referred to as plasma effluents) are not further excited in the substrate processing region.
In embodiments employing a chamber plasma region, the excited plasma effluents are generated in a section of the substrate processing region partitioned from a deposition region. The deposition region, also known herein as the substrate processing region, is where the plasma effluents mix and react to etch the patterned substrate (e.g., a semiconductor wafer). The excited plasma effluents may also be accompanied by inert gases (in the exemplary case, argon). The substrate processing region may be described herein as “plasma-free” during etching of the substrate. “Plasma-free” does not necessarily mean the region is devoid of plasma. A relatively low concentration of ionized species and free electrons created within the remote plasma region do travel through pores (apertures) in the partition (showerhead/ion suppressor) due to the shapes and sizes of through-holes 1056. In some embodiments, there is essentially no concentration of ionized species and free electrons within the substrate processing region. In embodiments, the electron temperature may be less than 0.5 eV, less than 0.45 eV, less than 0.4 eV, or less than 0.35 eV in substrate processing region 1070 during excitation of a remote plasma. The borders of the plasma in the chamber plasma region are hard to define and may encroach upon the substrate processing region through the apertures in the showerhead. In the case of an inductively-coupled plasma, a small amount of ionization may be effected within the substrate processing region directly. Furthermore, a low intensity plasma may be created in the substrate processing region without eliminating desirable features of the forming film. All causes for a plasma having much lower intensity ion density than the chamber plasma region (or a remote plasma region, for that matter) during the creation of the excited plasma effluents do not deviate from the scope of “plasma-free” as used herein.
The fluorine-containing precursor) may be flowed into chamber plasma region 1020 at rates between about 5 sccm and about 500 sccm, between about 10 sccm and about 300 sccm, between about 25 sccm and about 200 sccm, between about 50 sccm and about 150 sccm or between about 75 sccm and about 125 sccm in embodiments.
The flow rate of the fluorine-containing precursor into the chamber may account for 0.05% to about 20% by volume of the overall gas mixture; the remainder being carrier gases. The fluorine-containing precursor are flowed into the remote plasma region but the plasma effluents have the same volumetric flow ratio, in embodiments. A purge or carrier gas may be initiated into the remote plasma region before that of the fluorine-containing gas to stabilize the pressure within the remote plasma region.
Plasma power applied to the remote plasma region can be a variety of frequencies or a combination of multiple frequencies. In the exemplary processing system the plasma is provided by unipolar oscillating power delivered between lid 1021 and showerhead 1053. The energy is applied using a capacitively-coupled plasma unit. The remote plasma source power may be between about 10 watts and about 3000 watts, between about 20 watts and about 2000 watts, between about 30 watts and about 1000 watts, or between about 40 watts and about 500 watts in embodiments.
Substrate processing region 1070 can be maintained at a variety of pressures during the flow of carrier gases and plasma effluents into substrate processing region 1070. The pressure within the substrate processing region is below or about 50 Torr, below or about 30 Torr or below or about 20 Torr. The pressure may be above or about 0.1 Torr, above or about 0.2 Torr, above or about 0.5 Torr or above or about 1 Torr in embodiments. Lower limits on the pressure may be combined with upper limits on the pressure to obtain embodiments.
In one or more embodiments, the substrate processing chamber 1001 can be integrated into a variety of multi-processing platforms, including the ProducerTM GT, CenturaTM AP and EnduraTM platforms available from Applied Materials, Inc. located in Santa Clara, Calif. Such a processing platform is capable of performing several processing operations without breaking vacuum. Processing chambers that may implement embodiments of the present invention may include dielectric etch chambers or a variety of chemical vapor deposition chambers, among other types of chambers.
Embodiments of the etching systems may be incorporated into larger fabrication systems for producing integrated circuit chips. FIG. 5 shows one such system 1101 of etching, deposition, baking and curing chambers according to embodiments. In the figure, a pair of FOUPs (front opening unified pods) 1102 supply substrate substrates (e.g., 300 mm diameter wafers) that are received by robotic arms 1104 and placed into a low pressure holding areas 1106 before being placed into one of the wafer processing chambers 1108a-f. A second robotic arm 1110 may be used to transport the substrate wafers from the low pressure holding areas 1106 to the wafer processing chambers 1108a-f and back. Each wafer processing chamber 1108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes described herein in addition to cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etch, pre-clean, degas, orientation and other substrate processes.
The wafer processing chambers 1108a-f may include one or more system components for depositing, annealing, curing and/or etching a dielectric film on the substrate wafer. In one configuration, two pairs of the processing chamber (e.g., 1108c-d and 1108e-f) may be used to deposit dielectric material on the substrate, and the third pair of processing chambers (e.g., 1108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 1108a-f) may be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be carried out on chamber(s) separated from the fabrication system shown in different embodiments.
The substrate processing system is controlled by a system controller. In an exemplary embodiment, the system controller includes a hard disk drive, a floppy disk drive and a processor. The processor contains a single-board computer (SBC), analog and digital input/output boards, interface boards and stepper motor controller boards. Various parts of CVD system conform to the Versa Modular European (VME) standard which defines board, card cage, and connector dimensions and types. The VME standard also defines the bus structure as having a 16-bit data bus and a 24-bit address bus.
System controller 1157 is used to control motors, valves, flow controllers, power supplies and other functions required to carry out process recipes described herein. A gas handling system 1155 may also be controlled by system controller 1157 to introduce gases to one or all of the wafer processing chambers 1108a-f. System controller 1157 may rely on feedback from optical sensors to determine and adjust the position of movable mechanical assemblies in gas handling system 1155 and/or in wafer processing chambers 1108a-f. Mechanical assemblies may include the robot, throttle valves and susceptors which are moved by motors under the control of system controller 1157.
In an exemplary embodiment, system controller 1157 includes a hard disk drive (memory), USB ports, a floppy disk drive and a processor. System controller 1157 includes analog and digital input/output boards, interface boards and stepper motor controller boards. Various parts of multi-chamber processing system 1101 which contains substrate processing chamber 1001 are controlled by system controller 1157. The system controller executes system control software in the form of a computer program stored on computer-readable medium such as a hard disk, a floppy disk or a flash memory thumb drive. Other types of memory can also be used. The computer program includes sets of instructions that dictate the timing, mixture of gases, chamber pressure, chamber temperature, RF power levels, susceptor position, and other parameters of a particular process.
A process for etching, depositing or otherwise processing a film on a substrate or a process for cleaning chamber can be implemented using a computer program product that is executed by the controller. The computer program code can be written in any conventional computer readable programming language: for example, 68000 assembly language, C, C++, Pascal, Fortran or others. Suitable program code is entered into a single file, or multiple files, using a conventional text editor, and stored or embodied in a computer usable medium, such as a memory system of the computer. If the entered code text is in a high level language, the code is compiled, and the resultant compiler code is then linked with an object code of precompiled Microsoft Windows® library routines. To execute the linked, compiled object code the system user invokes the object code, causing the computer system to load the code in memory. The CPU then reads and executes the code to perform the tasks identified in the program.
The interface between a user and the controller may be via a touch-sensitive monitor and may also include a mouse and keyboard. In one embodiment two monitors are used, one mounted in the clean room wall for the operators and the other behind the wall for the service technicians. The two monitors may simultaneously display the same information, in which case only one is configured to accept input at a time. To select a particular screen or function, the operator touches a designated area on the display screen with a finger or the mouse. The touched area changes its highlighted color, or a new menu or screen is displayed, confirming the operator's selection.
As used herein “substrate” may be a support substrate with or without layers formed thereon. The patterned substrate may be an insulator or a semiconductor of a variety of doping concentrations and profiles and may, for example, be a semiconductor substrate of the type used in the manufacture of integrated circuits. Exposed “silicon” of the patterned substrate is predominantly Si but may include minority concentrations of other elemental constituents (e.g. nitrogen, oxygen, hydrogen, carbon). Exposed “silicon nitride” of the patterned substrate is predominantly Si3N4 but may include minority concentrations of other elemental constituents (e.g. oxygen, hydrogen, carbon). Exposed “silicon oxide” of the patterned substrate is predominantly SiO2 but may include minority concentrations of other elemental constituents (e.g. nitrogen, hydrogen, carbon). In some embodiments, silicon oxide films etched using the methods disclosed herein consist essentially of silicon and oxygen.
The term “precursor” is used to refer to any process gas which takes part in a reaction to either remove material from or deposit material onto a surface. “Plasma effluents” describe gas exiting from the chamber plasma region and entering the substrate processing region. Plasma effluents are in an “excited state” wherein at least some of the gas molecules are in vibrationally-excited, dissociated and/or ionized states. A “radical precursor” is used to describe plasma effluents (a gas in an excited state which is exiting a plasma) which participate in a reaction to either remove material from or deposit material on a surface. “Radical-fluorine”) are radical precursors which contain fluorine but may contain other elemental constituents. The phrase “inert gas” refers to any gas which does not form chemical bonds when etching or being incorporated into a film. Exemplary inert gases include noble gases but may include other gases so long as no chemical bonds are formed when (typically) trace amounts are trapped in a film.
The terms “gap” and “trench” are used throughout with no implication that the etched geometry has a large horizontal aspect ratio. Viewed from above the surface, trenches may appear circular, oval, polygonal, rectangular, or a variety of other shapes. A trench may be in the shape of a moat around an island of material. The term “via” is used to refer to a low aspect ratio trench (as viewed from above) which may or may not be filled with metal to form a vertical electrical connection. As used herein, a conformal etch process refers to a generally uniform removal of material on a surface in the same shape as the surface, i.e., the surface of the etched layer and the pre-etch surface are generally parallel. A person having ordinary skill in the art will recognize that the etched interface likely cannot be 100% conformal and thus the term “generally” allows for acceptable tolerances.
Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the disclosed embodiments. Additionally, a number of well known processes and elements have not been described to avoid unnecessarily obscuring the present invention. Accordingly, the above description should not be taken as limiting the scope of the invention.
Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.
As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a process” includes a plurality of such processes and reference to “the dielectric material” includes reference to one or more dielectric materials and equivalents thereof known to those skilled in the art, and so forth.
Also, the words “comprise,” “comprising,” “include,” “including,” and “includes” when used in this specification and in the following claims are intended to specify the presence of stated features, integers, components, or steps, but they do not preclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

## Claims

1. A method of etching a substrate, the method comprising:
transferring the substrate into a substrate processing region of a substrate processing chamber;
flowing a fluorine-containing precursor into a remote plasma region fluidly coupled to the substrate processing region while forming a plasma in the remote plasma region to produce plasma effluents;
flowing the plasma effluents into the substrate processing region housing the substrate, wherein the plasma effluents flow into the substrate processing region through perforations in an ion suppression element disposed between the remote plasma region and the substrate processing region; and
etching an n-type silicon portion faster than a p-type silicon portion by flowing the plasma effluents into the substrate processing region, wherein the substrate comprises the n-type silicon portion and the p-type silicon portion.

2. The method of claim 1 wherein the n-type silicon portion is phosphorus-doped.

3. The method of claim 1 wherein the p-type silicon portion is boron-doped.

4. The method of claim 1 wherein etching the n-type silicon portion comprises etching the n-type silicon portion faster than the p-type silicon portion by a multiplicative factor of at least two.

5. The method of claim 1 wherein the n-type silicon portion is below the p-type silicon portion when the substrate is horizontal with n-type silicon portion and p-type silicon portion on top of the substrate.

6. The method of claim 1 wherein a dopant concentration of the n-type silicon portion is greater than or about 1014 cm−3.

7. The method of claim 1 wherein a dopant concentration of the p-type silicon portion is greater than or about 1015 cm−3.

8. A method of etching a patterned substrate, the method comprising:
transferring the patterned substrate into a substrate processing region of a substrate processing chamber wherein the patterned substrate comprises polysilicon, a gate oxide and an active area of single crystal silicon, wherein the polysilicon is above the gate oxide which is above the active area of single crystal silicon;
flowing a fluorine-containing precursor into a remote plasma region fluidly coupled to the substrate processing region while forming a plasma in the remote plasma region to produce plasma effluents;
flowing the plasma effluents into the substrate processing region housing the patterned substrate, wherein the plasma effluents flow into the substrate processing region through perforations in an ion suppression element disposed between the remote plasma region and the substrate processing region; and
etching the polysilicon and the active area of single crystal silicon with the plasma effluents, wherein the polysilicon is etched at greater than twice the rate of the active area of single crystal silicon.

9. The method of claim 8 wherein the active area of single crystal silicon is n-type and the polysilicon is p-type.

10. The method of claim 8 wherein the polysilicon is exposed on two opposing sides during etching the polysilicon and the active area of single crystal silicon.

11. The method of claim 8 wherein the active area of single crystal silicon is exposed on two opposing sides during etching the polysilicon and the active area of single crystal silicon.

12. The method of claim 8 wherein a width of the active area of single crystal silicon is smaller than a width of the polysilicon following etching the polysilicon and the active area of single crystal silicon.

13. The method of claim 8 wherein a width of the polysilicon is larger than a width of the active area of single crystal silicon by at least 1 nm following etching the polysilicon and the active area of single crystal silicon.

14. The method of claim 8 further comprising forming a conducting wordline which extends to within 20 nm of the active area of single crystal silicon, wherein the conducting wordline is configured to apply charge to the polysilicon by tunneling electrons only through the gate oxide.

15. The method of claim 8 wherein the gate oxide is thermal silicon oxide.