# Patent

## Title
Rectifier-free piezoelectric energy harverster and battery charger

## Abstract

A circuit for harvesting electrical energy from a piezoelectric source and for storing the electrical energy in a battery includes an inductor that is configured to store electrical energy. A diode bridge-free switching network is configured to: direct electrical energy from the piezoelectric source to the inductor during a first portion of a piezoelectric charge generating cycle; and direct electrical energy from the inductor to the battery during a second portion of the piezoelectric charge generating cycle.

## Background
CROSS-REFERENCE TO RELATED APPLICATION(S)
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 61/345,770, filed May 18, 2010, the entirety of which is hereby incorporated herein by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrical energy harvesting systems and, more specifically, to an electrical energy harvesting system that is rectifier free.
2. Description of the Related Art
Microscale and nanoscale integrated devices are used in a variety of applications, including in biomedical implants and sensors. Many such devices are powered by electrical energy. Conventional power sources, such as electrochemical batteries, are often used to power such integrated devices. However, in certain applications, such as biomedical implants, replacing or recharging batteries may be difficult and costly. One approach to recharging such batteries is to harvest electrical energy from piezoelectric structures subjected to ambient motion (such as muscle flexing in the case of biomedical implants or vibration in the case of environmental sensors, etc.). Typical piezoelectric structures include cantilevers made from a piezoelectric material, such as certain crystals, organic materials and ceramic structures, generate electrical charge when subject to mechanical force. For example, a zinc oxide crystal will generate a charge imbalance when subjected to a bending force. Other piezoelectric structures generate charge when subjected to stress or strain.
Given that many piezoelectric structures are subject to periodic movements that have both a positive cycle and a negative cycle (such as a vibrating cantilever), the electricity generated by a piezoelectric structure is typically in the alternating current form. However, most batteries require direct current to be recharged. Therefore, recharging a battery from a piezoelectric structure usually requires a device to convert the alternating current to direct current.
A typical microscale alternating current to direct current converter includes a diode bride rectifier. Such a rectifier employs an arrangement of diodes that channels current during both the positive cycle and the negative cycle onto an output in the form of a series of positive half-waves. In such a rectifier, current from the piezoelectric structure usually must pass through two diodes and each diode typically has a voltage drop of between 0.2 V to 0.7 V (depending on the semiconductor technology employed). This voltage drop can be greater than the voltage output from the piezoelectric structure and, therefore, usually requires that a voltage boost be applied to the output from the piezoelectric structure so that the voltage being applied to the battery is greater than the voltage of the battery, otherwise no current would flow into the battery. Such a system tends to waste a considerable amount of energy.
The problem is rectifying unpredictably small ac signals (which are prevalent in small volumes and with weak vibrations whose peak voltages fall below the rectified output level targeted, requires low-loss, no-threshold rectifiers. Quasi-lossless LC energy-transfer networks that precede or follow the rectifier can extract all the energy stored in the piezoelectric capacitance and therefore overcome the basic threshold-voltage limitation, except the rectifier and its controller's headroom and quiescent current nonetheless limit the input voltage range of the system and dissipate power.
Miniaturized mobile electronic systems, such as biomedical drug-delivery implants, acceleration-monitoring and pressure-monitoring sensors, and micro-sensor nodes in wireless networks, have so little space for energy storage that they suffer from short operational lives. Unfortunately, replacing easily exhaustible onboard batteries is prohibitive because the systems often conduct in situ measurements in unreachable places and operate in concert with numerous other devices, where the personnel and logistical costs of maintaining all batteries charged are unacceptably high. Harvesting energy, however, from light, heat, radiation, and motion is an attractive, though not easy alternative for replenishing small batteries and capacitors.
Although the application ultimately determines what energy source suits best, harvesting kinetic energy is promising because motion and vibrations are abundant and produce moderate power levels. For context, solar light generates more power, but only when exposed directly to the sun, and power densities derived from indoor lighting, thermal gradients, and radio-frequency (RF) waves fall well below their kinetic counterparts, although not all motion-based transducers perform equally well. Piezoelectric devices, in fact, when constrained to small platforms, generate more power than variable (electrostatic) capacitors and moving (electromagnetic) coils.
When considering a piezoelectric source, the internal charge configuration of the material changes (much like an ac current source) to generate an alternating voltage across the equivalent capacitance that its opposing surfaces present. The harvester circuit must therefore extract energy from the changing voltages of the piezoelectric capacitor and deposit charge into an energy-storage device. Because harvested power is low and uncorrelated to the load, a small battery or capacitor serves as the reservoir from which electrical functions in the system draw power on demand.
Conventional approaches first rectify the incoming ac voltage with a diode bridge. Some techniques reduce the voltage (and therefore power losses) across the pn-junction diodes by using MOS switches and driving them with a comparator that senses and ensures only small positive terminal voltages allow the switches to close. Unfortunately, input voltages must nonetheless exceed their rectified outputs for the MOS switches to conduct, which means rectifiers place a threshold limit on the mechanical input. In other words, rectified harvesters only harvest energy above a minimum input level, so they cannot extract all the energy the piezoelectric material offers. Although some systems extract more energy from the environment by boosting the transducer's electrical damping force with higher (LC-induced) piezoelectric voltages, the subsequent rectifier still suffers from a threshold minimum below which the harvester cannot harness energy. Furthermore, drawing maximum power requires an optimal rectified output voltage, so some approaches, at the cost of power, employ a correcting feedback loop that senses the harvester's output current to set the optimal rectified level.
Therefore, there is a need for an alternating current to direct current converter that does not incur the losses associated with a bridge rectifier.
SUMMARY OF THE INVENTION
The disadvantages of the prior art are overcome by the present invention which, in one aspect, is a circuit for harvesting electrical energy from a piezoelectric source and for storing the electrical energy in a battery that includes an inductor that is configured to store electrical energy. A diode bridge-free switching network is configured to: direct electrical energy from the piezoelectric source to the inductor during a first portion of a piezoelectric charge generating cycle; and direct electrical energy from the inductor to the battery during a second portion of the piezoelectric charge generating cycle.
In another aspect, the invention is a circuit for harvesting electrical energy that includes an alternating current source that is coupled between a first note and a second node. A load is coupled between a fifth node and the second node. An inductor, coupled between a third node and a fourth node, is configured to store electrical energy. A first switch is coupled between the first node and the third node. A second switch is coupled between the fourth node and the second node. A first unidirectional current directing device is coupled between the third node and the fifth node and is configured to allow current to flow only from the third node to the fifth node. A second unidirectional current directing device is coupled between the fourth node and the fifth node and is configured to allow current to flow only from the fourth node to the fifth node. A switch state controller is configured to control the first switch and the second switch. The switch state controller directs electrical energy from the alternating current source to the inductor during a first portion of an alternating current charge generating cycle and directs electrical energy from the inductor to the load during a second portion of the alternating current charge generating cycle.
In yet another aspect, the invention is a method of harvesting energy from a piezoelectric current generating source, in which an inductor is charged with a first bias during a first positive portion of a piezoelectric charge generating cycle from the piezoelectric current generating source. Current from the inductor is directed to a positive terminal of a load during a second positive portion of the piezoelectric charge generating cycle by coupling a first terminal of the inductor to the positive terminal of the load along a first circuit path. The inductor is charged with a second bias, opposite the first bias, during a first negative portion of the piezoelectric charge generating cycle from the piezoelectric current generating source. Current is directed from the inductor to the positive terminal of the load during a second negative portion of the piezoelectric charge generating cycle by coupling a second terminal of the inductor, different from the first terminal of the inductor, to the positive terminal of the load along a second circuit path, different from the first circuit path.
These and other aspects of the invention will become apparent from the following description of the preferred embodiments taken in conjunction with the following drawings. As would be obvious to one skilled in the art, many variations and modifications of the invention may be effected without departing from the spirit and scope of the novel concepts of the disclosure.



BRIEF DESCRIPTION OF THE FIGURES OF THE DRAWINGS
FIG. 1 is a schematic diagram showing one embodiment of an alternating current to direct current conversion circuit.
FIGS. 2A-2D are a series of schematic diagrams showing current paths in the circuit shown in FIG. 1.
FIGS. 3A-3B are two graphs showing electrical characteristics of the circuit shown in FIG. 1 in relation to time.
FIG. 4 is a schematic diagram showing one embodiment of a switch state control circuit.
FIG. 5 is a schematic diagram showing one embodiment of a delay circuit.
FIG. 6 is a schematic diagram showing one embodiment of one experimental embodiment of a piezoelectric energy harvesting system.



DETAILED DESCRIPTION OF THE INVENTION
A preferred embodiment of the invention is now described in detail. Referring to the drawings, like numbers indicate like parts throughout the views. Unless otherwise specifically indicated in the disclosure that follows, the drawings are not necessarily drawn to scale. As used in the description herein and throughout the claims, the following terms take the meanings explicitly associated herein, unless the context clearly dictates otherwise: the meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.”
As shown in FIG. 1, one embodiment of a circuit 100 for harvesting electrical energy from a piezoelectric source 10 (which can include a piezoelectric structure 12 and an inherent capacitance 14), or other type of alternating current source, and for storing the electrical energy in a battery 20, or other type of load, includes an inductor 118 that stores electrical energy from the piezoelectric source 10. A diode bridge-free switching network 110 directs electrical energy from the piezoelectric source 12 to the inductor 118 during a first portion of a piezoelectric charge generating cycle (such a as a period between when the piezoelectric source 10 begins either a positive (or negative) voltage cycle and when it reaches a maximum (or minimum) voltage peak) and directs electrical energy from the inductor 118 to the battery 20 during a second portion (e.g., after a voltage peak) of the piezoelectric charge generating cycle.
The piezoelectric source 10 is coupled between a first node 111 and a second node 112, the inductor 118 is coupled between a third node 113 and a fourth node 114, and the battery 20 is coupled between a fifth node 115 and the second node 112. The switching network includes: a first switch 120 coupled between the first node 111 and the third node 113; a second switch 122 coupled between the fourth node 114 and the second node 112. A first unidirectional current directing device 124 coupled between the third node 113 and the fifth node 115. The first unidirectional current directing device 124 allows current to flow only from the third node 113 to the fifth node 115. Similarly, a second unidirectional current directing device 126 is coupled between the fourth node 114 and the fifth node 115. The second unidirectional current directing device 126 allows current to flow only from the fourth node 114 to the fifth node 115.
In one embodiment, both the first unidirectional current directing device 124 and the second unidirectional current directing device 126 each include a transistor 128 having a source, a drain and a gate. A comparator 130 compares the voltage at the source to the voltage at the drain and drives the gate so as to put the transistor 128 in a conducting state when current is flowing into the source side of the transistor 128. A driver element (such as a plurality of cascaded inverters, shown in FIG. 6) may be disposed between the output of the comparator and the gate of the transistor.
A switch state controller 140, which is coupled to the piezoelectric source 10 via a resistor 142 and a series capacitor 144 (also, the addition of a parallel capacitor might be necessary if the inherent capacitance 14 of the piezoelectric source is insufficient), controls the states of the first switch 120 and the second switch 122, based on a voltage sensed at the piezoelectric source 10.
Both the first switch 120 and the second switch 122 are closed during a first portion of a positive current generating portion of the piezoelectric charge generating cycle, as shown in FIG. 2A, during which time the inductor 118 is charged. Then the first switch 120 is maintained in a closed state and the second switch 122 is opened during a second portion of the positive current generating portion of the piezoelectric charge generating cycle. At the beginning of a first portion of a negative current generating portion of the piezoelectric charge generating cycle, as shown in FIG. 2C, both the first switch 120 and the second switch 122 are again closed, thereby charging the inductor 118 with a polarity opposite of the polarity it was charged in FIG. 2A. Then, as shown in FIG. 2D, the first switch 120 is opened and the second switch 122 is maintained in a closed state during a second portion of the negative current generating portion of the piezoelectric charge generating cycle, thereby allowing current to flow from the inductor 118 into the battery. As shown in the graph 300 in FIG. 3A, both switches 120 and 122 are closed in τL+ during which the inductor 118 is charged from the piezoelectric source 10. Then the first switch 120 is maintained in a closed state and the second switch 122 is opened during τB+ to allow the inductor to charge the battery. As shown in the graph 310 in FIG. 3B, both switches 120 and 122 are closed during τL−, thereby charging the inductor 118 with a polarity opposite of the polarity it was charged in the positive cycle. Then, the first switch 120 is opened and the second switch 122 is maintained in a closed state during τB− to allow the current to flow from the inductor 118 into the battery 20.
As shown in FIG. 4, one embodiment of the switch state controller 140 includes a comparator 410 coupled across resistor 142 and decoupled from a ground via capacitor 412. The comparator 410 detects the positive and negative voltage events across resistor 142 and generates an output 414 representative thereof, which is fed into a delay circuit 420 (one embodiment of which is shown in FIG. 5). The comparator output 414 and the delay output 416 are fed into both an AND gate 422 and a NOR gate 432. A first driver element 424, which includes a plurality of cascaded inverters, repowers the output from the AND gate 422 to generate a first switch control signal 425 that drives the first switch 120. Similarly, a second driver element 434, which includes a second plurality of cascaded inverters, repowers the output from NOR gate 432 to generate a second switch control signal 435 that drives the second switch 122. The first switch 120 and the second switch 122 each include a first transistor 426 and a second transistor 428, whose gates are coupled to each other. The first transistor 426 has a leakage current that flows in a first direction and the second transistor 428 has a leakage current that flows in a second direction that is opposite of the first direction.
One experimental embodiment 500 is shown in FIG. 6. In this embodiment 500, most of the components of the diode bridge-free switching network 510, except for the inductor 518, can be embodied on a single chip.
In this experimental embodiment, when vibrations move the piezoelectric cantilever in the positive cycle, the system waits until the voltage across piezoelectric capacitance CPZT peaks, which happens when the transducer's cantilever reaches its maximum displacement. At this point, the system energizes harvesting inductor LH from CPZT in energizing time τL+ and then de-energizes LH into the battery in de-energizing time τB+. Transferring energy this way only requires a few microseconds, which represents a negligible fraction of the millisecond vibration period, so the position of the transducer is, for all practical purposes, static during the transfer. Similarly, after depositing positive-cycle charge into the battery, the system waits until the piezoelectric device charges CPZT in the negative direction to its negative peak. The switched-inductor circuit then quickly energizes and de-energizes LH in τL− and τB− from CPZT to the battery. This negative-cycle transfer concludes the full cycle, and the sequence repeats as long as vibrations persist.
CPZT stores the energy that the piezoelectric material produces each half cycle (EIN+) and the switched-inductor converter extracts EIN+ from CPZT to reset CPZT's voltage vPZT to 0 V. Assuming piezoelectric current iPZT is sinusoidal at IPZT sin(ωVIBt), vPZT rises in positive-cycle time τC+ to




  
    
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After τC+, CPZT accumulates





  
    
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Since the negative cycle generates an equivalent amount (i.e., EIN+≈EIN−), the system harnesses 4IPZT2/ωVIB2CPZT from each vibration period, which is four times (4×) more energy than the ideal diode-rectified case can possibly induce.

In the positive cycle, with switch SI open, the switched-inductor power stage waits for iPZT to charge CPZT to peak positive voltage VPIEZOP+. VPIEZOP+ is not the actual peak because the implemented circuit includes delay and offset, the causes and implications of which subsequent subsections will address. The controller then closes SI and SN to discharge CPZT into LH for energizing time τL+, allowing LH's current iL to reach positive peak current ILP+. Because a capacitor fully discharges into an inductor in a quarter of its LC resonance period, the system sets τL+ to one-fourth of 2π√(LHCPZT). After τL+, SN opens and iL charges the parasitic capacitance at vSW+ until non-inverting diode DN forward biases and steers iL's de-energizing (battery) current iBAT+ into the battery. Once DN completely drains LH, after de-energizing time τB+, DN opens automatically (i.e., asynchronously).
The negative cycle operates similarly, except the power stage inverts its functionality to realize an inverting buck-boost translation. As such, the system waits for iPZT to charge CPZT in the negative direction until vPZT reaches negative peak voltage VPIEZOP−. (Like before, VPIEZOP− is not accurate because of non-idealities in the circuit.) SI and SN then drain CPZT into LH for one-fourth of LH-CPZT's resonance period, after which point SI opens and iL charges vSW−'s parasitic capacitance until inverting diode DI forward biases and conducts iL's de-energizing (battery) current iBAT− into the battery.
Unlike many rectified harvesters, this embodiment of a switched-inductor circuit can de-energize (and therefore harness) all piezoelectric energy in CPZT, which is to say the circuit does not suffer from a minimum input threshold. What is more, LH automatically raises vSW+ and vSW− to whatever voltage the battery demands, which means the circuit does not require the additional dc-dc converter stage that use to drive charge into the battery. Unlike some other converters, which include a lossy feedback loop to adjust the rectifier output voltage to draw the maximum power from CPZT, embodiments of the present invention can derive four times (4×) more energy than rectified harvesters without a correcting loop.
An integrated circuit version of this embodiment integrates the switches, controller, and bias generator into a single 2-μm BiCMOS IC. Bias resistor RPTAT and delay filter elements RD and CD are off chip for testing flexibility. For the same reasons, external voltages VADJ+ and vADJ− adjust energizing times τL+ and τL− externally. The piezoelectric cantilever, the battery, and LH are also off chip.
A series combination of two NMOS transistors in an isolated p-well implements both SI and SN. The purpose of the back-to-back body diodes is to block the undesired diode current that would otherwise result through the body diode of a single transistor when vPZT swings below ground (in the negative cycle) or above battery voltage VBAT (in the positive cycle). Note that the series combination of two switches increases channel resistance and gate capacitance, which raise conduction and switching losses, respectively, but not to the extent body-diode conduction would dissipate power.
Allowing vPZT to swing below ground demands that SN's gate driver GDSN outputs a negative voltage. The reason for this is that, while SN is open during the negative cycle, when vPZT falls below ground, SI remains closed and, as a result, switch-node voltages vSW+ and vSW− follow vPZT below ground. During this time, driving SN's gate to zero would not disengage SN. To avoid this problem, GDSN's last inverter stage connects to vPZT instead of ground. Accordingly, GDSN's output vGDSN—OUT follows vPZT during the negative cycle and nears VBAT otherwise. Because SN's gate capacitance is orders of magnitude below CPZT's, GDSN hardly drains CPZT, that is, has negligible impact on vPZT.
To reduce the diode-voltage conduction loss across battery-charging diodes DN and DI in the power stage, the circuit replaces them with low-drop synchronous MOS switches MPDN and MPDT. Here, comparators CPDN and CPDI sense when DN and DP's anode (switching) voltages vSW+ and vSW− just surpass their cathode counterpart VBAT to engage MPDN and MPDI, and switch them off otherwise. CPDN and CPDI must therefore (i) respond quickly (to reduce the time the lossy body-diodes conduct charging currents and keep MPDN and MPDI from draining the battery with negative current) and (ii) and dissipate little energy.
A fast response implies considerable quiescent current and low energy means the comparators must operate only when needed (asynchronously): when LH drains iL into the battery (during τB+ and τB−). Fortunately, τB+ and τB− are a small fraction of the vibration period so energy remains low (at 0.5 nJ per cycle in the prototyped case). Considering that, the comparator powers only when iL is non-zero and the corresponding switching (anode) voltage vSW is well above zero (above MPB and MNB's combined gate-source voltages), which only happens when LH is ready to charge the battery. During that time, some of iL (as limited by RBIAS) flows into bias mirror MNB-MNO to establish a threshold current about which MPO determines the state of the comparator. That way, since MPB and MPO match, MPO conducts less current and engages MPDN (or MPDI) when VBAT is below vSW, and vice versa otherwise.
Because the comparator does not draw current until vSW rises well above ground, iL charges vSW's parasitic capacitance CSW—PAR quickly and MNO sinks sufficient current to ensure VCP—OUT transitions low quickly (to engage MPDN or MPDI). Note MPDN's (or MPDI's) body diode conducts current while the comparator reacts to close MPDN (or MPDI). Once engaged, vSW remains above VBAT by the Ohmic voltage iL produces across MPDN's (or MPDI's) series resistance. As a result, vSW decreases with LH's falling iL, as LH de-energizes. When iL reaches zero, which happens when the system exhausts LH's energy, vSW falls to VBAT and the comparator transitions to disengage MPDN (or MPDI). Because iL no longer carries sufficient current to power the comparator, the circuit shuts down automatically.
During the turn-off transition, the comparator receives a small overdrive voltage so its shut-off time is longer than its counterpart is. As a result, while still closed, MPDN's (or MPDI's) reverse current can not only discharge the battery but also dissipate power. To prevent this reverse current, the comparator shifts the shut-off trip-point up to transition earlier (when vSW is slightly above VBAT) by leaking current away from MNB through MNH1. The positive feedback that MNH1 creates engages only after VCP—OUT rises above ground by more than MNH1's VTN, which happens after the comparator decides to raise VCP—OUT. In other words, MNH1 accelerates the circuit only after it begins to trip. MNH1 also imbalances gate-coupled pair MPB-MPO with MNH2's current to offset vSW's rising trip-point (and create a hysteresis) that helps in preventing transient and ringing events in vSW from asserting inadvertent transitions in the comparator.
The purpose of the control block is to determine when to start and stop energizing LH. First, SI and SN should start discharging CPZT into LH when vPZT peaks. To this end, comparator CPPK compares vPZT with a delayed version of itself (vD) to capture the moments when vPZT stops leading vD. That is to say, vPZT drops below vD when vPZT just begins falling from its positive peak and vPZT rises above vD when vPZT just begins increasing from its negative peak.
CPPK incorporates about ±10 mV of hysteresis to deglitch noise in vPZT and vD. The cross-coupled, positive-feedback p-type mirror load unbalances the n-type differential pair in both directions for that purpose. The circuit operates in sub-threshold to minimize power (with nano-amps) so its delay is on the microsecond range. Such a slow response is tolerable because microseconds constitute a negligible fraction of the millisecond vibration period, meaning vPZT does not change appreciably in microseconds. To mitigate risk in evaluating the power stage and its basic control scheme, external negative source VSS extends CPPK's input common-mode range (ICMR) below ground so it can accommodate negative vPZT voltages.
Ideally, the harvester should stop energizing LH after one-fourth of LH-CPZT's resonance period, after energizing periods τL+ and τL−. For that, vADJ+-RADJ+ and vADJ−-RADJ− set the source and sink currents that charge and discharge CADJ so that CADJ's voltage reaches the threshold of the ensuing inverter in 1⁄2π√(LHCPZT). Since tolerance in RADJ and CADJ offset this time, and other parasitic effects similarly shift how long CPZT should discharge into LH, vADJ+ and vADJ− are adjustable (and off chip for testing flexibility).
After discounting losses, the system harnesses up to 30 μW (PH) from 72 μW of transducer-generated power (PIN(LOADED)). Without the harvester (i.e., unloaded) and under equal mechanical stimulation, energy per cycle in CPZT (i.e., CPZTΔvPZT(UNLOADED)2fVIB) can generate less power (PIN(UNLOADED)) than when loaded (e.g., 40 versus 72 μW). This results, as expected, because extracting all CPZT'S positive- and negative-cycle energy resets (i.e., conditions) vPZT to zero, further increasing the transducer's electrical damping force and thereby inducing it to derive more energy from the environment. Note PIN(UNLOADED) also represents the maximum input power a rectifier-based circuit can produce because a rectifier draws charge from CPZT without conditioning its voltage. In other words, the best possible (and ideal) rectifier-based system would draw roughly 56% of what this embodiment can (e.g., 40 of 72 μW).
Although increasing the transducer's output power by up to 78% or 1.78× (when ΔvPZT(UNLOADED) is 1.2 V) by loading it with the prototyped harvester corroborates theory, which predicts a 4× (i.e., 400%) improvement. One reason for this discrepancy is CPPK's 36-mV input-referred offset causes the system to discharge CPZT past vPZT's peak after CPZT loses some energy to vibrations. What is more, since the offset voltage does not scale with the input, the fraction of energy lost to vibrations is larger for smaller inputs, so loaded-to-unloaded input-power ratio PIN(LOADED)/PIN(UNLOADED) decreases from 1.78 rapidly (i.e., nonlinearly) with respect to ΔvPZT(UNLOADED). Parasitic resistances in switches SN and SI and across LH also reduce the transducer's output power because, instead of fully draining CPZT into LH by lowering vPZT to zero, the converter pulls vPZT to the voltage drop across SN, LH, and SI's combined series resistance RSN+RESR RSI. This non-zero voltage not only represents remnant energy that the system does not harvest but also lowers the peak amplitude (i.e., electrical damping force) of the ensuing half cycle.
Ultimately, the harvesting conversion efficiency of the system with respect to PIN(LOADED) across vibration strength falls between 40% and 50%. The system loses conduction energy EC to the switches' finite resistances and LH's equivalent-series resistance (ESR) when iL flows through LH during LH's positive- and negative-cycle energizing and de-energizing times τL+, τB+, τL−, and τB−. However, LH de-energizes in considerably less time than it energizes (i.e., τL+ and τL− are considerably longer than τB+ and τB−) so EC mostly consists of energizing losses:




  
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where energizing times τL+ and τL− equal (to τLE) and ILP+/√3 and ILP−/√3 are the root-mean-squared (RMS) currents flowing through the resistors across τL+ and τL−, respectively. EC falls with increasing LH values because, even though τLE increases with LH0.5 (from 1⁄2π√(LHCPZT)), (ILP+)2 and (ILP−)2 decrease with LH1. Wider MOS transistors (i.e., lower RSI and RSN) also decrease EC, but at the expense of silicon real estate and higher switching gate-drive losses ESW(GD), as the following discussion will elucidate.

The system loses ESW(GD) in inverter drivers when they charge and discharge parasitic gate capacitances in SI, SN, and DN and DI's MPDN and MPDI. Since all the switches in this embodiment engage and disengage once per cycle, gate-drive losses amount to

ESW(GD)≈(CSI+CDI+CDN)VDD2+CSN(VDD+|VPIEZOP−|)2 

where CSI, CDI, CDN, and CSN refer to the parasitic capacitances that SI, DI's MPDI, DN's MPDN, and SN introduce, respectively, which scale with transistor channel widths. Note SN causes more energy loss than other switches because its gate swings between VDD and VPIEZOP−.

The system also loses overlap losses ESW(IV) when MOS drain currents and drain-source voltages shortly overlap every time they transition. This overlap occurs when SN and SI open because vSW+ and vSW− transition with a non-zero iL:

ESW(IV)≈(0.5ILP+τSN—OFF+0.5ILP−τSI—OFF)(VBAT+VD)

where VD refers to MPDN and MPDI's as body-diode voltage. Here, because iL is triangular and τSN—OFF and τSI—OFF are SN and SI's corresponding off times, 0.5ILP+τSN—OFF and 0.5ILP−τSI—OFF represent SN and SI's total conducted charge during transitions.

Peak-detector comparator CPPK, the nanoamp-bias generator, adjustable delay block τADJ, the logic gates, and DN and DI's comparators CPDN and CPDI also dissipate quiescent energy (EQ). The losses in CPPK and the bias circuit, however, dominate EQ because they operate through the entire vibration cycle, whereas the other circuits only engage for a substantially smaller fraction. Overall, although higher input power increases |VPIEZOP−|, ILP+, and ILP− and their associated switching losses ESW(GD) and ESW(IV), conduction losses EC scales more rapidly with power (i.e., proportional to (ILP+)2 and (ILP−)2) so EC ultimately dominates and limits ηH when mechanical vibrations are strong. Conversely, when vibrations are weak, EQ may dominate because EC, ESW(GD), and ESW(IV) scale with power.
Vibrations in practical operating environments occur, for the most part, at relatively low frequencies, between maybe 1 Hz for a person walking to 167 Hz for an engine cycling at 10,000 revolutions per minute. What is more, the rate is often inconsistent and maybe even non-recurring, as in the case of human motion, wind-propelled movements, and vibrations generated from impact. What all this means is that matching the narrow band of a transducer to vibrations, which is the recipe for high conversion efficiency, is oftentimes impractical and unrealistic.
Because the prototyped harvester automatically detects when to draw energy from CPZT, the system is capable of harnessing energy from non-periodic stimuli. When dropping a 145-g official major-league baseball from 40 cm above the experimental setup table, for example, the impact of the ball bouncing once off the table induces the piezoelectric cantilever to vibrate and produce the pulse train. In this case, the prototyped system charged 500 nF (from 3.04 V) from a single bounce for three separate trials by roughly 200 mV.
Each drop produces the decaying vibrations where the system harvests energy by quickly draining CPZT into LH and then LH into the 500-nF capacitor each time vPZT peaks. As vPZT's peaks (and mechanical strength) decrease, however, peak-detector comparator CPPK's offset has a larger impact on how much input power PIN(LOADED) the system harnesses so output power PH decreases more than basic theory predicts. Under these weak vibrations, in fact, RD-CD and CPPK's delays increase CPPK's offset to degrade performance. In contrast, just as CPPK's offset adds to the effects of CPPK's delay in the positive half-cycle, the offset cancels delay in the negative half-cycle which means alternating the polarity of the offset can improve overall performance.
Although the immediate aim of this research is to raise PH by increasing ηH and PIN(LOADED), the ultimate metric is end-to-end harvesting conversion efficiency ηTOTAL, which refers to how much mechanical energy EME reaches the output as harvested energy EH. A means of applying a known value for EME (and approximating ηTOTAL) is to tie an object of known mass mW to the tip of the piezoelectric cantilever with a light string and subsequently cut the link. Since the cantilever's elastic force FC balances the object's gravitational pull FG, EME relates to FG and the cantilever's tip displacement distance dC:




  
    E
    ME
  
  =
  
    
      
        
          K
          C
        
        ⁢
        
          d
          C
          2
        
      
      2
    
    =
    
      
        
          
            (
            
              
                K
                C
              
              ⁢
              
                d
                C
              
            
            )
          
          ⁢
          
            d
            C
          
        
        2
      
      =
      
        
          
            
              F
              C
            
            ⁢
            
              d
              C
            
          
          2
        
        =
        
          
            
              
                F
                G
              
              ⁢
              
                d
                C
              
            
            2
          
          =
          
            
              
                (
                
                  
                    m
                    W
                  
                  ⁢
                  g
                
                )
              
              ⁢
              
                d
                C
              
            
            2
          
        
      
    
  




where KC and g refer to the spring constant and gravity's acceleration, respectively.

This way, neglecting parasitic weights and assuming the string severs instantaneously, the prototyped harvester charged (experimentally) 500 nF by roughly 400 mV from a 3-g weight. As a result, subtracting the external supply's quiescent energy EQ (to the chip for CPPK, bias generator, adjustable delay, and logic gates) and gate-driving losses ESW(GD) from the energy deposited in the 500-nF capacitor reduces EH to

EH=0.5CBAT(VBAT(F)2−VBAT(I)2)−EQ−ESW(GD) 

which ranged between 100 and 660 nJ when stimulated with 1.2 to 10.8 μJ of EME from 1-, 2-, and 3-g weights to yield 6.1±1.5% to 8.8±6.9% of ηTOTAL or EH/EME.

ηTOTAL incorporates the collective performance of the transducer (ηPZT(LOADED)) and the harvester (ηH), which means ηPZT(LOADED is ηTOTAL/ηH or roughly 14%-20% when assuming ηH is 45% on average. Since ηPZT(LOADED) includes a factor improvement the harvester induces, the unloaded counterpart (ηPZT(UNLOADED)) is less than 14%-20% by up to 1.78×. Although this simple analysis is by no means accurate or complete, it shows that mechanical losses are significant at around 80% and conditioning the transducer to increase PIN(LOADED) is as important as reducing the losses across the switched-inductor converter (i.e., increasing ηH).
The embodiment of a 2-μm BiCMOS switched-inductor piezoelectric harvester generates and steers up to 30 μW from a periodic 72-μW piezoelectric source into a capacitor or battery directly. In doing so, it increases the piezoelectric cantilever's electrical damping force to raise the transducer's (and therefore system's end-to-end) mechanical-electrical efficiency by up to 78%. The system also harnesses up to 659 nJ from non-periodic vibrations with 6.1±1.5% to 8.8±6.9% end-to-end mechanical-electrical efficiencies. One key feature of the presented harvester is that it eliminates the need for a rectifier. As a result, the system no longer (i) places a threshold limit imposed by diodes and/or the output voltage on mechanical vibrations, (ii) loses power across an otherwise additional stage (i.e., across a rectifier), and (iii) limits how much the circuit dampens the transducer (to produce more power). Conditioning the piezoelectric device to generate more power is an important attribute, as is the relatively simple and low-loss control strategy the system adopts to energize and de-energize the inductor directly into the energy-storage device. From a practical standpoint, the harvester is also able to harness energy from short, non-periodic mechanical vibrations, which are more prevalent in real-life applications, such as in human motion, wind-propelled movements, vibrations that objects crashing produce, and so on.
The above described embodiments, while including the preferred embodiment and the best mode of the invention known to the inventor at the time of filing, are given as illustrative examples only. It will be readily appreciated that many deviations may be made from the specific embodiments disclosed in this specification without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be determined by the claims below rather than being limited to the specifically described embodiments above.

## Claims

1. A circuit for harvesting electrical energy from a piezoelectric source and for storing the electrical energy in a battery, comprising:
(a) an inductor configured to store electrical energy; and
(b) a diode bridge-free switching network that is configured to:
(i) direct electrical energy from the piezoelectric source to the inductor during a first portion of a piezoelectric charge generating cycle; and
(ii) direct electrical energy from the inductor to the battery during a second portion of the piezoelectric charge generating cycle.

2. The circuit of claim 1, wherein the piezoelectric source is coupled between a first node and a second node, the inductor is coupled between a third node and a fourth node, and the battery is coupled between a fifth node and the second node, and wherein the switching network comprises:
(a) a first switch coupled between the first node and the third node;
(b) a second switch coupled between the fourth node and the second node;
(c) a first unidirectional current directing device coupled between the third node and the fifth node and configured to allow current to flow only from the third node to the fifth node;
(d) a second unidirectional current directing device coupled between the fourth node and the fifth node and configured to allow current to flow only from the fourth node to the fifth node; and
(e) a switch state controller that is configured to control the first switch and the second switch.

3. The circuit of claim 2, wherein the switch state controller is configured to:
(a) close both the first switch and the second switch during a first portion of a positive current generating portion of the piezoelectric charge generating cycle;
(b) maintain the first switch in a closed state and open the second switch during a second portion of the positive current generating portion of the piezoelectric charge generating cycle;
(c) close both the first switch and the second switch during a first portion of a negative current generating portion of the piezoelectric charge generating cycle; and
(d) open the first switch and maintain the second switch in a closed state during a second portion of the negative current generating portion of the piezoelectric charge generating cycle.

4. The circuit of claim 2, wherein the switch state controller comprises:
(a) a resistor and a capacitor coupled across the piezoelectric source;
(b) a comparator having a first input coupled to a first terminal of the resistor and a second input coupled to a second terminal of the resistor, the comparator configured to generate an output representative of a voltage event generated by the piezoelectric source;
(c) a delay circuit responsive to the comparator output and configured to generate a delay output that is representative of the comparator output that has been delayed by a predetermined amount of time; and
(d) a logic circuit that is responsive both the comparator output and the delay output and to generate a first switch control signal and a second switch control signal based on a current state of the comparator output and the delay output.

5. The circuit of claim 4, wherein the logic circuit includes an AND gate that is configured to AND the comparator output and the delay output, thereby generating a first switch control signal and wherein the logic circuit includes an NOR gate that is configured to NOR the comparator output and the delay output, thereby generating a second switch control signal.

6. The circuit of claim 5, further comprising:
(a) a first driver element disposed between the AND gate and the first switch; and
(b) a second driver element disposed between the NOR gate and the second switch.

7. The circuit of claim 2, wherein the first switch and the second switch each include a first transistor in series with a second transistor, wherein the first transistor has a leakage current that flows in a first direction and the second transistor has a leakage current that flows in a second direction opposite of the first direction, wherein the first transistor and the second transistor each have a gate that is responsive to a switch control signal from the switch state controller.

8. The circuit of claim 2, wherein each of the first unidirectional current directing device and the second unidirectional current directing device comprises:
(a) a transistor having a gate, a source coupled to a selected one of the third node and the fourth node, and a drain coupled the fifth node; and
(b) a comparator having a negative input coupled to a selected one of the third node and the fourth node, and a positive input coupled to the fifth node and an output coupled the gate of the transistor.

9. The circuit of claim 8, further comprising a driver element disposed between the output of the comparator and the gate of the transistor.

10. A circuit for harvesting electrical energy, comprising:
(a) an alternating current source coupled between a first note and a second node;
(b) a load coupled between a fifth node and the second node;
(c) an inductor, coupled between a third node and a fourth node, configured to store electrical energy;
(d) a first switch coupled between the first node and the third node;
(e) a second switch coupled between the fourth node and the second node;
(f) a first unidirectional current directing device coupled between the third node and the fifth node and configured to allow current to flow only from the third node to the fifth node;
(g) a second unidirectional current directing device coupled between the fourth node and the fifth node and configured to allow current to flow only from the fourth node to the fifth node; and
(h) a switch state controller that is configured to control the first switch and the second switch so as to:
(i) direct electrical energy from the alternating current source to the inductor during a first portion of an alternating current charge generating cycle; and
(ii) direct electrical energy from the inductor to the load during a second portion of the alternating current charge generating cycle.

11. The circuit of claim 10, wherein the alternating current source comprises a piezoelectric element.

12. The circuit of claim 10, wherein the load comprises a battery.

13. The circuit of claim 10, wherein the switch state controller is configured to:
(a) close both the first switch and the second switch during a first portion of a positive current generating portion of the alternating current charge generating cycle;
(b) maintain the first switch in a closed state and open the second switch during a second portion of the positive current generating portion of the alternating current charge generating cycle;
(c) close both the first switch and the second switch during a first portion of a negative current generating portion of the alternating current charge generating cycle; and
(d) open the first switch and maintain the second switch in a closed state during a second portion of the negative current generating portion of the alternating current charge generating cycle.

14. The circuit of claim 10, wherein the switch state controller comprises:
(a) a resistor and a capacitor coupled across the alternating current source;
(b) a comparator having a first input coupled to a first terminal of the resistor and a second input coupled to a second terminal of the resistor, the comparator configured to generate an output representative of a voltage event generated by the alternating current source;
(c) a delay circuit responsive to the comparator output and configured to generate a delay output that is representative of the comparator output that has been delayed by a predetermined amount of time; and
(d) a logic circuit that is responsive both the comparator output and the delay output and to generate a first switch control signal and a second switch control signal based on a current state of the comparator output and the delay output.

15. The circuit of claim 14, wherein the logic circuit includes an AND gate that is configured to AND the comparator output and the delay output, thereby generating a first switch control signal and wherein the logic circuit includes an NOR gate that is configured to NOR the comparator output and the delay output, thereby generating a second switch control signal.

16. The circuit of claim 15, further comprising:
(a) a first driver element disposed between the AND gate and the first switch; and
(b) a second driver element disposed between the NOR gate and the second switch.

17. The circuit of claim 10, wherein the first switch and the second switch each include a first transistor in series with a second transistor, wherein the first transistor has a leakage current that flows in a first direction and the second transistor has a leakage current that flows in a second direction opposite of the first direction, wherein the first transistor and the second transistor each have a gate that is responsive to a switch control signal from the switch state controller.

18. The circuit of claim 10, wherein each of the first unidirectional current directing device and the second unidirectional current directing device comprises:
(a) a transistor having a gate, a source coupled to a selected one of the third node and the fourth node, and a drain coupled the fifth node; and
(b) a comparator having a negative input coupled to a selected one of the third node and the fourth node and a positive input coupled to the fifth node and an output coupled the gate of the transistor.

19. The circuit of claim 18, further comprising a driver element disposed between the output of the comparator and the gate of the transistor.

20. A method of harvesting energy from a piezoelectric current generating source, comprising the steps of:
(a) charging, from the piezoelectric current generating source, an inductor with a first bias during a first positive portion of a piezoelectric charge generating cycle;
(b) directing current from the inductor to a positive terminal of a load during a second positive portion of the piezoelectric charge generating cycle by coupling a first terminal of the inductor to the positive terminal of the load along a first circuit path;
(c) charging, from the piezoelectric current generating source, the inductor with a second bias, opposite the first bias, during a first negative portion of the piezoelectric charge generating cycle; and
(d) directing current from the inductor to the positive terminal of the load during a second negative portion of the piezoelectric charge generating cycle by coupling a second terminal of the inductor, different from the first terminal of the inductor, to the positive terminal of the load along a second circuit path, different from the first circuit path.