NESC tech bulletin

National Aeronautics and Space Administration

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Power MOSFET Thermal Instability

In the quest for faster switching times and lower “on resistance” the Metal-Oxide Semiconductor Field-Effect 

Transistor (MOSFET), produced since 1998, has achieved most intended goals. Unfortunately, lower “on resis-

tance” and higher switching speeds in the designs now being produced allow the charge carrier dominated 

region to develop conditions that could lead to thermal runaway. Temperatures above 450o C on any location 

within the part can cause the metals to begin migrating causing a fatal short circuit. 

 NESC-TB-10-01

Applicability

Any power MOSFET that is used with a low 

gate voltage (not switched mode) for peri-

ods of time greater than 10 microseconds. 

The problem is more pronounced with 

parts produced since 1998.

Background

Based on recent testing and failure inves-

tigations, it appears that the “old” manu-

facturer application curves are inaccurate 

with regard to application of some MOSFET 

parts. These parts may be used extensively in flight hardware 

and ground support equipment.

The push for faster switching and lower “on resistance” pow-

er MOSFETs resulted in an unintended consequence similar 

to the secondary voltage breakdown effect that has not been 

seen since the prime of the bipolar transistor. When MOS-

FETs are in the charge carrier dominated region (low gate to 

source voltage, Vgs) the device allows more current to flow as 

the temperature increases causing a thermal runaway. It was 

discovered that the safe operating area (SOA) curves provided 

by the manufacturers were lacking in describing the region of 

thermal instability. The problem was identified during a test 

of a protection circuit that provided a low voltage on the gate 

of a MOSFET, which failed within seconds. The MOSFET was

replaced and a new corrected test was performed. The out-

come of the second test was the failure of the second MOS-

FET. Examination of the de-lidded part revealed a “bulls-eye” 

heating pattern and aluminum spheres. The failure mode for 

the two MOSFETs was determined to be common and was the 

result of the MOSFETs being placed in a thermal runaway con-

dition when the gate voltage was low, but well within the SOA 

for the MOSFET. This problem, known as “thermal instability” 

in the industry, has been experienced in the automotive indus-

try since 1997 when advanced, very fast, switching MOSFET

devices became available and found wide usage. 

MOSFET Failures inside the

Advertised SOA

Thermal runaway is a problem affecting a wide range of mod-

ern MOSFETs from more than one manufacturer. Older parts 

can also display thermal runaway, usually 

well outside the SOA. 

Therefore, one may experience other 

problems first with those older parts. 

Thermal runaway is caused at low gate 

to source voltages when the drain current 

increases at higher temperatures caus-

ing a positive feedback effect. Thermal 

runaway is currently over a larger area of 

the Vds-Id plane and inside the advertised 

SOA. The recommended new limit for the 

SOA can be determined using the Spirito 

stability formula where Stability (S) is less than one. When S 

equals one, the calculated temperature approaches an infinite 

value theoretically. A proper derating is necessary to bring 

the temperature down to a value below the MOSFET failure 

temperature. As found in testing, the leakage current of a 

MOSFET starts to become uncontrollable at about 250o C, so 

the standard temperature limit of 175o C is recommended. 

However, the dynamic temperature at the hottest point within 

the device must be constrained to safe limits.

References

1) IRF510 Data Sheet: 5.6A, 100V, 0.540 Ohm, N-Channel 

Power MOSFET’; Fairchild Semiconductor; January 2002. 

2) Marie Denison, Martin Pfost, Klaus-Willi Pieper, Stefan

Märkl, Dieter Metzner, Matthias Stecher; Influence of

Inhomogeneous Current Distribution on the Thermal SOA of 

Integrated DMOS Transistors; Proceedings of 2004 Interna-

tional Symposium on Power Semiconductor Devices & ICs; 

Kitakyushu; pp. 409–412. 

3) P.L.Hower and P.K.Govil; IEEE Transactions on Electron

Devices; Volume ED-21, Number 10; October 1974,

pp. 617–623.

4) P. Spirito, G. Breglio, V. d’Alessandro, N. Rinaldi; Analyti-

cal Model for Thermal Instability Of Low Voltage Power MOS 

and S.O.A. In Pulse Operation; 14th International Symposium 

on Power Semiconductor Devices & ICS; Santa Fe, NM; 4–7 

June 2002; pp. 269–272.

NASA Engineering and Safety Center Technical Bulletin No. 10-01

Failed Field-Effect Transistor