# Patent

## Title
Digital boost feedback voltage controller for switch-mode power supplies using pulse-frequency modulation

## Abstract

A controller produces high-side and low-side control signals. The high and low-side signals are used to switch high-side and low-side transistors in the power stage to control the voltage across the power stage output capacitor of the power stage. A boost feedback charge pump receives the low or high-side signal to increase the charge on a charge pump output capacitor. The controller is configured to send Pulse Frequency Modulation (PFM) high and low-side signals that control the voltage on the power stage output capacitor and charge the charge pump output capacitor. The controller is also configured to send boost feedback (BFB) high and low-side signals that charge the boost feedback capacitor, but are designed to not significantly change the charge on the power stage output capacitor.

## Background
BACKGROUND
DC-to-DC converters are used in a variety of applications to produce a regulated DC output from an unregulated DC input. Typically, a battery is used as the DC input of the DC-to-DC converter. The battery can decline in voltage over time as the battery discharges or gets older and there can be variations in the DC voltage output of different batteries.
The DC-to-DC converter can ensure that a regulated DC output is produced. One type of DC-to-DC converter is a buck converter that produces a lower DC voltage output than the DC voltage input. A controller can produce high-side and low-side control signals that selectively switch the DC input voltage into an inductor-capacitor (LC) circuit. The high-side and low-side control signals can be sent in different modes such as a Pulse Frequency Modulation (PFM) mode where the pulse lengths are fixed but the pulse frequency varies, or a Pulse-Width Modulation (PWM) mode where the pulse width varies but the pulse frequency remains the same.
An additional power rail can be produced using a charge pump circuit. The circuit can be powered by the input voltage source, another output voltage rail, or any other source. The charge pump is switched using one of the driver signals from the main switch-mode power supply channel. The charge pump establishes an output voltage that is a certain multiple of the input voltage, depending on the number of stages used in the charge pump less the voltage drops introduced by the diode forward-bias voltages as well as any parasitic resistances.
The charge pump feature is useful when a step-up voltage is required (as opposed to the step-down voltage produced by a buck converter). The additional power rail can be used for a number of purposes requiring relatively low current compared to the main output channel, such as powering a switch used to enable or disable a load.
The charge pump circuit generally runs in open-loop, where the output voltage is regulated to an approximate value. The switching signal frequency, duty ratio, and charge pump capacitance is assumed to be adequate to support the required boost feedback load. Operation in open loop is usually sufficient for controllers that operate only in Pulse-Width Modulation (PWM) mode. However, for controllers employing Pulse-Frequency Modulation (PFM) or mixed-mode control (both PWM and PFM), the switching signal frequency can become arbitrarily low, making it impossible to guarantee that the charge pump output voltage is always above the required minimum value.
SUMMARY
Embodiments of the present invention provide a solution for controllers using a PFM mode to simultaneously regulate both the main switch-mode power supply voltage as well as the output of a boost feedback charge pump circuit. When PFM mode is active, the control method allows additional switching pulses to be applied to maintain the boost feedback voltage, with minimal effect on the main switch-mode power supply voltage.
These boost feedback (BFB) pulses are designed with the high-side on-time/low-side on-time ratio being less than the PFM pulses. Theoretically, if the BFB high-side pulse is half the length of the PFM high-side pulse and the low-side pulse is kept the same, then the net charge at the output capacitor of the power stage will be unaffected by the BFB pulses. Alternately, any other BFB high side and BFB low side pulses with a high-side on-time/low-side on-time ratio of half the high-side on-time/low-side on-time ratio of the PFM pulses (such as doubling the low-side on time and keeping the high side on-time the same) will theoretically not affect the net charge at the output capacitor of the power. An offset can further be subtracted from the BFB high-side pulse (or added to the BFB low-side pulse) to ensure that the net charge at the output capacitor of the power stage will be slightly negative.
This system can be used inside digital controllers for switch mode power supplies where the gating signals or driver outputs are connected to boost feedback charge pumps and high efficiency is desired at light load conditions.
The system and method of the present invention is useful for synchronous converters, where there is both a high-side switch and a low-side switch. In non-synchronous converters, where only a diode is used instead of a low-side MOSFET, only one switching signal is used for the high-side, and the low-side conducts automatically whenever the high-side is off and there is current flowing through the inductor. In that case, BFB type pulses could not be made because there is no independent control over the low-side length.
High efficiency can be achieved in systems using BFB pulses by allowing the PFM mode to be employed that would otherwise be forced to only use the PWM mode.
A high level of programmability is available, making the invention suitable in a wide variety of applications. A modular architecture supports compatibility with multi-channel systems. There is minimal disturbance in power stage output voltage due to boost feedback charging.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a system diagram of one embodiment of the present invention.
FIG. 2 is a flow chart that shows a method of one embodiment of the present invention.
FIG. 3 shows a Pulse-Frequency Modulation (PFM) timing diagram and resulting inductor current.
FIG. 4 shows a boost feedback (BFB) timing diagram and resulting inductor current.



DETAILED DESCRIPTION OF THE PRESENT INVENTION
FIG. 1 shows a system diagram of one embodiment of the present invention.
A system 100 includes a controller 102 to produce high-side and low-side control signals. A power stage 112 includes a power stage output capacitor 114.
The high-side signals on line 104 and low-side signals on line 106 are used to switch a high-side transistor 108 and low-side transistor 110 in the power stage 112 to control the voltage across the power stage output capacitor 114.
A boost feedback charge pump includes a charge pump output capacitor 118. The boost feedback charge pump 116 receives one of the high or low-side signals to increase the charge on the charge pump output capacitor 118. In this case, the low-side signal is provided to the boost feedback charge pump 116.
The controller 102 is configured to send Pulse Frequency Modulation (PFM) high and low-side signals that controls the voltage on the power stage output capacitor and charges the charge pump output capacitor 118. The controller 102 also sends boost feedback (BFB) high and low-side signals that charge the boost feedback capacitor 118, but are designed to not significantly change the charge on the power stage output capacitor 114.
The controller 102 can sample an output voltage of the power stage 112 and an output voltage of the feedback charge pump to determine when to send the PFM signals and when to send the BFB signals. When the BFB output capacitor is low and no PFM signals are to be sent, the BFB signals can be sent. PFM signals can be prioritized over BFB signals and if the controller determines that both PFM and BFB signals would otherwise be desirable, the controller will send the PFM signals.
The controller 102 can sample an input DC voltage of the power stage to determine an on-time of the BFB high-side and low-side signals so that the net charge to the power stage output capacitor is near zero.
In one embodiment, the BFB high-side on-time/BFB low side on-time ratio is first set to be roughly half the PFM high-side on-time/PFM low side on-time ratio so that the net charge to the power stage output capacitor is not significantly affected. For example, the BFB high-side pulse can be selected to have an on-time of half of the PFM high-side pulse on-time or the BFB low-side pulse can be selected to have an on-time of twice the PFM low-side pulse on-time. An offset can be further subtracted from the BFB high-side signal (or added to the BFB low-side pulse) to ensure that there is never any positive charge applied to the power stage output by the BFB signals.
A PFM dead zone period and BFB dead zone period can be stored by the controller so that controller 102 does not produce PFM signals in the PFM dead zone period and does not produce BFB signals in the BFB dead zone period. The BFB dead zone period can be different than the PFM dead zone period. In one embodiment, the BFB dead zone period is greater than the PFM dead zone period because of the relative slowness of the boost feedback charge pump 116 to respond to the BFB and PFM signals.
A comparator 120 connected to the output of the boost feedback charge pump 116 can be used to ensure that the output voltage of the boost feedback charge pump 116 does not get too small.
The controller 102 can switch the system into another mode, such as a PWM mode, if the output voltages of the power stage 112 gets too large or too small.
The controller 102 can include BFB/PFM Digital Logic 122, an analog-to-digital converter (ADC), a steady-state duty ratio look-up table (LUT), programmable registers 128, two digital-to-analog converters (DAC's) 130 and 132 for producing boost feedback (BFB) and pulse-frequency modulation (PFM) reference signals, and two comparators 120 and 134 for monitoring the BFB and PFM voltages. The controller 102 can be, or be part of, an integrated circuit.
The controller can operate in a system consisting of gate drivers 140, a power stage 112, and a boost feedback charge pump 116. These features, or portions of these features, can be part of or separate from an integrated circuit containing all or portions of the controller 102.
The ADC 124 can be used for measuring the input voltage of the power stage 112. This measurement can be used for the calculation of the steady-state duty ratio, referred to as D.
The look-up table (LUT) 126 can be used to convert the output of the ADC 124 into steady-state duty ratio. It can be implemented as digital logic and consists of a table mapping input and output voltages to digital values corresponding to the steady-state duty ratio. The steady-state duty ratio can be calculated in order to determine the sizes of the BFB and PFM pulses that are sent to the gate drivers.
The programmable registers 128 can consist of registers for storing digital configuration values. These values can be used to promote modularity and allow the system to operate in a wide variety of conditions and applications. In one embodiment, the registers allow the following values to be programmed:

    
    
        Vref (the power stage output voltage reference
        VBFB—ref (the BFB voltage reference)
        PFM switching period
        The dead-zone for BFB pulses
        The dead-zone for PFM pulses
        The offset for BFB pulses
    
    


For regulating the power stage output voltage and the charge pump output voltage, two comparators 120 and 134 can be used. The references of these comparators can be set using programmable DAC's 130 and 132 allowing the regulation points to be customized.
The BFB/PFM Digital Logic module 122 can be responsible for monitoring the BFB and PFM comparator outputs to determine when pulses should be sent. Exemplary operation of this block is illustrated in the flowchart shown in FIG. 2.
Looking at FIG. 2, it is checked if the Vref comparator is low and Vref dead time has passed in step 202. If so, the PFM signals are determined in step 204. If not, in step 206, it is determined if the BFB comparator is low and the BFB dead time has passed. If so, in step 208, the BFB signals are determined. If not, the process returns to step 202. After the PFM signals are determined in step 204 or after the BFB signals are determined in step 208, in step 210, the determined signals are sent and the process returns to step 202.
An exemplary step 204, for the determination of the PFM signals can include measuring Vin of the power stage in step 204a, determining the steady state duty ratio in step 204b and setting the on-time of the high and low-signals based on the steady state ratio in step 204c. 
An exemplary step 208 for the determination of the BFB signals can calculate what would be the PFM high side and low side on-times in steps 208a, 208b and 208c that track the features of steps 204a, 204b and 204c. After these steps, the high-side output on-time can be cut in half in step 208d. (alternately, the low side on time could be doubled or both the low side and high side on-times can be changed so that the high side on-time/low side on-time ratio is halved) An offset can be subtracted from the high-side on-time (or added to the BFB low-side on-time) in step 208e after step 208d. 
In step 220, if the Vout voltage falls below Vref− or rises above Vref+, then in step 222, another mode, such as the PWM mode, can be entered.
A timing diagram for PFM pulses is shown in FIG. 3. When the power stage output voltage falls below Vref, D (corresponding to the steady-state duty ratio outputted from the LUT) can be used to calculate the on-time of the high-side pulse THS. THS is set such that the ratio between THS and TS (where TS is the total of the on-times of the high-side and low-side pulses) is equal to the steady-state duty ratio, D:




  
    
      
        
          
            T
            HS
          
          
            T
            S
          
        
        =
        
          D
          =
          
            
              V
              out
            
            
              V
              in
            
          
        
      
    
    
      
        (
        1
        )
      
    
  
  
    
      
        
          T
          HS
        
        =
        
          DT
          s
        
      
    
    
      
        (
        2
        )
      
    
  




THS is calculated to be proportional to D so that the low-side switching signal, GL, goes low approximately when the inductor current IL, is equal to zero. This ensures that for synchronous power stage topologies, high efficiency is achieved by avoiding diode conduction in the low-side switch. When Vin changes, a different duty ratio will be produced by the LUT to ensure that the low-side switch turns off approximately when the inductor current reaches zero.
The BFB/PFM Digital Logic can also consist of a digital pulse-width modulator (DPWM). The DPWM receives the digital values calculated for the on-times of the high-side and low-side pulses, and produces pulses of the appropriate widths that are sent to the gate drivers.
After each PFM pulse is sent, the logic will wait until the dead-zone has lapsed. The dead-zone is a period of time that can be set using a programmable register. The main purpose of the dead-zone is to ensure that the inductor current is always zero at the start of each PFM pulse, in case of any non-idealities in the calculation of pulse width in the previous cycle. Another purpose of the PFM dead-zone is to avoid sending pulses too frequently and to ensure that discontinuous conduction occurs. When a PFM pulse is sent, switching noise can cause the PFM comparator to trigger prematurely. By waiting until the dead-zone has lapsed, the controller avoids sending pulses due to switching noise.
When the BFB feature is enabled, the module can also monitor the output of the BFB comparator. When the PFM switching frequency is high enough such that the VBFB is maintained at a value greater than VBFB—reg, no additional action is necessary. However, when the PFM switching frequency is very low (due to a low power stage load) additional pulses can be injected in order to sustain the charge pump output voltage. When the charge pump voltage, VBFB, falls below VBFB—ref, the controller can send a BFB pulse in order to toggle the charge pump, increasing VBFB. The BFB pulse can have a similar structure as a PFM pulse: a high-side switching pulse is sent, followed by a low-side switching pulse. However, the on-time of the high-side pulse can be decreased to half of what it would be for a PFM pulse, as illustrated in FIG. 4. Optionally, an additional high-side pulse can be sent following the low-side pulse to improve efficiency so that the inductor current flows through the high-side switch instead of the high-side diode. When the high-side on-time is set to half of THS, the net charge delivered to the output capacitor of the power stage is zero. The proof for this is shown below. It is assumed that the effects of dead-time, diode forward-bias voltages, equivalent series resistances, and other parasitic elements are negligible.
Assume T′HS is set to half of THS:




  
    
      
        
          T
          HS
          ′
        
        =
        
          
            
              1
              2
            
            ⁢
            
              T
              HS
            
          
          =
          
            
              
                1
                2
              
              ⁢
              
                DT
                S
              
            
            =
            
              
                
                  V
                  out
                
                
                  2
                  ⁢
                  
                    
                  
                  ⁢
                  
                    V
                    in
                  
                
              
              ⁢
              
                T
                S
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




In PFM mode, pulses are discontinuous and, as a result, the current is zero at the start of each pulse (either a PFM pulse or a BFB pulse). When the high-side switch is on, the slope of the inductor current is:




  
    
      
        
          S
          HS
        
        =
        
          
            
              V
              in
            
            -
            
              V
              out
            
          
          L
        
      
    
    
      
        (
        4
        )
      
    
  




where L is the inductance and Vin and Vout are the input and steady-state output voltages, respectively. When the low-side switch is on, the slope of the inductor current is:




  
    
      
        
          S
          LS
        
        =
        
          -
          
            
              V
              out
            
            L
          
        
      
    
    
      
        (
        5
        )
      
    
  




The peak voltage reached is found to be:




  
    
      
        
          T
          peak
          ′
        
        =
        
          
            
              T
              HS
              ′
            
            ⁢
            
              S
              HS
            
          
          =
          
            
              
                V
                out
              
              
                2
                ⁢
                
                  
                
                ⁢
                
                  V
                  in
                
              
            
            ⁢
            
              
                
                  V
                  in
                
                -
                
                  V
                  out
                
              
              L
            
            ⁢
            
              T
              s
            
          
        
      
    
    
      
        (
        6
        )
      
    
  




The area of triangle 1 is therefore equal to:




  
    
      
        
          A
          1
        
        =
        
          
            
              1
              2
            
            ⁡
            
              [
              
                T
                HS
                ′
              
              ]
            
          
          ⁡
          
            [
            
              T
              peak
              ′
            
            ]
          
        
      
    
    
      
        (
        7
        )
      
    
  








  
    
      
        
          
            A
            1
          
          =
          
            
              
                1
                2
              
              ⁡
              
                [
                
                  
                    
                      V
                      out
                    
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      
                        V
                        in
                      
                    
                  
                  ⁢
                  Ts
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    V
                    out
                  
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      in
                    
                  
                
                ⁢
                
                  
                    
                      V
                      in
                    
                    -
                    
                      V
                      out
                    
                  
                  L
                
                ⁢
                Ts
              
              ]
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            A
            1
          
          =
          
            
              
                
                  V
                  out
                  2
                
                ⁡
                
                  (
                  
                    
                      V
                      in
                    
                    -
                    
                      V
                      out
                    
                  
                  )
                
              
              ⁢
              
                T
                s
                2
              
            
            
              8
              ⁢
              
                
              
              ⁢
              
                V
                in
                2
              
              ⁢
              L
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




The area of triangle 2 is equal to:




  
    
      
        
          
            A
            2
          
          =
          
            
              
                1
                2
              
              ⁡
              
                [
                
                  T
                  LSp
                  ′
                
                ]
              
            
            ⁡
            
              [
              
                T
                peak
                ′
              
              ]
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            A
            2
          
          =
          
            
              
                1
                2
              
              ⁡
              
                [
                
                  
                    T
                    peak
                    ′
                  
                  
                    -
                    
                      S
                      LS
                    
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    V
                    out
                  
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      in
                    
                  
                
                ⁢
                
                  
                    
                      V
                      in
                    
                    -
                    
                      V
                      out
                    
                  
                  L
                
                ⁢
                
                  T
                  s
                
              
              ]
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            A
            2
          
          =
          
            
              
                1
                2
              
              ⁡
              
                [
                
                  
                    
                      
                        V
                        out
                      
                      
                        2
                        ⁢
                        
                          
                        
                        ⁢
                        
                          V
                          in
                        
                      
                    
                    ⁢
                    
                      
                        
                          V
                          in
                        
                        -
                        
                          V
                          out
                        
                      
                      L
                    
                    ⁢
                    
                      T
                      S
                    
                  
                  
                    
                      V
                      out
                    
                    L
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    V
                    out
                  
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      in
                    
                  
                
                ⁢
                
                  
                    
                      V
                      in
                    
                    -
                    
                      V
                      out
                    
                  
                  L
                
                ⁢
                
                  T
                  S
                
              
              ]
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            A
            2
          
          =
          
            
              
                1
                8
              
              ⁡
              
                [
                
                  
                    
                      
                        V
                        in
                      
                      -
                      
                        V
                        out
                      
                    
                    
                      V
                      in
                    
                  
                  ⁢
                  Ts
                
                ]
              
            
            ⁡
            
              [
              
                
                  
                    V
                    out
                  
                  
                    V
                    in
                  
                
                ⁢
                
                  
                    
                      V
                      in
                    
                    -
                    
                      V
                      out
                    
                  
                  L
                
                ⁢
                
                  T
                  S
                
              
              ]
            
          
        
      
    
    
      
        (
        9
        )
      
    
  
  
    
      
        
          A
          2
        
        =
        
          
            
              
                
                  V
                  out
                
                ⁡
                
                  (
                  
                    
                      V
                      in
                    
                    -
                    
                      V
                      out
                    
                  
                  )
                
              
              2
            
            ⁢
            
              T
              S
              2
            
          
          
            8
            ⁢
            
              
            
            ⁢
            
              V
              in
              2
            
            ⁢
            L
          
        
      
    
    
      
        (
        10
        )
      
    
  




We can find the time when the low-side switch is on and the current is negative (T′LSn) as follows:

T′HS+T′LS=T′s 

T′HS+T′LSp+T′LSn=Ts−T′HS 

T′LSn=Ts−2T′Hs−T′LSp  (11)





  
    
      
        
          
            T
            LSn
            ′
          
          =
          
            
              T
              S
            
            -
            
              
                
                  V
                  out
                
                
                  V
                  in
                
              
              ⁢
              
                T
                S
              
            
            -
            
              
                
                  
                    V
                    in
                  
                  -
                  
                    V
                    out
                  
                
                
                  2
                  ⁢
                  
                    
                  
                  ⁢
                  
                    V
                    in
                  
                
              
              ⁢
              
                T
                S
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            T
            LSn
            ′
          
          =
          
            
              [
              
                
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      in
                    
                  
                  -
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      out
                    
                  
                  -
                  
                    V
                    in
                  
                  +
                  
                    V
                    out
                  
                
                
                  2
                  ⁢
                  
                    
                  
                  ⁢
                  
                    V
                    in
                  
                
              
              ]
            
            ⁢
            
              T
              S
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            T
            LSn
            ′
          
          =
          
            
              
                [
                
                  
                    
                      V
                      in
                    
                    -
                    
                      V
                      out
                    
                  
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      in
                    
                  
                
                ]
              
              ⁢
              
                T
                S
              
            
            =
            
              T
              LSp
              ′
            
          
        
      
    
    
      
        (
        12
        )
      
    
  




The valley voltage is found to be:




  
    
      
        
          T
          valley
          ′
        
        =
        
          
            
              T
              LSn
              ′
            
            ⁢
            
              S
              LS
            
          
          =
          
            
              
                -
                
                  
                    V
                    out
                  
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      in
                    
                  
                
              
              ⁢
              
                
                  
                    V
                    in
                  
                  -
                  
                    V
                    out
                  
                
                L
              
              ⁢
              
                T
                S
              
            
            =
            
              T
              peak
              ′
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




The area of triangle 3 is therefore found to be:




  
    
      
        
          
            A
            3
          
          =
          
            
              
                1
                2
              
              ⁡
              
                [
                
                  T
                  LSn
                  ′
                
                ]
              
            
            ⁡
            
              [
              
                
                  T
                  ′
                
                ⁢
                valley
              
              ]
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            A
            3
          
          =
          
            
              
                1
                2
              
              ⁡
              
                [
                
                  
                    
                      T
                      S
                    
                    ⁡
                    
                      (
                      
                        
                          V
                          in
                        
                        -
                        
                          V
                          out
                        
                      
                      )
                    
                  
                  
                    2
                    ⁢
                    
                      
                    
                    ⁢
                    
                      V
                      in
                    
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  -
                  
                    
                      V
                      out
                    
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      
                        V
                        in
                      
                    
                  
                
                ⁢
                
                  
                    (
                    
                      
                        V
                        in
                      
                      -
                      
                        V
                        out
                      
                    
                    )
                  
                  L
                
                ⁢
                
                  T
                  S
                
              
              ]
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            A
            3
          
          =
          
            -
            
              
                
                  1
                  8
                
                ⁡
                
                  [
                  
                    
                      
                        
                          V
                          in
                        
                        -
                        
                          V
                          out
                        
                      
                      
                        V
                        in
                      
                    
                    ⁢
                    
                      T
                      S
                    
                  
                  ]
                
              
              ⁡
              
                [
                
                  
                    
                      V
                      out
                    
                    
                      V
                      in
                    
                  
                  ⁢
                  
                    
                      (
                      
                        
                          V
                          in
                        
                        -
                        
                          V
                          out
                        
                      
                    
                    L
                  
                  ⁢
                  
                    T
                    S
                  
                
                ]
              
            
          
        
      
    
    
      
        (
        14
        )
      
    
  
  
    
      
        
          A
          3
        
        =
        
          
            -
            
              
                
                  
                    
                      V
                      out
                    
                    ⁡
                    
                      (
                      
                        
                          V
                          in
                        
                        -
                        
                          V
                          out
                        
                      
                      )
                    
                  
                  2
                
                ⁢
                
                  T
                  S
                  2
                
              
              
                8
                ⁢
                
                  
                
                ⁢
                
                  V
                  in
                  2
                
                ⁢
                L
              
            
          
          =
          
            -
            
              A
              2
            
          
        
      
    
    
      
        (
        15
        )
      
    
  




T′off, the time from when the low-side switch turns off until the inductor current reaches zero, can be found to be:




  
    
      
        
          
            T
            off
            ′
          
          =
          
            
              -
              
                T
                valley
                ′
              
            
            
              S
              HS
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            T
            off
            ′
          
          =
          
            
              
                
                  V
                  out
                
                
                  2
                  ⁢
                  
                    
                  
                  ⁢
                  
                    V
                    in
                  
                
              
              ⁢
              
                
                  
                    V
                    in
                  
                  -
                  
                    V
                    out
                  
                
                L
              
              ⁢
              
                T
                S
              
            
            
              
                
                  V
                  in
                
                -
                
                  V
                  out
                
              
              L
            
          
        
      
    
    
      
        (
        16
        )
      
    
  
  
    
      
        
          T
          off
          ′
        
        =
        
          
            
              V
              out
            
            
              2
              ⁢
              
                
              
              ⁢
              
                V
                in
              
            
          
          ⁢
          
            T
            S
          
        
      
    
    
      
        (
        17
        )
      
    
  




Then the area of triangle 4 is found to be:




  
    
      
        
          
            A
            4
          
          =
          
            
              
                1
                2
              
              ⁡
              
                [
                
                  T
                  off
                  ′
                
                ]
              
            
            ⁡
            
              [
              
                T
                valley
                ′
              
              ]
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            A
            4
          
          =
          
            
              
                1
                2
              
              ⁡
              
                [
                
                  
                    
                      V
                      out
                    
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      
                        V
                        in
                      
                    
                  
                  ⁢
                  
                    T
                    S
                  
                
                ]
              
            
            ⁡
            
              [
              
                
                  -
                  
                    
                      V
                      out
                    
                    
                      2
                      ⁢
                      
                        
                      
                      ⁢
                      
                        V
                        in
                      
                    
                  
                
                ⁢
                
                  
                    
                      V
                      in
                    
                    -
                    
                      V
                      out
                    
                  
                  L
                
                ⁢
                
                  T
                  S
                
              
              ]
            
          
        
      
    
    
      
        (
        18
        )
      
    
  
  
    
      
        
          A
          4
        
        =
        
          
            -
            
              
                
                  
                    V
                    out
                    2
                  
                  ⁡
                  
                    (
                    
                      
                        V
                        in
                      
                      -
                      
                        V
                        out
                      
                    
                    )
                  
                
                ⁢
                
                  T
                  S
                  2
                
              
              
                8
                ⁢
                
                  
                
                ⁢
                
                  V
                  in
                  2
                
                ⁢
                L
              
            
          
          =
          
            -
            
              A
              1
            
          
        
      
    
    
      
        (
        19
        )
      
    
  




The total charge delivered as a result of the BFB pulse is therefore found to be:

Ctotal=A1+A2+A3+A4  (20)

Ctotal=0  (21)

Therefore, a pulse with a high-side on-time that is half of the nominal value will result in zero net current delivered to the output capacitor.
As such, from (3) the steady-state duty ratio, D, is used to calculate the high-side and low-side on times for the BFB pulse as follows:



  
    
      T
      HS
      ′
    
    =
    
      
        
          1
          2
        
        ⁢
        
          DT
          S
        
      
      =
      
        
          
            V
            out
          
          
            2
            ⁢
            
              
            
            ⁢
            
              V
              in
            
          
        
        ⁢
        
          T
          S
        
      
    
  




  
    
      T
      LS
      ′
    
    =
    
      
        
          (
          
            1
            -
            D
          
          )
        
        ⁢
        
          T
          S
        
      
      =
      
        
          
            
              V
              in
            
            -
            
              V
              out
            
          
          
            V
            in
          
        
        ⁢
        
          T
          S
        
      
    
  



The high-side on-time is thus half of what it would be for a PFM pulse and the low-side on-time remains the same. The division by two can be implemented in a very simple fashion in digital logic as a bit shift operation. As with the PFM pulses, Vin is measured and the LUT output is used to compensate for any changes in V.
After the BFB pulse has been sent, VBFB increases while Vout remains constant (except for any discharge due to the power stage load) since zero net charge is delivered to the power stage output capacitor. Before sending another BFB pulse, the controller will wait for the BFB dead-zone to lapse. It exists to prevent a series of BFB pulses from being unnecessarily sent due to switching noise and the delay of the BFB charge pump. The BFB dead-zone should not necessarily be equal to the PFM dead-zone since it should be set depending on the characteristics of the BFB charge pump circuit, and thus is not correlated to the power stage. The BFB dead-zone can be calculated and programmed based the charge pump circuit parameters such as the capacitor sizes and diode specifications.
It is possible that both the conditions for generating BFB pulses (the BFB dead-zone lapses and the BFB comparator triggers) and PFM pulses (the PFM dead-zone lapses and the PFM comparator triggers) occur at the same time. In such a case, the PFM pulse takes priority over the BFB pulse. The PFM pulse will simultaneously increase Vout and VBFB, after which sending a BFB pulse is no longer necessary. If a BFB pulse were to be sent in this scenario, VBFB would increase but Vout would remain below Vref, causing a sag in the power stage output voltage.
Although the BFB pulses are timed so that there will be no affect on Vout, in a practical implementation of the system, the pulse can cause Vout to either increase or decrease. This can be due to quantization errors in measuring Vin, quantization errors in the sizes of the output pulses from the DPWM, and non-idealities in the power stage such as parasitics, and voltage drops across the diodes and switches. If a series of BFB pulses results in a significant decrease in Vout, the PFM comparator will trigger and a PFM pulse will be sent. Thus, a BFB pulse that causes a decrease in Vout will not be harmful as Vout is regulated to be above Vref when PFM mode is employed. However, if the BFB load is relatively high and the PFM load is relatively low, BFB pulses will be sent frequently and PFM pulses will be sent infrequently. In this case, if quantization errors and non-idealities cause each BFB pulse to increase Vout, the power stage output voltage can increase without bounds. To prevent this from occurring, an offset is subtracted from T′HS (or added to the T′LS) before the BFB pulse is generated. This offset, which is programmable, reduces the probability that a BFB pulse will cause Vout to increase.
The design also includes a safety mechanism that can be used with controllers that employ both PWM and PFM modes, as shown in FIG. 1. Two additional comparators are used to monitor Vout. One of the comparators has a reference, Vref+, that is larger than Vref and the other has a reference, Vref−, that is smaller than Vref. If Vout falls or rises outside of the range bounded by the two references, the controller will exit PFM mode and enter PWM mode. This feature is included as a precautionary measure in case the BFB pulse generation causes Vout to rise or fall to a significant degree.
The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

## Claims

1. A system comprising:
a controller to produce high-side and low-side control signals;
a power stage including a power stage output capacitor, the high and low-side signals being used to switch high-side and low-side transistors in the power stage to control the voltage across the power stage output capacitor of the power stage; and
a boost feedback charge pump including a charge pump output capacitor, the boost feedback charge pump receiving the low-side or high-side signal to increase the charge on the charge pump output capacitor;
wherein the controller is configured to send Pulse Frequency Modulation (PFM) high and low-side signals that controls the voltage on the power stage output capacitor and charges the charge pump output capacitor and configured to send Boost Feedback (BFB) high and low-side signals that charge the boost feedback capacitor, but are designed to not significantly change the charge on the power stage output capacitor.

2. The system of claim 1, wherein the controller samples an output voltage of the power stage and an output voltage of the feedback charge pump to determine when to send the PFM signals and when to send the BFB signals.

3. The system of claim 1, wherein the controller samples an input voltage of the power stage to determine an on-time of the BFB high-side and low-side signals so that the net charge to the power stage output capacitor is near zero.

4. The system of claim 3, wherein an offset is subtracted from the BFB high-side signal or added to the BFB low-side signal to ensure that there is never any positive charge applied to the power stage output by the BFB signals.

5. The system of claim 1, wherein a PFM dead zone period and BFB dead zone period are stored by the controller and the controller does not produce PFM signals in the PFM dead zone period and does not produce BFB signals in the BFB dead zone period.

6. The system of claim 5, wherein the BFB dead zone period is different from than the PFM dead zone period.

7. The system of claim 1, further comprising:
a comparator connected to the output of the boost feedback charge pump that is used to ensure that the output voltage of the boost feedback charge pump does not get too small.

8. The system of claim 7, wherein the controller switches the system into another mode if the output voltage of the power stage gets too large or too small.

9. The system of claim 1, wherein PFM signals are prioritized over BFB signals and if the controller determines that both PFM and BFB signals would otherwise be desirable, the controller sends the PFM signals.

10. The system of claim 1, wherein the BFB high-side on-time/BFB low side on-time ratio is first set to be roughly half the PFM high-side on-time/PFM low side on-time ratio and thereafter an offset period is subtracted from the BFB high-side on-time or added to the BFB low-side on-time.

11. A controller for a Pulse Frequency Modulation (PFM) power supply with a boost feedback charge pump with an output capacitor and a power storage with output capacitor, the controller configured to produce PFM high-side and low-side signals and Boost Feedback (BFB) high-side and low-side signals, the PFM signals being used to control the charge on the output capacitor of a power stage and to charge the output capacitor of the boost feedback charge pump, the BFB signals being adapted to charge the output capacitor of the boost feedback charge pump, but to not significantly affect the charge on the power stage output capacitor.

12. The controller of claim 11, wherein the controller samples an output voltage of the power stage and an output voltage of the boost feedback charge pump to determine when to send the PFM signals and when to send the BFB signals.

13. The controller of claim 11, wherein the controller samples an input voltage of the power stage to determine an on-time of the BFB high-side and low-side signals so that the net charge to the power stage output capacitor is near zero.

14. The controller of claim 13, wherein an offset is subtracted from the BFB high-side signal or added to the BFB low-side pulse signal to ensure that there is never any positive charge applied to the power stage output signal by the BFB signals.

15. The controller of claim 11, wherein a PFM dead zone period and BFB dead zone period are stored by the controller and the controller does not produce PFM signals in the PFM dead zone period and does not produce BFB signals in the BFB dead zone period.

16. The controller of claim 15, wherein the BFB dead zone period is different than the PFM dead zone period.

17. The controller of claim 11, further comprising:
a comparator connected to the output of the boost feedback charge pump that is used to ensure that the output voltage of the boost feedback charge pump does not get too small.

18. The controller of claim 17, wherein the controller switches the system into another mode if the output voltage of the power stage gets too large or too small.

19. The controller of claim 11, wherein PFM signals are prioritized over BFB signals and if the controller determines that both PFM and BFB signals would otherwise be desirable, the controller sends the PFM signals.

20. The controller of claim 11, wherein the BFB high-side on-time/BFB low side on-time ratio is set to be roughly half the PFM high-side on-time/PFM low side on-time ratio and thereafter an offset period is subtracted from the BFB high-side on-time or added to the BFB low-side on-time.