# Patent

## Title
All-NMOS 4-transistor non-volatile memory cell

## Abstract

A non-volatile memory cell includes NMOS programming, read, erase, and control transistors having gate electrodes connected to a storage node. The erase and control transistors have interconnected source, drain, and bulk electrodes. The cell is programmed by setting source, drain, bulk, and gate electrodes of all transistors to a positive voltage. An inhibiting voltage is applied to source, drain, and bulk electrodes of the read transistor, while setting source and drain electrodes of the programming transistor to the positive voltage and the bulk electrode of the programming transistor to the positive voltage or the inhibiting voltage. Source, drain, and bulk electrodes of the control transistor are then ramped to a negative control voltage while ramping source, drain, and bulk electrodes of the erase transistor to a negative erase voltage and then back to the positive voltage. Source, drain. bulk, and gate electrodes of the programming, erase, and control transistors are then returned to the positive voltage, while setting the source, drain, and bulk electrodes of the read transistor to the inhibiting voltage.

## Background
FIELD OF THE INVENTION
The present invention relates to integrated circuit memory devices and, in particular, to an all-NMOS 4-transistor non-volatile memory (NVM) cell that utilizes reverse Fowler-Nordheim tunneling for programming.
BACKGROUND OF THE INVENTION
Commonly-assigned U.S. Pat. No. 7,164,606, which issued on Jan. 16, 2007, to Poplevine et al., discloses an all-PMOS 4-transistor non-volatile memory (NVM) cell that utilizes reverse Fowler-Nordheim tunneling for programming.
Referring to FIG. 1, as disclosed in U.S. Pat. No. 7,164,606, in accordance with the method of programming an NVM array that includes all-PMOS 4-transistor NVM cells 100 having floating gate electrodes that are commonly-connected to a storage node Ps, for each NVM cell in the array that is to be programmed, all of the electrodes of the cell are grounded. An inhibiting voltage Vn is then applied to the bulk-connected source electrode Vr of the cell's read transistor Pr, to the commonly-connected drain, bulk region and source electrodes Ve of the cell's erase transistor Pe, and to the drain electrode Dr of the read transistor Pr. The source electrode Vp and the drain electrode Dp of the cell's programming transistor Pw are grounded. The voltage applied to the bulk region electrode Vnw of the programming transistor Pw is optional; it can be grounded or it can remain at the inhibiting voltage Vn. For all NVM cells in the array that are not selected for programming, the inhibiting voltage Vn is applied to the Vr, Ve and Dr electrodes and is also applied to the Vp, Dp and Vnw electrodes. For cells to be programmed, the control voltage Vc of the cell's control transistor Pc is then swept from 0V to a maximum programming voltage Vcmax in a programming time Tprog. The control voltage Vc is then ramped down from the maximum programming voltage Vcmax to 0V. All electrodes of the cell and the inhibiting voltage Vn are then returned to ground.
As described in detail in the '606 patent, the all-PMOS 4-transistor NVM cell disclosed therein relies on reverse Fowler-Nordheim tunneling for programming. That is, when the potential difference between the floating gate electrode of the programming transistor of the all-PMOS NVM cell and the drain, source and bulk region electrodes of the programming transistor exceeds a tunneling threshold voltage, electrons tunnel from the drain and source electrodes to the floating gate, making the floating gate negatively charged.
U.S. Pat. No. 7,164,606 is hereby incorporated by reference herein in its entirety to provide background information regarding the present invention.
The all-PMOS 4-transistor NVM cell programming technique disclosed in the '606 patent provides advantages of both low current consumption, allowing the ability to simultaneously program a large number of cells in a cell array without the need for high current power sources, and a simple program sequence. However, the 4-transistor PMOS NVM cell cannot be used in certain integrated circuit fabrication processes wherein n-epitaxial silicon is grown that shorts all N-wells together or where each N-well needs to be surrounded by an individual N+, P+, or trench guard ring and charge will be lost if the floating polysilicon gate crosses the guard ring.
Thus, there is a need for an NVM cell design that can be used in processes where an all-PMOS 4-transistor NVM cell is not possible, but retains the advantages of the all-PMOS 4-transistor cell.
SUMMARY OF THE INVENTION
The present invention provides a method of programming a non-volatile (NVM) memory cell array that includes a plurality of all-NMOS 4-transistor NVM cells. Each all-NMOS NVM cell in the NVM cell array includes a first NMOS programming transistor having a drain electrode, a bulk region electrode, a source electrode and a gate electrode connected to a common storage node, a second NMOS read transistor having a drain electrode, a bulk region electrode, a source electrode and a gate electrode connected to the common storage node, a third NMOS erase transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the common storage node, and a fourth NMOS control transistor having commonly-connected source, drain and bulk region electrodes and a gate electrode connected to the common storage node. The programming method comprises: for each NVM cell in the array, setting the source, drain and bulk region electrodes and the gate electrodes of the first, second, third and fourth NMOS transistors to a positive reference voltage; for each NVM cell in the array selected for programming, applying an inhibiting voltage to the source, drain and bulk region electrodes of the second NMOS read transistor while setting the source and drain electrodes of the first NMOS programming transistor to the positive reference voltage and maintaining the bulk region electrode of the first NMOS programming transistor at either the positive reference voltage or at the inhibiting voltage; for each NVM cell in the NVM cell array not selected for programming, setting the source, drain and bulk region electrodes of the second NMOS read transistor and of the first NMOS programming transistor to the inhibiting voltage; for each NVM cell in the array selected for programming, ramping down the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor from the positive reference voltage to a minimum control voltage for a preselected programming time while ramping down the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor from the positive reference voltage to a minimum erase voltage for the preselected programming time; for each NVM cell in the array selected for programming, at the end of the preselected programming time, ramping up the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor from the minimum control voltage to the positive reference voltage while ramping up the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor from the minimum erase voltage to the positive reference voltage; and, for each NVM cell in the array selected for programming, returning the source and drain electrodes and the gate electrodes of the first, third and fourth NMOS transistors to the positive reference voltage while setting the source, drain and bulk region electrodes of the second NMOS read transistor to the inhibiting voltage.
The features and advantages of the various aspects of the present invention will be more fully understood and appreciated upon consideration of the following detailed description of the invention and the accompanying drawings, which set forth illustrative embodiments in which the concepts of the invention are utilized.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram illustrating an all-PMOS 4-transistor NVM cell.
FIG. 2 is a schematic diagram illustrating an embodiment of an all-NMOS 4-transistor NVM cell in accordance with the concepts of the present invention.
FIG. 3 is a schematic diagram illustrating an embodiment of the FIG. 2 NVM cell adapted for incorporation into an NVM cell array.
FIG. 3A is a schematic diagram illustrating an alternate embodiment of the FIG. 2 NVM cell adapted for incorporation into an NVM cell array.
FIG. 4 is a schematic diagram illustrating an embodiment of an NVM cell array that includes a plurality of adapted NVM cells of the type shown in FIGS. 3 and 3A.
FIG. 5 is a cross-section drawing illustrating the FIG. 1 all-PMOS 4-transistor NVM cell.
FIG. 6 is a cross-section drawing illustrating the FIG. 2 embodiment of an all-NMOS NVM cell in accordance with concepts of the present invention.
FIG. 7 is a flow chart showing a programming sequence for a non-volatile memory cell.
FIG. 8 is a flow chart showing a programming sequence for a non-volatile memory cell array.



DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 shows an all-NMOS 4-transistor non-volatile memory (NVM) cell 200 that includes four NMOS transistors connected to a common storage node Ns. As described in greater detail below, one NMOS transistor is provided for each of the four NVM cell functions: program (or write), read, erase and control.
The programming function of the NVM cell 200 is controlled by a first NMOS programming transistor Nw having a source electrode that receives a source programming voltage Vp, a drain electrode that receives a drain programming voltage Dp and a bulk region electrode that receives a bulk programming voltage Vpwp. The gate electrode of programming transistor Nw is connected to the common storage node Ns.
The read function of the NVM cell 200 is controlled by a second NMOS read transistor Nr having a source electrode that receives a source read voltage Vr, a drain electrode that receives a drain read voltage Dr and a bulk region electrode that receives a bulk read voltage Vpwr. The gate electrode of the read transistor Nr is connected to the common storage node Ns.
The erase function of the NVM cell 200 is controlled by a third NMOS erase transistor Ne having interconnected source, drain and bulk region electrodes to which an erase voltage Ve is applied. The gate electrode of the erase transistor Ne is connected to the common storage node Ns.
The control function of the NVM cell 200 is controlled by a fourth NMOS control transistor Nc having interconnected source, drain and bulk region electrodes to which a control voltage Vc is applied. The gate electrode of the control transistor Nc is connected to the common storage node Ns.
The above-referenced '606 patent describes in detail how the reverse Fowler-Nordheim tunneling programming technique works for the all-PMOS 4-transistor NVM cell and the sequences for program, erase and read operations. The program, erase and read operations for the all-NMOS 4-transistor NVM cell 200 of the present invention are complimentary to those operations for the all-PMOS cell. That is, the program, erase and read sequences are the same with different polarity for voltages. In the case of the all-PMOS cell, the circuit reference voltage is 0V; for the all-NMOS cell, the reference voltage is positive (VDD). In the case of the all-PMOS cell, the inhibiting voltage Vn is a positive voltage; in the case of the all-NMOS cell, the inhibiting voltage Vn is 0V. In the case of the all-PMOS cell, the control voltage Vc and the erase voltage Ve are positive voltages Vcmax and Vemax, respectively; for the all-NMOS cell, the control voltage Vc and the erase voltage Ve are negative voltages Vcmin and Vemin, respectively.
With reference to FIG. 2, to program the all-NMOS 4-transistor NVM cell 200, the source, drain, bulk region and gate electrodes of the first NMOS programming transistor Nw, the second NMOS read transistor Nr, the third NMOS erase transistor Ne and the fourth NMOS control transistor Nc are all initially set to the positive reference voltage VDD. The inhibiting voltage Vn (0V) is applied to the source, drain and bulk region electrodes of the second NMOS read transistor Nr while setting the source and drain electrodes of the first NMOS programming transistor Nw to the positive reference voltage VDD and maintaining the bulk region electrode of the first NMOS programming transistor Nw at the positive reference voltage. VDD or the inhibiting voltage Vn (0V). The interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor Nc are then ramped down from the positive reference voltage VDD to a minimum negative control voltage Vcmin for a programming time Tprog while ramping down the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor Ne from the positive reference voltage VDD to a minimum negative erase voltage Vemin for the programming time Tprog. At the end of the programming time Tprog, the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor Nc are ramped up from the minimum negative control voltage Vcmin to the positive reference voltage while ramping up the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor Ne from the minimum negative erase voltage Vemin to the positive reference voltage VDD. The source, drain and bulk region electrodes of the first, third and fourth NMOS transistors are then returned to the positive reference voltage VDD while setting the source, drain and bulk region electrodes of the second NMOS read transistor Nr to the inhibiting voltage Vn (0V).
FIG. 7 is a flow chart showing a programming sequence 700 for the NMV cell 200 of FIG. 2.
FIG. 3 shows the all-NMOS transistor NVM cell 200 adapted to include additional N-channel pass transistors N1 and N2 for facilitating use of NVM cell 200 within an NVM cell array. For example, to read data from the common storage node Ns, N-channel pass transistor N1 is used by placing logic hi on read word line node RWL and sensing current on read bit line node RBL. To program data to the common storage node Ns, N-channel pass transistor N2 is used by placing logic hi on program word line node PWL and logic hi on program bit line node PBL to get logic hi on the programming transistor source node Vp of the cell to be programmed (or by placing logic low on node PBL to get logic low on the source node Vp to keep the cell at the erase stage). The dashed circles in FIG. 3 show a possible alternate implementation of the programming transistor Nw with interconnected source, drain and bulk region electrodes utilizing a programming transistor Nw with interconnected source and drain electrodes and a bulk region electrode that can be set to either the positive reference voltage VDD or the inhibiting voltage 0V.
FIG. 3A shows an alternate embodiment of the FIG. 3 adapted NVM cell. All aspects of the FIG. 3A adapted cell are the same as those of the FIG. 3 adapted cell except for the configuration of the programming transistor Nw. FIG. 3A shows a programming transistor Nw having a source electrode and commonly-connected drain and bulk region electrodes and a gate electrode connected to the common storage node Ns. The dashed circles in FIG. 3A show another possible alternate embodiment in which the programming transistor Nw having independent source, drain and bulk region electrodes and a gate electrode connected to the common storage node Ns.
Thus, possible biasing combinations for the programming transistor Nw are as follows:
1) Vp=VDD, Dp=VDD, Vpwp=VDD (FIG. 3)
2) Vp=VDD, Dp=VDD, Vpwp=Vss (FIG. 3 alternate)
3) Vp=VDD, Dp=floating, Vpwp=VDD (FIG. 3A)
4) Vp=VDD, Dp=floating, Vpwp=Vss (FIG. 3A alternate)
Those skilled in the art will appreciate that, from a transistor point of view, the source and drain are interchangeable, so Vp=VDD, Dp floating are equal to Vp floating, Dp=VDD from a functionality point of view.
FIG. 4 shows a plurality of NVM cells 200, which may be of the type shown in FIGS. 3 and 3A, incorporated into an NVM cell array 400. The erase voltage Ve and the control voltage Vc are applied directly to each NVM cell in the array 500. With no high voltage switches or other supporting circuitry, significantly simplified connection can be made from the array 500 to external or internal voltage and signal sources and to signal destinations. As stated above, the program voltage Vp is delivered to each cell individually through N-channel pass transistor N2 (FIGS. 3, 3A) to program the cell or to keep it at the erase stage.
During the erase mode, all read word lines (RWL) and program word lines (PWL) of the array 400 are at logic low and the erase voltage Ve is applied; the rest of the circuit lines of the array 400 are held at the positive reference voltage VDD.
During the programming mode, all of the read word lines (RWL) of the array 400 are at logic low, one of the program word lines, e.g., PWL(0), will be at logic hi, while the remaining program world lines PWL(1)-PWL(N−1) will be at logic low. To program a particular cell in the array 400, the corresponding program bit line, e.g., PBL(0), will be at logic high; to keep the remaining cells in the array 500 at the erase state, the corresponding program bit line PBL will be at logic low. Then both the control voltage Vc and the erase voltage Ve are applied to all cells in the array 400, while the rest of the signal lines are set at the positive reference voltage VDD.
During the read mode, all program word lines (PWL) in the array 400 are at logic low, one of the read word lines, e.g., RWL(0), will be at logic hi, while the remaining read word lines RWL(0)-RWL(N−1) in the array 400 will be at logic low. On each of the read bit lines RBL(0)-RBL(M−1), a high current or voltage will be received for each corresponding cell in the array that had been programmed, while a low current or voltage will be received for each corresponding cell that had been erased.
Referring to FIGS. 2, 3, 3A and 4, a summary of the program, erase and read sequences for the all-NMOS cell in an array 400 is as follows:
Program Sequence
Setting the source, drain, bulk region and gate electrodes of the first NMOS programming transistor Nw, the second NMOS read transistor Nr, the third NMOS erase transistor Ne and the fourth NMOS control transistor Nc to a positive reference voltage (VDD). For each NVM cell in the NVM cell array 400 selected for programming, applying an inhibiting voltage (0V) to the source, drain and bulk region electrodes of the read transistor Nr while setting the source and drain electrodes of the programming transistor Nw to the positive reference voltage and maintaining the bulk region electrode of the programming transistor at either the positive reference voltage (VDD) or the inhibiting voltage (0V). For each NVM cell in the NVM cell array 400 not selected for programming, setting the source, drain and bulk region electrodes of the read transistor Nr and of the programming transistor Nw to the inhibiting voltage (0V). Ramping down the interconnected source, drain and bulk region electrodes of the control transistor Nc from the positive supply voltage (VDD) to a predefined negative control voltage Vcmin for a preselected programming time Tprog while ramping down the interconnected source, drain and bulk region electrodes of the erase transistor Ne to a predefined negative erase voltage Vemin for the preselected programming time Tprog. For each NVM cell in the NVM cell array 400 selected for programming, at the end of the preselected programming time Tprog, ramping up the interconnected source, drain and bulk region electrodes of the control transistor Nc from the predefined negative control voltage Vcmin to the positive reference voltage (VDD) while ramping up the interconnected source, drain and bulk region electrodes of the erase transistor Ne from the predefined negative erase voltage Vemin to the positive reference voltage (VDD). For each NVM cell in the NVM cell array, returning the source, drain, bulk region and gate electrodes of the programming transistor Nw, the erase transistor Ne and the control transistor Nc to the positive reference voltage (VDD) while setting the source, drain and bulk region electrodes of the read transistor Nr to the inhibiting voltage (0V).
FIG. 8 is a flow chart showing a programming sequence 800 for the NMV cell array 400 of FIG. 4.
Erase Sequence
For each NVM cell in the array 400 to be erased, ramp down the erase voltage electrode Ve from the positive reference voltage (VDD) to the predefined negative erase voltage Vemin for a preselected erase time Terase and then ramp the erase voltage electrode Ve from the negative erase voltage Vemin back to the positive reference voltage (VDD). All other electrodes in the cell to be erased are set to the positive reference voltage (VDD).
Read Sequence
For each NVM cell in the array 400 to be read, set the read voltage electrode Vr to about 1V and the drain and bulk region electrodes of the read transistor Nr to 0V (e.g., sufficient voltage to be able to read the cell current while preventing disturb to the programmed cells.) All other electrodes in the cell to be read are set to the positive reference voltage (VDD).
Those skilled in the art will appreciate that the voltage levels utilized in the program, erase and read sequences will depend upon the thickness of the gate oxide utilized in the NMOS transistors of the NVM cell. For example, for a gate oxide thickness of 80 Å, VDD=3.3V, Vcmin=Vemin=−6.7V, Tprog=Terase=20-50 ms. For a gate oxide thickness of 120 Å, VDD=5V, Vcmin=Vemin=−11V.
FIG. 5 and FIG. 6 show, respectively, cross-sections of the FIG. 1 all-PMOS 4-transistor NVM cell and the FIG. 2 all-NMOS NVM cell. As shown in FIG. 6, the all-NMOS NVM cell utilizes an isolated P-well (PWELL). This results in smaller cell area compared to the all-PMOS cell because the spacing between the separated P-wells (which represent minimum N-well width) is smaller than the spacing between the separated N-wells in a P-substrate.
It should be understood that the particular embodiments of the invention described above have been provided by way of example and that other modifications may occur to those skilled in the art without departing from the scope of the invention as expressed in the appended claims and their equivalents.

## Claims

1. A non-volatile memory (NVM) cell comprising:
a first NMOS programming transistor having a drain electrode, a bulk region electrode, a source electrode, and a gate electrode connected to a common storage node;
a second NMOS read transistor having a drain electrode, a bulk region electrode, a source electrode, and a gate electrode connected to the common storage node;
a third NMOS erase transistor having interconnected source, drain and bulk region electrodes and a gate electrode connected to the common storage node; and
a fourth NMOS control transistor having interconnected source, drain and bulk region electrodes and a gate electrode connected to the common storage node.

2. A method of programming a non-volatile memory (NVM) cell, the NVM cell including a first NMOS programming transistor having a drain electrode, a bulk region electrode, a source electrode and a gate electrode connected to a common storage node, a second NMOS read transistor having a drain electrode, a bulk region electrode, a source electrode and a gate electrode connected to the common storage node, a third NMOS erase transistor having interconnected source, drain and bulk region electrodes and a gate electrode connected to the common storage node, and a fourth NMOS control transistor having interconnected source, drain and bulk region electrodes and a gate electrode connected to the common storage node, the NVM cell programming method comprising:
setting the source, drain, bulk region and the gate electrodes of the first, second, third and fourth NMOS transistors to a positive reference voltage;
applying an inhibiting voltage to the source, drain and bulk region electrodes of the second NMOS read transistor while setting the source and drain electrodes of the first NMOS programming transistor to the positive reference voltage and maintaining the bulk region electrode of the first NMOS programming transistor at either the positive reference voltage or the inhibiting voltage;
ramping down the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor from the positive reference voltage to a predefined negative control voltage for a preselected programming time while ramping down the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor from the positive reference voltage to a predefined negative erase voltage for the preselected programming time;
at the end of the preselected programming time, ramping up the interconnected source, drain and bulk regions electrodes of the fourth NMOS control transistor from the predefined negative control voltage to the positive reference voltage while ramping up the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor from the predefined negative erase voltage to the positive reference voltage; and
returning the source, drain, bulk region and gate electrodes of the first, third and fourth NMOS transistors to the positive reference voltage while setting the source, drain and bulk region electrodes of the second NMOS read transistor to the inhibiting voltage.

3. The method of claim 2, wherein the inhibiting voltage is 0V.

4. A method of programming a non-volatile memory (NVM) cell array that includes a plurality of NVM cells, each NMV cell in the array including a first NMOS programming transistor having a drain electrode, a bulk region electrode, a source electrode and a gate electrode connected to a common storage node, a second NMOS read transistor having a drain electrode, a bulk region electrode, a source electrode and a gate electrode connected to the common storage node, a third NMOS erase transistor having interconnected source, drain and bulk region electrodes and a gate electrode connected to the common storage node, and a fourth NMOS control transistor having interconnected source, drain and bulk region electrodes and a gate electrode connected to the common storage node, the NMV cell array programming method comprising:
setting the source, drain, bulk region and gate electrodes of the first, second, third and fourth NMOS transistors to a positive reference voltage;
for each NVM cell in the NVM cell array selected for programming, applying an inhibiting voltage to the source, drain and bulk region electrodes of the second NMOS read transistor while setting the source and drain electrodes of the first NMOS programming transistor to the positive reference voltage and maintaining the bulk region electrode of the first NMOS programming transistor at either the positive reference voltage or the inhibiting voltage;
for each NVM cell in the NVM cell array not selected for programming, setting the source, drain and bulk region electrodes of the second NMOS read transistor and of the first NMOS programming transistor to the inhibiting voltage;
for each NVM cell in the NVM cell array selected for programming, ramping down the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor from the positive reference voltage to a predefined negative control voltage for a preselected programming time while ramping down the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor from the positive reference voltage to a predefined negative erase voltage for the preselected programming time;
for each NVM cell in the NVM cell array selected for programming, at the end of the preselected programming time, ramping up the interconnected source, drain and bulk region electrodes of the fourth NMOS control transistor from the predefined negative control voltage to the positive reference voltage while ramping up the interconnected source, drain and bulk region electrodes of the third NMOS erase transistor from the predefined negative erase voltage to the positive reference voltage; and
for each NVM cell in the NVM cell array, returning the source, drain, bulk region and gate electrodes of the first, third and fourth NMOS transistors to the positive reference voltage while setting the source, drain and bulk region electrodes of the second NMOS read transistor to the inhibiting voltage.

5. The method of claim 4, wherein the inhibiting voltage is 0V.