# Patent

## Title
PFC switching power conversion circuit providing low total harmonic distortion

## Abstract

A PFC switching power conversion circuit providing low THD, including: a bridge rectifier for providing an input voltage according to an AC voltage; an electromagnetic interference filtering circuit for providing a line voltage according to the input voltage; a switching power converter for converting the line voltage to an output voltage or current under a control of a driving voltage, the driving voltage causing a switching current to flow through a main inductor; and a controller for receiving and processing at least one feedback signal from the switching power converter to generate the driving voltage in a constant on-time manner, the controller including an off-time detector and a timer, the off-time detector being used to detect decreasing periods of the switching current to determine respective off-time periods, and the timer being used to set a minimum limit on the respective off-time periods.

## Background
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a switching power conversion circuit providing a PFC (power factor correction) function with low THD (total harmonic distortion) while converting a standard AC (alternating current) voltage or a phase-cut AC voltage to a DC (direct current) output voltage or a DC output current.
Description of the Related Art
Conventional switching power conversion circuits are generally used to convert an AC voltage source to a DC output voltage or a DC output current for a load, and the load can be an LED (light emitting diode) module, a battery or an electronic device, etc.
Besides, when converting an AC voltage source to a DC output voltage or a DC output current, a good power factor is generally required. Taking a buck-boost power converter with a constant on-time mechanism operating in a BCM (boundary conduction mode) for example (the major operation waveforms thereof are shown in FIG. 1), the operation principle thereof can be characterized by the equations as follows:

IPK=(VIN/LMAIN)*TON,  (1)

where VIN is a full-wave rectified voltage derived from a standard AC voltage; LMAIN is an inductance value of a main inductor for storing and releasing energy in terms of current; TON is a turn-on time for building up a current flowing through the main inductor in each cycle of the switching cycles, and the switching cycles have different periods corresponding to different levels of the full-wave rectified voltage VIN present at different start time points of the switching cycles; and IPK is a peak value of the current through the main inductor built up per switching cycle, and IPK has different values corresponding to different levels of VIN respectively.

TOFF=(VIN/VOUT)*TON,  (2)

where VOUT is a DC output voltage, TOFF is a turn-off time in each switching cycle for discharging the current through the main inductor, and the length of TOFF is dependent on the corresponding voltage level of VIN. In general, there are many switching cycles during a half sinusoidal period of VIN, each switching cycle corresponds to a different level of VIN, and the higher/lower the level of VIN is, the longer/shorter the length of TOFF will be. That is, when VIN is at higher/lower levels, IPK will get higher/lower, and it will take longer/shorter time to discharge the current through the main inductor.




  
    
      
        
          
            (
            3
            )
          
          ⁢
          
            I
            
              IN
              ⁢
              
                -
              
              ⁢
              AVG
            
          
        
        =
        
        ⁢
        
          
            (
            
              1
              /
              2
            
            )
          
          *
          Ton
          *
          
            
              I
              PK
            
            /
            
              (
              
                
                  T
                  ON
                
                +
                
                  T
                  OFF
                
              
              )
            
          
        
      
    
  
  
    
      
        =
        
        ⁢
        
          
            (
            
              1
              /
              2
            
            )
          
          *
          Ton
          *
          
            [
            
              
                V
                OUT
              
              /
              
                (
                
                  
                    L
                    MAIN
                  
                  *
                  
                    (
                    
                      
                        V
                        IN
                      
                      +
                      
                        V
                        OUT
                      
                    
                    )
                  
                
                )
              
            
            ]
          
          *
          
            V
            IN
          
        
      
    
  
  
    
      
        
          =
          
          ⁢
          
            G
            *
            
              V
              IN
            
          
        
        ,
      
    
  




where IIN-AVG is an averaged input current per switching cycle, and G=(1⁄2)*Ton*[VOUT/(LMAIN*(VIN+VOUT))] is not a constant gain but inversely proportional to VIN, given fixed values of LMAIN and VOUT. That is, when VIN is at higher/lower levels, G will become lower/higher to introduce a THD into the input current.
To reduce the THD of the input current, one solution is using a sampling circuit to periodically sample the voltage of VIN, and use the sampled voltage of VIN to modify the value of the gain G so as to keep the envelope of the input current as close to the envelope of VIN as possible. However, this kind of solutions generally makes the control mechanism of the switching power converter more complex.
To solve the foregoing problems, a novel switching power conversion circuit is needed.
SUMMARY OF THE INVENTION
One objective of the present invention is to disclose a PFC switching power conversion circuit, which is capable of providing low THD without the need of sensing the level of an input voltage.
Another objective of the present invention is to disclose a PFC switching power conversion circuit, which uses a simple and robust control mechanism to compensate a nonlinear relationship between an input current and an input voltage, thereby minimizing the THD of the input current.
Still another objective of the present invention is to disclose a PFC switching power conversion circuit, which is capable of reducing the THD of an input current by setting a minimum limit on the off time per switching cycle.
To attain the foregoing objectives, a PFC switching power conversion circuit providing low total harmonic distortion is proposed, including:
a bridge rectifier for providing an input voltage by performing a rectifying operation on an AC voltage;
an electromagnetic interference filtering circuit for providing a line voltage by performing a filtering operation on the input voltage;
a switching power converter for converting the line voltage to an output voltage or an output current for a load under a control of a driving voltage, wherein the driving voltage causes a switching current to flow through a main inductor of the switching power converter in a waveform of triangular pulses; and
a controller for receiving at least one feedback signal from the switching power converter to generate the driving voltage, the controller operating in a constant on-time mode to determine an on-time period of the driving voltage by processing the at least one feedback signal, and the on-time period determines a rising period for each of the triangular pulses of the switching current;
wherein the controller includes an off-time detector and a timer, the off-time detector being used to detect decreasing periods of the switching current by processing the at least one feedback signal to determine off-time periods respectively, and the timer being used to set a minimum limit on the off-time periods.
In one embodiment, the controller further includes a driver for providing the driving voltage.
In one embodiment, the controller further includes a feedback circuit for processing the at least one feedback signal to generate an on-time determining signal for determining the on-time period, and generate an end-of-off-time signal for the off-time detector to determine the off-time periods.
In one embodiment, the controller further includes an on-time control unit for determining the on-time period according to the on-time determining signal.
In one embodiment, the AC voltage is a phase-cut AC voltage.
In one embodiment, the at least one feedback signal includes a voltage feedback signal and/or a current feedback signal.
In one embodiment, the switching power converter is an isolated switching power converter.
In one embodiment, the switching power converter is a non-isolated switching power converter.
In one embodiment, the controller includes a compensation circuit for adjusting the on-time period according to the at least one feedback signal.
In one embodiment, the timer has a fixed counting duration or an adjustable counting duration for determining the minimum limit.
To make it easier for our examiner to understand the objective of the invention, its structure, innovative features, and performance, we use preferred embodiments together with the accompanying drawings for the detailed description of the invention.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates major operation waveforms of a prior art buck-boost power converter with a constant on-time mechanism operating in a boundary conduction mode.
FIG. 2 illustrates a circuit diagram of a PFC switching power conversion circuit providing low total harmonic distortion according to an embodiment of the present invention.
FIG. 3a-3b illustrate operation waveforms of the power converter of the present invention in comparison with operation waveforms of a conventional power converter.



DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Please refer to FIG. 2, which illustrates a circuit diagram of a PFC switching power conversion circuit providing low total harmonic distortion according to an embodiment of the present invention. As illustrated in FIG. 2, the PFC switching power conversion circuit includes a bridge rectifier 110, an electromagnetic interference filtering circuit 120, a switching power converter 130, a load 140, and a controller 150, the controller 150 including a feedback circuit 151, an on-time control unit 152, an off-time detector 153, a timer 154, and a driver 155.
The bridge rectifier 110 is used for providing an input voltage VIN by performing a rectifying operation on an AC voltage VAC. The AC voltage VAC can be a standard AC voltage or a phase-cut AC voltage. The phase-cut AC voltage is generally generated by a dimmer circuit including a TRIAC.
The electromagnetic interference filtering circuit 120 is used for providing a line voltage VL by performing a filtering operation on the input voltage VIN to filter out accompanying noises.
The switching power converter 130, which can be an isolated switching power converter (generally using a transformer for power transformation) or a non-isolated switching power converter, is used for converting the line voltage VL to an output voltage VOUT or an output current IOUT for the load 140 under a control of a driving voltage VDRV. When in operation, the driving voltage VDRV will cause a switching current having a waveform of triangular pulses to flow through a main inductor (not shown in the figure) of the switching power converter 130.
The controller 150 is used for receiving at least one feedback signal SFB, which can include a voltage feedback signal and/or a current feedback signal, from the switching power converter 130 to generate the driving voltage VDRV, the controller 150 operates in a constant on-time mode to determine an on-time period, which may be a same on time for each switching cycle of the driving voltage VDRV, by processing the at least one feedback signal SFB, and the on-time period determines a rising period for each of the triangular pulses of the switching current. Besides, the controller 150 can also include a compensation circuit for adjusting the on-time period according to the at least one feedback signal to enhance the power factor and reduce the THD.
When in operation, the feedback circuit 151 will use the at least one feedback signal SFB to generate an on-time determining signal SOT and an end-of-off-time signal SEOOFT.
The on-time control unit 152 operates in a constant on-time mode and determines the on-time period for each switching cycle of the driving voltage VDRV according to the on-time determining signal SOT. In one embodiment, the on-time control unit 152 performs a low-pass filtering operation on an error signal representing a difference between the on time determining signal SOT and a reference level to generate a threshold signal, and uses the threshold signal to compare with a sawtooth signal to determine the on-time period. The sawtooth signal can be generated by repeatedly charging and discharging a capacitor with a current source and a discharging circuit (not shown in the figure) respectively, and the value of the current source can be a fixed value or adjusted by a modulation signal generated according to the at least one feedback signal SFB.
The off-time detector 153 is used to detect decreasing periods of the switching current according to the end-of-off-time signal SEOOFT to determine off-time periods of switching cycles respectively, and the timer 154, which can repeatedly count for a predetermined duration, is used to set a minimum limit on each of the off-time periods, and the off-time detector 153 generates resultant off-time periods according to the off-time periods and the minimum limit in a way that, any of the resultant off-time periods is set to be equal to the minimum limit when a corresponding period of the off-time periods is shorter than the minimum limit, and any of the resultant off-time periods is set to be equal to a corresponding period of the off-time periods when the corresponding period is not shorter than the minimum limit. That is, the resultant off-time period is set to be equal to a larger one of the off-time period and the minimum limit. Besides, the predetermined duration of the timer 154 can be a fixed counting duration or an adjustable counting duration.
The driver 155 will provide the driving voltage VDRV having an active period and an inactive period in each cycle of switching cycles, wherein each period of the active periods is defined by the on-time period, and inactive periods are defined by the resultant off-time periods correspondingly.
Besides, as is known from the description of related art above, when a power converter operates in a constant on-time mode, the relation between the average input current TIN-AVG and the full-wave rectified input voltage VIN can be expressed as IIN-AVG=G*VIN, G=(1⁄2)*Ton*[VOUT/(LMAIN*(VIN+VOUT))], wherein the gain G is inversely proportional to VIN. That is, the gain G is higher when the full-wave rectified input voltage VIN is at low levels than when the full-wave rectified input voltage VIN is at high levels, and this non-uniform variation causes substantial THD to the input current.
As the gain G can also be expressed as G=(1⁄2)*[TON2/(LMAIN*(TON+TOFF))], therefore, by setting a minimum limit on the off-time period TOFF, the gain G can be kept at a lower value rather than rising up when the full-wave rectified input voltage VIN is approaching low levels, and the THD can be effectively reduced accordingly. That is, when the full-wave rectified input voltage VIN is at low levels to cause off-time periods shorter than a preset value, by using the preset value as a minimum limit for the off-time period TOFF at these instances, the distortion of the gain G can be effectively compensated. Please refer to the table below, which gives experiment results of THD at different AC voltages for the present invention (with minimum TOFF) and a conventional scheme (without limiting TOFF) respectively. As can be seen in the table, the THD values of the present invention are much lower than the corresponding THD values of the conventional scheme.













THD of the 
THD of a 



present invention
conventional scheme


AC voltage
(with minimum TOFF)
( without limiting TOFF)







120 V
 9.90%
18.70%


230 V
12.50%
26.20%


277 V
14.30%
27.80%









Thanks to the designs disclosed above, the present invention offers the advantages as follows:
1. The PFC switching power conversion circuit of the present invention can provide low THD without the need of sensing the level of an input voltage.
2. The PFC switching power conversion circuit of the present invention uses a simple and robust control mechanism to compensate a nonlinear relationship between an input current and an input voltage, thereby minimizing the THD of the input current.
3. The PFC switching power conversion circuit of the present invention can reduce the THD of an input current by setting a minimum limit on the off time per switching cycle.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
In summation of the above description, the present invention herein enhances the performance over the conventional structure and further complies with the patent application requirements and is submitted to the Patent and Trademark Office for review and granting of the commensurate patent rights.

## Claims

1. A PFC switching power conversion circuit providing low total harmonic distortion, including:
a bridge rectifier for providing an input voltage by performing a rectifying operation on an AC voltage;
an electromagnetic interference filtering circuit for providing a line voltage by performing a filtering operation on the input voltage;
a switching power converter for converting the line voltage to an output voltage or an output current for a load under a control of a driving voltage, wherein the driving voltage causes a switching current to flow through a main inductor of the switching power converter in a waveform of triangular pulses; and
a controller for receiving at least one feedback signal from the switching power converter to generate the driving voltage, the controller operating in a constant on-time mode to determine an on-time period of the driving voltage by processing the at least one feedback signal, and the on-time period determines a rising period for each of the triangular pulses of the switching current;
wherein the controller includes an off-time detector and a timer, the off-time detector being used to detect decreasing periods of the switching current by processing the at least one feedback signal to determine off-time periods respectively, and the timer being used to set a minimum limit on the off-time periods.

2. The PFC switching power conversion circuit providing low total harmonic distortion as claim 1, wherein the controller further includes a driver for providing the driving voltage.

3. The PFC switching power conversion circuit providing low total harmonic distortion as claim 1, wherein the controller further includes a feedback circuit for processing the at least one feedback signal to generate an on-time determining signal for determining the on-time period, and generate an end-of-off-time signal for the off-time detector to determine the off-time periods.

4. The PFC switching power conversion circuit providing low total harmonic distortion as claim 3, wherein the controller further includes an on-time control unit for determining the on-time period according to the on-time determining signal.

5. The PFC switching power conversion circuit providing low total harmonic distortion as claim 1, wherein the AC voltage is a phase-cut AC voltage.

6. The PFC switching power conversion circuit providing low total harmonic distortion as claim 1, wherein the at least one feedback signal includes a voltage feedback signal and/or a current feedback signal.

7. The PFC switching power conversion circuit providing low total harmonic distortion as claim 1, wherein the switching power converter is an isolated switching power converter.

8. The PFC switching power conversion circuit providing low total harmonic distortion as claim 1, wherein the switching power converter is a non-isolated switching power converter.

9. The PFC switching power conversion circuit providing low total harmonic distortion as claim 1, wherein the controller includes a compensation circuit for adjusting the on-time period according to the at least one feedback signal.

10. The PFC switching power conversion circuit providing low total harmonic distortion as claim 1, wherein the timer has a fixed counting duration or an adjustable counting duration for determining the minimum limit.