# Patent

## Title
Pulsed current source with internal impedance matching

## Abstract

Pulsed current circuitry for electromigration testing of semiconductor integrated circuits and components. The circuit includes a multiplexer that outputs analog voltage pulses, and is capable of generating both bipolar and unipolar voltage pulses. At least one operational amplifier and resistor receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses. A charge booster circuit is provided for minimizing overshoots and undershoots during transitions between current levels in the test circuit.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a Continuation-in-Part of U.S. application Ser. No. 14/937,297, filed on Nov. 10, 2015, which is herein incorporated by reference in its entirety.


BACKGROUND
The present invention relates generally to circuitry for testing electrical components and circuits. More particularly, the present invention relates to current pulse circuitry for use in electromigration testing of semiconductor integrated circuits and components.
Semiconductor reliability tests require continuous application of electrical stimulus, usually at a controlled temperature ranging from −50° C. to +350° C. based on the specific test parameter (e.g., hot carrier, electromigration, etc.). For electromigration testing in particular, testing using DC current has always been the preferred approach due to its simplicity, built-in conservatism, and relatively low cost. However, advances in process miniaturization have rendered DC tests insufficient, thus making similar testing under pulsed conditions a necessity.
Current pulses are thus often employed in testing electrical components and circuits. An ideal pulsed stimulus should allow flexible control of Pulse-Repetition-Rate, Duty-Cycle, Polarity, and Intensity (Amplitude). These parameters are illustrated in FIGS. 1A and 1B, where T is the period, frequency (f) is the pulse repetition rate (Hz), duty cycle is 2 tp/T; positive amplitude is Ap, and negative amplitude is An (Volt, Amp). When high repetition rate current pulses are required, for example with pulsed electromigration tests, the desired pulse is typically rectangular. Therefore, the transition between current levels must be abrupt with minimal overshoot to effectively provide the intended current drive at each level. FIGS. 1A and 1B show the transition between current levels for bipolar and unipolar current pulses, respectively. Ideally, the transition from the “DC Level” (frequently “GND”) to the required current (“Ap” or “An,” or generally “A” for simplicity) is abrupt, as shown in FIGS. 1A and 1B.
In reality, however, such transitions take time and can be too slow to reach the required maximum current level A. An effective technique to achieve current pulses is implemented by using two constant current (DC) sources and charge booster circuit, as described in U.S. Pat. No. 6,249,137 to Krieger et al., entitled “CIRCUIT AND METHOD FOR PULSED RELIABILITY TESTING” and in U.S. Pat. No. 7,049,713 to Cuevas et al., entitled “PULSED CURRENT GENERATOR CIRCUIT WITH CHARGE BOOSTER.” However, using this technique has become difficult due to its dependence on discrete and potentially obsolete transistors. In addition, aggressive semiconductor scaling has been pushing down pulse current levels, making it difficult to eliminate pulse overshoots. The relatively large number of discrete components in the circuit, combined with its complex calibration and adjustment, increase manufacturing and maintenance costs. Therefore, it is desirable to provide a high quality pulse current source that can achieve the desired current pulses as well as overcome the limitations discussed above.
SUMMARY
In accordance with an embodiment, a test circuit is provided for applying current pulses to a device under test (DUT). The test circuit includes a multiplexer and at least one operational amplifier and resistor. The multiplexer outputs analog voltage pulses, and is capable of generating both bipolar and unipolar voltage pulses. The at least one operational amplifier and resistor receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses. An operational amplifier outputs current pulses, and the current pulses are bipolar or unipolar current pulses depending on whether the operational amplifier and resistor receive bipolar or unipolar voltage pulses.
In accordance with another embodiment, a method is provided for providing a pulsed current to a device under test (DUT). A plurality of different voltage levels are provided to a plurality of input terminals of a multiplexer. Voltage pulses are generated from a selected voltage level by using input select combination of input select lines of the multiplexer to determine which of the input terminals of the multiplexer is connected to an output of the multiplexer. Input select combination of the multiplexer is performed by assigning address values to input select lines of the multiplexer in a way such that any transitional address value leads to a monotonic change of the output of the multiplexer, which comprise voltage pulses. The voltage pulses are converted to current pulses using a plurality of resistors, operational amplifiers, and capacitors
In accordance with yet another embodiment, a single circuit that is capable of providing both unipolar and bipolar current pulses is provided. The circuit includes a multiplexer and at least one operational amplifier and resistor. The multiplexer receives at least one positive voltage signal and at least one negative voltage signal, and the multiplexer is capable of generating both bipolar and unipolar voltage pulses from the voltage signals it receives. The operational amplifier and resistor receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses. An operational amplifier outputs bipolar or unipolar current pulses depending on whether the at least one operational amplifier and resistor receive bipolar or unipolar voltage pulses.
In accordance with another embodiment, a test circuit is provided for applying current pulses to a device under test (DUT). The test circuit includes a multiplexer, at least one operational amplifier and resistor, and a charge booster circuit for minimizing overshoots and undershoots during transitions between current levels. The multiplexer outputs analog voltage pulses, and the multiplexer is capable of generating both bipolar and unipolar voltage pulses. The operational amplifier and resistor receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses. The operational amplifier outputs current pulses that are bipolar or unipolar current pulses depending on whether the at least one operational amplifier and resistor receive bipolar or unipolar voltage pulses. The charge booster circuit includes at least one operational amplifier, a plurality of resistors, and a capacitor.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention, together with further objects and advantages thereof, may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which:
FIGS. 1A and 1B illustrate bipolar pulses and unipolar pulses, respectively, that are useful in testing electronic components.
FIG. 2 is a conceptual schematic diagram of pulsed current circuitry in accordance with an embodiment
FIG. 3 is a conceptual schematic diagram of a charge booster circuit in accordance with an embodiment.
FIG. 4 is a conceptual schematic diagram of a pulsed current circuit and a charge booster circuit, in accordance with an embodiment.
FIG. 5 is a flow chart of a method of providing a pulsed current to a device under test (DUT).



DETAILED DESCRIPTION OF EMBODIMENTS
The present invention relates generally to testing electrical components and circuits. The embodiments herein describe pulsed current circuitry for electromigration testing of semiconductor integrated circuits and components.
Referring to FIGS. 2-5, embodiments of pulsed current test circuitry will be described. FIG. 2 is a conceptual schematic diagram of pulsed current test circuitry 100 in accordance with an embodiment. In the illustrated embodiment, the pulsed current test circuitry 100 includes a high-speed analog multiplexer 110. An exemplary multiplexer is the ADV3221/ADV3222 analog multiplexer, which is available commercially from Analog Devices, Inc. of Norwood, Mass. The multiplexer 110 can generate either unipolar or bipolar voltage pulses at repetition rates as high as 10 MHz (40 nS pulse). The rest of the circuit 100 converts these voltage pulses (Vin) to current pulses (Idut) accordingly, using fast operational amplifiers, which function properly at these rates.
The sensitivity of the circuit 100 to common-mode errors is minimized by positioning the device under test (DUT) between ground and the output of the current source. Another advantage is attained by not using a differential amplifier, which is commonly associated with high leakage currents.
DACp and DACn 130 are digital-to-analog converters that convert a digital voltage signal to an analog voltage signal. The DACp 120 and DACn 130 provide the required discrete analog voltage levels Vp and Vn to the second and third input terminals of the analog multiplexer M1 110, respectively. That is, Vp and Vn should be sufficient to drive the desired current through RDUT. The first input terminal of the multiplexer M1 110 is connected to ground voltage GND or to an additional digital-to-analog converter (DACg) to have control over a desired DC component added to current pulse. In Example 1 below with three voltage levels, the fourth input of the multiplexer M1 110 is still used and is connected to the first input to achieve monotonic change of output even though only three voltage levels are needed for a bipolar pulse in this example.
Generally, the multiplexer M1 110 has one less input select line than voltage levels, as shown in the examples below. In Example 1, the two input select lines A0 and A1 determine which of the inputs of the multiplexer M1 110 is connected to the output of the multiplexer M1 110 (Vin). As explained herein, the particular connectivity is intentional rather than arbitrary, with the second input connected to the highest maximum voltage (Vp in this example), the first and fourth inputs connected to the intermediate (GND or DACg, if applicable), and the third input connected to the lowest voltage (Vn).
Input select combination of multiplexer M1 110 by assigning address values to the input select lines A0 and A1 is performed in a way such that any transitional address value always leads to a monotonic, and therefore seamless, change of the output (e.g., high=>low=>lower; low=>high=>higher), with the following example demonstrating it in more detail:
EXAMPLE 1
Bipolar Pulse (Three Voltage Levels)














M1 Output Status


M1 Output Voltage
Input Select (Address)
(Stable/Transitional)







Vp
A0 = 0, A1 = 1
Stable


Vg
A0 = 0, A1 = 0
Stable


Vg
A0 = 1, A1 = 1
Transitional


Vn
A0 = 1, A1 = 0
Stable









As shown in the example above, only one address line changes during transitions from Vp to Vg and from Vp to Vg. However, if a transition from Vp to Vn takes place, assigning the input select as A0=1 and A1=1 as a transitional address of Vg ensures that no matter which address line changes state first—the output voltage of the MUX M1 110 follows the desired voltage transition monotonically. It will be understood that, in other embodiments, the three-level case described above can be expanded to four- and five-level pulse, with monotonic transitions ensured, using a similar addressing approach with three and four input select lines, respectively, as shown in the examples below.
EXAMPLE 2
Bipolar Pulse (Four Voltage Levels)














M1 Output Status


M1 Output Voltage
Input Select (Address)
(Stable/Transitional)







V1 (max)
A0 = 0, A1 = 0, A2 = 1
Stable


V2 (V3 < V2 < V1)
A0 = 0, A1 = 0, A2 = 0
Transitional


V2 (V3 < V2 < V1)
A0 = 0, A1 = 1, A2 = 1
Transitional


V2 (V3 < V2 < V1)
A0 = 0, A1 = 1, A2 = 0
Stable


V3 (V4 < V3 < V2)
A0 = 1, A1 = 1, A2 = 1
Stable


V3 (V4 < V3 < V2)
A0 = 1, A1 = 1, A2 = 0
Transitional


V3 (V4 < V3 < V2)
A0 = 1, A1 = 0, A2 = 1
Transitional


V4 (min)
A0 = 1, A1 = 0, A2 = 0
Stable









In Example 2 above, in the transition from V1 to V4, there are two input select lines changing state: A2 from 1 to 0 and A0 from 0 to 1. If A2 transitions before A0, the resulting transitional pattern is 000, which is assigned to V2. If, on the other hand, A0 transitions before A2A0, the resulting transitional pattern is 101, which is assigned to V3. Therefore, the resulting voltage change is monotonic while the address pattern is changing.
EXAMPLE 3
Bipolar Pulse (Five Voltage Levels)














M1 Output Status




(Stable/


M1 Output Voltage
Input Select (Address)
Transitional)







V1 (max)
A0 = 0, A1 = 0, A2 = 1, A3 = 1
Stable


V2 (V3 < V2 < V1)
A0 = 0, A1 = 0, A2 = 1, A3 = 0
Transitional


V2 (V3 < V2 < V1)
A0 = 1, A1 = 0, A2 = 1, A3 = 1
Transitional


V2 (V3 < V2 < V1)
A0 = 0, A1 = 0, A2 = 0, A3 = 1
Stable


V2 (V3 < V2 < V1)
A0 = 0, A1 = 1, A2 = 1, A3 = 1
Transitional


V3 (V4 < V3 < V2)
A0 = 1, A1 = 0, A2 = 1, A3 = 0
Transitional


V3 (V4 < V3 < V2)
A0 = 0, A1 = 1, A2 = 0, A3 = 1
Transitional


V3 (V4 < V3 < V2)
A0 = 1, A1 = 1, A2 = 1, A3 = 1
Transitional


V3 (V4 < V3 < V2)
A0 = 0, A1 = 0, A2 = 0, A3 = 0
Stable


V3 (V4 < V3 < V2)
A0 = 0, A1 = 1, A2 = 1, A3 = 0
Transitional


V3 (V4 < V3 < V2)
A0 = 1, A1 = 0, A2 = 0, A3 = 1
Transitional


V4 (V5 < V4 < V3)
A0 = 1, A1 = 0, A2 = 0, A3 = 0
Transitional


V4 (V5 < V4 < V3)
A0 = 1, A1 = 1, A2 = 0, A3 = 1
Transitional


V4 (V5 < V4 < V3)
A0 = 0, A1 = 1, A2 = 0, A3 = 0
Stable


V4 (V5 < V4 < V3)
A0 = 1, A1 = 1, A2 = 1, A3 = 0
Transitional


V5 (min)
A0 = 1, A1 = 1, A2 = 0, A3 = 0
Stable









Thus, as shown above, with every change of a single address line, the next voltage is selected. For example, transitioning from V2 to V5, the voltages V3, V4, and V5 will always be selected in that order (i.e., monotonic changes), with no gaps or duplicate voltage selections.
Assuming that the parasitic capacitance Cpar 160 and capacitor C1 170 are very small (R5*C1 is less than one percent of Tp or Tn; and Rn*Cpar is less than one percent of Tp or Tn), their charging and discharging will take much less time than tp and tn (FIG. 1). Given that, the current IDUT flowing through RDUT 180 is the same as the current flowing through Rnet 190, and the following relation is valid:




  
    
      
        
          
            
              (
              
                
                  V
                  DUT
                
                +
                
                  
                    I
                    DUT
                  
                  ⁢
                  
                    R
                    net
                  
                
              
              )
            
            ⁢
            
              (
              
                
                  R
                  4
                
                
                  
                    R
                    3
                  
                  +
                  
                    R
                    4
                  
                
              
              )
            
          
          -
          
            V
            off
            1
          
        
        =
        
          
            
              
                
                  V
                  DUT
                
                -
                
                  V
                  off
                  2
                
                -
                
                  V
                  
                    i
                    ⁢
                    
                      
                    
                    ⁢
                    n
                  
                
              
              
                
                  R
                  1
                
                +
                
                  R
                  2
                
              
            
            ⁢
            
              R
              1
            
          
          +
          
            V
            
              i
              ⁢
              
                
              
              ⁢
              n
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




where Voff1 and Voff2 are the offset voltages of the operational amplifiers OPA1 140 and OPA2 150, respectively. It will be understood that input bias currents are ignored because they are too small to have any significant effect on the circuit 100.

Combining and arranging terms in equation (1) above yields:




  
    
      
        
          
            
              V
              DUT
            
            ⁡
            
              (
              
                
                  
                    R
                    1
                  
                  
                    
                      R
                      1
                    
                    +
                    
                      R
                      2
                    
                  
                
                -
                
                  
                    R
                    4
                  
                  
                    
                      R
                      3
                    
                    +
                    
                      R
                      4
                    
                  
                
              
              )
            
          
          +
          
            
              V
              
                i
                ⁢
                
                  
                
                ⁢
                n
              
            
            ⁢
            
              
                R
                2
              
              
                
                  R
                  1
                
                +
                
                  R
                  2
                
              
            
          
          -
          
            
              V
              off
              2
            
            ⁢
            
              
                R
                1
              
              
                
                  R
                  1
                
                +
                
                  R
                  2
                
              
            
          
          +
          
            V
            off
            1
          
        
        ==
        
          
            I
            DUT
          
          ⁢
          
            R
            net
          
          ⁢
          
            
              R
              4
            
            
              
                R
                3
              
              +
              
                R
                4
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




By setting R1=KR2 and R3=KR4 (with K being a constant that is subject to modification), the terms having VDUT cancel and equation (2) can be simplified to:




  
    
      
        
          
            
              V
              
                i
                ⁢
                
                  
                
                ⁢
                n
              
            
            
              K
              +
              1
            
          
          -
          
            
              KV
              off
              2
            
            
              K
              +
              1
            
          
          +
          
            V
            off
            1
          
        
        =
        
          
            
              KI
              DUT
            
            ⁢
            
              R
              net
            
          
          
            K
            +
            1
          
        
      
    
    
      
        (
        3
        )
      
    
  
  
    
      and
    
    
      
        
      
    
  
  
    
      
        
          I
          DUT
        
        =
        
          
            
              
                V
                
                  i
                  ⁢
                  
                    
                  
                  ⁢
                  n
                
              
              
                KR
                net
              
            
            +
            
              
                
                  
                    (
                    
                      K
                      +
                      1
                    
                    )
                  
                  ⁢
                  
                    V
                    off
                    1
                  
                
                -
                
                  KV
                  off
                  2
                
              
              
                KR
                net
              
            
          
          =
          
            
              
                V
                
                  i
                  ⁢
                  
                    
                  
                  ⁢
                  n
                
              
              
                KR
                net
              
            
            +
            δ
          
        
      
    
    
      
        (
        4
        )
      
    
  




where Vin=Vp for the “high” part of the pulse and Vin=Vn for the “low” part of the pulse, and





  δ
  ≡
  
    
      
        
          (
          
            K
            +
            1
          
          )
        
        ⁢
        
          V
          off
          1
        
      
      -
      
        KV
        off
        2
      
    
    
      KR
      net
    
  




Apart from the error introduced by the offset voltages, the required current pulse is attained by setting DACp and DACn to Vp=IpRnet and Vn=Rnet, respectively. To assess the accuracy of the current source, the worst case error δmax is defined as:




  
    δ
    
      ma
      ⁢
      
        
      
      ⁢
      x
    
  
  ≡
  
    Max
    ⁢
    
      {
      
        
          
            
            
              
                (
                
                  K
                  +
                  1
                
                )
              
              ⁢
              
                V
                off
                1
              
            
            
          
          +
          
            
            
              KV
              off
              2
            
            
          
        
        
          KR
          net
        
      
      }
    
  
  ≤
  
    
      
        (
        
          2
          +
          
            1
            /
            K
          
        
        )
      
      ⁢
      
        
        
          
            V
            off
          
          ⁡
          
            (
            max
            )
          
        
        
      
    
    
      R
      net
    
  




where Voff (max) is the largest possible offset value of (Voff1, Voff2,) under the entire operating range (mainly temperature). The ratio between the maximum error and the desirable current provides a conservative gauge of accuracy for the pulsed current source:





  
    
      
        
          Max
          ⁢
          
            
          
          ⁢
          Relative
          ⁢
          
            
          
          ⁢
          Error
        
        ≤
        
          ±
          
            
              
                (
                
                  2
                  +
                  
                    1
                    /
                    K
                  
                
                )
              
              ⁢
              
                
                
                  
                    V
                    off
                  
                  ⁡
                  
                    (
                    max
                    )
                  
                
                
              
            
            
              
              
                V
                DUT
              
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




This relative error can be a limitation for low currents. However, measurements are typically carried out in a controlled environment, where the ambient temperature varies only by a few degrees relative to the set room temperature. This enables nearly complete elimination of the error, using calibration, pre-test offset measurement, and common correction algorithms.
The circuit will not be complete as long as capacitors C1 and Cpar are restricted to very low values. For C1, which is connected to suppress high-frequency oscillations, it is not a real limitation because it functions effectively by increasing the pulse rise and fall times by a few nanoseconds only.
Cpar, on the other hand, poses a real challenge as its total value can reach 50 pF or more (combination of the packaged DUT, printed circuit board capacitance, and layout). For example, with RDUT=1kΩ and Cpar=50 pF, the resulting time constant RDUTCpar is 50 nS (5×10−8 seconds), making low current pulses shorter than 250 nS practically impossible.
The solution involves a separate charge booster. Unlike U.S. Pat. No. 6,249,137, which uses discrete (and potentially obsolete) transistors and a relatively complex circuitry, according to an embodiment, a charge booster circuit 200, as shown in FIG. 3, is provided. This approach is based on the “balanced-attenuator” concept, which aims at eliminating overshoots and undershoots during abrupt changes, such as rise and fall of a pulse. As discussed in more detail below, the charge booster circuit 200 has input voltage signals Vbp and Vbn, which are converted from digital to analog signals by two DACs (DACbp 220 and DACbn 230), and the charge booster circuit 200 returns its output signal to the top of RDUT (marked as “VDUT” in FIG. 2). Similar to OPA1 140 and OPA2 150 (FIG. 2), operational amplifier OPA3 260 in the charge booster circuit 200 is sufficiently fast to function properly at the required pulse repetition rates.
As shown in FIG. 3, the charge booster circuit 200 is driven by a combination of two DACs (DACbp 220 and DACbn 230) and a 4:1 Analog Multiplexer (M2) 210, similar to the conceptual current source shown in FIG. 2. The same input select lines are used for both M1 110 and M2 210, but the two pairs of DACs (120, 130 and 220, 230) are independent, meaning that the input signal to the inverting input of OPAL 140 (Vin) and the input signal to the non-inverting input of OPA3 260 (Vinb) are synchronized but their voltage levels are independent. The output voltage of the charge booster circuit 200 (i.e. the output of OPA3 260) is coupled to the DUT (VDUT) via capacitor C2270, as shown in FIG. 4.
Denoting the time just following a rise or fall (transition) of the pulse t=0+ and neglecting the offset voltage and input currents of OPA2 150 and OPA3 260, the current through capacitors C2 270 and Cpar 160 just after the transition satisfies the following relation:




  
    
      
        
          
            V
            DUT
            
              0
              +
            
          
          -
          
            V
            DUT
            
              0
              -
            
          
        
        =
        
          
            (
            
              
                V
                bp
              
              -
              
                V
                bn
              
            
            )
          
          ⁢
          
            (
            
              1
              +
              
                
                  R
                  6
                
                
                  R
                  7
                
              
            
            )
          
          ⁢
          
            (
            
              
                C
                2
              
              
                
                  C
                  2
                
                +
                
                  C
                  par
                
              
            
            )
          
        
      
    
    
      
        (
        6
        )
      
    
  




Once the transition is complete (t>0+), the current flows only through the resistors, according to equation (4) above. Neglecting the offsets and imposing the equality between the change in DUT voltage according to equation (6) and the difference between the two “steady” DUT levels according to equation (4), Equation (7a) represents the transition from low(n) to high (p) and Equation (7b) represents the transition from high (p) to low (n):




  
    
      
        
          
            
              
                V
                p
              
              -
              
                V
                n
              
            
            
              KR
              net
            
          
          ⁢
          
            R
            DUT
          
        
        =
        
          
            (
            
              
                V
                bp
              
              -
              
                V
                bn
              
            
            )
          
          ⁢
          
            (
            
              1
              +
              
                
                  R
                  6
                
                
                  R
                  7
                
              
            
            )
          
          ⁢
          
            (
            
              
                C
                2
              
              
                
                  C
                  2
                
                +
                
                  C
                  par
                
              
            
            )
          
        
      
    
    
      
        (
        
          7
          ⁢
          a
        
        )
      
    
  
  
    
      
        
          
            
              
                V
                n
              
              -
              
                V
                p
              
            
            
              KR
              net
            
          
          ⁢
          
            R
            DUT
          
        
        =
        
          
            (
            
              
                V
                bn
              
              -
              
                V
                bp
              
            
            )
          
          ⁢
          
            (
            
              1
              +
              
                
                  R
                  6
                
                
                  R
                  7
                
              
            
            )
          
          ⁢
          
            (
            
              
                C
                2
              
              
                
                  C
                  2
                
                +
                
                  C
                  par
                
              
            
            )
          
        
      
    
    
      
        (
        
          7
          ⁢
          b
        
        )
      
    
  




Equations (7a) and (7b) are similar to the basic (passive) balanced attenuator condition, where the transition is dominated by charge distribution via capacitive coupling, while the “steady state” is determined by the current flowing through RDUT from the current source. The values of K, R6, R7, and C2 are optimized for the best circuit performance in terms of maximum speed, minimum noise, and best stability. An embodiment of a combined circuit 300 (current source 100 and booster 200) is shown in FIG. 4.
FIG. 5 is a flow chart of a method 500 of providing a pulsed current to a device under test (DUT). In Step 510, a plurality of different voltage levels is provided by DACs to a plurality of input terminals of a multiplexer in pulsed current test circuit. In Step 520, voltage pulses are generated from a selected voltage level by using input select combination of input select lines of the multiplexer to determine which of the input terminals of the multiplexer is connected to an output of the multiplexer. The input select combination of the multiplexer is performed in a way that any transitional address value for the multiplexer leads to a monotonic change of the output of the multiplexer, and voltage pulses are the output of the multiplexer. The voltage pulses are then converted to current pulses using a plurality of resistors, operational amplifiers, and capacitors in Step 530. The method 500 can further include Steps 540 and 550. In Step 540, a charge booster circuit connected to the pulsed current test circuit is used to minimize overshoots and undershoots during transitions between current levels. The charge booster circuit is driven by a combination of two DACs, which provide a plurality of different voltage levels to a plurality of input terminals of a multiplexer in the charge booster circuit, which further includes an operational amplifier, a plurality of resistors, and a capacitor. The signal to the inverting input of the operation amplifier of the pulsed current test circuit and the input signal to the non-inverting input of the operational amplifier in the charge booster circuit are synchronized but their voltage levels are independent because both multiplexers are fed from the same input select lines, but the two pairs of DACs (one pair in the pulsed current test circuit and the other pair in the charge booster circuit) are independent. In Step 550, a charge stored in the capacitor is allowed to stabilize such that current flows only through resistors.
A real-time computer can be used to control the circuitry described herein. According to an embodiment, the first step is setting the current source to DC levels Ip, and In, by setting DACp to Vp and DACn to Vn, and fixing the input select terminals of the analog multiplexers M1 and M2 accordingly—all while the booster switch is open (i.e. disconnecting the booster from the DUT). The resulting DC voltage levels (VDUT driven by Vp and Vn) are then acquired from their respective peak detectors and stored for reference (hereunder “Vpdc” and “Vndc”). Next, DACbp is set to a sufficiently lower level than required and DACbn is set to a sufficiently higher level than required, assuring undershoots rather than overshoots. S1 is then engaged and the input select terminals of M1 and M2 are activated with the required waveform. Following that, the peak detectors readings are acquired (Vpp, Vnn) and compared with Vpdc and Vpdc, respectively. In the likely case of |Vpp<|Vpdc| and |Vnn<|Vndc|, more boosting is needed. Increasing the boosting action is attained by varying Vbp and Vbn until the resulting peak detectors readings just exceed Vpdc and Vndc, respectively. At this point the boosting action is decreased incrementally and the process is repeated in a converging manner to the point where any further change has a negligible effect. For sufficiently long pulses VDUT will gradually “converge” to the proper levels Vpdc and Vndc, even without boosting; however, as the related time constant is longer than short pulses (typically for pulse width <500 nS), such “convergence” provides little help and efficient boosting is therefore necessary. Note that the actual algorithm used for the above iterations (i.e. increasing and decreasing boosting action) is not related to the invention, as it is a matter of efficient convergence. In reality, various algorithms such as binary search (when applicable) are effective, but the invention is not limited to one particular algorithm or another.
Although only a few embodiments have been described in detail, it should be appreciated that the invention may be implemented in many other forms without departing from the scope of the invention. In view of all of the foregoing, it should be apparent that the present embodiments are illustrative and not restrictive and the invention is not limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

## Claims

1. A test circuit for applying current pulses to a device under test (DUT), the test circuit comprising:
a first multiplexer that outputs analog voltage pulses, the first multiplexer being capable of outputting both bipolar and unipolar voltage pulses; and
at least one operational amplifier and resistor that receive the voltage pulses from the first multiplexer and convert the voltage pulses to current pulses, wherein an operational amplifier outputs current pulses, wherein the current pulses are bipolar or unipolar current pulses depending on whether the at least one operational amplifier and resistor receive bipolar or unipolar voltage pulses,
wherein the first multiplexer has one less input select line than voltage levels provided to its input terminals,
wherein the first multiplexer has three voltage levels provided to four input terminals, and
wherein an intermediate voltage level is selected with a transitional address for an input select combination of the first multiplexer, wherein the input select combination comprises address values assigned to the input select lines.

2. The test circuit of claim 1, further comprising a charge booster circuit for minimizing overshoots and undershoots during transitions between current levels, wherein the charge booster circuit comprises at least one operational amplifier and a plurality of resistors.

3. The test circuit of claim 2, wherein the charge booster circuit receives voltage pulses from a second multiplexer, wherein the voltage pulses from the second multiplexer are synchronized with but independent from the voltage pulses received from the first multiplexer and the charge booster circuit delivers its output to the DUT, wherein the DUT is positioned between ground and the output of the current pulses.

4. The test circuit of claim 3, wherein the first and second multiplexers have the same input select lines.

5. The test circuit of claim 1, wherein only one input select address line changes during a transition from highest voltage to intermediate voltage or from lowest voltage to intermediate voltage.

6. The test circuit of claim 1, wherein the multiplexer generates an analog signal from discrete voltages.

7. The test circuit of claim 1, wherein at least two operational amplifiers and five resistors receive the voltage pulses from the first multiplexer and convert the voltage pulses to current pulses.

8. A method of providing a pulsed current to a device under test (DUT), the method comprising:
providing a plurality of different voltage levels to a plurality of input terminals of a first multiplexer;
generating voltage pulses from a selected voltage level by using input select combination of input select lines of the first multiplexer to determine which of the input terminals of the first multiplexer is connected to an output of the first multiplexer, wherein input select combination of the first multiplexer is performed by assigning address values to input select lines of the first multiplexer in a way such that any transitional address value leads to a monotonic change of the output of the first multiplexer, wherein the output of the first multiplexer comprises voltage pulses; and
converting the voltage pulses to current pulses using a plurality of resistors, operational amplifiers, and capacitors.

9. The method of claim 8, wherein converting further comprises:
using a charge booster circuit to minimize overshoots and undershoots, the charge booster circuit comprising an operational amplifier, a plurality of resistors, and a capacitor.

10. The method of claim 9, wherein using the charge booster circuit comprises providing a second multiplexer that receives a plurality of voltage levels independent from the voltage levels provided to the first multiplexer.

11. The method of claim 10, wherein using the charge booster circuit further comprises allowing a charge stored in the capacitor to stabilize such that current flows only through resistors.

12. A single circuit capable of providing both unipolar and bipolar current pulses, the circuit comprising:
a multiplexer that receives at least one positive voltage signal and at least one negative voltage signal, wherein the multiplexer is capable of outputting both bipolar and unipolar voltage pulses from the voltage signals it receives; and
at least one operational amplifier and resistor that receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses, wherein an operational amplifier outputs bipolar or unipolar current pulses depending on whether the at least one operational amplifier and resistor receive bipolar or unipolar voltage pulses,
wherein the first multiplexer has one less input select line than voltage levels provided to its input terminals,
wherein the first multiplexer has three voltage levels provided to four input terminals, and
wherein an intermediate voltage level is selected with a transitional address for an input select combination of the first multiplexer, wherein the input select combination comprises address values assigned to the input select lines.

13. The circuit of claim 12, wherein at least two operational amplifiers and five resistors that receive the voltage pulses from the multiplexer and convert the voltage pulses to current pulses.

14. A test circuit for applying current pulses to a device under test (DUT), the test circuit comprising:
a first multiplexer that outputs analog voltage pulses, the first multiplexer being capable of outputting both bipolar and unipolar voltage pulses;
at least one operational amplifier and resistor that receive the voltage pulses from the first multiplexer and convert the voltage pulses to current pulses, wherein an operational amplifier outputs current pulses, wherein the current pulses are bipolar or unipolar current pulses depending on whether the at least one operational amplifier and resistor receive bipolar or unipolar voltage pulses; and
a charge booster circuit for minimizing overshoots and undershoots during transitions between current levels, wherein the charge booster circuit comprises at least one operational amplifier, a plurality of resistors, and a capacitor,
wherein the first multiplexer has one less input select line than voltage levels provided to its input terminals,
wherein the first multiplexer has three voltage levels provided to four input terminals, and
wherein an intermediate voltage level is selected with a transitional address for an input combination of the first multiplexer, wherein the input select combination comprises address values assigned to the input select lines.

15. The test circuit of claim 14, wherein the charge booster circuit further comprises a second multiplexer receives a voltage signal and outputs voltage pulses, wherein the first and second multiplexers have the same input select lines.

16. The test circuit of claim 14, wherein the output of the charge booster circuit is delivered to the DUT.