# Patent

## Title
Method and apparatus for reformatting and retiming digital telecommunications data for reliable retransmission via USB

## Abstract

A method for retiming digital telecommunications data received by a digital logger from a plurality of T-carrier type telephone lines respectively having differing clock sources ensures efficient transmission of received digital audio data to a host computer via a Universal Serial Bus (“USB”) interface. Also the digital logger includes volatile memory for temporarily storing digital audio data received from the plurality of T-carrier type telephone lines for:

    
    
        1. ensuring that the host computer receives digital audio data correctly via the USB interface;
        2. buffering the digital audio data within the digital logger during interruptions in transmission of digital audio data from the digital logger via the USB interface; and
        3. reducing audible latency of speech communications.

## Background
CLAIM OF PROVISIONAL APPLICATION RIGHTS
This patent application claims the benefit of U.S. Provisional Patent Application No. 61/200,448 filed on Nov. 28, 2008. U.S. Provisional Patent Application No. 61/200,448 is hereby incorporated by reference as though fully set forth here.


COPYRIGHT NOTICE
A portion of the disclosure of this patent document contains material that is protected by copyright. The copyright owner hereby grants others a right to reproduce copies of the patent document or the patent disclosure exactly as it appears in the files of the United States Patent and Trademark Office, but otherwise reserves all rights whatsoever under copyright specifically including the right to produce derivative works.
COMPACT DISK APPENDIX
Appendix I hereto, comprising a pair of identical compact disks (“CD-Rs”), is hereby incorporated by reference. The accompanying pair of identical compact disks have the following characteristics.










Machine Format: IBM-PC


Operating System Compatibility: Microsoft Windows XP









Creation Date
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txc_tepro_m13_config_api.c


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TXC_06830_SDRV_SC_ed_2_0\src\mboxpal









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\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\


TXC_06830_SDRV_SC_ed_2_0\txc









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CLSID_USB8T1.CPP


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ChannelLevelAdapter.cpp


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CommonDefinitions.h


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InterfaceDefinition.h


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InterfaceIncludes.h


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REDEBUG.BAT


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RERELEAS.BAT


08/16/2007 09:46 PM
137
SearchInterfaceMacros.h


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1,439
Server.cpp


08/16/2007 09:46 PM
264
USB8T1.DEF


08/24/2007 09:42 AM
7,706
USB8T1.cpp


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6,579
USB8T1.dsp


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1,175
USB8T1.dsw


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2,060
USB8T1.h


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7,249
USB8T1.plg


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USB8T1Config.cpp


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USB8T1Config.h


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176
attantion.txt


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126
usb8T1_version.h







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\


USB8T1_framework_v12









05/26/2006 12:31 AM
22,325
adi_m29w64d.c


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adi_m29w64d.h


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84
dummy.c


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140,378
linker_log.xml


11/26/2008 02:58 AM
1,209
main.dpg


11/26/2008 02:58 AM
11,087
main.dpj


09/06/2007 01:01 AM
34,082
main.ldf


10/12/2007 04:19 PM
4,969
main.mak


10/12/2007 04:20 PM
1,004,005
main.map.xml


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main_basiccrt.s


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2,121
main_heaptab.c







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\


USB8T1_framework_v12\Common









10/12/2007 01:07 PM
5,584
CoreaDLM.c


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2,155
CorebDLM.c


09/03/2007 11:57 PM
1,368
DynFramework.h


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7,100
LoadFlat.c


08/23/2005 10:25 AM
2,622
LoadFlat.h


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1,190
MakeDataStream.c


08/11/2007 03:53 PM
5,803
SendDataStream.c


08/04/2007 06:41 PM
911
UART_Trace.c


08/11/2007 10:03 AM
1,391
UART_Trace.h


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302
export.h


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20,652
ezkitutilities.c


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2,027
ezkitutilities.h


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865
l2_variables.h


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30,432
m29w64d.c


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669
sdram_variables.h







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\


USB8T1_framework_v12\DLM









11/26/2008 02:58 AM
10,455
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1,448
DLM.ldf


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DLM.mak


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596
DynFramework.c







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\


USB8T1_framework_v12\coreA









11/26/2008 02:58 AM
5,581
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coreA.mak


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loopback.c


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11,397
main_A.c







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\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\


USB8T1_framework_v12\coreB









11/26/2008 02:58 AM
6,045
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coreB.mak


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651
coreB_buffer_structure.h


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4,089
main_B.c







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\


USB8T1_framework_v12\sml2









08/14/2007 08:35 PM
836
sml2.c


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sml2.dpj


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sml2.mak







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\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\


USB8T1_framework_v12\sml3









09/05/2007 12:52 AM
757
sml3.c


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sml3.dpj


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sml3.mak







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\DeviceAdapters\USB8T1AudioLogger\common









08/24/2007 11:06 AM
16,253
USB8T1DriverAdapter.cpp


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USB8T1DriverAdapter.h


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USB8T1DriverAdapterSM.cpp


05/26/2006 12:31 AM
715
adiguid.h


08/20/2007 01:06 AM
441
usb8t1_frame_structure.h


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6,025
usbcmd.h







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\ThreadLib\proj









02/16/2005 05:08 AM
5,323
ThreadLib.dsp


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ThreadLib.dsw


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ThreadLibDll.dsp


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ThreadLibDll_NET.dsp


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ThreadLibDll_NET.vcproj


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ThreadLibDll_NET.vcproj.ACER-KIDUYS8U77.brom.user


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ThreadLibDll_NET.vcproj.HOME1.Brom.user


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ThreadLibExe_NET.vcproj







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\Loggerapp_service_and_8T1_code\com_2\ThreadLib\proj\include









02/16/2005 05:07 AM
600
CMcl.h


02/16/2005 05:07 AM
751
CMclAutoLock.h


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CMclCritSec.h


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CMclEvent.h


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CMclGlobal.h


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CMclKernel.h


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CMclLinkedLists.h


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CMclMailbox.h


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CMclMonitor.h


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CMclMutex.h


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CMclSemaphore.h


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CMclSharedMemory.h


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CMclThread.h


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CMclWaitableCollection.h


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CMclWaitableObject.h


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LockableQueue.h







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\Loggerapp_service_and_8T1_code\com_2\ThreadLib\proj\src









02/16/2005 05:08 AM
1,492
CMclAutoLock.cpp


02/16/2005 05:08 AM
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CMclAutoPtr.cpp


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CMclCritSec.cpp


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CMclEvent.cpp


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649
CMclGlobal.cpp


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CMclKernel.cpp


02/16/2005 05:08 AM
13,089
CMclMailbox.cpp


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CMclMonitor.cpp


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1,176
CMclMutex.cpp


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CMclSemaphore.cpp


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CMclSharedMemory.cpp


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2,789
CMclThread.cpp


02/16/2005 05:08 AM
2,453
CMclWaitableCollection.cpp


02/16/2005 05:08 AM
15,435
Mcl.mak







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\common









09/11/2008 11:30 PM
41,651
COMPortAdapter.cpp


08/23/2008 11:51 PM
5,414
COMPortAdapter.h


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4,061
ClassImplementation.h


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3,055
CommonClassImplementation.h


02/16/2005 04:43 AM
228
ConsoleDebugSchem.h


11/12/2008 03:22 PM
4,242
DLI_CSVSerializer.cpp


11/02/2008 12:09 PM
708
DLI_CSVSerializer.h


11/21/2008 03:23 PM
8,523
DLI_Header_Parameters.h


11/11/2008 02:25 AM
3,212
DLI_PGSerializer.cpp


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812
DLI_PGSerializer.h


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DLI_XMLSerializer.cpp


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767
DLI_XMLSerializer.h


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DTMFDialing_22050Hz8bit.cpp


02/16/2005 04:43 AM
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DTMFDialing_22050Hz8bit.h


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DTMFDialing_32000Hz8bit.cpp


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DTMFDialing_32000Hz8bit.h


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8,630
DeviceConfig.h


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8,671
DeviceConfig.old


02/16/2005 05:02 AM
2,649
ErrMsgApp.h


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2,572
ErrMsgApp.old


10/25/2008 12:19 AM
21,044
FTD2XX_Adapter.cpp


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2,170
FTD2XX_Adapter.h


12/17/2007 06:56 PM
1,865
FTD2XX_Stub.h


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3,731
Fifo.cpp


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576
Fifo.h


07/07/2008 06:36 PM
1,346
GlobalEventsOops.cpp


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307
GlobalEventsOops.h


03/15/2008 10:35 AM
21,408
HS_enum.cpp


11/26/2007 09:14 PM
206
HS_enum.h


02/16/2005 04:43 AM
493
IAdapter.h


04/23/2008 09:17 PM
4,682
IFTD2XX.H


02/16/2005 04:43 AM
283
IPhoneLineStateAdapter.h


09/30/2006 10:16 AM
8,258
LocalDebugSchem.h


02/16/2005 04:43 AM
2,548
LocalDebugSchem.old


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LocalDebugSchem.old1


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LogMacrosDefinition.h


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LogMessageTypes.h


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1,632
LoggerParameterRequests.h


02/16/2005 04:43 AM
851
MemoryImage.h


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4,009
Message.h


12/22/2007 04:59 PM
2,651
Message.old


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992
MutexLocker.cpp


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1,245
MutexLocker.h


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207
ObjectDefinition.h


11/05/2007 01:47 PM
15,133
PcmDriver.cpp


10/18/2007 11:51 PM
9,385
PcmDriver.cpp.old


11/05/2007 01:22 PM
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PcmDriver.h


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1,574
PcmDriver.h.old


06/07/2005 09:19 PM
8,014
PhoneLineStateAdapter.cpp


02/16/2005 04:44 AM
2,246
PhoneLineStateAdapter.h


03/11/2007 09:13 PM
976
PostMessageRedefinition.h


02/16/2005 04:44 AM
83
RecurciveException.cpp


02/16/2005 04:44 AM
2,138
RecurciveException.h


11/08/2005 01:54 PM
576
SchedulerNotificator.h


09/30/2006 09:49 AM
9,051
SimpleDebugSchem.h


02/16/2005 04:44 AM
21,658
USBDescriptors.h


01/24/2006 10:45 PM
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UlawLib.cpp


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252
UlawLib.h


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VUMeterConfigFromINI.cpp


01/29/2006 11:21 PM
556
VUMeterConfigFromINI.h


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909
WaveHeader_22050Hz8bit.h


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909
WaveHeader_32000Hz8bit.h


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2,027
WinDebugSchem.cpp


10/01/2007 11:07 PM
9,056
WinDebugSchem.h


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522
base_au_header.h


02/22/2008 09:05 PM
226
base_dimensions.h


03/11/2007 07:56 PM
6,555
common.h


03/11/2007 12:57 PM
1,311
fmteventlog.h


11/01/2008 11:21 AM
8,077
loggerMacros.h


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565
loggerappconst.h


02/13/2007 03:55 PM
1,809
loggerapptypes.h


10/24/2007 11:40 PM
26,645
usbid.cpp


02/16/2005 04:44 AM
228
usbid.h


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303
version.h


02/16/2005 04:44 AM
1,306
virtual_common_variable_length_object.h


02/16/2005 04:44 AM
542
wavehdrs.h







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\common\GUI









05/04/2000 05:44 PM
9,016
GCColorEdit.cpp


08/04/2005 08:34 PM
7,143
GCColorEdit.h


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51,987
GCMultiFieldEdit.cpp


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50,143
GCMultiFieldEdit.h


11/01/2005 09:23 AM
12,047
GCTimeCtrl.cpp


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GCTimeCtrl.h


08/16/2005 05:00 PM
3,652
GCWeek.cpp


08/13/2005 08:45 AM
1,664
GCWeek.h


08/24/2005 11:44 AM
9,955
LinkedClass.hpp


07/14/2008 01:16 PM
17,551
TaskBarApplet.cpp


07/14/2008 11:54 AM
6,036
TaskBarApplet.hpp


07/06/2008 10:02 PM
2,073
TaskBarAppletMain.hpp







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\common\XML









03/19/2005 12:22 AM
279
FmtLogEventInterface.h


11/09/2005 04:19 PM
423
NonFmtLogEventInterface.h


02/16/2005 04:44 AM
352
ParametersTypes.h


06/09/2008 03:33 PM
2,147
XMLLibrary.cpp


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430
XMLLibrary.h


06/09/2008 03:33 PM
1,876
XMLMacroses.h


06/09/2008 03:22 PM
8,661
XMLSerializer.h







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\common\mixapp









02/16/2005 04:43 AM
10,032
appport.h


02/16/2005 04:43 AM
5,945
debug.cpp


02/16/2005 04:43 AM
2,067
debug.h


02/16/2005 04:43 AM
26,266
mactrls.cpp


02/16/2005 04:43 AM
808
macustom.cpp


02/16/2005 04:43 AM
25,283
mafader.cpp


02/16/2005 04:43 AM
39,134
mainit.cpp


02/16/2005 04:43 AM
2,755
makefile


02/16/2005 04:43 AM
16,733
malines.cpp


02/16/2005 04:43 AM
22,874
malist.cpp


02/16/2005 04:43 AM
20,274
mameter.cpp


02/16/2005 04:43 AM
808
manumber.cpp


02/16/2005 04:43 AM
808
maslider.cpp


02/16/2005 04:43 AM
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maswitch.cpp


02/16/2005 04:44 AM
806
matime.cpp


02/16/2005 04:44 AM
32,606
mixapp.cpp


02/16/2005 04:44 AM
3,910
mixapp.dsp


02/16/2005 04:44 AM
535
mixapp.dsw


02/16/2005 04:44 AM
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mixapp.h


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51,261
mixapp.map


02/16/2005 04:44 AM
5,318
mixapp.plg


02/16/2005 04:44 AM
7,136
mixapp.rc


02/16/2005 04:44 AM
680
mixapp.rcv


02/16/2005 04:44 AM
4,489
muldiv32.h


02/16/2005 04:44 AM
29
readme.txt


02/16/2005 04:44 AM
17,393
tlb.cpp


02/16/2005 04:44 AM
2,905
tlb.h







List of files for directory


\Loggerapp_service_and_8T1_code\com_2\loggerApp









04/09/2006 06:35 PM
825
AuFileInfo.h


06/10/2008 01:41 PM
8,568
CSVSerializer.h


04/15/2006 07:45 PM
894
CallAnalysisConfig.cpp


04/10/2008 05:59 PM
428
CallAnalysisConfig.h


04/15/2006 07:48 PM
1,976
CallAnalysisConfigManager.cpp


04/15/2006 07:47 PM
1,061
CallAnalysisConfigManager.h


10/29/2008 10:44 PM
25,283
CallAnalysisTask.cpp


12/12/2007 11:45 PM
1,653
CallAnalysisTask.h


10/30/2008 12:34 AM
2,196
CallInfo.h


09/03/2008 09:19 PM
23,226
ChannelManager.cpp


09/03/2008 09:18 PM
4,656
ChannelManager.h


02/16/2005 05:02 AM
183
ChannelModes.ol1


02/16/2005 05:02 AM
174
ChannelModes.old


09/16/2008 04:52 PM
14,815
Channels.cpp


09/12/2008 11:07 AM
2,896
Channels.h


02/26/2006 08:16 PM
3,073
CommonCallAnalysisConfig.cpp


02/26/2006 08:16 PM
504
CommonCallAnalysisConfig.h


10/29/2008 06:48 PM
17,341
CommonDeviceAdapter.cpp


10/29/2008 07:52 PM
5,757
CommonDeviceAdapter.h


11/11/2008 01:32 AM
4,033
CommonLoggerConfig.cpp


02/22/2008 11:47 PM
2,830
CommonLoggerConfig.h


05/04/2006 01:27 AM
428
ConfigMacros.h


10/29/2008 08:01 PM
39,201
DLI20_LogFileManager.cpp


07/15/2008 11:50 PM
4,699
DLI20_LogFileManager.h


06/19/2008 10:09 AM
11,065
DLI20_XMLLogFileManager.cpp


06/18/2008 03:27 PM
766
DLI20_XMLLogFileManager.h


06/20/2008 02:34 AM
1,733
DTMF.txt


09/12/2008 10:27 AM
1,980
DeviceControlMacros.h


07/28/2008 02:33 PM
12,596
DeviceManager.cpp


07/28/2008 02:13 PM
3,695
DeviceManager.h


09/13/2008 11:31 AM
7,391
DeviceManagerControl.cpp


10/29/2008 07:38 PM
11,526
DeviceManagerInformation.cpp


02/16/2005 05:02 AM
1,956
ErrMsgApp.mc


01/06/2006 03:44 PM
0
Fifo.cpp


06/25/2006 05:34 PM
740
FileManagerConfig.h


09/12/2008 10:10 AM
2,562
IDeviceManagerControl.h


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7,211
IDeviceManagerInformation.h


07/26/2005 10:23 AM
627
ILoggerControl.h


02/27/2007 11:30 PM
1,109
ILoggerInformation.h


06/06/2008 12:11 PM
883
IXMLSerializer.h


11/07/2008 02:14 PM
7,432
IniFile.cpp


09/16/2006 10:35 PM
5,963
IniFile.cpp.old


09/11/2008 04:53 PM
1,719
IniFile.h


04/09/2008 07:32 PM
20,380
LogFileManager.cpp


04/10/2008 05:59 PM
2,370
LogFileManager.h


11/16/2008 01:15 AM
13,017
Logger24.cpp


11/01/2008 10:35 AM
3,119
Logger24.h


03/11/2007 10:37 PM
1,240
LoggerControlMacros.h


01/02/2008 10:23 PM
734
LoggerInformationMacros.h


03/11/2007 05:45 PM
614
LoggerTasks.h


02/16/2005 05:02 AM
331
LoggerappExtLog.h


11/21/2008 03:07 PM
2,177
PGDatabaseGreateMacroces.h


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2,070
PGDatabaseRecordMacroces.h


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1,523
PGDatabaseTableMacroces.h


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287
PGDatabaseUndefMacroces.h


10/31/2008 10:41 PM
4
PGSerializer.cpp


11/19/2008 03:40 PM
6,552
PGSerializer.h


10/03/2008 10:08 PM
11,185
Purge.cpp


07/07/2008 01:55 PM
4,540
Purge.h


10/03/2008 08:44 PM
14,495
PurgeChannel.cpp


03/23/2007 09:33 AM
2,917
PurgeChannel.h


07/07/2008 02:40 PM
9,065
PurgeDrive.cpp


05/19/2007 12:31 PM
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PurgeDrive.h


05/18/2007 10:03 PM
11,099
PurgeTask.cpp


03/19/2007 03:31 AM
2,084
PurgeTask.h


03/11/2007 10:01 PM
1,503
ReflectionMacroses.h


11/11/2008 01:30 AM
858
SystemConfig.h


03/11/2007 10:52 AM
3,939
SystemTask.cpp


03/22/2005 03:27 PM
603
SystemTask.h


06/21/2008 01:08 AM
2,277
Task.cpp


03/11/2007 05:45 PM
1,895
Task.h


11/21/2006 06:40 PM
4,127
TemplateDialog.cpp


03/25/2005 06:33 PM
1,046
TemplateDialog.h


03/27/2005 01:47 AM
1,424
UserMessageDialog.cpp


04/08/2005 03:54 PM
467
UserMessageDialog.h


04/18/2006 07:51 PM
2,714
UserTask.cpp


04/08/2005 03:54 PM
472
UserTask.h


04/28/2008 10:52 AM
33,546
VuWindow.cpp


07/13/2006 02:16 AM
3,315
VuWindow.h


04/28/2008 10:53 AM
16,606
VuWindowTask.cpp


01/09/2006 01:53 PM
572
VuWindowTask.h


11/07/2008 12:59 PM
30,138
WorkerTask.cpp


07/27/2008 08:52 PM
3,045
WorkerTask.h


06/06/2008 11:11 AM
614
XMLSerializerMacros.h


04/18/2006 07:49 PM
6,208
XmlLogTask.cpp


01/09/2006 09:50 AM
2,885
XmlLogTask.h


10/11/2005 10:47 AM
11,470
common.cpp


10/29/2008 07:59 PM
4,875
deviceinformationmacros.h


01/08/2008 12:16 AM
2,015,840
dtmf_input.txt


02/16/2005 05:02 AM
309
log.xml


03/27/2008 06:42 PM
145
logger_app_version.h


03/05/2006 01:27 AM
179
loggerapp.bbs


11/09/2008 02:21 PM
18,826
loggerapp.dsp


02/16/2005 05:02 AM
1,131
loggerapp.dsw


01/03/2008 05:20 PM
6,889
main.cpp


02/16/2005 05:03 AM
410
resource.h







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\Loggerapp_service_and_8T1_code\com_2\utilLib\proj









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\Loggerapp_service_and_8T1_code\com_2\utilLib\proj\include









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\Loggerapp_service_and_8T1_code\pgsql\include









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\Loggerapp_service_and_8T1_code\pgsql\include\server









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BACKGROUND
1. Technical Field
The present invention relates generally to recording digital telecommunication data, and more particularly to systems for reliably recording high performance digital voice telecommunication data.
2. Background Art
Problems exist in communications between personal computers (“PCs”) and higher performance legacy telecommunications devices. Reliably communicating with digital telecommunications interfaces such as multiple T1/E1 lines and DS3/OC3 interfaces requires an error-free method of transferring data between the telecom line and a host PC. High density multi-channel telecommunications data is often transmitted using different clock speeds for different channels. Multiple channels of telecom audio with disparate clock frequencies are particularly difficult to group, packetize, synchronize and transmit over an interface that is prone to transmission errors.
Current implementations of Peripheral Component Interconnect (“PCI”) bus telecommunication interface cards use the PCI, PCI-X, and PCI-Express bus interfaces. These comparatively expensive bus interfaces offer error free reliable bidirectional transmission.
Alternatively, the Universal Serial Bus (“USB”) interface offers a fast, flexible, and efficient method of connecting external peripheral devices to a PC. The main advantages of USB connected devices are ease of use and “hot plug” ability. Despite recent attempts to improve reliability and performance of USB host controllers and target devices, in actual field conditions data transmission errors occur due to the nature of the USB hot plug interface. Data integrity cannot be fully guaranteed using conventional USB transfer methods.
DEFINITIONS


    
    
        T-CARRIER A generic name for any of several digital, multiplexed telecommunications carrier systems originally developed by Bell Laboratories that are used in North America, Japan, and Korea.
        DS0 Digital Signal 0, the basic unit of the T-carrier system, has a transmission rate of 64 kbit/s, and is commonly used for one voice-frequency-equivalent telecommunication channel. The DS0 channel forms the basis for a multiplexed digital telephonic transmission hierarchy both for the early plesiochronous systems such as T-carrier, and for modern synchronous systems such as SDH/SONET. Each DS0 channel may support twenty 2.4 kbit/s channels, ten 4.8 kbit/s channels, five 9.67 kbit/s channels, one 56 kbit/s channel, or one 64 kbit/s clear channel. For carrying a typical phone call, audio sound is digitized at an 8 kbit/s sample rate using 8-bit pulse-code modulation, usually u-law, which occupies the 64 kbit/s data rate of one DS0 clear channel. Multiple DS0 channels are multiplexed together to form higher capacity telecommunication circuits.
        DS1 Digital Signal 1 is a T-carrier telecommunications signaling standard for carrying multiple DS0 channels each of which may carry voice and/or data transmissions between a network and a user. The DS1 signaling scheme is a widely used in North American, Japanese and South Korean telecommunications to transmit voice and data between devices. Technically, DS1 is the logical bit pattern transmitted over a physical T1 line, and, strictly speaking, DS1 is the data signal carried on a T1 circuit. However, the terms “DS1” and “T1” are often used interchangeably. A DS1 signal consists of twenty-four 8-bit channels (also identified as timeslots or DS0 channels), each channel carrying 64 kbit/s. A DS1 signal operates as a full-duplex circuit, which means the circuit concurrently transmits and receives 1.544 Mbit/s. A 1.536 Mbit/s bandwidth is achieved by sampling each of the twenty-four 8-bit DS0 channels 8000 times per second. An additional 8 kbit/s of overhead results from adding framing bits to the twenty-four 8-bit channels for a total bandwidth of 1.544 Mbit/s. Frame synchronization is necessary to identify the timeslots within each 24-channel frame. Synchronization takes place by allocating a framing, or 193rd, bit. This results in 8 kbit/s of framing data, for each DS1. Because this 8-kbit/s channel framing data overhead is used only by the transmitting equipment. A DS1 signal provides a user with only a 1.536 Mbit/s data rate.
        T1 A physical copper wire telephone line called a T1 span which provides the first, lowest data rate of multiplexed T-carrier telecommunications. Outside of central offices “COs,” a T1 span consists of conditioned cable pairs. A T1 span generally requires signal repeaters every 6000 feet, depending on cable gauge, with no more than 36 dB of loss before requiring a repeater. Presently, T1 copper spans are being replaced by optical communication systems. However, if a copper (metallic) span is used for a T1 span, it is provided by a HDSL encoded copper line. When a T-carrier communication system carries a DS0 channel, “robbed bit signaling” means that the transmitted DS0 channel is not guaranteed to be an error-free bit-stream. Voice equipment typically coerces the “robbed bits” for signaling to a state that will result in the far end properly handling errors, while applying an often different state to the customer equipment connected to the alarmed equipment.
        E1 A European E-carrier standard, analogous to T1, that form part of the Plesiochronous Digital Hierarchy (PDH). An E1 link operates over two separate sets of wires, usually a twisted pair cable. The link's data rate is 2.048 Mbit/s (full duplex, i.e. 2.048 Mbit/s downstream and 2.048 Mbit/s upstream) which is split into 32 timeslots, each timeslot being allocated 8 bits, i.e. a single DS0 channel, in turn. Unlike the earlier T-carrier systems developed in North America, all 8 bits in each timeslot are available for each telephone call. This allows the E1 systems to be used equally well for circuit switch data calls, without risking the loss of any information. One of the 32 timeslots, i.e. timeslot (TS0), is reserved for framing purposes, and alternately transmits a fixed pattern. This allows the receiver to lock onto the start of each frame and match up each channel in turn. To detect if the circuit is losing bits (information), the E1 standard allows for a full Cyclic Redundancy Check to be performed across all bits transmitted in each frame. One timeslot (TS16) is often reserved for signalling purposes, to control call setup and teardown in accordance with one of several standard telecommunications protocols.
        PRI Primary Rate Interface (“PRI”) Integrated Services Digital Network (“ISDN”) is a telecommunications signaling standard for carrying multiple DS0 voice and/or data transmissions between a network and a user. All data and voice channels are ISDN and operate at 64 kbit/s. For PRI ISDN, North American and Japanese telephone systems use a T1 system of 23 B channels each of which carries one DS0 signal, and one D channel which carries control and signaling information. Europe, Australia and most of the rest of the world use the slightly higher capacity E1 system, which is composed of 30 B channels, one synchronization channel and one D channel.
        DS3 Digital Signal 3 is another T-carrier telecommunications signaling standard for carrying multiple DS0 voice and/or data transmissions between a network and a user. Generally, DS3 is used for transmitting multiplexed digital telecom data between COs. A DS3 channel, which operates at 44.736 Mbps, carries 28 DS1 channels, i.e. 672 DS0 channels (672 individual telephone calls), multiplexed into one single faster communications channel. Strictly speaking, a DS3 channel is the data carried on a T3 circuit, but in practice the terms are used interchangeably. Because each source of T1 data multiplexed into the DS3 channel has its own clock rate, each T1 channel carried on a DS3 channel may have a slightly different clock rate. For example, a difference of 50 parts (samples) per million in clock frequency may be found in the field. This clock rate difference means that 50/1,000,000 drift can occur between DS0 channel sampling rates found within signals carried on a single DS3 channel. For example, 0.005%*1.544 Mbps equals 77 bytes of drift per second. 77 bytes/24 channels equals up to 3.2 samples (bytes) timing difference among DS0 channels. DS3 channels are rare except within buildings where they are used for interconnections and as an intermediate step before being multiplexed onto a SONET circuit. A customer who orders a DS3 channel usually has a SONET circuit entering its building with a multiplexer mounted in a utility box.
        T3 A physical copper wire telephone line which carries DS3 signaling of multiplexed T-carrier telecommunications. T3 telephone lines is mostly used between telephone carriers, both wired and wireless. A T3 circuit has two coax cables (1 coax cable for sending and 1 coax cable for receiving) having BNC connectors on both ends. The coax cables must be made with true 75 ohm cable and connectors. Bellcore standard GR-139-CORE defines type 734 and 735 cables for a T3 circuit. Due to losses, each type of cable has differing distance limitations. 734 cable has a larger center conductor and insulator than the 735 cables, and therefore exhibits lower losses for a given distance. A T3 circuit can extend only about 600 feet (180 m) between repeaters.
        EAST/WEST Telephone data transmission is split into inbound and outbound streams (east and west directions) and combined only upon arrival near a telephone.
        CONTROL Data indicating various different telephone set conditions such as on-hook, off-hook, Caller-ID, number dialed, routing information for the call, etc.
        
            As described above, DS1 signaling is framed to provide 24 logical 64 Kbps DS0 channels. Each DS0 channel is designed to carry a single digitized telephone call. A T1 line provides 24×64 Kbps in usable bandwidth. This equates to 1.536 Mbps. The total bandwidth of a T1 line is actually 1.544 Mbps, which includes 8 Kbps in overhead.
            Framing of DS1 signaling is necessary to provide a common data format and to provide a means for synchronizing the network. Two (2) common framing standards currently in use.
            D4 framing is the principal framing method that was initially used with T1 networks. D4 framing is also known as SF format and as D3/D4 format framing. The D4 frame does not include a dedicated timeslot for the transfer of channel signaling. When end-to-end transfer of signaling is necessary, a technique called “robbed-bit signaling” is used. The “robbed bit” is the least significant bit (bit 8) of the channel byte, and is actually “robbed” only once in every six frames.
            A D4 frame consists of 24 one byte samples from each of the 24 DS0s (192 bits). A single framing bit is sent in front of every 192 bit structure ([24×8]+1=193 bits per frame).
            The D4 format provides limited supervision capabilities such as end-to-end reporting of local loss-of-signal (yellow alarm).
            The F-bit pattern defines the structure of frames and multiframes. In D4 framing, the F-bit of consecutive frames is alternately interpreted as an Ft bit (terminal framing bit) or Fs bit (frame signaling bit).
            
                Ft pattern: alternating 0's and 1's, defines the frame boundaries.
                Fs pattern: fixed 001110 pattern, defines the multiframe boundaries, so that one frame may be distinguished from another. In particular, the Fs pattern is needed so that frames 6 and 12 may be identified to enable recovery of signaling bits.
            
            
            In the ESF frame format, the multiframe structure is extended to 24 frames, but the frame and channel structure are the same as in D4 framing. The ESF format provides improved supervision capabilities, and allows better utilization of the 8 kbps framing timeslots. The major advantage of the ESF format is that it supports on-line link performance monitoring (by means of a 2 kbps Cyclic Redundancy Check (CRC) channel) and in addition provides a 4 kbps end-to-end supervision and control data link. As described above, the PRI ISDN telecommunications signaling standard includes a D channel which carries control and signaling information. When carried on a T1 line, as described above PRI ISDN has 23 B channels each of which carries one DS0 signal, and the D control and signaling information channel.
        
        
        FIFO First in, first out circular buffer for telecommunications data.
        HOT PLUG Removal or insertion of an attached USB device while the power is applied to the controlling PC and the PC is operating.
    
    


U.S. Pat. No. 6,021,129 entitled “System and Method for Communicating Information from a Communications Link to a Host Using a Universal Serial Bus” that issued Feb. 1, 2000, on a patent application filed by Kimberly I. Martin, Kenneth A. Lauffenburger, Klaus S. Fosmark and William A. Perry, Jr. (“the Kimberly, et al. patent”) discloses a modem for communicating information from a communications link to a host PC via the USB. The modem includes a memory for storing a plurality of network protocol Asynchronous Transfer Mode (“ATM”) small fixed-sized digital data cells. ATM is a cell relay, packet switching protocol which provides data link layer services that run over Layer 1 links. This differs from other technologies based on packet-switched networks (such as the Internet Protocol or Ethernet) which employ variable sized packets (known as frames when referencing Layer 2). ATM data cells transport real-time video and audio as well as image files, text and email. The disclosed modem includes a receive manager that receives a plurality of ATM cells from the communications link and stores the ATM cells in the modem's memory. The receive manager formats the ATM cells into USB packets, and transmits each USB packet to a host PC as soon as the packet is full. The modem further includes a short packet instigator which determine if an ATM cell contains a termination condition associated with the content of the ATM cell. It an ATM cell contains a termination condition, short packet instigator transmits a short USB packet which carries less data than its capacity. Queuing delay in transmitting ATM cells and jitter in cell arrival render ATM unsuitable for voice telephonic communication. In addition to disclosing a modem that is unsuitable for voice telephonic communication, USB communication with the ATM modem disclosed in the Kimberly, et al. patent lacks any error correction capability.
U.S. Pat. No. 6,675,250 entitled “Fault Tolerant Communications Using a Universal Serial Bus” that issued Jan. 6, 2004, on a patent application filed by John Ditner and Marc Morin (“the Ditner, et al. patent”) discloses a USB system for communication between two (2) or more USB hosts. The disclosed USB system provides a USB tree between each USB host and at least one USB function. The system further permits isolating a specified USB host from the at least one USB function. The Ditner, et al. patent discloses adding fault tolerance to USB devices by disconnecting failing USB hosts.
Published United States Patent Application no. 2006/0034230 entitled “Telecommunication Device” that was published Feb. 16, 2006, for a patent application filed in the names of Thomas Wellhausen and Ivo Gadow (“the Wellhausen published patent application”) discloses a communication device that provides connections for a speech data transfer and digital data transfer between digital telecommunications terminals, analog telecommunications terminals and data processing appliances via Digital Subscriber Line (“DSL”). DSL is a family of technologies that provides digital data transmission over the wires of a local telephone network. DSL can be used at the same time and on the same telephone line with conventional telecommunications, i.e. plain old telephone service (“POTS”), because DSL uses frequency bands that are higher than the frequency band required for POTS telecommunication. xDSL is a general expression for high-speed DSL service in which x is replaced, for example, by A for an Asynchronous DSL transmission technique (“ADSL”), by S for a Synchronous DSL transmission technique (“SDSL”), by V for Very High Speed Digital Subscriber Line (“VDSL”), etc. The Wellhausen published patent application's disclosed xDSL terminal adapter autonomously sets up and clears connections in a public telecommunications network as well as on the Internet. The disclosed xDSL terminal adapter includes:

    
    
        1. an xDSL modem that connects to an xDSL data line or to a broadband connection;
        2. an ISDN signal converter connected to the xDSL modem and having at least one S0 connection for ISDN terminals; and
        3. an analog signal converter connected to the xDSL modem and having at least one a/b connection for analog terminals.

The xDSL terminal adapter includes a local area network (“LAN”) port which is connected to a local area network, and a USB port which connects to the xDSL modem through a USB signal converter. A personal computer may be connected to the Internet by xDSL and through the USB and/or LAN interface provided in the xDSL terminal adapter. The LAN port's or the USB port's connection to the personal computer permits configuring the xDSL terminal adapter. The xDSL's terminal's single channel S0 connection lacks error correction and is prone to audio interruption whenever a USB error occurs.

    
    


U.S. Pat. No. 6,978,412 entitled “Method And Apparatus For Adaptive Frame Tracking” that issued Dec. 20, 2005, on a patent application filed by Daniel B. Reents and Patrick Maupin (“the Reents, et al. patent”) discloses a method for adaptively tracking and compensating for USB frame errors at the USB wire line level using a time stamp synchronizer. USB system communication sends and receives packets of data to and from computer peripherals and computer systems. The Reents, et al. patent discloses that packets of data, particularly isochronous frames of data, transmitted via a USB often lose synchronous flow thereby causing transmission errors. The Reents, et al. patent discloses an adaptive frame tracking unit capable of:

    
    
        1. receiving and sending at least one data packet;
        2. automatically adjusting data packet data rate by determining if at least one data frame error occurs; and
        3. correcting for the data frame error upon determining that there exists at least one the data frame error.

The method disclosed in the Reents, et al. patent reduces small errors in USB bus packet transmission, but does not disclose transferring packets of data having embedded parity, and cannot transfer data having a clock rate that differs from USB clock rate.

    
    


Similar to the Reents, et al. patent, U.S. Pat. No. 6,658,499 entitled “System and Method for ADSL USB Bandwidth Negotiation” that issued Dec. 2, 2003, on a patent application filed in the names of Robert A. Day, Kamran Khederzadeh and Kamal Patel (“the Day, et al. patent”) discloses a system and method for ADSL USB bandwidth negotiation. The system comprises a modem that is configured to transfer data between an ADSL line and a USB bus. The modem is further configured to:

    
    
        1. receive an ADSL line rate setting;
        2. submit an isochronous bandwidth request to a computer;
        3. reduce the isochronous bandwidth request in response to the availability of isochronous bandwidth;
        4. modify the ADSL line rate setting in response to the availability of isochronous bandwidth; and
        5. modify the USB bus transfer mode in response to the availability of isochronous bandwidth.
    
    


In view of the preceding summaries of various, a need presently exists for error free communications of multi-channel telecommunications data having differing clock rates via the hot-pluggable but error prone fixed clock rate USB interface.
BRIEF SUMMARY
An object is receiving DS0 digital audio data from two or more T-carrier lines and reliably transmitting the received digital audio data to a computer via a USB interface.
Another object is receiving DS0 digital audio data from two or more T-carrier lines and efficiently transmitting the received digital audio data to a computer via a USB interface.
Briefly, among other concepts disclosed herein is a method for retiming digital telecommunications data received by a digital logger from a plurality of T-carrier type telephone lines respectively having differing clock sources. The method for retiming includes the steps of:

    
    
        1. extracting a single frame of digital audio data from each incoming T-carrier DS0 channel received by the digital logger;
        2. analyzing clock rates of digital audio data streams for all incoming T-carrier DS0 channels;
        3. without affecting T-carrier signaling data, increasing digital audio data of T-carrier DS0 channels determined to have a slow clock rate by appropriately adding a byte of digital audio data to digital audio data carried by such T-carrier DS0 channels;
        4. without affecting T-carrier signaling data, decreasing digital audio data of T-carrier DS0 channels determined to have a fast clock rate by appropriately removing a byte of digital audio data from digital audio data carried by such T-carrier DS0 channels; and
        5. after processing digital audio data for all received T-carrier DS0 channels, repackaging all frames of received digital audio data into a single T-carrier super-frame.
    
    


Another aspect disclosed herein is a digital logger for:

    
    
        1. receiving digital telecommunications data that includes digital audio data from a plurality of T-carrier type telephone lines; and
        2. retransmitting received digital audio data via a Universal Serial Bus (“USB”) interface.

The disclosed digital logger includes volatile memory for temporarily storing digital audio data received from the plurality of T-carrier type telephone lines for buffering the digital audio data within the digital logger during interruptions in transmission of digital audio data from the digital logger via the USB interface. Another aspect of the digital logger's volatile memory is temporarily storing digital audio data received from the plurality of T-carrier type telephone lines. In temporarily storing digital audio data to reduce audible latency of speech communications:

        1. an amount of volatile memory used for temporarily storing digital audio data received from the plurality of T-carrier type telephone lines is resized automatically; and
        2. clock rate is dynamically shifted slightly.
    
    


These and other features, objects and advantages will be understood or apparent to those of ordinary skill in the art from the following detailed description of the preferred embodiment as illustrated in the various drawing figures.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram depicting a 8-channel digital logger in accordance with the present disclosure adapted for exchanging digitized voice telephone data with eight T-carrier lines, and for also exchanging that digital telephone data with a host computer via the host computer's USB port;
FIG. 2 is a block diagram depicting in greater detail a clock generator circuit illustrated in FIG. 1; and
FIG. 3 is a schematic diagram depicting one (1) of eight (8) isolation circuits included in the 8-channel digital logger illustrated in FIG.



DETAILED DESCRIPTION
The block diagram of FIG. 1 depicts an 8-channel digital logger indicated by the general reference number 20. The 8-channel digital logger 20 is preferably assembled on two (2) separate printed circuit boards. A T1 interface board 22 of the 8-channel digital logger 20, enclosed within a dashed line in FIG. 1, receives and transmits bidirectional digitized voice and signaling telephonic communications via a 16 port RJ45 connector 24. The 16 port RJ45 connector 24 connects the T1 interface board 22 to eight (8) bidirectional T-carrier type telephone lines. The 8-channel digital logger 20 also includes a digital signal processor (“DSP”) board 26, also enclosed within a dashed line in FIG. 1. The DSP board 26 exchanges digitized voice data and telephonic signaling for digital telephonic communications with a host PC, not illustrated in any of the FIGs., via a USB-B connector 28 that connects by a USB cable, also not illustrated in any of the FIGs., to the host PC's USB-A connector.
Within the DSP board 26, the USB-B connector 28 connects to a USB controller 32 that is included in a digital signal processor IC 34. The digital signal processor 34 is preferably an ADSP-BF548 Blackfin Embedded Processor sold by Analog Devices of Norwood, Mass.
Two (2) buses, a host bus 42 and a H.100 bus 44, interconnect the digital signal processor 34 of the 8-channel digital logger 20 with a Channelized DS3 Access Device 52 included in the T1 interface board 22. The Channelized DS3 Access Device 52 is preferably a TEProTM Channelized DS3 Access Device TXC-06830 sold by TranSwitch Corporation of Shelton, Conn. For digital audio data received via the 16 port RJ45 connector 24, the Channelized DS3 Access Device 52 retimes the data to a clock signal generated within the 8-channel digital logger 20.
A computer program executed by the digital signal processor 34 communicates with the Channelized DS3 Access Device 52 via the host bus 42 to control operation of the Channelized DS3 Access Device 52. The Channelized DS3 Access Device 52 and the digital signal processor 34 exchange digital voice data via the H.100 bus 44. Signal lines included in the H.100 bus 44 interconnecting the Channelized DS3 Access Device 52 and the digital signal processor 34 carry:

    
    
        1. framing data that identifies that particular DSO of twenty-four (24) DSOs carried on a T1 line whose data is presently being transferred via the H.100 bus 44;
        2. a clock signal for the data transfer; and
        3. the digital voice data.

Operating the 8-channel digital logger 20 for acquiring digital voice data causes most digital voice data transmissions via the digital signal processor 34 to go from the Channelized DS3 Access Device 52 to the digital signal processor 34. However, to provide warning messages and other instructions, the digital signal processor 34 can transmit digital voice data to the Channelized DS3 Access Device 52 via the H.100 bus 44.

    
    


As understood by those skilled in the art and as described above, the signal on a T1 line of a T-carrier type telephone line travels over conditioned cable pairs known as a T1 span. One pair of each T1 span carries incoming digital voice data while the other pair carries outgoing digital voice data. As described above, this voice data transmission convention, sometimes referred to as East/West, splits each of the 24 telephone calls carried on a T1 line into inbound and outbound streams (East and West directions) that are combined only upon arrival near a telephone. To comply with this convention, the T1 interface board 22 includes two (2) eight channel line interface ICs 56 disposed between the Channelized DS3 Access Device 52 and the 16 port RJ45 connector 24. Each line interface IC 56 is preferably an IDT82V2088 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit sold by Integrated Device Technology, Inc. of Santa Clara, Calif.
Though not separately depicted in FIG. 1, to avoid requiring a separate electrical termination for the T1 line at the 8-channel digital logger 20, the 8-channel digital logger 20 includes eight (8) isolation circuits, one for each T1 span, that are located between the 16 port RJ45 connector 24 and the line interface IC 56. One of these isolation circuits is illustrated in FIG. 3 and described in greater detail below.
In addition to the Channelized DS3 Access Device 52 and the two (2) line interface ICs 56, the T1 interface board 22 includes an (“EEPROM”) 58 that is coupled to the Channelized DS3 Access Device 52, and which stores a computer program that is loaded into and executed by the Channelized DS3 Access Device 52. Lastly the T1 interface board 22 includes a clock generator circuit that, as depicted in greater detail in FIG. 2, includes a 32 MHz crystal oscillator 62, a phase locked loop (“PLL”) 62 and a complex programmable logic device (“CPLD”) 66.
Considering again the DSP board 26 illustrated in FIG. 1, the 8-channel digital logger 20 preferably includes a liquid crystal display (“LCD”) 72 that is coupled to one (1) of four (4) serial ports 74 included in the preferred digital signal processor 34. The DSP board 26 also permits connecting a secure data card (“SDC”) 76 to a SDIP interface 78 of the digital signal processor 34. A JTAG emulator 82 included in the digital signal processor 34 facilitates debugging a computer program executed by the digital signal processor 34.
A non-volatile 32 MByte flash memory 92 included in the DSP board 26 is coupled to the digital signal processor 34 and supplies a computer program executed by the digital signal processor 34. The digital signal processor 34 uses a 64 MByte double data rate synchronous dynamic random access memory (“DDR SDRAM”) memory 96 for program storage and for temporarily storing digital voice data either between its reception from the Channelized DS3 Access Device 52 and transmission to the USB-B connector 28, or conversely. If the digital voice data exceeds the capacity of the 64 MByte DDR SDRAM memory 96, the digital signal processor 34 stores additional digital voice data in a SDC 76 connected to the SDIP interface 78. Storing digital voice data in the SDC 76 is particularly useful if the host PC becomes unavailable perhaps because it must be rebooted, or if software executed by the host PC is being upgraded. When the host PC resumes normal operation, the computer program executed by the digital signal processor 34 transfers received and stored digital audio data from the 64 MByte DDR SDRAM memory 96 and the SDC 76 to the host PC via the DSP board 26.
FIG. 3 depicts the isolation circuit for a single T-carrier line, specifically for a T1 span. As stated previously, the 8-channel digital logger 20 includes eight (8) isolation circuits of the type illustrated in FIG. 3. For receiving an inbound digital telecommunication signal, each isolation circuit of the 8-channel digital logger 20 includes an inbound transformer 102 having a primary winding 104 that connects via the 16 port RJ45 connector 24 to the inbound (East) line of a T1 span. A secondary winding 106 of the inbound transformer 102 connects via lines 112 and 114 to input terminals of the line interface IC 56. A resistor 118, preferably having a resistance of 220 ohms (“Ω”), connects across the lines 112 and 114. Cathodes of a first pair of protection diodes 122 and 124 connect respectively to one of the lines 112 and 114 while anodes of the protection diodes 122 and 124 connect in parallel to circuit ground 126. Anodes of a second pair of protection diodes 132 and 134 connect respectively to one of the lines 112 and 114 while cathodes of the protection diodes 132 and 134 connect in parallel to a positive supply voltage 136, preferably +3.3 volts (“V”) direct current (“DC”).
In addition to the inbound transformer 102, each isolation circuit also preferably includes an outbound transformer 142 having a primary winding 144. The primary winding 144 connects via lines 152 and 154 respectively to terminals of resistors 156a and 156b that preferably have a resistance of 9.1Ω. Other terminals of the resistors 156a and 156b connect to output terminals of the line interface IC 56. A capacitor 158, preferably having a capacitance of 560 pico Farads (“pF”), connects in parallel with the primary winding 144 between terminals of the resistors 156a and 156b. A secondary winding 162 of the outbound transformer 142 connects via the 16 port RJ45 connector 24 to the outbound (West) line of a T1 span for transmitting a digital telecommunication signal from the 8-channel digital logger 20.
Data Reformatting and Retiming
The following data reformatting and retiming method provides reliable retransmission to a host PC via a conventional USB connection and protocols for received multi-channel digital telecommunications data that has been previously multiplexed onto a T1 and/or T3 span of a T-carrier type telephone line. The method provides error free transmission over the unreliable conventional USB connection while retaining the ability to hot-plug USB devices.
The basic data transfer process is described below as encoding and handshaking. For clarity, the description below explains the transfer in a single direction, i.e. from the 16 port RJ45 connector 24 to the USB-B connector 28. The process is simply reversed to move data in the opposite direction, i.e. from the USB-B connector 28 to the 16 port RJ45 connector 24.
Data Encoding and Transfer Process
(16 Port RJ45 Connector 24 to USB-B Connector 28, as Viewed from the Digital Signal Processor 34)

    
    
        1. Sample a single frame of digital audio data from each DS0 channel of a T1 line, i.e. from each DSO. The frame size should be as small as possible to reduce latency, i.e. 64-256 bytes.
        2. Analyze clock rate of all incoming DSO DS0 channels. This is accomplished by first unpacking each DS0 stream and then analyzing the minimum and maximum data rate of every DS0 contained within every T1 line, E1 line, or PRI included in every DS3. For a T1 line, all DSO channels will typically operate at the same clock rate. Determine the minimum and maximum real-time clock rates.
        3. Interpolate audio data in the digital signal processor 34, adding a byte where necessary to the DS0 data for channels with slow clock rates without affecting the signaling information. The position of embedded D4 framing in DS1 signaling is mapped around and avoided.
        4. Where extra bytes exists in a DS0, removing only audio, not signaling information. If necessary, add a byte of digital audio data to the DS0 data, leaving the signaling streams unchanged. Adding and removing only audio bytes is important to preserve the data integrity of the voice communication. To do this, the digital signal processor 34 must parse every stream to determine where the signaling bytes (or bits) are located.
        5. To enhance audio quality, the digital signal processor 34 does not add bytes which are simply a duplicate of the previous byte in that stream (as done in conventional telecommunications products). The digital signal processor 34 instead interpolates the audio waveform and inserts a byte at a level between the previous and subsequent audio samples. Adding interpolated bytes to digital voice data provides slight a improvement in audio quality.
        6. Once add and slip (insert and remove) processing is completed, the computer program executed by the digital signal processor 34 repackages all frames into a single superframe.
        7. Then the computer program executed by the digital signal processor 34 generates a CRC code for the superframe, and attaches a packet identifier to the superframe.
        8. The digital signal processor 34 then sends the identifier, superframe, and CRC to the host PC via the USB-B connector 28 and waits for acknowledgement. While waiting for an acknowledgement from the host PC, the digital signal processor 34 continues buffering digital telecom data through the USB handshaking process.
        9. If the PC acknowledges receipt of a valid superframe with CRC, the digital signal processor 34 then proceeds to process the next frame of digital voice data.
        
            If the host PC does not acknowledge receipt of a valid superframe with CRC, hold the superframe which was not successfully transmitted in a circular RAM FIFO buffer. Check the threshold limit (#1 below), and continue the encoding process (#1 above).

T-Carrier Control Information

        
        
    
    


As known to those skilled in the art, DS1, DS3 and PRI signaling includes control information. However, as described above control information varies in format depending on the type of signaling format carried on a T1 line, i.e. DS1 or DS3 signaling format which uses D4 framing for control information or PRI ISDN signaling format that includes a separate “D channel” for control information. Operation of the Channelized DS3 Access Device 52 extracts control information bits from the telecommunication signals received by the 8-channel digital logger 20. As described previously, for DS1 or DS3 signaling that uses D4 framing, the control information bits are buried in the audio, i.e. “robbed bit signaling. As also described previously, PRI ISDN signaling transmits control information on a separate “D channel.”
Note that DS3 signaling may carry a mix of different T-carrier signaling formats, i.e. a number of DS1 channels that use D4 framing for control information combined with a number of PRI ISDN channels that use the “D channel” for control information. Retiming of every DS0 channel received by the 8-channel digital logger 20 to a single clock signal within the digital signal processor 34 permits the 8-channel digital logger 20 to operate successfully in this complex signaling environment. For example, retiming of DS0 channels within the digital signal processor 34 permits the 8-channel digital logger 20 to operate successfully with perhaps five (5) T1 lines connected to the 16 port RJ45 connector 24 together with three (3) PRI ISDN lines connected to the 16 port RJ45 connector 24.
Note that the computer program executed by the digital signal processor 34 transmits digital audio data to the PC host via the USB controller 32 and the USB-B connector 28 for only those received DS0 channels that are “off hook” as indicated by control information extracted by the Channelized DS3 Access Device 52 from signals on the various T-carrier lines connected to the 16 port RJ45 connector 24. Transmitting from the 8-channel digital logger 20 to the host PC only digital audio data for DS0 channels that are “off hook” saves USB bandwidth while concurrently reducing the load on the host PC. Saving USB bandwidth improves USB performance and increases USB data transmission reliability. Note that USB “DMA transfers” adversely affect host PC performance even if data transferred via the USB is discarded and never used by computer program(s) executed by the host PC. Consequently, transmitting from the 8-channel digital logger 20 to the host PC only digital audio data for DS0 channels that are “off hook” permits transferring many more channels of digital audio data without overburdening the host PC.
Method for Handling USB Data Transfer Interruptions


    
    
        1. When digital voice data stored in the 64 MByte DDR SDRAM memory 96 exceeds a pre-established threshold, the computer program executed by the digital signal processor 34 begins initializing a FIFO in non-volatile 32 MByte flash memory 92 to support buffering throughout long interruptions in USB communications with the host PC (such as a machine reboot or operating system update).
        2. As the FIFO in the 64 MByte DDR SDRAM memory 96 approaches the memory's capacity, the computer program executed by the digital signal processor 34 begins storing untransmitted superframes sequentially into a second FIFO located in the SDC 76. A sequential serial number is attached to each superframe stored into this second FIFO.
        3. After the 8-channel digital logger 20 re-establishes a USB connection to the host PC as evidenced by successful USB enumeration, the computer program executed by the digital signal processor 34 begins emptying the digitized audio data first from the SDC 76 transferring packets to the host PC at the maximum available USB data rate.

Handshaking Process Viewed from the Host PC

        1. Receive initialization including serial number and type of attached device upon initial USB connection and enumeration. Open a pipe with appropriate communications driver matching the attached device.
        2. Wait for arrival of a superframe of data from the USB-B connector 28.
        3. Assign USB endpoints for the received data.
        4. Receive the superframe of digital voice data, check serial number of superframe and check the CRC to assess whether the received data is correct.
        5. If the is CRC correct, then send a message confirming receipt of good superframe to the digital signal processor 34 via USB. Record the superframe of digital voice data in local PC buffer and unpack.
        
            if the CRC is incorrect, send an error report to digital signal processor 34 requesting that the digital signal processor 34 resend the missing data.
        
        
        6. Check serial number of received superframe. Send matching superframe from the host PC to the 8-channel digital logger 20, i.e. in the opposite direction, to maintain East-West audio time synchronization.
        7. Return to #2 above

In the case of larger blocks of errors which activate the non-volatile memory buffer in the 8-channel digital logger 20, a timeout will cause the system to reconnect using #1 above. The digital signal processor 34 and the host PC will then transfer digital voice data swiftly until emptying the FIFO in the SDC 76.

    
    


For data sent from the PC to a T1 line via the 8-channel digital logger 20, the preceding processes operate in reverse, with the host PC buffering the digital voice data being transferred to the digital signal processor 34. The digital signal processor 34 then becomes responsible for synchronizing the East data streams to West clock during digital voice data transmission via the Channelized DS3 Access Device 52.
Note that the USB transfer rate is set more than double the aggregate data rate of the incoming telecommunications data. That is, a 480 Mbs USB transmission rate will typically support a telecommunications data rate via the 16 port RJ45 connector 24 of slightly more than 200 Mbs aggregate.
Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is purely illustrative and is not to be interpreted as limiting. For example, although the preferred embodiment of the 8-channel digital logger 20 uses the digital signal processor 34, it is readily apparent to those skilled in the art that the 8-channel digital logger 20 disclosed herein could alternatively be implemented using a complex instruction set computer (“CISC”) or a reduced instruction set computer (“RISC”) processor. Similarly, the USB controller 32 may be included in the digital signal processor 34, or the USB controller 32 may be implemented as a separate IC. Consequently, without departing from the spirit and scope of the disclosure, various alterations, modifications, and/or alternative applications will, no doubt, be suggested to those skilled in the art after having read the preceding disclosure. Accordingly, it is intended that the following claims be interpreted as encompassing all alterations, modifications, or alternative applications as fall within the true spirit and scope of the disclosure including equivalents thereof. In effecting the preceding intent, the following claims shall:

    
    
        1. not invoke paragraph 6 of 35 U.S.C. §112 as it exists on the date of filing hereof unless the phrase “means for” appears expressly in the claim's text;
        2. omit all elements, steps, or functions not expressly appearing therein unless the element, step or function is expressly described as “essential” or “critical;”
        3. not be limited by any other aspect of the present disclosure which does not appear explicitly in the claim's text unless the element, step or function is expressly described as “essential” or “critical;” and
        4. when including the transition word “comprises” or “comprising” or any variation thereof, encompass a non-exclusive inclusion, such that a claim which encompasses a process, method, article, or apparatus that comprises a list of steps or elements includes not only those steps or elements but may include other steps or elements not expressly or inherently included in the claim's text.

## Claims

1. A digital logger for:
a. receiving digital telecommunications data that includes digital audio data from at least one T-carrier type telephone line; and
b. retransmitting received digital audio data via a USB interface,

the digital logger comprising volatile memory for temporarily storing digital audio data received from the at least one T-carrier type telephone line wherein to reduce the audible latency of speech communications:
a. an amount of volatile memory used for temporarily storing digital audio data received from the at least one T-carrier type telephone line is resized and emptied automatically; and
b. clock rate is dynamically shifted slightly before transmitting digital audio data from the digital logger via the USB interface.