# Patent

## Title
Fill-in etching free pore device

## Abstract

A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

## Background
PARTIES TO A JOINT RESEARCH AGREEMENT
International Business Machines Corporation, a New York corporation, Macronix International Corporation, Ltd., a Taiwan corporation, and Infineon Technologies A.G., a German corporation, are parties to a Joint Research Agreement.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high density memory devices based on memory materials, for example phase change memory (PCM) devices, and to methods for manufacturing such devices. The memory material is switchable between electrical property states by the application of energy. The memory materials may be phase change based memory materials, including chalcogenide based materials, and other materials.
2. Description of Related Art
Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.
Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state; this difference in resistance can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.
The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and by reducing the size of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.
One direction of development has been toward using small quantities of programmable resistive material, particularly in small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.
In phase change memory, data is stored by causing transitions in the phase change material between amorphous and crystalline states using current. Current heats the material and causes transitions between the states. The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the active phase change material element in the cell. One problem associated with phase change memory devices arises because the magnitude of the current required for reset operations depends on the volume of phase change material that must change phase. Thus, cells made using standard integrated circuit manufacturing processes have been limited by the minimum feature size of manufacturing equipment. Thus, techniques to provide sublithographic dimensions for the memory cells must be developed, which can lack uniformity or reliability needed for large scale, high density memory devices.
One approach to controlling the size of the active area in a phase change cell is to devise very small electrodes for delivering current to a body of phase change material. This small electrode structure induces phase change in the phase change material in a small area like the head of a mushroom, at the location of the contact. See, U.S. Pat. No. 6,429,064, issued Aug. 6, 2002, to Wicker, “Reduced Contact Areas of Sidewall Conductor;” U.S. Pat. No. 6,462,353, issued Oct. 8, 2002, to Gilgen, “Method for Fabricating a Small Area of Contact Between Electrodes;” U.S. Pat. No. 6,501,111, issued Dec. 31, 2002, to Lowrey, “Three-Dimensional (3D) Programmable Device;” U.S. Pat. No. 6,563,156, issued Jul. 1, 2003, to Harshfield, “Memory Elements and Methods for Making Same.”
Accordingly, an opportunity arises to devise methods and structures that form memory cells with structures that have small active regions of programmable resistive material using reliable and repeatable manufacturing techniques.
BRIEF SUMMARY OF THE INVENTION
A first example of a memory cell includes a bottom electrode layer comprising a bottom electrode and a memory cell layer over the bottom electrode layer. The memory cell layer includes a first dielectric layer over the bottom electrode layer and a second dielectric layer over the first dielectric layer. The memory cell layer also includes a top electrode over the second dielectric layer, the top electrode being spaced apart from the bottom electrode. The dielectric layers define a via, the via having a first part bounded by the first dielectric layer and the bottom electrode and a second apart bounded by the second dielectric layer and the top electrode. The first part is substantially smaller than and is generally centered on the second part. A memory element is within the via and comprises a memory material switchable between electrical property states by the application of energy. The memory element is in electrical contact with the top electrode and with the bottom electrode. In some embodiments the first part of the via comprises a constricted region and the second part of the via comprises an enlarged region, the constricted region causing energy passing through the memory element to be concentrated in the constricted region. In some embodiments the constricted region may have a width which is smaller than the minimum feature size of the process used to form the enlarged region of the via.
A second example of a memory device comprises an array of memory elements having bottom surfaces, and an array of bottom electrodes having top surfaces in contact with the bottom surfaces of respective memory elements. Top electrodes are in contact with the memory elements in the array of memory elements. A separation layer is between an insulating layer and the bottom electrode. The insulating layer is between the separation layer and the top electrode. The memory elements comprise first and second memory element portions within the separation layer and the insulating layer, respectively. In some embodiments the first and second memory element portions are self-aligned. In some embodiments the top surfaces of the bottom electrodes have top surface areas substantially larger than bottom surface areas of the bottom surfaces of the respective memory elements.
A method for manufacturing an array of memory cells as described herein includes forming an array of bottom electrodes, forming a separation layer on the array of bottom electrodes, an isolation layer on the separation layer, and a sacrificial layer on the separation layer. The method includes forming an array of openings overlying the array of bottom electrodes and extending into the separation layer. Etch masks are formed within the array of openings and etching is performed through the separation layer using the etch masks, thereby exposing upper surfaces of the corresponding bottom electrodes. The etch masks are then removed to define an array of vias within the separation layer, the vias having constricted parts extending to the upper surfaces of the corresponding bottom electrodes, and having enlarged parts on the constricted parts. Memory elements are then formed within the vias, the memory elements having first memory element portions within the constricted parts and having second memory element portions within the enlarged parts, the memory elements comprising a memory material. Top electrodes are then formed on the memory elements.
A memory cell as described herein results in an active region within the constricted part of the via that can be made extremely small, thereby reducing the amount of current needed for reset. The constricted part of the via has a width that is preferably less than a minimum feature size for a process, typically a lithographic process, used to form the memory cell. The small constricted part concentrates current in the portion of the memory element adjacent the bottom electrode, thereby reducing the magnitude of the current needed to induce a phase change in the active region.
Processes described herein result in variations in the constricted part of the via that are independent of, and controlled over a range much less than, the variation in the enlarged part of the via. This results in variations in the width of the first portion of the memory element that is smaller than the variations in the width of the second portion of the memory element. The small variation in the width of the first portion of the memory element improves uniformity of operation of an array of memory cells.
Other features, aspects and advantages of the present invention can be seen on review the figures, the detailed description, and the claims which follow.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an integrated circuit device in accordance with the present invention;
FIG. 2 is a partial schematic diagram of a representative memory array as shown in FIG. 1;
FIG. 3 is a simplified cross-sectional view of one example of a memory cell made according to the present invention;
FIGS. 4-12 illustrate stages in an example of the manufacture of the memory cell of FIG. 3.



DETAILED DESCRIPTION OF THE INVENTION
The following description of the invention will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals.
Referring to FIG. 1, shown is a simplified block diagram of an integrated circuit 10 in which the present invention may be implemented. Circuit 10 includes a memory array 12 implemented using phase change memory cells (not shown) on a semiconductor substrate, discussed more fully below. A word line decoder 14 is in electrical communication with a plurality of word lines 16. A bit line decoder 18 is in electrical communication with a plurality of bit lines 20 to read data from, and write data to, the phase change memory cells (not shown) in array 12. Addresses are supplied on bus 22 to word line decoder and drivers 14 and bit line decoder 18. Sense amplifiers and data-in structures in block 24 are coupled to bit line decoder 18 via data bus 26. Data is supplied via a data-in line 28 from input/output ports on integrated circuit 10, or from other data sources internal or external to integrated circuit 10, to data-in structures in block 24. Other circuitry 30 may be included on integrated circuit 10, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by array 12. Data is supplied via a data-out line 32 from the sense amplifiers in block 24 to input/output ports on integrated circuit 10, or to other data destinations internal or external to integrated circuit 10.
A controller 34 implemented in this example, using a bias arrangement state machine, controls the application of bias arrangement supply voltages 36, such as read, program, erase, erase verify and program verify voltages. Controller 34 may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, controller 34 comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of controller 34.
As shown in FIG. 2 each of the memory cells of array 12 includes an access transistor (or other access device such as a diode), four of which are shown as 38, 40, 42 and 44, and a phase change element, shown as 46, 48, 50 and 52. Sources of each of access transistors 38, 40, 42 and 44 are connected in common to a source line 54 that terminates in a source line termination 55. In another embodiment the source lines of the select devices are not electrically connected, but independently controllable. A plurality of word lines 16 including word lines 56 and 58 extend parallel along a first direction. Word lines 56 and 58 are in electrical communication with word line decoder 14. The gates of access transistors 38 and 42 are connected to a common word line, such as word line 56, and the gates of access transistors 40 and 44 are connected in common to word line 58. A plurality of bit lines 20 including bit lines 60 and 62 have one end of phase change elements 46 and 48 connected to bit line 60. Specifically, phase change element 46 is connected between the drain of access transistor 38 and bit line 60, and phase change element 48 is connected between the drain of access transistor 48 and bit line 60. Similarly, phase change element 50 is connected between the drain of access transistor 42 and bit line 62, and phase change element 52 is connected between the drain of access transistor 44 and bit line 62. It should be noted that four memory cells are shown for convenience of discussion and in practice array 12 may comprise thousands to millions of such memory cells. Also, other array structures may be used, e.g. the phase change memory element is connected to source.
FIG. 3 illustrates an example of a memory cell 64 made according to the invention. Memory cell 64 includes a bottom electrode layer 66 and a memory cell layer 68 on top of layer 66. Bottom electrode layer 66 has an upper surface 70 and includes a dielectric fill layer 72, typically made of silicon dioxide and bottom electrode 74, typically made of tungsten or titanium nitride, within fill layer 72 and extending to upper surface 70. The portion of bottom electrode 74 at upper surface 70 may be made of an electrically conductive material such as TiN, WN, TiAlN or TaN, to provide enhanced contact with a memory element 76 of memory cell layer 68. Memory element 76 includes a memory material switchable between electrical property states by the application of energy. The memory material is typically a phase change material such as GST, discussed in more detail below.
Memory cell layer 68 includes a first dielectric layer (a first separation layer) 78 on a surface 70, a second dielectric layer (a second separation layer) 80 on the first dielectric layer 78 with the first and second dielectric layers 78, 80 defining a via 82, see FIG. 10, containing memory element 76. Memory cell layer 68 also includes a top electrode 84. First dielectric layer 78 is of a different material than second dielectric layer 80 and acts as an etch stop layer, discussed in more detail below. In one example first dielectric layer 78 is silicon nitride while second dielectric layer 80 is silicon dioxide. Top electrode 84 is preferably of electrically conductive material, such as TiN, chosen to provide enhanced contact with a memory element 76 of memory cell layer 68; other appropriate materials for top electrode 84 include WN, TiAlN or TaN.
Via 82 includes a first, constricted part 86 centered with a second, enlarged part 88 with first, constricted part 86 being surrounded by dielectric layer 78. This results in an electrical property state change region 90 within first, constricted part 86. When memory element 76 comprises a phase change material, region 90 acts as a phase change transition region for memory element 76. The top surface of bottom electrode 74 has a surface area substantially larger than the bottom surface area of that portion of memory element 76 formed within first, constricted part 86 of via 82 that contacts bottom electrode 74.
FIGS. 4-12 illustrate steps in the manufacture of one example of memory cell device 64. As will be understood, the steps illustrated in FIGS. 4-12 can be used to form an array of memory cells 64 arranged along columns and rows, for example like the array illustrated in FIG. 2.
In FIG. 4 bottom electrode layer 66 is shown with four layers of material formed on its upper surface 70. In particular, a separation layer 79 is formed on the bottom electrode 74, the separation layer 79 comprising a first separation layer 78 and a second separation layer 80. An isolation layer 92 is formed on the separation layer 79 and a sacrificial layer 94 is formed on the isolation layer 92. In the illustrated embodiment the first separation layer 78 comprises silicon nitride, the second separation layer 80 comprises silicon dioxide, the isolation layer 92 comprises polysilicon or amorphous silicon, and the sacrificial layer comprises silicon nitride. Bottom electrode 74 extends through dielectric layer 72 to an appropriate isolation device, typically a transistor type or diode type isolation device.
In the illustrated embodiment of FIG. 4 the separation layer 79 comprises two layers. Alternatively the separation layer 79 comprises a single layer.
Next, an opening 98 is formed overlying the bottom electrode 74, the opening extending into the separation layer 79 to expose the first separation layer 78, resulting in the structure illustrated in FIG. 5. In the illustrated embodiment the opening is formed by an etching process and the first separation layer 78 acts as an etch stop layer. The width 99 of opening 98 is preferably equal to a minimum feature size for a process, typically a lithographic process, used to form the opening. For example the width 99 can be about 90-110 nm.
FIG. 6 illustrates a next stage in the process, in which the opening 98 is subjected to a selective undercutting etching process to remove part of the isolation layer 92 while leaving the sacrificial layer 94 and the separation layer 79 intact. In embodiments in which the isolation layer 92 comprises silicon, the selective etching may comprise applying dilute KOH to slowly remove the silicon. The selective etching process forms overhang portions 106 of the sacrificial layer 94 having an overhang dimension 107 which can be very well controlled, and is not significantly affected by variations in the width 99 of the opening 98. Thus, the overhang dimension 107 can be very uniform across an array of cells. After the selective etching, the opening 98 has an upper opening segment 102 within the sacrificial layer 94 and a lower opening segment 104 within the isolation layer 92, the lower opening segment 104 having a width 110 that is greater than the width 108 of the upper opening segment 102.
In an alternative process to that of FIG. 6, the sacrificial layer 94 comprises a material which can be selectively expanded to create the overhang.
Next, a conformal fill material 112 is formed on the structure illustrated in FIG. 6, resulting in the structure illustrated in FIG. 7 having a self aligned void 114 within the lower opening segment 104 of the opening 98. The fill material 112 is formed by a process that grows the material at a substantially equal rate on the walls of the upper and lower segments of the opening 98, resulting in the formation of a void 114 when the top of the opening 98 closes before the interior is filled. In the illustrated embodiment the fill material 112 comprises amorphous silicon and is formed using chemical vapor deposition CVD. Other materials chosen for their etch chemistry and the ability to grow conformal layers within high aspect ratio vias could also be used for the fill material 112. Also, other procedures, such as atomic layer deposition, physical layer deposition, low-pressure chemical vapor deposition (LPCVD) or high density plasma chemical vapor deposition (HDPCVD) could be used to deposit the fill material 112, depending on materials and geometries involved.
The deposition of fill material 112 creates the self-aligned void 114 centered within the lower opening segment 104 of opening 98. The void 114 has a width 116 with a variation among voids in an array which is significantly less than the variation in widths 108, 110 of the opening 98. This is because the deposition of fill material 112 into two different openings having different widths will result in more material being formed on the sidewall of the opening having the larger width. The width 116 of void 114 is thus primarily controlled by the overhang dimension 107 and by variations in the deposition rates within the lower and upper opening segments of opening 98, and is independent of the lithographic process used to form the openings 98.
Next, fill material 112 is etched using an anisotropic etching process to expose the first separation layer 78 and form etch mask 122 comprising the fill material 112, resulting in the structure illustrated in FIG. 8. The etch mask 122 has an opening dimension 120 that is substantially determined by the width 116 of the void 114.
Next, the first separation layer 78 is etched using the etch mask 122, thereby exposing the upper surface of the bottom electrode 74 and forming a constricted part 86 of a via within the first separation layer 78, resulting in the structure illustrated in FIG. 9. As can be seen in FIG. 9, the etching also removes the sacrificial layer 94. The constricted part 86 has a width 87 determined by the opening dimension 120 of the etch mask 122, and thus width 87 is determined by the width 114 of the void 116. As described above, the voids 114 in an array of memory cells have variations determined by the overhang 106 (See FIG. 6) while the width 99 in the second separation layer 80 in an array have variations in width determined by the process, typically by a lithographic process, used to form the openings 98. Thus, the openings within the first separation layer 78 vary among cells in an array by significantly less than the openings within the second separation layer 80. Thus, the subsequently formed memory element (See FIG. 11, reference number 76) will have a first portion within the first separation layer 78 having a variation in width among cells in an array which is significantly less than the variation in width of a second portion within the second separation layer 80. Specifically, for at least two cells in an array, the respective diameters of the first portions of the memory elements differ by less than the respective diameters of the second portions of the memory elements.
The etch mask 122 and the isolation layer 92 are then removed to form a via 82 within the separation layer 79, resulting in the structure illustrated in FIG. 10. The via 82 has a constricted part 86 within the first separation layer 78 and an enlarged part 88 within the second separation layer 80. In embodiments in which the isolation layer 92 and the etch mask 122 comprises silicon, etching may be performed using dilute KOH to remove the etch mask 122 and the isolation layer 92.
A memory material is deposited into via 82 and planarized for example by CMP, resulting in the structure illustrated in FIG. 11 having memory element 76. The memory element 76 has a first portion within the constricted part 86 of the via 82, and a second portion within the enlarged part 88 of the via 82.
Thereafter, top electrode 84 is formed on the memory element 76 and coupled to a bit line. Alternatively, the top electrode 84 may comprise a portion of a bit line.
One of the advantages associated with some examples of the invention is that first memory element portion within constricted part 86 can have a very small width and be formed within a very thin first separation layer 78. This results in the volume of memory material within constricted part 86 of via 82 being very small. The amount of energy needed to cause the desired phase change transitions is also reduced substantially. Another advantage is that via 82, and in particular constricted part 86, can be filled with phase change material to create memory element 76 without damage on the side wall of the phase change material as can occur when phase change material is etched to create sub lithographically sized, or other reduced sized, phase change regions.
Advantages accruing from the invention can be further appreciated by comparing it to conventional processes and devices. The memory material-containing vias of conventional memory cells typically vary in diameter by 5% percent across an array. Therefore, upon dividing an array into subregions, for example into 4 quadrants, and taking a representative cell from each quadrant, the diameter of the vias in the representative cells will vary by about 5%, or about 4.5 nm, for vias having a typical minimum lithographic size diameter of 90 nm. With the present invention, the average width or diameter 87 of constricted part 86, as well as the resulting pillar of phase change material within constricted part 86, is determined by overhanging 106 and the conformality of the deposition process used to form void 114. The conformality of the deposition process is characterized by a uniformity of deposition rate on the side walls defining opening 98, including overhanging portion 106; the deposition process also compensates for variations in the diameter of opening 98. For the process described, the diameter of constricted part 86 of via 82, typically about 40 nm, will typically also vary by the same 5%, so the variation can be no more than about 2 nm, much less than the 4.5 nm variation associated with conventional processes and devices.
Dielectric materials may comprise an electrical insulator including one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C. In preferred devices, the dielectric materials have a low thermal conductivity, less than about 0.014 J/cm*K*sec. In other preferred embodiments, when memory element 76 is made from a phase change material, the thermally insulating dielectric material of layer 78 may have a thermal conductivity less than that of the amorphous state of the phase change material, or less than about 0.003 J/cm*K*sec for a phase change material comprising GST. Representative thermally insulating materials include materials that are a combination of the elements silicon Si, carbon C, oxygen O, fluorine F, and hydrogen H. Examples of thermally insulating materials which are candidates for use for the thermally insulating dielectric material include SiO2, SiCOH, polyimide, polyamide, and fluorocarbon polymers. Other examples of materials which are candidates for use for the thermally insulating dielectric material include fluorinated SiO2, silsesquioxane, polyarylene ethers, parylene, fluoro-polymers, fluorinated amorphous carbon, diamond like carbon, porous silica, mesoporous silica, porous silsesquioxane, porous polyimide, and porous polyarylene ethers. In other embodiments, the thermally insulating structure comprises a gas-filled void for thermal insulation. A single layer or combination of layers within the dielectric materials can provide thermal and electrical insulation.
Useful characteristics of a programmable resistive type of memory material, like a phase change material, include the material having a resistance which is programmable, and preferably in a reversible manner, such as by having at least two solid phases that can be reversibly induced by electrical current. These at least two phases include an amorphous phase and a crystalline phase. However, in operation, the programmable resistive material may not be fully converted to either an amorphous or crystalline phase. Intermediate phases or mixtures of phases may have a detectable difference in material characteristics. The two solid phases should generally be bistable and have different electrical properties. The programmable resistive material may be a chalcogenide material. A chalcogenide material may include GST. In following sections of the disclosure, the phase change or other memory material is often referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory cell as described herein is Ge2Sb2Te5.
A memory cell 64 as described herein is readily manufacturable using standard lithography and thin film deposition technologies, without requiring extraordinary steps to form sub-lithographic patterns, while achieving very small dimensions for the region of the cell that actually changes resistivity during programming. In embodiments of the invention, the memory material may be a programmable resistive material, typically a phase change material, such as Ge2Sb2Te5 or other materials described below. The region 90 in memory cell 64 that changes phase is small; and accordingly, the magnitude of the reset current required for changing the phase is very small.
Embodiments of memory cell 64 include phase change based memory materials, including chalcogenide based materials and other materials, for memory element 76. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VIA of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IV of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b), where a and b represent atomic percentages that total 100% of the atoms of the constituent elements. One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. (Ovshinsky ‘112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7. (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v.3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky ‘112 at columns 11-13, which examples are hereby incorporated by reference.
Chalcogenides and other phase change materials are doped with impurities in some embodiments to modify conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides. Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium and titanium oxide. See, e.g. U.S. Pat. No. 6,800,504, and U.S. Patent Application Publication No. US 2005/0029502.
Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These phase change materials are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.
Phase change materials can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state, and is referred to as a reset pulse. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state, and is referred to as a program pulse. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined empirically, without undue experimentation, specifically adapted to a particular phase change material and device structure.
The following are short summaries describing four types of resistive memory materials.
1. Chalcogenide material

    
    
        GexSbyTez 
        x:y:z=2:2:5
        Or other compositions with x: 0 ̃5; y: 0 ̃5; z: 0 ̃10
        GeSbTe with doping, such as N—, Si—, Ti—, or other element doping may also be used.
        Formation method: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N2, and/or He, etc chalcogenide @ the pressure of 1 mtorr ̃100 mtorr. The deposition is usually done at room temperature. The collimator with aspect ratio of 1 ̃5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. On the other hand, the combination of DC bias and the collimator can be used simultaneously.
        The post deposition annealing treatment with vacuum or N2 ambient is sometimes needed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges 100 C to 400 C with an anneal time of less than 30 minutes.
        The thickness of chalcogenide material depends on the design of cell structure. In general, a chalcogenide material with thickness of higher than 8 nm can have a phase change characterization so that the material exhibits at least two stable resistance states.
    
    


2. CMR (colossal magneto resistance) material

    
    
        PrxCayMnO3 
        x:y=0.5:0.5
        Or other compositions with x: 0 ̃1; y: 0 ̃1
        Another CMR material that includes Mn oxide may be used
        Formation method: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N2, O2, and/or He, etc. at the pressure of 1 mtorr ̃100 mtorr. The deposition temperature can range from room temperature to  ̃600 C, depending on the post deposition treatment condition. A collimator with an aspect ratio of 1 ̃5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. On the other hand, the combination of DC bias and the collimator can be used simultaneously. A magnetic field of several ten gauss to 10,000 gauss may be applied to improve the magnetic crystallized phase.
        The post deposition annealing treatment with vacuum or N2 ambient or O2/N2 mixed ambient may be needed to improve the crystallized state of CMR material. The annealing temperature typically ranges 400 C to 600 C with an anneal time of less than 2 hours.
        The thickness of CMR material depends on the design of cell structure. The CMR thickness of 10 nm to 200 nm can be used to be the core material.
        A buffer layer of YBCO (YBaCuO3, a kind of high temperature superconductor material) is often used to improve the crystallized state of CMR material. The YBCO is deposited before the deposition of CMR material. The thickness of YBCO ranges 30 nm to 200 nm.
    
    


3. 2-element compound

    
    
        NixOy; TixOy; AlxOy; WxOy; ZnxOy; ZrxOy; CuxOy; etc
        x:y=0.5:0.5
        Other compositions with x: 0 ̃1; y: 0 ̃1
        Formation method:
        1. Deposition: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N2, O2, and/or He, etc. at the pressure of 1 mtorr ̃100 mtorr, using a target of metal oxide, such as NixOy; TixOy; AlxOy; WxOy; ZnxOy; ZrxOy; CuxOy; etc. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1 ̃5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. If desired, they combination of DC bias and the collimator can be used simultaneously.
        The post deposition annealing treatment with vacuum or N2 ambient or O2/N2 mixed ambient as sometimes needed to improve the oxygen distribution of metal oxide. The annealing temperature ranges 400 C to 600 C with an anneal time of less than 2 hours.
        2. Reactive deposition: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar/O2, Ar/N2/O2, pure O2, He/O2, He/N2/O2 etc. at the pressure of 1 mtorr ̃100 mtorr, using a target of metal oxide, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1 ̃5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several ten to several hundred volts is also used. If desired, the combination of DC bias and the collimator can be used simultaneously.
        The post deposition annealing treatment with vacuum or N2 ambient or O2/N2 mixed ambient is sometimes needed to improve the oxygen distribution of metal oxide. The annealing temperature ranges 400 C to 600 C with an anneal time of less than 2 hours.
        3. Oxidation: By a high temperature oxidation system, such as furnace or RTP system. The temperature ranges from 200 C to 700 C with pure O2 or N2/O2 mixed gas at a pressure of several mtorr to 1 atm. The time can range several minute to hours. Another oxidation method is plasma oxidation. An RF or a DC source plasma with pure O2 or Ar/O2 mixed gas or Ar/N2/O2 mixed gas at a pressure of 1 mtorr to 100 mtorr is used to oxidize the surface of metal, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The oxidation time ranges several seconds to several minutes. The oxidation temperature ranges room temperature to 300 C, depending on the degree of plasma oxidation.
    
    


4. Polymer material

    
    
        TCNQ with doping of Cu, C60, Ag etc.
        PCBM-TCNQ mixed polymer
        Formation method:
        1. Evaporation: By thermal evaporation, e-beam evaporation, or molecular beam epitaxy (MBE) system. A solid-state TCNQ and dopant pellets are co-evaporated in a single chamber. The solid-state TCNQ and dopant pellets are put in a W-boat or a Ta-boat or a ceramic boat. A high electrical current or an electron-beam is applied to melt the source so that the materials are mixed and deposited on wafers. There are no reactive chemistries or gases. The deposition is done at a pressure of 10-4 torr to 10-10 torr. The wafer temperature ranges from room temperature to 200C.
        The post deposition annealing treatment with vacuum or N2 ambient is sometimes needed to improve the composition distribution of polymer material. The annealing temperature ranges room temperature to 300 C with an anneal time of less than 1 hour.
        2. Spin-coat: By a spin-coater with the doped-TCNQ solution @ the rotation of less than 1000 rpm. After spin-coating, the wafer is put to wait the solid-state formation @ room temperature or temperature of less than 200 C. The waiting time ranges from several minutes to days, depending on the temperature and on the formation conditions.
    
    


For additional information on the manufacture, component materials, use and operation of phase change random access memory devices, see U.S. patent application Ser. No. 11/155,067, filed 17 Jun. 2005, entitled Thin Film Fuse Phase Change Ram And Manufacturing Method.
Is preferred that all or part of the portions of bottom and top electrodes 74, 84 contacting memory element 76 comprise an electrode material, such as TiN, or another conductor selected for compatibility with the phase change material of memory element 76. Types of conductors can be used for the plug structures and the top and bottom electrodes structures, including for example aluminum and aluminum alloys, TiN, TaN, TiAlN or TaAlN. Other conductors that might be used comprise one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, Ru and O. TiN may be preferred because it makes good contact with GST (discussed above) as memory material element 76, it is a common material used in semiconductor manufacturing, and it provides a good diffusion barrier at the higher temperatures at which GST transitions, typically in the 600-700° C. range.
The above descriptions may have used terms such as above, below, top, bottom, over, under, et cetera. These terms are used to aid understanding of the invention are not used in a limiting sense.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
Any and all patents, patent applications and printed publications referred to above are hereby incorporated by reference.

## Claims

1. A method for manufacturing an array of memory cells, the method comprising:
forming an array of bottom electrodes;
forming a separation layer on the array of bottom electrodes, an isolation layer on the separation layer, and a sacrificial layer on the isolation layer;
forming an array of openings overlying the array of bottom electrodes and extending into the separation layer, the forming an array of openings comprises forming lower opening segments within the isolation layer and forming upper opening segments within the sacrificial layer, the lower opening segments having widths greater than those of corresponding opening segments;
forming etch masks within the array of openings, including depositing a fill material in the array of openings by a process causing formation of voids within the lower segments of the openings; and anisotropically etching the fill material to open the voids and expose the separation layer, thereby forming the etch masks comprising fill material within the openings;
etching through the separation layer using the etch masks, thereby exposing upper surfaces of the corresponding bottom electrodes;
removing the etch masks to define an array of vias within the separation layer, the vias having constricted parts extending to the upper surfaces of the corresponding bottom electrodes, and having enlarged parts on the constricted parts;
forming memory elements within the vias, the memory elements having first memory element portions within the constricted parts and having second memory element portions within the enlarged parts, the memory elements comprising a memory material; and
forming top electrodes on the memory elements.

2. The method of claim 1, wherein the voids have widths determined by the differences in the widths of the upper and lower segments of the vias.

3. The method of claim 1, wherein the forming memory elements within the vias comprises:
filling the vias with the memory material; and
planarizing the memory material within the vias.

4. The method of claim 1, wherein:
the separation layer comprises a layer of silicon nitride and a layer of silicon dioxide on the layer of silicon nitride;
the isolation layer comprises silicon; and
the sacrificial layer comprises silicon nitride.

5. A method for manufacturing an array of memory cells, the method comprising:
forming an array of bottom electrodes;
forming a first separation layer on the array of bottom electrodes and forming a second separation layer on the first separation layer;
forming an isolation layer on the second separation layer and a sacrificial layer on the isolation layer;
forming an array of openings overlying the array of bottom electrodes and extending through the second separation layer; and
forming etch masks within the array of openings;
etching through the first separation layer using the etch masks, thereby exposing upper surfaces of the corresponding bottom electrodes;
removing the etch masks to define an array of vias within the separation layer, the vias have the constricted parts within the first separation layer and have the enlarged parts within the second separation layer;
forming memory elements within the vias the memory elements having first memory element portions within the constricted parts and having second memory element portions within the enlarged parts, the memory elements comprising a memory material; and
forming top electrodes on the memory elements.

6. The method of claim 5, wherein the first separation layer is an etch stop layer during the forming the array of openings step.

7. The method of claim 5, wherein:
the etching through the second separation layer step removes the sacrificial layer; and
the removing the etch masks step removes the isolation layer.

8. The method of claim 5, wherein the first memory element portions within the constricted parts of the vias having a width less than a minimum feature size for a lithographic process used to form the array of memory cells.

9. The method of claim 5, wherein the first memory element portions of the memory elements in the memory cells of the array have respective diameters, and the second memory element portions of the memory elements in the memory cells of the array have respective diameters, and for at least two cells in the array the respective diameters of the first memory element portions differ by less than the respective diameters of the second memory element portions.

10. A method for manufacturing memory cells, the method comprising:
forming a bottom electrode;
forming a separation layer on bottom electrode, an isolation layer on the separation layer, and a sacrificial layer on the isolation layer;
etching through the sacrificial layer into the separation layer to form an opening overlying the bottom electrode;
forming an etch mask within the opening, wherein the etch mask comprises a material different that that of the sacrificial layer;
etching through the separation layer using the etch mask, thereby exposing upper surface of the bottom electrode;
removing the etch mask to define via within the separation layer, the via having a constricted part extending to the upper surface of the bottom electrode, and having an enlarged part on the constricted part;
forming memory element within the via, the memory element having a first memory element portion within the constricted part and having a second memory element portion within the enlarged part, the memory element comprising a memory material; and
forming a top electrode on the memory element.

11. The method of claim 10, wherein the forming memory element within the via comprises:
filling the via with the memory material; and
planarizing the memory material within the via.

12. The method of claim 10, wherein:
the separation layer comprises a layer of silicon nitride and a layer of silicon dioxide on the layer of silicon nitride;
the isolation layer comprises silicon; and
the sacrificial layer comprises silicon nitride.