# Patent

## Title
Configurable ports for a host ethernet adapter

## Abstract

A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is related to the following copending U.S. patent applications:
U.S. patent application Ser. No. 11/097,609, entitled “Host Ethernet Adapter for Networking Offload in Server Environment”, filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application Ser. No. 11/096,363, entitled “Method and System for Accommodating Several Ethernet Ports and a Wrap Transmitted Flow Handled by a Simplified Frame-By-Frame Upper Structure”, filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application Ser. No. 11/096,571, entitled “Method and Apparatus for Providing a Network Connection Table”, filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application Ser. No. 11/097,051, entitled “Network Communications for Operating System Partitions”, filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application Ser. No. 11/096,365, entitled “System and Method for Parsing, Filtering, and Computing the Checksum in a Host Ethernet Adapter (HEA)”, filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application Ser. No. 11/096,353, entitled “System and Method for a Method for Reducing Latency in a Host Ethernet Adapter (HEA)”, filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application Ser. No. 11/097,055, entitled “Method and Apparatus for Blind Checksum and Correction for Network Transmissions”, filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application Ser. No. 11/096,362, entitled “Method and System for Performing a Packet Header Lookup”, filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application Ser. No. 11/097,430, entitled “System and Method for Computing a Blind Checksum in a Host Ethernet Adapter (HEA)”, filed on even date herewith and assigned to the assignee of the present invention.
FIELD OF THE INVENTION
The present invention relates generally to a server environment and more specifically to adapters utilized in such an environment.
BACKGROUND OF THE INVENTION
The Internet and its applications have tremendously increased the number of clients'requests a server has to satisfy. Each client's request generates both network and storage I/Os. In addition, the advent of 10 gigabit (G) Ethernet and IP storage makes it possible to consolidate the data center communications on a single backbone infrastructure: Ethernet, TCP/IP.
Adapters are utilized in Network Interface Controllers (NICs) to receive data from 10 G sources. In such an adapter it is also desirable to handle data from other sources. For example there are still a significant number of 1 G sources. However it is a problem to support 1 G ports through the same interface as the 10 G port. The problem is that the 10 G port is a serial interface while the 1 G port is typically a parallel interface. Typically to accommodate both types of data sources would require additional pins on the NIC. These additional pins would necessarily increase the cost and complexity of the device.
Accordingly, what is desired is an adapter which can be utilized in a server environment which can accommodate multiple data sources but does not have any of the above-identified problems. The adapter should be easily implemented utilizing existing technologies. The adapter should also be cost effective and easily adapted to existing server environments.
The present invention addresses such a need.
SUMMARY OF THE INVENTION
An Ethernet adapter is disclosed. The adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a high speed serializer/deserializer (high speed serdes) to receive data from and provide data to different speed data sources on the same pins.
A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a server system in accordance with the present invention.
FIG. 2 is a simple block diagram of the a Host Ethernet Adapter (HEA) in accordance with the present invention.
FIG. 3 is a block diagram of the HEA with a more detailed view of the MAC and Serdes Layer.
FIG. 4 is a more detailed diagram of the high speed serdes.



DETAILED DESCRIPTION
The present invention relates generally to a server environment and more specifically to adapters utilized in such an environment. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. To more particularly describe the features of the present invention refer now to the accompanying drawings in conjunction with the accompanying Figures.
FIG. 1 is a block diagram of a server system 100 in accordance with the present invention. The server system 100 includes a processor 102 which is coupled between a memory 104 and an interface adapter chip 106. The interface adapter chip 106 includes an interface 108 to the private (Gx) bus of the processor 102 and a Host Ethernet Adapter (HEA) 110. The HEA 110 receives and transmits signals from and to the processor 102.
The HEA 110 is an integrated Ethernet adapter. A set of accelerator features are provided such that a server TCP/IP stack uses those features when and as required. The interface between the processor 102 and the interface adapter chip 106 has been streamlined by bypassing the PCI bus and providing interface techniques that enable demultiplexing and multiqueueing and packet header separation. In so doing an Ethernet adapter is provided that allows for improved functionality with high speed system while allowing for compatibility with legacy server environments.
FIG. 2 is a simple block diagram of the HEA 110 in accordance with the present invention. As is seen, the HEA 110 has a three layer architecture. The first layer comprises a Media Access Controller (MAC) and Serialization/Deserialization (Serdes) layer 202 which provides a plurality of interfaces from and to other devices on the Ethernet network. In the layer 202 the same chip I/Os are used to provide a plurality of interfaces. For example, in a preferred embodiment, the same chip I/Os are utilized to provide either a 10 Gigabit interface or multiple 1 Gigabit interfaces.
The second layer comprises a Packet Acceleration and Virtualization Layer 204. The layer 204 provides for receiving packets and demultiplexing the flow of packets for enabling virtualization. The layer 204 enables virtualization or partitioning of the operating system of a server based upon the packets. The layer 204 also provides packet header separation to enable zero copy operations and therefore provide improved latency. Also since layer 204 interacts directly with the private bus (Gx) through the Host Interface Layer 206, a low latency, high bandwidth connection is provided.
The third layer comprises the Host Interface Layer 206. The Host Interface Layer 206 provides the interface to the Gx or private bus of the processor and communicates with layer 204. The layer 206 provides for multiple receive sub-queues per Queue Pair (QP) to enable effective buffer management for a TCP stack. The host layer 206 provides the context management for a given flow of data packets.
To describe the features of the HEA 100 in more detail refer now to the following discussion in conjunction with the accompanying figures.
MAC and Serdes Layer 202
FIG. 3 is a block diagram of the HEA 110 with a more detailed view of the MAC and Serdes Layer 202. As is seen in this embodiment there is one 10 Gigabit MAC 302 and two 1 Gigabit MACs 304a and 304a. The MACs 302, 304a and 304b include physical coding units 308a, 308b and 308c for aligning and coding the received packets. The MACs 302, 304a and 304b are coupled to a High Speed Serializer/Deserialization (high speed serdes) 306. The high speed serdes 306 is capable of receiving data from and providing data to one 10 G source or four 1 G. As before mentioned the high speed serdes 306 includes a mechanism for ensuring that data from and to the data sources are handled appropriately. To describe this feature more detail refer now to the following discussion in conjunction with the accompanying Figures.
FIG. 4 is a more detailed diagram of the high speed serdes 306. As is seen in this embodiment the high speed serdes 306 includes a receive section 602 and a transmit section 604. There are four lanes associated with the high speed serdes 306. Each lane corresponds to one up bottom arrow and one down bottom arrow on the receive section 602 and the transmit section 604 respectively. In this embodiment a 10 G source requires four lanes and a 1 G source requires one lane. The high speed serdes 306 also includes a Phase Locked Loop (PLL) 606 which receives a reference clock signal from the NIC (not shown). The reference clock is relatively low compared to the data sources because the PLL 606 can be set to different frequency multiplication ratios to allow the different data sources. The high speed serdes 306 also can configured to allow for multiple modes of operation. In so doing, the different data sources can be accommodated since the PLL 606 has different multiplication ratios.
Below is an example of the operation of the high speed serdes 306 using a 312.5 MHz reference clock
10 G data source: Full rate mode at 3.125 Gbps
1 G data source: Half-rate mode at 1.25 Gbps
The same high speed serdes Ref Clock can be used in both modes, because internal high speed serdes PLL 606 can be set to different frequency multiplication ratios.
312.5 MHz Ref Clock×10=3.125 GHz
312.5 MHz Ref Clock×8=2.5 GHz (high speed serdes half-rate mode then leads to 1.25 Gbps)
A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

## Claims

1. An Ethernet adapter comprising:
a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor; wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins; wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets, wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios; wherein the frequency of the reference clock is relatively low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources.

2. The Ethernet adapter of claim 1 wherein the different speed data sources comprise a 10 Gigabit (G) source and a plurality of 1 G sources.

3. The Ethernet adapter of claim 1 wherein the high speed serdes comprises a receive section for receiving data from a data source;
a transmit section for transmitting data to a data source; and
a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.

4. The Ethernet adapter of claim 3 wherein the receive section and transmit share a plurality of lanes.

5. The Ethernet adapter of claim 1 wherein the different modes of operation comprise full rate mode and half rate mode.

6. The Ethernet adapter of claim 3 wherein the PLL controls the data rate by setting different multiplication ratios.

7. A network interface controller (NIC) comprising:
an interface to a private bus; and
an Ethernet adapter coupled to the interface; the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor; wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins; wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets; wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios; wherein the frequency of the reference clock is relatively low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources.

8. The NIC of claim 7 wherein the different speed data sources comprise a 10 Gigabit (G) source and a plurality of 1 G sources.

9. The NIC of claim 7 wherein the high speed serdes comprises:
a receive section for receiving data from a data source;
a transmit section for transmitting data to a data source; and
a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.

10. The NIC of claim 7 wherein the receive section and transmit share a plurality of lanes.

11. The NIC of claim 7 wherein the different modes of operation comprise full rate mode and half rate mode.

12. The NIC of claim 7 wherein the PLL controls the data rate by setting different multiplication ratios.

13. A network interface controller (NIC) comprising:
an interface coupled to a private bus; and
an Ethernet adapter coupled to the interface, a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor via the private bus, wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to a 10 Gigabit (G) source and a plurality of 1 G sources on the same pins, wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets, wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios; wherein the frequency of the reference clock is relative low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources.

14. The NIC of claim 13 wherein the high speed serdes comprises a receive section for receiving data from a data source;
a transmit section for transmitting data to a data source; and
a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.

15. The NIC of claim 14 wherein the receive section and transmit share a plurality of lanes.

16. The NIC of claim 14 wherein the PLL controls the data rate by setting different multiplication ratios.

17. A server comprising: a processor; the processor including a private bus; and a network interface controller (NIC) coupled to the private bus, the NIC including an Ethernet adapter; the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to the processor; wherein the plurality of layers include in one layer a plurality of media access controllers (MACs) and a high speed serializer/deserializer (high speed serdes) to receive data from and provide data to different speed data sources on the same pins; wherein each of the plurality of MACs includes its own physical coding unit for aligning and coding the transmit packets, wherein the high speed serdes can be configured in different modes of operation by setting different frequency multiplication ratios; wherein the frequency of the reference clock is relatively low compared to the data sources because a phase locked loop (PLL) is adjustable to different frequency multiplication ratios to allow the different data sources.