# Patent

## Title
Apparatus and method for calibrating in-phase and quadrature-phase mismatch

## Abstract

A method and device for calibrating in-phase and quadrature-phase (IQ) mismatch. The device is used in a direct down-conversion circuit of a communication system. The device has a first mixer for mixing an RF signal with a first carrier signal, so as to generate an in-phase analog signal; a second mixer for mixing the RF signal with a second carrier signal, so as to generate a quadrature-phase analog signal; an operation unit for executing a Least Mean Square (LMS) algorithm and thereby generating a compensation signal according to the in-phase analog signal and the quadrature-phase analog signal; and a calibration unit for compensating the in-phase analog signal and the quadrature-phase analog signal according to the compensation signal, so as to calibrate the IQ mismatch between the in-phase analog signal and the quadrature-phase analog signal.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This is a continuation-in-part of U.S. application Ser. No. 10/905,496, which was filed on Jan. 7, 2005 and is included herein by reference.


BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a method for calibrating signals, and more particularly, to an apparatus and a method for calibrating mismatch between in-phase and quadrature-phase signals.
2. Description of the Prior Art
FIG. 1 is a diagram showing a conventional zero-IF receiver 10. The zero-IF receiver 10 includes an antenna 11, a low noise amplifier (LNA) 12, mixers 14 and 24, low pass filters (LPFs) 16 and 26, analog to digital converters (ADCs) 18 and 28, and a digital signal processor (DSP) 19. Antenna 11 receives a radio signal, and LNA 12 amplifies the radio signal. Mixer 14 mixes the radio signal with a first carrier wave(COSωct in FIG. 1), so as to generate an analog signal Sa1. The other mixer 24 mixes the radio signal with a second carrier wave (SIN(ωct+δ) in FIG. 1), so as to generate an analog signal Sa2. LPFs 16,26 filter out high frequency components of the analog signals Sa1, Sa2, respectively. Additionally, ADCs 18,28 convert the analog signals Sa1 and Sa2 to corresponding digital signals Sd1 and Sd2, respectively, and DSP 19 further processes the digital signals Sd1 and Sd2.
Ideally, there should be a 90° phase difference between the above-mentioned first carrier wave and the second carrier wave for generating analog signals Sa1 and Sa2 with quadrature relation (i.e., an in-phase signal and a quadrature-phase signal). However, in actual apparatus, temperature variation, process variation, and drift of supplied power may cause a phase offset δ between the first carrier wave and the second carrier wave such that the phase difference can't be ideal. This problem is called IQ mismatch.
IQ mismatch influences demodulation of signals and thereby increases the bit error rate in a communication system. Therefore, it is needed to compensate for the above-mentioned phase offset δ, so as to correct the analog signals Sa1, Sa2 and increase the bit rate of the communication system.
There are two typical calibration methods for solving the IQ mismatch in a zero-IF receiver. One is to generate a phase difference signal by measuring the phase offset δ of the digital signals Sd1 and Sd2 and then generate a calibration signal according to the phase difference signal for compensating for the phase offsetδ of the analog signals Sa1 and Sa2. The other is also to generate a phase difference signal by measuring the phase offset δ of the digital signals Sd1 and Sd2 but generate a calibration signal according to the phase difference signal for compensating for the phase offset δ of the digital signals Sd1 and Sd2.
The above-mentioned methods both measure the phase offset δ of digital signals Sd1, Sd2 by utilizing a digital circuit of a DSP executing a Discrete Fourier Transform (DFT) on the digital signals Sd1, Sd2. Besides, phase compensation is done to the analog signals Sa1 and Sa2 by executing a Gram-Schmidt orthogonal procedure or done to the digital signals Sd1 and Sd2 by utilizing the digital circuit executing a LMS (Least-Mean-Square) algorithm. The related prior art are disclosed by the reference “Adaptive IQ mismatch cancellation for quadrature IF receiver”, Isis Mikhael, Wasfy. B. Mikhael, http://bruce.engr.ucf.edu/%7Eprp/paper6.
SUMMARY OF INVENTION
Therefore, it is an objective of the claimed invention to provide a calibration device and method to solve the above-mentioned IQ mismatch.
According to an embodiment of the claimed invention, a calibrating method for IQ mismatch comprises the following steps: respectively mixing an RF signal with a first and a second carrier signals for generating an in-phase analog signal and a quadrature-phase analog signal; executing a Least Mean Square (LMS) algorithm for generating a compensation signal according to the in-phase analog signal and the quadrature-phase analog signal; and compensating for the in-phase analog signal and quadrature-phase analog signal according to the compensation signal, so as to calibrate IQ mismatch between the in-phase analog signal and quadrature-phase analog signal.
According to an embodiment of the claimed invention, an IQ mismatch calibration device comprises a first mixer for mixing an RF signal with a first carrier signal to generate an in-phase analog signal; a second mixer for mixing the RF signal with a second carrier signal to generate a quadrature-phase analog signal; an operation unit for executing a Least Mean Square (LMS) algorithm to generate a compensation signal according to the in-phase and quadrature-phase analog signals; and a calibration unit for calibrating IQ mismatch between the in-phase analog signal and the quadrature-phase analog signal according to the compensation signal.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.



BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a diagram of a conventional zero-IF receiver.
FIG. 2 is a diagram of a zero-IF transceiver according to an embodiment of the present invention.
FIG. 3 is a diagram of the calibration unit and the operation unit of FIG. 2.



DETAILED DESCRIPTION
Please refer to FIG. 2. FIG. 2 is a diagram of a zero-IF transceiver 40 according to an embodiment of the present invention. The zero-IF transceiver 40 comprises an antenna 41, a low noise amplifier (LNA) 42, mixers 44 and 54, and low pass filters (LPFs) 46 and 56. Because the general operation of the zero-IF transceiver 40 is known to a person of ordinary skill in the art, further description about the operation is omitted herein for the sake of brevity. Please note that the mixer 44 utilizes the first carrier wave C1 for directly converting the RF signal to generate an in-phase analog signal It. Additionally, the mixer 54 utilizes the second carrier wave CQ for directly converting the RF signal to generate a quadrature-phase analog signal Qt. In the present invention, the zero-IF transceiver 40 further comprises an operation unit 36 for measuring the gain and phase mismatch between the in-phase analog signal It and the quadrature-phase analog signal Qt and a calibration unit 34 for calibrating the gain mismatch and the phase mismatch between the in-phase analog signal It and the quadrature-phase analog signal Qt according to the measuring result. Accordingly, a corrected in-phase analog signal It′ and a corrected quadrature-phase analog signal Qt′ are generated by the calibration unit 34. Besides, the transceiver 40 further comprises the ADCs 48 and 58 for respectively converting the corrected in-phase and quadrature-phase analog signals It′ and Qt′ to corresponding in-phase and quadrature-phase digital signals. In the end, a digital signal processor (DSP) 49 executes the digital signal processing on the in-phase and quadrature-phase digital signals.
Please refer to FIG. 3. FIG. 3 is a diagram showing the calibration unit 34 and the operation unit 36 of FIG. 2. In this embodiment, the calibration unit 34 comprises a programmable gain compensation unit 62 and a programmable phase compensation unit 72. The operation unit 36 comprises sampling units 64 and 74, a delay unit 66, a synthesizing unit 76, and an LMS operation unit 78.
The programmable gain compensation unit 62 utilizes an initial gain compensating value ω1 to adjust the gain of the in-phase analog signal It and outputs the corrected in-phase analog signal It′. The programmable phase compensation unit 72 utilizes an initial phase compensating valueψ1 to adjust the phase of the quadrature-phase analog signal Qt and outputs the corrected quadrature-phase analog signal Qt′. Although the gain of the in-phase analog signal It and the phase of the quadrature-phase analog signal Qt are respectively adjusted in this embodiment for calibrating IQ mismatch between the in-phase and quadrature-phase analog signals It and Qt, those skilled in the art easily appreciate that IQ mismatch can be calibrated by only adjusting the gain and phase of one of the in-phase and quadrature-phase analog signals It and Qt.
Please refer to FIG. 3. The sampling units 64 and 74 sample the corrected in-phase analog signal It′ and the corrected quadrature-phase analog signal Qt′ and thus generate two sampling signals E, G, respectively. The sampling frequency is at least two times the frequency of the sampled signals (i.e., the corrected in-phase and quadrature-phase analog signals It′ and Qt′). In this embodiment, the sampling frequency is four times the frequency of the sampled signals, but not limited to that. Otherwise, the delay unit 66 delays the sampling signal E for a quarter of its period in this embodiment, so as to generate a delay signal F. The synthesizing unit 76, an adder in this embodiment, synthesizes the delay signal F and the sampling signal G and thus generate a synthesized signal Y inputted into the least mean square (LMS) operation unit 78. The LMS operation unit 78 generates an error signal ε according to the synthesized signal Y and an error toleration threshold value d, wherein the error toleration threshold value d represents the tolerable amount of error for adjusting the synthesized signal Y during executing the LMS algorithm. In this embodiment, zero is set to the error toleration threshold value d. Additionally, the delay signal F and the sampling signal E are used for generating the input parameters X1 and X2 which are necessary for executing the LMS algorithm. Consequently, the LMS operation unit 78 generates a gain compensating value ω2 to update the initial gain compensating valueω1 of the programmable gain compensation unit 62, and generates a phase compensating value ψ2 to update the initial phase compensating valueψ1 of the programmable phase compensation unit 72 according to the delay signal F, the sampling signal E, and the error signal ε. Hence, by utilizing the calibration unit 34 and the operation unit 36, the corrected analog in-phase signal It′ and the corrected analog quadrature-phase signal Qt′ are generated with the same amplitude and orthogonal characteristic.
The operation of the operation unit 36 is further described as follows.
The RF signal VRF received by the Antenna 41 is:

VRF=sin(wLOt+wmt+θ0), wherein frequencies ωLO, ωm are known values.

The first and the second carrier wave received by the mixers 44 and 54 are:

CI=sin(wLOt)

CQ=(1+ε1)*cos(wLOt+δ1)

, whereinε1 represents the gain mismatch between the carrier signals CI, CQ, and δ1 represents the phase mismatch between the carrier signals CI, CQ.
Consequently, the in-phase analog signal It and the quadrature-phase analog signal Qt respectively corresponding to the formulas 1 and 2 shown below are generated by down converting the RF signal VRF according to carrier signals CI and CQ, respectively.

It=cos(wmt+θ0)  (formula 1)

Qt=−(1+ε1)sin(wmt+θ0−δ1)  (formula 2)

The corrected in-phase analog signal It′ and the corrected quadrature-phase analog signal Qt′ respectively corresponding to the formulas 3 and 4 shown below are generated by executing the gain and phase compensation on the in-phase analog signal It and the quadrature-phase analog signal Qt, respectively. The parameter W of formula 3 represents the gain compensating value offered by the programmable gain compensation unit 62, and the parameter ψ of formula 4 represents the phase compensating value offered by the programmable phase compensation unit 72 during calibration.

It′=W*cos(wmt+θ0)  (formula 3)

Qt′=−(1+ε1)sin(wmt+θ0−δ1+φ)  (formula 4)

Formula 5 shown below represents that the corrected in-phase signal It′ is sampled within time t according to a period T0, so as to generate k sampled values and output the sampling signal E(k). Formula 6 shown below means that the sampling signal E(k) is delayed by a period T0, wherein T0 is a quarter of 2π/ωm and thereby the cosine function is translated into the sine function in formula 6.

E(k)=W*cos(wmkT0+θ0), where t=k*T0  (formula 5)

F(k)=W*cos[wm(k−1)T0+θ0]=W*sin(wmkT0+θ0)  (formula 6)

Formulas 7, 8, and 9 are shown below, wherein formula 7 represents that quadrature-phase signal Qt′ is sampled within time t according to a period T0, so as to generate k sampled values and output the sampling signal G(k). Formula 8 means that the sampling signal G(k) and the delay signal F(k) are synthesized to form a synthesized signal y(t). As for formula 9, d(t) represents the toleration error threshold value for executing the LMS algorithm so that the tolerable amount of error is set for calibrating the phase and gain mismatch.

G(k)=−(1+ε1)sin(wmkT0+θ0−δ1+φ), where t=k*T0  (formula 7)

y(t)=G(k)+F(k)=W*sin(wmkT0+θ0)−(1+ε1)sin(wmkT0+θ0−δ1+φ)  (formula 8)

ε(t)=d(t)−y(t)=−W*sin(wmkT0+θ0)−(1+ε1)sin(wmkT0+θ0−δ1+φ), where d(t)=0  (formula 9)

The parameters X1(k) and X2(k) shown in formulas 10 and 11 are necessary for executing the LMS algorithm. According to formulas 10 and 11, it is obvious that the parameter X1(k) is the inversion of the delay signal F(k) and the parameter X2(k) is the sampling signal E(k).





  
    
      
        
          
            X
            2
          
          ⁡
          
            (
            k
            )
          
        
        =
        
          
            
              ∂
              
                ɛ
                ⁡
                
                  (
                  k
                  )
                
              
            
            
              ∂
              φ
            
          
          =
          
            cos
            ⁡
            
              (
              
                
                  
                    w
                    m
                  
                  ⁢
                  k
                  ⁢
                  
                    
                  
                  ⁢
                  
                    T
                    0
                  
                
                +
                
                  θ
                  0
                
                -
                
                  δ
                  1
                
                +
                φ
              
              )
            
          
        
      
    
    
      
        (
        
          formula
          ⁢
          
            
          
          ⁢
          10
        
        )
      
    
  
  
    
      
        
          
        
        ⁢
        
          
            
              ≅
              
                W
                *
                
                  cos
                  ⁡
                  
                    (
                    
                      
                        
                          w
                          m
                        
                        ⁢
                        k
                        ⁢
                        
                          
                        
                        ⁢
                        
                          T
                          0
                        
                      
                      +
                      
                        θ
                        0
                      
                    
                    )
                  
                
              
            
            =
            
              E
              ⁡
              
                (
                k
                )
              
            
          
          ,
        
      
    
    
      
        
      
    
  
  
    
      
        where
        ⁢
        
          
        
        ⁢
        ψ
        ⁢
        
          
        
        ⁢
        is
        ⁢
        
          
        
        ⁢
        less
        ⁢
        
          
        
        ⁢
        than
        ⁢
        
          
        
        ⁢
        1
      
    
    
      
        
      
    
  
  
    
      
        
          
            X
            1
          
          ⁡
          
            (
            k
            )
          
        
        =
        
          
            
              ∂
              
                ɛ
                ⁡
                
                  (
                  k
                  )
                
              
            
            
              ∂
              W
            
          
          =
          
            
              -
              
                sin
                ⁡
                
                  (
                  
                    
                      
                        w
                        m
                      
                      ⁢
                      k
                      ⁢
                      
                        
                      
                      ⁢
                      
                        T
                        0
                      
                    
                    +
                    
                      θ
                      0
                    
                  
                  )
                
              
            
            =
            
              -
              
                F
                ⁡
                
                  (
                  k
                  )
                
              
            
          
        
      
    
    
      
        (
        
          formula
          ⁢
          
            
          
          ⁢
          11
        
        )
      
    
  




As shown below, formula 12 and formula 13 are known for executing LMS algorithm such that the operation unit 36 performs the LMS operation to calibrate the gain and the phase mismatch.

W(k+1)=W(k)+2μ*sign[−y(k)]*sign[−F(k)]  (formula 12)

φ(k+1)=φ(k)+2μ*sign[−y(k)]*sign[E(k)]  (formula 13)

Please note that the transceiver of the present invention can also send a test signal from the transmitter to the receiver of the transceiver before communicating with the remote communication system, so as to execute the phase and gain compensation in advance.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

## Claims

1. A method for calibrating in-phase and quadrature-phase (IQ) mismatch in a direct down-conversion circuit of a communication system, the method comprising: generating an in-phase analog signal and a quadrature-phase analog signal according to an RF signal, utilizing a first mixer and a second mixer, respectively; generating, with a first sampling circuit, a first reference signal according to the in-phase analog signal; generating, with a second sampling circuit, a second reference signal according to the quadrature-phase signal; delaying the first reference signal by a predetermined period utilizing a delay circuit, and thus generating a first delay signal; generating, with a synthesizing device, a synthesized signal according to the first delay signal and the second reference signal; executing, with an algorithm operation device, a predetermined algorithm on the synthesized signal, the first reference signal, and the first delay signal to thereby output a compensation signal; wherein executing the predetermined algorithm further comprises executing a least mean squares (LMS) algorithm on the synthesized signal, the first reference signal, and the first delay signal according to an error threshold limit value, so as to thereby output the compensation signal; and utilizing a calibrating device for calibrating IQ mismatch between the in-phase analog signal and the quadrature-phase analog signal according to the compensation signal.

2. The method of claim 1, wherein the step of generating the in-phase and quadrature-phase analog signals further comprises:
mixing the RF signal with a first carrier signal, so as to generate a first mixing signal;
filtering the first mixing signal and thus generating the in-phase analog signal;
mixing the RF signal with a second carrier signal, so as to generate a second mixing signal; and
filtering the second mixing signal and thus generating the quadrature-phase analog signal.

3. The method of claim 1, wherein the step of generating the compensation signal further comprises:
respectively sampling the in-phase analog signal and the quadrature-phase analog signal according to a sampling frequency and thereby generating the first reference signal and the second reference signal.

4. The method of claim 3, wherein the sampling frequency is at least four times the frequency of the in-phase analog signal or the quadrature-phase analog signal.

5. The method of claim 1, wherein the predetermined period corresponds to the sampling frequency such that the first delay signal is orthogonal to the first sampling signal.

6. The method of claim 1, wherein the compensation signal comprises at least one of a phase compensation signal and a gain compensation signal.

7. The method of claim 6, wherein the step of calibrating IQ mismatch between the in-phase analog signal and the quadrature-phase analog signal further comprises:
executing at least one of a phase compensation or a gain compensation according to at least one of the phase compensation signal and the gain compensation signal.

8. The method of claim 7, further comprising:
adjusting, with a phase compensation device, at least one of the phases of the in-phase and quadrature-phase analog signals during executing the phase compensation; and
adjusting, with a gain compensation device, at least one of the amplitudes of the in-phase and quadrature-phase analog signals during executing the gain compensation.

9. The method of claim 1, further comprising:
after calibrating the IQ mismatch between the in-phase analog signal and the quadrature-phase analog signal:
converting the in-phase analog signal into an in-phase digital signal with a first analog to digital converter;
converting the quadrature-phase analog signal into a quadrature-phase digital signal with a second analog to digital converter; and
executing digital signal processing on the in-phase and the quadrature-phase digital signals with a digital signal processing device.

10. A device for calibrating in-phase and quadrature-phase (IQ) mismatch, said device used in a direct down-conversion circuit of a communication system, the device comprising: a first mixer for mixing an RF signal with a first carrier signal, so as to generate an in-phase analog signal; a second mixer for mixing the RF signal with a second carrier signal, so as to generate a quadrature-phase analog signal; a first sampling unit for sampling the in-phase analog signal according to a sampling frequency, so as to generate a first sampling signal; a second sampling unit for sampling the quadrature-phase analog signal according to the sampling frequency, so as to generate a second sampling signal; a delay unit for generating a first delay signal according to the first sampling signal and a predetermined period; a synthesizing unit for generating a synthesized signal according to the first delay signal and the second sampling signal; an algorithm operation unit for generating a compensation signal by executing a predetermined algorithm according to the synthesized signal, the first sampling signal and the first delay signal; wherein the algorithm operation unit is a least mean squares (LMS) operation unit for executing an LMS algorithm on the synthesized signal, the first sampling signal, and the first delay signal according to an error threshold limit value, so as to thereby generate the compensation signal; and a calibration unit for calibrating the IQ mismatch between the in-phase analog signal and the quadrature-phase analog signal according to the compensation signal.

11. The device of claim 10, further comprising:
an antenna for receiving the RF signal;
a first low pass filter (LPF) for filtering out a high frequency component of the in-phase analog signal; and
a second LPF for filtering out a high frequency component of the quadrature-phase analog signal.

12. The device of claim 10, wherein the predetermined period corresponds to the sampling frequency such that the first delay signal and the first sampling signal are orthogonal to each other.

13. The device of claim 10, wherein the sampling frequency is at least four times the frequency of the in-phase or quadrature-phase analog signal.

14. The device of claim 10, wherein the compensation signal comprises at least one of a phase compensation signal and a gain compensation signal.

15. The device of claim 14, wherein the calibration unit further comprises:
a phase compensation unit for adjusting at least one of the phases of the in-phase and quadrature-phase analog signals according to the phase compensation signal during executing the phase compensation; and
a gain compensation unit for adjusting at least one of the amplitudes of the in-phase and quadrature-phase analog signals according to the gain compensation signal during executing the gain compensation.

16. The device of claim 15, wherein the phase compensation unit executes phase compensation on the quadrature-phase analog signal.

17. The device of claim 15, wherein the gain compensation unit executes gain compensation on the in-phase analog signal.

18. The device of claim 15, further comprising:
a first analog to digital converter (ADC) for generating a corresponding in-phase digital signal according to the in-phase analog signal;
a second ADC for generating a corresponding quadrature-phase digital signal according to the quadrature-phase analog signal; and
a digital signal processor (DSP) for executing digital signal processing on the in-phase and the quadrature-phase digital signals.

19. The device of claim 10, wherein the IQ mismatch calibration device is applied to a transceiver.

20. The device of claim 19, wherein the RF signal is a test signal outputted from a transmitter of the transceiver and then received by a receiver of the transceiver.