# Patent

## Title
Systems, apparatus and methods relating to bandgap circuits

## Abstract

A system includes a bandgap reference voltage circuit, a plurality of trimming resistors, a plurality of trimming switches to connect the bandgap reference voltage circuit to one or more of the plurality of trimming resistors, and an output terminal to connect to at least one of the bandgap reference voltage circuit and the plurality of trimming resistors. The system may provide a trimmed reference voltage independent of at least one of the resistance of any of the plurality of trimming switches and the voltage across any of the plurality of trimming switches.

## Background
TECHNICAL FIELD
The present invention relates to a circuit for providing a voltage, and relates particularly, though not solely, to a bandgap reference voltage circuit.
BACKGROUND
It is useful in the field of electronic circuits to provide a constant and stable reference voltage. For example reference voltages of around 1.25V are common as this is close to the theoretical bandgap of silicon at 0 K.
An example prior art system that provides a reference voltage is a “bandgap reference voltage circuit”. Various methods have been proposed including those by Widlar, R., “New Developments in IC Voltage Regulators,” IEEE Journal of Solid-State Circuits, Vol. SC-6, pp. 2-7, February 1971; K. Kuijk, “A Precision Reference Voltage Source,” IEEE Journal of Solid-State Circuits, Vol. SC-8, pp. 222-226, June 1973; and H. Banba, et. al., “A CMOS Bandgap Reference Circuit with sub-1-V Operation,” IEEE Journal of Solid-State Circuits, Vol. 34, pp. 670-674, May 1999.



BRIEF DESCRIPTION OF THE DRAWINGS
Exemplary embodiments will now be described for the sake of example only with reference to the drawings, in which:
FIGS. 1a-1c show circuit diagrams of a bandgap circuit with a trimming circuit according to example embodiments.
FIG. 2 shows a circuit diagram of a bandgap circuit with a trimming circuit according to a further example embodiment;
FIG. 3 shows a circuit diagram of a bandgap circuit with a trimming circuit according to a still further example embodiment;
FIG. 4 shows a flow diagram for a method of trimming R4 in FIG. 1a or FIG. 2;
FIG. 5 shows a flow diagram for a method of trimming R4 in FIG. 3; and
FIG. 6 shows a flow diagram for a method of trimming R3 in FIG. 3.



DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
Referring to FIG. 1a a bandgap circuit 100 is shown according to an exemplary embodiment. An operational amplifier OPAMP 102 has a positive input terminal V+ a negative input terminal V− and an OPAMP output Vout. A first resistor R1 is connected to the positive input terminal V+. A second resistor R2 is connected to the negative input terminal V−. A third resistor R3 is connected between the negative input terminal V− and the first resistor R1. A first PNP bipolar transistor Q1 has the emitter connected to the positive input terminal V+, the collector and the base connected to ground, and emitter current I1. A second PNP bipolar transistor Q2 has the emitter connected to the second resistor R2, the collector and the base connected to ground, and emitter current I2. The OPAMP 102 operates to equalize the voltage at its inputs V+−V− ̃0V, as shown in equation 1:

I1*R1=I2*R3  (1)

I1 and I2 are the currents through the emitter of each bipolar transistor. ΔVEB is the difference between VEBQ1 and VEBQ2, and can be calculated according to equation (2):




  
    
      
        
          
            
              
                Δ
                ⁢
                
                  
                
                ⁢
                
                  V
                  EB
                
              
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                -
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
          
        
        
          
            
              =
              
                
                  I
                  2
                
                *
                
                  R
                  2
                
              
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




Therefore, the temperature stability of the bandgap circuit output voltage Vref without g (i.e R4=0Ω) may be analyzed using equation (3):




  
    
      
        
          
            
              
                V
                ref
              
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    I
                    2
                  
                  *
                  
                    R
                    3
                  
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    (
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        
                          V
                          EB
                        
                        /
                        
                          R
                          2
                        
                      
                    
                    )
                  
                  *
                  
                    R
                    3
                  
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    (
                    
                      
                        R
                        3
                      
                      /
                      
                        R
                        2
                      
                    
                    )
                  
                  *
                  
                    V
                    t
                  
                  *
                  
                    Ln
                    ⁡
                    
                      [
                      
                        
                          (
                          
                            
                              R
                              3
                            
                            /
                            
                              R
                              1
                            
                          
                          )
                        
                        *
                        
                          (
                          
                            
                              I
                              
                                S
                                ⁢
                                
                                  
                                
                                ⁢
                                2
                              
                            
                            /
                            
                              I
                              
                                S
                                ⁢
                                
                                  
                                
                                ⁢
                                1
                              
                            
                          
                          )
                        
                      
                      ]
                    
                  
                
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




In Equation (3), Vt is the thermal voltage (eg:  ̃26 mV@ 25° C.) and IS is the saturation current coefficient of Q1 and Q2. The bandgap circuit may have an operating configuration, for example equal bias currents (I1=I2 R1=R3) and bipolar device ratio scaling (IS2/IS1=N) or bias current scaling (I1=N*I2, R3/R1=N, IS1=IS2). In those configurations the circuit operation is characterized by Equation (4):

Vref=VEBQ1+(R3/R2)*Vt*Ln(N)  (4)

In Equation (4), VBEQ1 (“CTAT component”) is complementary to absolute temperature (CTAT). As such, the voltage reduces with increasing temperature and has approximate proportionally within small operating temperature ranges. The right hand term in Equation (4) (R3/R2*Vt*Ln(N)) (“PTAT component”), the Vt is proportional to absolute temperature (PTAT) so that the voltage increases with increasing temperature and has approximate proportionally within small operating temperature ranges. Thus, if the ratios between the resistor are appropriately designed, the CTAT component and the PTAT component will cancel each other out over a given temperature range, to achieve high temperature stability of Vref eg: zero temperature coefficient.
In practice the precision or accuracy of bandgap circuits may be limited by manufacturing variations eg: variations in VBE, and bipolar and resistor matching.
FIG. 1a shows a trimming circuit 104 connected between the output of the OPAMP Vout and the common point of R1 and R3. In operation the trimming circuit 104 may provide a predetermined trimming resistance that compensates for the voltage magnitude and/or the temperature coefficient.
The trimming circuit 104 comprises a series of trim resistors R4a-R4d connected to the common point between R1 and R3. A series of switch pairs S1-S5 have the first set of switches S1a-S5a connected between the output of the OPAMP Vout and the trim resistors, and the second set of switches S1b-S5b connected between the trim resistors and the output terminal Vref.
The trimming of R4 causes an adjustment of the positive temperature coefficient component according to Equation (5):




  
    
      
        
          
            
              
                V
                ref
              
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    I
                    2
                  
                  *
                  
                    R
                    3
                  
                
                +
                
                  
                    (
                    
                      
                        I
                        1
                      
                      +
                      
                        I
                        2
                      
                    
                    )
                  
                  *
                  
                    R
                    4
                  
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    I
                    2
                  
                  *
                  
                    (
                    
                      
                        R
                        3
                      
                      +
                      
                        R
                        4
                      
                    
                    )
                  
                
                +
                
                  
                    I
                    1
                  
                  *
                  
                    R
                    4
                  
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    I
                    2
                  
                  *
                  
                    (
                    
                      
                        R
                        3
                      
                      +
                      
                        R
                        4
                      
                    
                    )
                  
                
                +
                
                  
                    I
                    2
                  
                  *
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                  *
                  
                    
                      R
                      3
                    
                    /
                    
                      R
                      1
                    
                  
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    I
                    2
                  
                  *
                  
                    [
                    
                      
                        R
                        3
                      
                      +
                      
                        
                          R
                          4
                        
                        *
                        
                          (
                          
                            1
                            +
                            
                              
                                R
                                3
                              
                              /
                              
                                R
                                1
                              
                            
                          
                          )
                        
                      
                    
                    ]
                  
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    (
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        
                          V
                          EB
                        
                        /
                        
                          R
                          2
                        
                      
                    
                    )
                  
                  *
                  
                    [
                    
                      
                        R
                        3
                      
                      +
                      
                        
                          R
                          4
                        
                        *
                        
                          (
                          
                            1
                            +
                            
                              
                                R
                                3
                              
                              /
                              
                                R
                                1
                              
                            
                          
                          )
                        
                      
                    
                    ]
                  
                
              
            
          
        
        
          
            
              =
              
                
                  V
                  
                    EB
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                +
                
                  
                    [
                    
                      
                        (
                        
                          
                            R
                            3
                          
                          /
                          
                            R
                            2
                          
                        
                        )
                      
                      +
                      
                        
                          (
                          
                            
                              R
                              4
                            
                            /
                            
                              R
                              2
                            
                          
                          )
                        
                        *
                        
                          {
                          
                            1
                            +
                            
                              (
                              
                                
                                  R
                                  3
                                
                                /
                                
                                  R
                                  1
                                
                              
                              )
                            
                          
                          }
                        
                      
                    
                    ]
                  
                  *
                  
                    V
                    t
                  
                  *
                  
                    Ln
                    ⁡
                    
                      (
                      N
                      )
                    
                  
                
              
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




In Equation (5), R4 is the value of the resistance between the selected connection point/closed switch and the common point between R1 and R3.
One of the first set of switches S1a-S5a will carry the current that flows through R4. These switches are termed current force switches. The current force switches S1a-S5a do not affect the output voltage since the switches are not in the sense path of the Vref output terminal. By connecting the output terminal Vref to a high impedance load, any parasitic voltage drop across the second set of switches S1b-S5b will be negligible. The second sets of switches are termed the voltage sense switches. The circuit in FIG. 1a is configured so that the output voltage Vref is independent of the resistance and/or the voltage drop across any of the current force and voltage sense switches. The circuit in FIG. 1a is also configured so that the bipolar bias currents I1 and I2 do not become unmatched by trimming R4. In order to ensure correct performance over the operating range of temperatures, R2 is fixed and R1 and R3 are tracking. The voltage supply to the OPAMP, such as OPAMP 102 in FIG. 1a, should provide enough headroom for the voltage drop across the current force switches.
Turning to FIG. 1b, an alternative embodiment of the present invention is shown. Switches S1a-S5a are implemented with multi-way switch S9a and switches S1b-S5b are implemented with multi-way switch S9b. Switches S9a and S9b can also be implemented as a double-pole multi-way switch. A further alternative embodiment of the present invention is shown in FIG. 1c, where switches S1a-S5a and switches S1b-S5b are implemented as multiplexers 120a and 120b, respectively.
Referring to FIG. 2, a bandgap circuit 200 is shown according to a further exemplary embodiment. The bandgap circuit 200 operates similarly to the bandgap circuit 100 shown in FIG. 1a. FIG. 2 shows a trimming circuit 204 connected between the output of the OPAMP Vout and the common point of R1 and R3. In operation the trimming circuit 204 may provide a predetermined trimming resistance R4 that compensates for the voltage magnitude and/or the temperature coefficient.
The trimming circuit 204 comprises a series of trim resistors R4a-R4d connected between the common point between R1 and R3 and the output terminal Vref. A series of switches S1-S5 are connected between the output of the OPAMP Vout and the trim resistors. By connecting the output terminal Vref to a high impedance load, any parasitic voltage drop across the non current-carrying R4 resistors, between the output terminal Vref and the selected connection point/closed switch, will be negligible. The circuit in FIG. 2 is configured so that the output voltage Vref is independent of the resistance and/or the voltage drop across any of the switches.
Referring to FIG. 3 a bandgap circuit 300 is shown according to a still further exemplary embodiment. An operational amplifier OPAMP 302 has a positive input terminal V+ a negative input terminal V− and an OPAMP output Vout. A first PMOS transistor M1 has its drain terminal connected to the negative input terminal V−, its source terminal connected to a supply VCC, its gate terminal connected to the OPAMP output Vout, and drain current I1. A first resistance R1 is connected to the negative input terminal V−, with resistor current I1b. A first PNP bipolar transistor Q1 has its emitter terminal connected to the negative input terminal V−, its collector terminal and its base terminal connected to ground, and emitter current I1a. A second PMOS transistor M2 has its source terminal connected to the supply VCC, its gate terminal to connect to the OPAMP output Vout, and drain current I2. A second resistance R2 is connected to the drain terminal of the second PMOS transistor M2 with resistor current I2b. A second PNP bipolar transistor Q2 has its emitter terminal connected to the second end of the third plurality of trimming resistors, its collector terminal and its base terminal connected to ground, and an emitter current I2a. A third PMOS transistor M3 has its source terminal connected to the supply VCC, its gate terminal connected to the OPAMP output Vout, and a drain current I3.
FIG. 3 shows a first trimming circuit 304 connected between the second PMOS transistor M2 and the OPAMP 302. In operation the trimming circuit 304 may provide a predetermined trimming resistance R3 that compensates for the temperature coefficient.
The first trimming circuit 304 comprises a third plurality of trimming resistors R3 that are connected at a first end to the drain terminal of the second PMOS transistor M2. A first plurality of trimming switches S1-S4 is connected between the positive input terminal V+ and a selected connection point between two of the third plurality of trimming resistors R3.
FIG. 3 shows a second trimming circuit 306 connected between the third PMOS transistor M3 and ground. In operation the trimming circuit 306 may provide a predetermined trimming resistance R4 that compensates for the output voltage magnitude.
The second trimming circuit 306 comprises a fourth plurality of trimming resistors R4 that are connected at a second end to ground. A second plurality of trimming switches S5-S8 are connected between the drain terminal of the third PMOS transistor M3 and a selected connection point between two of the fourth plurality of trimming resistors R4.
An output terminal Vref is connected to the first end of the fourth plurality of trimming resistors R4. The trimming of R3 and/or R4 causes an adjustment of the output voltage Vref according to Equations (6) to (9):




  
    
      
        
          
            
              
                I
                1
              
              =
              
              ⁢
              
                
                  I
                  2
                
                =
                
                  I
                  3
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    I
                    
                      1
                      ⁢
                      a
                    
                  
                  +
                  
                    I
                    
                      1
                      ⁢
                      b
                    
                  
                
                =
                
                  
                    I
                    
                      2
                      ⁢
                      a
                    
                  
                  +
                  
                    I
                    
                      2
                      ⁢
                      b
                    
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  Δ
                  ⁢
                  
                    
                  
                  ⁢
                  
                    
                      V
                      
                        EB
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    /
                    
                      R
                      
                        3
                        ⁢
                        A
                      
                    
                  
                
                +
                
                  
                    V
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  /
                  
                    R
                    2
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    Δ
                    ⁢
                    
                      
                    
                    ⁢
                    
                      
                        V
                        
                          EB
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      /
                      
                        R
                        
                          3
                          ⁢
                          A
                        
                      
                    
                  
                  +
                  
                    
                      
                        [
                        
                          
                            V
                            
                              EB
                              ⁢
                              
                                
                              
                              ⁢
                              1
                            
                          
                          +
                          
                            
                              I
                              
                                2
                                ⁢
                                a
                              
                            
                            *
                            
                              R
                              
                                3
                                ⁢
                                B
                              
                            
                          
                        
                        ]
                      
                      /
                      
                        R
                        2
                      
                    
                    ⁢
                    
                      
                    
                    ⁢
                    where
                    ⁢
                    
                      
                    
                    ⁢
                    
                      R
                      2
                    
                  
                
                =
                
                  R
                  1
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  Δ
                  ⁢
                  
                    
                  
                  ⁢
                  
                    
                      V
                      
                        EB
                        ⁢
                        
                          
                        
                        ⁢
                        2
                      
                    
                    /
                    
                      R
                      
                        3
                        ⁢
                        A
                      
                    
                  
                
                +
                
                  
                    [
                    
                      
                        V
                        
                          EB
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      +
                      
                        
                          {
                          
                            Δ
                            ⁢
                            
                              
                            
                            ⁢
                            
                              
                                V
                                
                                  EB
                                  ⁢
                                  
                                    
                                  
                                  ⁢
                                  2
                                
                              
                              /
                              
                                R
                                
                                  3
                                  ⁢
                                  A
                                
                              
                            
                          
                          }
                        
                        *
                        
                          R
                          
                            3
                            ⁢
                            B
                          
                        
                      
                    
                    ]
                  
                  /
                  
                    R
                    1
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  (
                  
                    
                      V
                      
                        EB
                        ⁢
                        
                          
                        
                        ⁢
                        1
                      
                    
                    +
                    
                      Δ
                      ⁢
                      
                        
                      
                      ⁢
                      
                        V
                        
                          EB
                          ⁢
                          
                            
                          
                          ⁢
                          2
                        
                      
                      *
                      
                        [
                        
                          
                            R
                            1
                          
                          /
                          
                            R
                            
                              3
                              ⁢
                              A
                            
                          
                        
                        ]
                      
                      *
                      
                        {
                        
                          1
                          +
                          
                            
                              R
                              
                                3
                                ⁢
                                B
                              
                            
                            /
                            
                              R
                              1
                            
                          
                        
                        }
                      
                    
                  
                  )
                
                /
                
                  R
                  1
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                (
                
                  
                    V
                    
                      EB
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  +
                  
                    
                      [
                      
                        
                          R
                          1
                        
                        /
                        
                          R
                          
                            3
                            ⁢
                            A
                          
                        
                      
                      ]
                    
                    *
                    
                      {
                      
                        1
                        +
                        
                          
                            R
                            
                              3
                              ⁢
                              B
                            
                          
                          /
                          
                            R
                            1
                          
                        
                      
                      }
                    
                    *
                    
                      V
                      t
                    
                    *
                    Ln
                  
                
              
            
          
        
        
          
            
              
                
                  
                  ⁢
                  
                    [
                    
                      
                        
                          (
                          
                            I
                            
                              1
                              ⁢
                              a
                            
                          
                          )
                        
                        /
                        
                          (
                          
                            I
                            
                              2
                              ⁢
                              a
                            
                          
                          )
                        
                      
                      *
                      
                        (
                        
                          
                            Is
                            2
                          
                          /
                          
                            Is
                            1
                          
                        
                        )
                      
                    
                    ]
                  
                  )
                
                /
                R
              
              ⁢
              
                
              
              ⁢
              1
            
          
        
      
    
    
      
        (
        6
        )
      
    
  
  
    
      
        
          I
          
            2
            ⁢
            a
          
        
        =
        
          Δ
          ⁢
          
            
          
          ⁢
          
            
              V
              EB
            
            /
            
              R
              
                3
                ⁢
                A
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  
  
    
      
        
          
            
              
                I
                
                  1
                  ⁢
                  a
                
              
              =
              
                
                  I
                  1
                
                -
                
                  I
                  
                    1
                    ⁢
                    b
                  
                
              
            
          
        
        
          
            
              =
              
                
                  I
                  1
                
                -
                
                  
                    V
                    
                      EB
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  /
                  
                    R
                    1
                  
                
              
            
          
        
        
          
            
              =
              
                
                  
                    (
                    
                      
                        V
                        
                          EB
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                      
                      +
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        
                          V
                          
                            EB
                            ⁢
                            
                              
                            
                            ⁢
                            2
                          
                        
                        *
                        
                          [
                          
                            
                              R
                              1
                            
                            /
                            
                              R
                              
                                3
                                ⁢
                                A
                              
                            
                          
                          ]
                        
                        *
                        
                          {
                          
                            1
                            +
                            
                              
                                R
                                
                                  3
                                  ⁢
                                  B
                                
                              
                              /
                              
                                R
                                1
                              
                            
                          
                          }
                        
                      
                    
                    )
                  
                  /
                  
                    R
                    1
                  
                
                -
                
                  
                    V
                    
                      EB
                      ⁢
                      
                        
                      
                      ⁢
                      1
                    
                  
                  /
                  
                    R
                    1
                  
                
              
            
          
        
        
          
            
              =
              
                
                  (
                  
                    1
                    +
                    
                      
                        R
                        
                          3
                          ⁢
                          B
                        
                      
                      /
                      
                        R
                        1
                      
                    
                  
                  )
                
                *
                Δ
                ⁢
                
                  
                
                ⁢
                
                  
                    V
                    
                      EB
                      ⁢
                      
                        
                      
                      ⁢
                      2
                    
                  
                  /
                  
                    R
                    
                      3
                      ⁢
                      A
                    
                  
                
              
            
          
        
        
          
            
              =
              
                
                  (
                  
                    1
                    +
                    
                      
                        R
                        
                          3
                          ⁢
                          B
                        
                      
                      /
                      
                        R
                        1
                      
                    
                  
                  )
                
                *
                
                  I
                  
                    2
                    ⁢
                    a
                  
                
              
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




In Equation (8) the bipolar transistors Q1 and Q2 have PTAT bias currents. In Equations (6) to (9) R3A is the value of the resistance between selected connected point/closed switch S1-S4 and the second PNP bipolar transistor Q2, and R3B is the value of the resistance between selected connected point/closed switch S1-S4 and the second PMOS transistor M2. In Equation (6) VR2 is the voltage across the second resistor R2. I1-I3 are the currents through each of the PMOS transistors. I1a and I2a are the currents through the bipolar transistors, and I1b and I2b are the currents through R1 and R2 respectively.




  
    
      
        
          
            
              
                V
                ref
              
              =
              
              ⁢
              
                
                  I
                  3
                
                *
                
                  R
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In Equation (9) Vt is the thermal voltage (26 mV@ 25C), IS is the saturation current coefficient of the bipolar devices Q1 and Q2,
The PMOS transistors M1-M3 may have long channel lengths or an output impedance boost to minimize current differences I1-I3 due to different drain voltages and early voltage modulation effect.
According to Equation (9), switches S1-S4 trim the ratios R1/R3A and R3B/R1 to compensate for the temperature coefficient. By connecting switches S1-S4 to high impedance OPAMP input there would be negligible parasitic voltage drop across the switches S1-S4.
Switches S5-S8 trim the ratio R4/R1 to compensate the magnitude of the output voltage Vref. Switches S5-S8 do not affect the output voltage since the switches are not in the sense path of the Vref output terminal. The voltage drop across the switches S5-S8 will not affect the output voltage as long as there is enough supply voltage headroom.
By connecting the output terminal Vref to a high impedance load, any parasitic voltage drop across the portions of R4 between the output terminal Vref and the closed switch S5-S8 will be negligible. The circuit in FIG. 3 is configured so that the output voltage Vref is independent of the resistance and/or the voltage drop across the switches.
Any other errors in the circuit may be compensated for as is known in the art for example OPAMP offset may be handled by chopping.
A possible application for one or more embodiments is in a CMOS circuit. However it will be readily appreciated by the skilled reader that alternative applications are possible. Equally the skilled reader will appreciate the number of resistor sections and/or switches in each trim circuit can be tailored for the application.
The above example embodiments may be manufactured using fabrication techniques appropriate to the application. The trimming process in each case may occur at manufacturing for each circuit. Once the trimming has been completed the desired switch states may be stored in a Read Only Memory (ROM) or may be permanently set using fuses.
Referring to FIG. 4 an example method 400 of trimming R4 is shown, which may be employed during manufacturing of the example embodiment shown in FIG. 1a or FIG. 2. The initially closed switch is near the middle of the trim range eg: S3a (402). The output voltage Vref is measured (404). Based on the deviation ΔVref of the measured voltage Vref from the desired voltage Vdes (ΔVref=Vref−Vdes) (406), a look up table (408, 412) is used to select the correct trim switch to close (410, 414). The output voltage is again measured (416) and if it is within a threshold range Vdes±Vthres around the desired voltage (418), then the trimming process stops (420), otherwise the process is repeated.
Referring to FIG. 5 an example method 500 of trimming R4 is shown, which may be employed during manufacturing of the example embodiment shown in FIG. 3. The initially closed switch is near the middle of the trim range eg: S7 (502). The output voltage Vref is measured (504). Based on the deviation ΔVref of the measured voltage Vref from the desired voltage Vdes (ΔVref=Vref−Vdes) (506), a look up table (512) is used to select the correct trim switch to close (510, 514). The output voltage is again measured (516) and if it is within a threshold range Vdes±Vthres around the desired voltage (518), then the trimming process stops (520), otherwise the process is repeated.
Referring to FIG. 6 an example method 600 of trimming R3 is shown, which may be employed during manufacturing of the example embodiment shown in FIG. 3. The initially closed switch is near the middle of the trim range eg: S3 (602). The output voltage Vref is measured (604). Based on the deviation ΔVref of the measured voltage Vref from the desired voltage Vdes (ΔVref=Vref−Vdes) (606), a look up table (612) is used to select the correct trim switch to close (610, 614). The output voltage is again measured (616) and if it is within a threshold range Vdes±Vthres around the desired voltage (618), then the trimming process stops (620), otherwise the process is repeated.
Many variations of the above example embodiments, are possible within the scope of the following claims, as will be clear to a skilled reader.

## Claims

1. An apparatus comprising a bandgap reference voltage generator comprising:
a plurality of trimming resistors coupled in series;
a first plurality of trimming switches to couple a first bandgap terminal to a selected connection point between two of the plurality of trimming resistors to adjust the reference voltage, wherein said first plurality of trimming switches comprises at least one of a multi-way switch or a multiplexer; and
an output terminal coupled in series with the selected connection point and configured to provide a trimmed reference voltage a second plurality of trimming switches to coupled between the selected connected point and the output terminal.

2. The apparatus in claim 1, wherein the plurality of trimming resistors have a first end and a second end, the first end being coupled to a second bandgap terminal.

3. The apparatus in claim 2, wherein the output terminal is coupled to the second end.

4. The apparatus in claim 1, wherein the plurality of trimming resistors have a first end and a second end, the first end being coupled to ground.

5. The apparatus in claim 4, wherein the output terminal is coupled to the second end.

6. The apparatus of claim 1, further comprising a CMOS circuit.

7. An apparatus comprising a bandgap reference voltage generator comprising:
a plurality of trimming resistors coupled in series;
a first plurality of trimming switches to couple a first bandgap terminal to a selected connection point between two of the plurality of trimming resistors to adjust the reference voltage; and
an output terminal coupled in series with the selected connection point and configured to provide a trimmed reference voltage;
a second plurality of trimming switches to couple between the selected connection point and the output terminal, wherein
the plurality of trimming resistors have a first end and a second end, the first end being coupled to a second bandgap terminal, and
said first plurality of trimming switches and said second plurality of trimming switches comprise at least one of a double pole multi-way switch or a pair of multiplexers configured to be synchronized.

8. An apparatus comprising:
an operational amplifier having a positive input terminal, a negative input terminal and an OPAMP output;
a first resistance coupled to the positive input terminal;
a second resistance coupled to the negative input terminal;
a third resistance coupled between the negative input terminal and the first resistance;
a first PNP bipolar transistor having a first collector, first emitter and first base, the first emitter coupled to the positive input terminal, the first collector and the first base coupled to ground;
a second PNP bipolar transistor having a second collector, second emitter and second base, the second emitter coupled to the second resistance, the second collector and the second base coupled to ground; and
a fourth resistance coupled between the OPAMP output, and the first and third resistance.

9. The apparatus claimed in claim 8, wherein the fourth resistance comprises a first plurality of trimming resistors, having a first end and a second end, the first end being coupled to the first and third resistance, the apparatus further comprising a first plurality of trimming switches to couple the OPAMP output to a selected connection point between two of the plurality of trimming resistors.

10. The apparatus claimed in claim 9, further comprising:
an output terminal to provide a reference voltage, and
a second plurality of trimming switches coupled between the selected connection point and the output terminal.

11. The apparatus claimed in claim 9, further comprising:
an output terminal to provide a reference voltage and coupled to said second end.

12. An apparatus comprising:
an operational amplifier having a positive input terminal, a negative input terminal and an OPAMP output;
a first PMOS transistor having a first drain, a first source and a first gate, the first drain coupled to the negative input terminal, the first source coupled to a supply, and the first gate coupled to the OPAMP output;
a first resistance coupled to the negative input terminal;
a first PNP bipolar transistor having a first collector, a first emitter and a first base, the first emitter coupled to the negative input terminal, the first collector and the first base coupled to ground;
a second PMOS transistor having a second drain, a second source and a second gate, the second source coupled to the supply and the second gate coupled to the OPAMP output;
a second resistance coupled to the second drain;
a third plurality of trimming resistors having a first end and a second end, the first end of the third plurality of trimming resistors coupled to the second drain;
a first plurality of trimming switches to couple the positive input terminal to a selected connection point between two of the third plurality of trimming resistors;
a second PNP bipolar transistor having a second collector, a second emitter and a second base, the second emitter coupled to the second end of the third plurality of trimming resistors, the second collector and the second base coupled to ground;
a third PMOS transistor having a third drain, a third source and a third gate, the third source coupled to the supply and the third gate coupled to the OPAMP output;
a fourth plurality of trimming resistors having a first end and a second end, the second end of the fourth plurality of trimming resistors coupled to ground;
a second plurality of trimming switches to couple the third drain to a selected connection point between two of the fourth plurality of trimming resistors; and
an output terminal coupled to the first end of the fourth plurality of trimming resistors and provide a reference voltage.

13. The apparatus of claim 12, wherein the first and second plurality of trimming switches are configured to adjust the reference voltage.

14. The apparatus of claim 12, wherein the reference voltage is independent of a resistance of each of the third plurality of trimming resistors.

15. The apparatus of claim 12, wherein:
the first plurality of trimming switches are configured to adjust a temperature coefficient of the reference voltage, and
the second plurality of trimming switches are configured to adjust a magnitude of the reference voltage.

16. A method comprising:
providing a voltage reference circuit comprising
an amplifier having a first input terminal, a second input terminal and an output,
a first resistance coupled to the first input terminal,
a second resistance coupled to the second input terminal,
a third resistance coupled between the second input terminal and the first resistance,
a first transistor coupled between the first input terminal of the amplifier and a supply node, the first transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the first transistor is coupled to the third terminal,
a second transistor coupled between the second resistance and a supply node, the second transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the second transistor is coupled to the third terminal, and
an output terminal; and
selecting trim resistors to couple between the amplifier output, the first and third resistance, and the output terminal to trim the voltage at the output terminal.

17. A voltage reference comprising:
an amplifier having a first input terminal, a second input terminal and an output;
a first resistance coupled to the first input terminal;
a second resistance coupled to the second input terminal;
a third resistance coupled between the second input terminal and the first resistance;
a first transistor coupled between the first input terminal of the amplifier and a supply node, the first transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the first transistor is coupled to the third terminal;
a second transistor coupled between the second resistance and a supply node, the second transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the second transistor is coupled to the third terminal; and
a fourth resistance coupled between the output of the amplifier and the first and third resistance.

18. The voltage reference claimed in claim 17, wherein:
the fourth resistance comprises a first plurality of trimming resistors, having a first end and a second end, the first end being coupled to the first and third resistance; and
the voltage reference further comprises a first plurality of trimming switches to couple the amplifier output to a selected connection point between two of the plurality of trimming resistors.

19. The voltage reference claimed in claim 18, wherein the amplifier comprises an OPAMP.

20. The voltage reference claimed in claim 19, wherein the first input terminal of the amplifier comprises a positive input terminal, and the second input terminal of the amplifier comprises a negative input terminal.

21. The voltage reference claimed in claim 18, wherein:
the first and second transistor comprise bipolar transistors;
the first terminals of the first and second transistors comprise collectors;
the second terminals of the first and second transistors comprise emitters; and
the third terminals of the first and second transistors comprise bases.

22. The voltage reference claimed in claim 21, wherein the bipolar transistor comprises a PNP device.

23. The voltage reference claimed in claim 18, wherein the supply node comprises a ground node.

24. A voltage reference comprising:
an amplifier having a first input terminal, a second input terminal and an output;
a first transistor having a first terminal, a second terminal, and a third terminal, the first terminal coupled to the second input terminal of the amplifier, the second terminal coupled to a first supply, and the third terminal coupled to the output of the amplifier;
a first resistance coupled to the second input terminal;
a second transistor coupled between the second terminal of the amplifier and a second supply, the second transistor having a first terminal, a second terminal, and a third terminal, wherein first terminal of the second transistor is coupled to the third terminal of the second transistor;
a third transistor having a first terminal, a second terminal, and a third terminal, the second terminal of the third transistor coupled to the first supply and the third terminal of the third transistor coupled to the output of the amplifier;
a second resistance coupled to the first terminal of the third transistor;
a first plurality of trimming resistors having a first end and a second end, the first end of the first plurality of trimming resistors coupled to the first terminal of the third transistor;
a first plurality of trimming switches to couple the first input terminal of the amplifier to a selected connection point between two of the first plurality of trimming resistors;
a fourth transistor coupled between the second end of the first plurality of trimming resistors and the second supply, the fourth transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the fourth transistor is coupled to the third terminal of the fourth transistor;
a fifth transistor having a first terminal, a second terminal, and a third terminal, the second terminal of the fifth transistor coupled to the first supply and the third terminal of the fifth transistor coupled to the output of the amplifier;
a third resistance coupled between the first terminal of the fifth transistor and the second supply; and
an output terminal coupled to the first terminal of the fifth transistor to provide a reference voltage.

25. The voltage reference of claim 24, wherein:
the first, third and fifth transistors comprise MOS transistors;
the first terminals of the first, third and fifth transistors comprise drains;
the second terminals of first, third and fifth transistors comprise sources; and
the third terminals of first, third and fifth transistors comprise gates.

26. The voltage reference of claim 25, wherein the MOS transistors comprise PMOS transistors.

27. The voltage reference of claim 24, wherein:
the second and fourth transistors comprise bipolar transistors;
the first terminals of the second and fourth transistors comprise collectors;
the second terminals of the second and fourth transistors comprise emitters; and
the third terminals of the second and fourth transistors comprise bases.

28. The voltage reference of claim 27, wherein the bipolar transistors comprise PNP transistors.

29. The voltage reference of claim 28, wherein the second supply comprises ground.

30. The voltage reference of claim 24, wherein the third resistance comprises:
a second plurality of trimming resistors having a first end and a second end, the second end of the second plurality of trimming resistors coupled to the second supply; and
a second plurality of trimming switches to couple the first terminal of the fifth transistor to a selected connection point between two of the second plurality of trimming resistors.

31. A method comprising:
providing a voltage reference circuit comprising:
an amplifier having a first input terminal, a second input terminal and an output;
a first transistor having a first terminal, a second terminal, and a third terminal, the first terminal coupled to the second input terminal of the amplifier, the second terminal coupled to a first supply, and the third terminal coupled to the output of the amplifier;
a first resistance coupled to the second input terminal;
a second transistor coupled between the second terminal of the amplifier and a second supply, the second transistor having a first terminal, a second terminal, and a third terminal, wherein first terminal of the second transistor is coupled to the third terminal of the second transistor;
a third transistor having a first terminal, a second terminal, and a third terminal, the second terminal of the third transistor coupled to the first supply and the third terminal of the third transistor coupled to the output of the amplifier;
a second resistance coupled to the first terminal of the third transistor;
a fourth transistor coupled to the second supply, the fourth transistor having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the fourth transistor is coupled to the third terminal of the fourth transistor;
a fifth transistor having a first terminal, a second terminal, and a third terminal, the second terminal of the fifth transistor coupled to the first supply and the third terminal of the fifth transistor coupled to the output of the amplifier;
a third resistance to couple between the first terminal of the fifth transistor and the second supply; and

an output terminal coupled to the first terminal of the fifth transistor to provide a reference voltage,
selecting from a first plurality of trim resistors to couple between the first terminal of the third transistor, the first input terminal of the amplifier and the fourth transistor to trim the voltage at the output terminal.

32. The method of claim 31, wherein:
the third resistance comprises a second plurality of trim resistors; and
the method further comprises selecting from the second plurality of trim resistors to trim the voltage at the output terminal.

33. The method of claim 31, wherein selecting from the first plurality of trim resistors adjusts a temperature coefficient of the voltage at the output terminal.