# Patent

## Title
Bandgap voltage reference circuit working under wide supply range

## Abstract

Bandgap voltage reference circuitry working under a wide supply range is provided. The bandgap reference circuitry in accordance with the invention may provide an accurate reference voltage for systems with a supply voltage that may range from approximately 1.8V to approximately 5.5V. The circuitry may be designed using a standard process and standard devices without requiring the use of special low-threshold devices or deep N-well processes and may generate an internal regulated supply voltage that may remain at a substantially stable voltage level, in spite of variations in the power supply voltage. The bandgap reference circuitry may further use a voltage clamping structure to reduce leakage currents.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of provisional application 60/648,015 filed Jan. 28, 2005, which is hereby incorporated by reference herein in its entirety.
This is a divisional of commonly-assigned U.S. patent application Ser. No. 11/159,503, filed Jun. 22, 2005, now abandoned, which is hereby incorporated by reference herein in its entirety.


BACKGROUND OF THE INVENTION
This invention relates to bandgap reference circuitry, having a wide supply range, that may generate an accurate and stable voltage reference.
Many precision analog circuits operate with supply voltages that are in the 3V and 5V ranges. This is due in part to the increasing use of battery powered systems and semiconductor voltage specifications. In order to reduce the costs of these systems, the analog circuits need to be designed using standard manufacturing processes and devices.
Accurate and stable voltage reference circuits are required in almost every analog chip. Voltage reference circuits are capable of providing substantially constant reference voltages that are designed to be substantially independent of temperature and process variations.
As is known in the art, a bandgap voltage reference is a circuit having a positive temperature coefficient and a negative temperature coefficient that are combined to have a nominally zero temperature coefficient. A voltage with a negative temperature coefficient is derived from the base-emitter voltage of a bipolar transistor and a voltage with a positive temperature coefficient is derived from the difference between two bipolar transistors operating with different current densities. Summing the voltage with the negative temperature coefficient and the voltage with the positive temperature coefficient, according to a proper ratio, will result in a voltage having substantially zero temperature dependence.
The voltage levels of typical voltage reference circuits must remain within a stable and well-defined range in order to maintain a stable voltage reference output. However, in certain low-power devices, such as hard-disc-driving chips, accurate voltage references are needed both for the power-good mode (e.g., in the 3V or 5v ranges) and for low-power modes (e.g., an emergency-retract mode, in which the supply voltage may be as low as 1.8V).
In view of the foregoing, it would be desirable to provide a bandgap voltage reference circuit that may provide a stable voltage reference output under a wide range of supply voltages.
SUMMARY OF THE INVENTION
These and other objects of the invention are provided by bandgap voltage reference circuitry working under a wide supply range.
A bandgap reference circuit in accordance with the invention may provide an accurate reference voltage for systems having a supply voltage that may, for example, range from approximately 1.8V to approximately 5.5V. The bandgap reference circuit may be designed using a standard process and standard devices and without requiring the use of special low-threshold devices or deep N-well processes.
A bandgap reference circuit in accordance with the invention may generate an internal regulated supply voltage that may remain at a substantially stable voltage level, in spite of variations in the power supply voltage. A high-gain feedback loop may maintain the stability of the internal regulated power supply voltage, while the power supply voltage varies. The high-gain feedback loop may also improve the power supply rejection ratio (PSRR) from the power supply to the internal regulated power supply.
The bandgap reference circuit, in accordance with the invention, may further increase the accuracy of the voltage reference at high supply voltages by using a clamping structure to reduce leakage currents.
Further features of the invention, its nature and various advantages, will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a simplified diagram of a bandgap voltage reference circuit in accordance with some aspects of the present invention.
FIG. 2 shows a simplified small-signal circuit model of the bandgap voltage reference circuit in accordance with some aspects of the present invention.
FIG. 3 shows a simplified diagram of a bandgap voltage reference circuit with a low-pass filter in accordance with some aspects of the present invention.
FIG. 4 shows a simplified small-signal circuit model of the bandgap voltage reference circuit with a low-pass filter in accordance with some aspects of the present invention.
FIG. 5 shows a simplified diagram of a bandgap voltage reference circuit illustrating leakage currents in accordance with some aspects of the present invention.
FIG. 6 shows a simplified diagram of a bandgap voltage reference circuit having a clamping structure in accordance with some aspects of the present invention.



DETAILED DESCRIPTION
FIG. 1 shows bandgap voltage reference circuit 100 in accordance with some aspects of the present invention. Bandgap reference circuit 100 generates bandgap reference voltage VBG from power supply voltage Vpower using standard processes and devices. Vpower may, for example, range from a low voltage level of approximately 1.8V to a high voltage level of approximately 5.5V. Bandgap reference voltage VBG preferably remains at a substantially stable voltage level during temperature variations of bandgap voltage reference circuit 100, as well as during variations of the supply voltage Vpower.
Bandgap voltage reference circuit may primarily consist of three components, PTAT current generation circuitry 110, regulated voltage generation circuitry and feedback loop 120, and bandgap reference voltage output circuitry 130. The operation of bandgap reference circuit 100, its underlying components and their interrelation is explained in greater detail below.
In bandgap reference circuit 100, transistors P1, P2, P3, P4, P5, P6, and P7 all have the same W/L ratios. Transistors N1, N2, and N3 are also designed to have the same W/L ratios. The W/L ratios of transistors P15 and P14 are designed such that the W/L ratio of P15 is a multiple, A, times the W/L ratio of P14. Other W/L ratios may be used according to other embodiments of the present invention. However using the same W/L ratios may simplify the explanation and analysis of the circuit.
Transistors P1, P2, Q1, and Q2 and resistor R1, of PTAT current generation circuitry 110, are configured to generate reference current IPTAT. As long as Node1 and Node2 remain at substantially equal voltages, reference current IPTAT is said to be proportional to absolute temperature (PTAT), i.e., IPTAT is proportional to the temperature of bandgap reference circuit 100. IPTAT has a positive temperature coefficient and thus the current increases with increased temperature.
Transistor P7 of regulated voltage generation circuitry and feedback loop 120 may help maintain the equality condition of Node1 and Node2. The reference current passing through transistor P1 is mirrored through transistor P7 by transistors N2 and N7. With substantially equal currents passing through transistors P1 and P7, the gate-source voltage drop of P1 is substantially equal to the gate-source voltage drop of P7. Thus, connecting the gate of transistor P7 to Node2 maintains Node2 at a voltage level substantially equal to the voltage level of Node1 (i.e, approximately one gate-source voltage drop below VREG).
Although multiple current mirror pairs are used in bandgap reference circuit 100 to transfer reference current IPTAT from PTAT current generation circuitry 110 to regulated voltage generation circuitry and feedback loop 120 and to bandgap reference voltage output circuitry 130, this is just one embodiment of the present invention. Other current mirror configurations or current mirror alternatives may be also used in accordance with the present invention.
PTAT current IPTAT may be calculated from the equation,




  
    
      I
      PTAT
    
    =
    
      
        
          Δ
          ⁢
          
            
          
          ⁢
          
            V
            BE
          
        
        
          R
          ⁢
          
            
          
          ⁢
          1
        
      
      =
      
        
          V
          T
        
        ⁢
        
          
        
        ⁢
        ln
        ⁢
        
          
        
        ⁢
        N
      
    
  
  ⁢
  
    
  




where ΔVBE is the difference in the base-emitter voltages of transistors Q1 and Q2, VT is the thermal voltage constant, and N is the ratio of the emitter areas of Q1 and Q2.

Current mirrors in bandgap voltage reference circuit 100 mirror the PTAT current generated by transistors P1, P2, Q1, and Q2 through transistors P3-P6, N1-N3, N9-N11, P10-P11 and Q3. Accordingly, the voltage level at the output of bandgap reference circuit 100 may be expressed as,




  
    V
    BG
  
  =
  
    
      
        V
        
          BE
          ⁢
          
            
          
          ⁢
          3
        
      
      +
      
        
          I
          PTAT
        
        ×
        R
        ⁢
        
          
        
        ⁢
        2
      
    
    =
    
      
        
          V
          
            BE
            ⁢
            
              
            
            ⁢
            3
          
        
        +
        
          
            
              Δ
              ⁢
              
                
              
              ⁢
              
                V
                BE
              
            
            
              R
              ⁢
              
                
              
              ⁢
              1
            
          
          ×
          R
          ⁢
          
            
          
          ⁢
          2
        
      
      =
      
        
          V
          
            BE
            ⁢
            
              
            
            ⁢
            3
          
        
        +
        
          
            V
            T
          
          ⁢
          
            
          
          ⁢
          
            
              R
              ⁢
              
                
              
              ⁢
              2
            
            
              R
              ⁢
              
                
              
              ⁢
              1
            
          
          ⁢
          
            
          
          ⁢
          ln
          ⁢
          
            
          
          ⁢
          N
        
      
    
  




where VBE3 is the base-emitter voltage of transistor Q3.

Bandgap reference voltage VBG may be substantially independent of the temperature of bandgap voltage reference circuit 100. As seen from the above equation, bandgap reference voltage VBG is equal to the sum of VBE3 and IPTAT multiplied by resistor R2. VBE3 has a negative temperature coefficient (i.e., the value of VBE3 decreases as temperature increases) and IPTAT has a positive temperature coefficient (i.e., the value of IPTAT increases as temperature increases). Selecting suitable sizes for R1, R2, and N may allow the temperature coefficients of each of the terms in the equation for the bandgap reference voltage to substantially cancel each other out. Thus, the temperature coefficient of the bandgap reference voltage may be designed to be substantially equal to zero at 25° C.
Component 120 of bandgap reference circuit 100 may generate an internal regulated supply voltage, VREG and may have a feedback loop to maintain the voltage level of VREG. Internal regulated supply voltage, VREG, is generated in bandgap voltage reference circuit 100 to allow the circuit to operate with a low supply voltage. The DC voltage level of VREG is approximately equal to the base-emitter voltage of transistor Q2 plus the gate-source voltage of transistor P7. Thus VREG can be expressed as,

VREG=VBE2+VGS—P7.

The minimum supply voltage Vpower can thus be expressed as,

Vpower=VREG+Vds—P15=VBE2+VGS—P7+VDS—P15 

where VDS—P15 is the drain-source voltage of P15. Estimating the minimum operating values of each of the terms in the equation for Vpower, the minimum operating value of Vpower may be approximated to be approximately 1.8V with VREG estimated to be approximately 1.5V.

Common-source configured transistor N6 is connected to Node3. Neglecting N6 as well as Cc and Rc, Node3 is a high impedance node that does not have a well defined DC voltage level. By adding NMOS transistor N6 having a gate that is connected to Node3 and source that is connected to ground, the DC voltage level of Node3 may be set by the gate-to-source voltage of N6. Transistor N6 may also maintain the voltage of VREG as part of a negative feedback loop that maintains the substantial equality of Node1 and Node2. For example, when the voltage level of VREG rises, the voltage level of Node1 may also rise, due to the diode-connected PMOS transistor P1. However, the voltage level of Node2 may not change significantly due to the large channel resistance of PMOS transistor P2. Further, the drain currents of PMOS transistor P1 and of NMOS transistors N2 and N7 may also not change significantly in response to the rise of VREG. In contrast, the gate-to-source voltage of PMOS transistor P7 may change in accord with the change in the voltage level VREG. This change in the gate-to-source voltage of P6 may increase the drain current of P7 which may increase the voltage level of Node3. The increase in the voltage level of Node3 may then increase the current flowing through transistor N6, which may the reduce the voltage level of VREG. The high impedance of Node3 enhances the loop-gain of this negative feedback loop. The high loop-gain of the feedback loop also improves the power supply rejection ratio (PSRR) from the power supply voltage Vpower to the regulated supply voltage VREG. In turn, this PSRR reduction reduces the power supply noise on the bandgap reference voltage VBG. Miller compensation capacitor CC and resistor RC are included in the feedback loop to improve the stability of the loop.
The stability of the feedback loop of bandgap reference circuit 100 may be estimated by breaking the feedback loop at node 101 and performing a small signal analysis. FIG. 2 shows a simplified small signal circuit model 200 of bandgap voltage reference circuit 100 without any parasitic capacitance. Circuit model 200 may be used to show the operation of the feedback loop of bandgap voltage reference circuit 100 in greater detail. Voltage input, VIN represents the voltage variations at the regulated supply VREG. Neglecting the high frequency parasitic poles of the current mirrors and the pole at VREG due to the pole splitting due to the Miller compensation, the current flowing through branches 202 and 203 can be written as follows:




  
    
      
        
          
            
              (
              
                
                  V
                  IN
                
                -
                
                  V
                  1
                
              
              )
            
            ×
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                1
              
            
          
          +
          
            
              
                V
                IN
              
              -
              
                V
                1
              
            
            
              r
              1
            
          
        
        =
        
          
            V
            1
          
          
            
              R
              ⁢
              
                
              
              ⁢
              1
            
            +
            
              r
              
                e
                ⁢
                
                  
                
                ⁢
                1
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  
  
    
      
        
          
            
              (
              
                
                  V
                  IN
                
                -
                
                  V
                  1
                
              
              )
            
            ×
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                1
              
            
          
          +
          
            
              
                V
                IN
              
              -
              
                V
                2
              
            
            
              r
              2
            
          
        
        =
        
          
            V
            2
          
          
            r
            
              e
              ⁢
              
                
              
              ⁢
              2
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




where gm1 is the transconductance of transistors P1 through P7, re1 is the emitter resistance of transistor Q1, re2 is the emitter resistance of transistor Q2, r1 is the output impedance of transistor P1, and r2 is the output impedance of transistor P2. Solving equations (1) and (2) for V1 and V2, assuming r1>>1/gm1 and r2>>re1 results in





  
    V
    1
  
  =
  
    
      
        
          
            V
            IN
          
          ⁡
          
            (
            
              
                R
                ⁢
                
                  
                
                ⁢
                1
              
              +
              
                r
                
                  e
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            )
          
        
        
          
            1
            ⁢
            
              /
            
            ⁢
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                1
              
            
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            1
          
          +
          
            r
            
              e
              ⁢
              
                
              
              ⁢
              1
            
          
        
      
      ⁢
      
        
      
      ⁢
      and
      ⁢
      
        
      
      ⁢
      
        V
        2
      
    
    =
    
      
        V
        IN
      
      ×
      
        (
        
          1
          -
          
            
              
                R
                ⁢
                
                  
                
                ⁢
                1
              
              +
              
                r
                
                  e
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            
              
                1
                ⁢
                
                  /
                
                ⁢
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
              
              +
              
                R
                ⁢
                
                  
                
                ⁢
                1
              
              +
              
                r
                
                  e
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
          
        
        )
      
      ⁢
      
        g
        
          m
          ⁢
          
            
          
          ⁢
          1
        
      
      ⁢
      
        
      
      ⁢
      
        
          r
          
            e
            ⁢
            
              
            
            ⁢
            1
          
        
        .
      
    
  




The currents through branches 202 and 203, i1 and i2, are generated by VIN VIN represents the variation in the voltage of regulated power supply VREG. Currents i1 and i2 can be expressed as




  
    i
    1
  
  =
  
    
      
        
          V
          1
        
        
          
            R
            ⁢
            
              
            
            ⁢
            1
          
          +
          
            r
            
              e
              ⁢
              
                
              
              ⁢
              1
            
          
        
      
      ⁢
      
        
      
      ⁢
      and
      ⁢
      
        
      
      ⁢
      
        i
        2
      
    
    =
    
      
        g
        
          m
          ⁢
          
            
          
          ⁢
          1
        
      
      ⁢
      
        
      
      ⁢
      
        
          (
          
            
              V
              in
            
            -
            
              V
              2
            
          
          )
        
        .
      
    
  




Substituting for V1 and V2 in the above equation,




  
    
      
        i
        1
      
      =
      
        
          
            V
            IN
          
          
            
              1
              ⁢
              
                /
              
              ⁢
              
                g
                
                  m
                  ⁢
                  
                    
                  
                  ⁢
                  1
                
              
            
            +
            
              R
              ⁢
              
                
              
              ⁢
              1
            
            +
            
              r
              
                e
                ⁢
                
                  
                
                ⁢
                1
              
            
          
        
        =
        
          
            V
            IN
          
          ⁢
          
            g
            mx
          
        
      
    
    ,
    
      
        where
        ⁢
        
          
        
        ⁢
        
          g
          mx
        
      
      =
      
        1
        
          
            1
            ⁢
            
              /
            
            ⁢
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                1
              
            
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            1
          
          +
          
            r
            
              e
              ⁢
              
                
              
              ⁢
              1
            
          
        
      
    
  




  
    
      i
      2
    
    =
    
      
        
          V
          IN
        
        ⁢
        
          
        
        ⁢
        
          
            g
            
              m
              ⁢
              
                
              
              ⁢
              1
            
          
          ⁡
          
            [
            
              1
              -
              
                
                  (
                  
                    1
                    -
                    
                      
                        
                          R
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                        +
                        
                          r
                          
                            e
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                      
                      
                        
                          1
                          ⁢
                          
                            /
                          
                          ⁢
                          
                            g
                            
                              m
                              ⁢
                              
                                
                              
                              ⁢
                              1
                            
                          
                        
                        +
                        
                          R
                          ⁢
                          
                            
                          
                          ⁢
                          1
                        
                        +
                        
                          r
                          
                            e
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                        
                      
                    
                  
                  )
                
                ⁢
                
                  
                
                ⁢
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  r
                  
                    e
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
            ]
          
        
      
      =
      
        
          
            V
            IN
          
          ⁢
          
            
          
          ⁢
          
            g
            
              m
              ⁢
              
                
              
              ⁢
              1
            
          
          ⁢
          
            {
            
              1
              -
              
                
                  [
                  
                    1
                    -
                    
                      
                        (
                        
                          
                            R
                            ⁢
                            
                              
                            
                            ⁢
                            1
                          
                          +
                          
                            r
                            
                              e
                              ⁢
                              
                                
                              
                              ⁢
                              1
                            
                          
                        
                        )
                      
                      ⁢
                      
                        g
                        mx
                      
                    
                  
                  ]
                
                ⁢
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                
                  r
                  
                    e
                    ⁢
                    
                      
                    
                    ⁢
                    2
                  
                
              
            
            }
          
        
        =
        
          
            V
            IN
          
          ⁢
          
            
          
          ⁢
          
            g
            
              m
              ⁢
              
                
              
              ⁢
              1
            
          
          ⁢
          B
        
      
    
  



where B=1−[1−(R1+re1)gmx]gm1re2.

Variation current i1 is mirrored through transistor P15 of bandgap voltage reference circuit 100, which is represented in small signal circuit model 200 by current i3. Assuming a W/L ratio between P15 and P14 of approximately A to 1, current i3 may be expressed as

i3=Ai1=AVINgmx 

Applying KCL at node3

i2−i1=i4+i5 

which may also be written as





  
    
      
        
          
            V
            IN
          
          ⁡
          
            (
            
              
                
                  g
                  
                    m
                    ⁢
                    
                      
                    
                    ⁢
                    1
                  
                
                ⁢
                B
              
              -
              
                g
                mx
              
            
            )
          
        
        =
        
          
            
              V
              3
            
            
              r
              3
            
          
          +
          
            
              
                V
                3
              
              -
              
                V
                OUT
              
            
            
              
                R
                c
              
              +
              
                1
                ⁢
                
                  /
                
                ⁢
                
                  C
                  c
                
                ⁢
                
                  
                
                ⁢
                S
              
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




where r3 is the impedance seen at node3.

Applying KCL at VOUT 

i6+i7=i3+i5 

which may also be written as





  
    
      
        
          
            
              V
              3
            
            ⁢
            
              g
              
                m
                ⁢
                
                  
                
                ⁢
                6
              
            
          
          +
          
            
              V
              out
            
            
              r
              reg
            
          
        
        =
        
          
            
              
                V
                3
              
              -
              
                V
                out
              
            
            
              
                R
                c
              
              -
              
                1
                ⁢
                
                  /
                
                ⁢
                
                  C
                  c
                
                ⁢
                
                  
                
                ⁢
                S
              
            
          
          +
          
            
              V
              
                i
                ⁢
                
                  
                
                ⁢
                n
              
            
            ⁢
            
              g
              mx
            
            ⁢
            
              
            
            ⁢
            A
          
        
      
    
    
      
        (
        4
        )
      
    
  




where rREG is the impedance seen at VOUT and gm6 is the transconductance of transistor N6.

From equations (3) and (4), the transfer function of the feedback loop can be written as




  
    
      
        V
        out
      
      
        V
        
          i
          ⁢
          
            
          
          ⁢
          n
        
      
    
    ⁢
    
      
    
    ⁢
    
      (
      S
      )
    
  
  =
  
    
      -
      
        g
        my
      
    
    ⁢
    
      
    
    ⁢
    
      r
      3
    
    ⁢
    
      
    
    ⁢
    
      g
      
        m
        ⁢
        
          
        
        ⁢
        6
      
    
    ⁢
    
      r
      reg
    
    ⁢
    
      
    
    ⁢
    
      
        
          
            [
            
              
                R
                c
              
              -
              
                
                  1
                  
                    g
                    
                      m
                      ⁢
                      
                        
                      
                      ⁢
                      6
                    
                  
                
                ⁢
                
                  
                
                ⁢
                
                  (
                  
                    1
                    +
                    
                      A
                      ⁢
                      
                        
                      
                      ⁢
                      
                        g
                        mx
                      
                      ⁢
                      
                        /
                      
                      ⁢
                      
                        g
                        my
                      
                    
                  
                  )
                
              
            
            ]
          
          ⁢
          
            C
            c
          
          ⁢
          
            
          
          ⁢
          S
        
        +
        1
      
      
        
          
            g
            
              m
              ⁢
              
                
              
              ⁢
              6
            
          
          ⁢
          
            r
            reg
          
          ⁢
          
            C
            c
          
          ⁢
          
            
          
          ⁢
          S
        
        +
        1
      
    
  




where gmy=gm1B−gmx.

From this transfer function, it can be seen that the DC loop gain of the feedback loop is gmyr3 gm6rREG. The feedback loop has a dominant pole at 1/gm6rREGr3Cc due to Miller compensation. Further, if the value of RC is less than




  
    
      1
      
        g
        
          m
          ⁢
          
            
          
          ⁢
          6
        
      
    
    ⁢
    
      
    
    ⁢
    
      (
      
        1
        +
        
          A
          ⁢
          
            
          
          ⁢
          
            g
            mx
          
          ⁢
          
            /
          
          ⁢
          
            g
            my
          
        
      
      )
    
  
  ,




there is a zero in the right-hand plane with a frequency close to the unity-gain bandwidth of the system. This zero may affect the stability of the system.

FIG. 3 shows bandgap voltage reference circuit 300 in accordance with another embodiment of the present invention which may be able to prevent this zero in the right-hand plane. Bandgap voltage reference circuit 300 includes a low-pass filter including resistor Rx and capacitor Cx. FIG. 4 shows a simplified small signal circuit model 400 of bandgap voltage reference circuit 300. With the addition of the low pass filter, node equations (3) and (4) of a simplified small signal circuit model 200 may be rewritten as,




  
    
      
        
          
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If the value of RxCx is made much larger than the other node time constants of the circuit, the new transfer function may be expressed as





  
    
      
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The dominant poles remains at 1/(gm6rregr3Cc), but the zero is moved to 1/(Rc−1/gm6)Cc. This zero may be placed in the left-hand plane by making the value of RC greater than 1/gm6, which is practical. Accordingly, the low pass filter of bandgap voltage reference circuit 300 may not have the stability problem of bandgap voltage reference circuit 100.

As previously described with respect to bandgap voltage reference circuit 100, the PTAT current is generated by transistors P1, P2, Q1, and Q2 and resistor R1. The PTAT current is mirrored into bandgap reference voltage output circuitry 130 where it passes through resistor R2 and transistor Q3 to generate the bandgap reference voltage output VBG. Transistors P1, P2, Q1, and Q2 of PTAT current generation circuitry 310 are all powered by regulated voltage supply VREG. Bandgap reference voltage output circuitry 330, however, may need a higher voltage power supply. For example, the minimum power supply voltage needed to keep PMOS transistors P11 and P12 operating in the saturation region is approximately equal to VBG+VDsat(P11)+VDsat(P12), which may be around 1.7V. As VREG is only around 1.5V, there is a headroom problem. Accordingly, transistors P9 through P13 of bandgap reference voltage output circuitry 330 are all directly powered from power supply voltage Vpower instead of regulated voltage supply VREG.
When Vpower is at a relatively high voltage level (e.g., above 5V), a leakage current through transistor N12 may cause a rise in bandgap voltage reference output VBG. FIG. 5 shows bandgap voltage reference circuit 500 which may illustrate this leakage current. Bandgap voltage reference circuit 500 includes reverse-biased body diode 505 that is connected between node5 and ground. Reverse-biased body diode 505 is a parasitic diode of transistor N12. Because the bandgap reference circuit is fabricated without using a deep-Nwell process, the substrate of transistor N12 is not connected to ground. As a result, there is a reverse-biased body diode between the drain of N12 to ground, which may be modeled by diode 505.
The voltage level of Node5 is one gate-source voltage drop below the power supply voltage Vpower. When bandgap voltage reference circuit 500 is operating with a power supply voltage of around 5V or greater, Node5 is also at a relatively high voltage. As such, the reverse-biased voltage of diode 505 is also high, which may result in a high leakage current through diode 505. The leakage current through diode 505 may be expressed as

Ileakage=Is(e−V5/nVT−1)

where V5 is the voltage at Node5 and Is represents the scale current of the device, given by

Is=AD*JS 

where JS is the source-drain junction current density and AD is the area of the source and drain.

When bandgap voltage reference circuit 500 operates with a power supply voltage Vpower at a voltage level of approximately 5V or greater, the leakage current through diode 505 may be large enough to create an error current that is mirrored to transistor P11. This error current may increase the current flowing through transistor P11 and may thus introduce a non-linear error to bandgap reference voltage output VBG. The higher the voltage of the power supply voltage, the higher the error in VBG.
FIG. 6 shows bandgap voltage reference circuit 600 in accordance with this invention which may reduce this leakage current. Bandgap voltage reference circuit 600 contains additional transistors N16 through N18 and transistor P16 which may generate a clamping voltage VCLAMP. Clamping voltage VCLAMP powers transistors N10 through N13, transistors P9 through P13, transistor Q3, as well as resistor R2. Clamping voltage VCLAMP varies only slightly with variations in power supply voltage Vpower and maintains a voltage of around 3v. With a voltage of around 3V, only a negligible error is caused by a leakage current through transistor N12. Accordingly, bandgap voltage reference circuit 600 may generate a more accurate bandgap reference voltage VBG. Further, the PSRR of bandgap voltage reference circuit 600 remains high due to the high output impedance of transistor P16 and the cascode structure of transistors P11 and P12.
Thus it is seen that bandgap voltage reference circuitry working under a wide supply range, has been provided. It will be understood that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.

## Claims

1. A method for generating a bandgap reference voltage from an input power supply voltage having a wide voltage range, said method comprising:
generating a regulated power supply voltage from the input power supply voltage;
maintaining the regulated power supply voltage at a substantially constant voltage level relative to the input power supply voltage;
generating a proportional to absolute temperature (“PTAT”) current in a first resistor using PTAT current generation circuitry comprising a first diode-connected transistor having a first voltage drop and a second diode-connected transistor having a second voltage drop, wherein the PTAT current is proportional to a difference between the first and second voltage drops, and wherein the first and second diode-connected transistors are powered by the regulated power supply voltage;
generating a clamping voltage from the input power supply voltage that is greater than the regulated power supply voltage and less than the input power supply voltage;
maintaining the clamping voltage at a substantially constant voltage level relative to the input power supply voltage; and
generating the bandgap reference voltage using bandgap reference voltage generation circuitry comprising a third diode-connected transistor and a second resistor that are powered by the clamping voltage, wherein the bandgap reference voltage is generated using the PTAT current to produce a voltage across the second resistor proportional to a ratio between the first resistor and the second resistor.

2. The method of claim 1 wherein the input power supply voltage ranges from approximately 1.8 volts to approximately 5.5 volts.

3. The method of claim 2 wherein the bandgap reference voltage is generated at a substantially stable voltage level throughout the range of the input power supply voltage.

4. The method of claim 1
wherein the regulated power supply voltage is approximately 1.2 volts.

5. The method of claim 1 wherein the clamping voltage is approximately 3 volts.

6. The method of claim 5 wherein the clamping voltage level is substantially stable throughout the range of the input power supply voltage.

7. The method of claim 1 wherein a negative feedback loop maintains the regulated power supply voltage at a substantially constant voltage level relative to the input power supply voltage, and wherein the negative feedback loop maintains the PTAT current proportional to temperature.

8. An apparatus for generating a bandgap reference voltage from an input power supply voltage having a wide voltage range, said apparatus comprising:
means for generating a regulated power supply voltage from the input power supply voltage;
means for maintaining the regulated power supply voltage at a substantially constant voltage level relative to the input power supply voltage;
means for generating a proportional to absolute temperature (“PTAT”) current in a first resistor using PTAT current generation circuitry comprising a first diode-connected transistor having a first voltage drop and a second diode-connected transistor having a second voltage drop, wherein the PTAT current is proportional to a difference between the first and second voltage drops, and wherein the first and second diode-connected transistors are powered by the regulated power supply voltage;
means for generating a clamping voltage from the input power supply voltage that is greater than the regulated power supply voltage and less than the input power supply voltage;
means for maintaining the clamping voltage at a substantially constant voltage level relative to the input power supply voltage; and
means for generating the bandgap reference voltage using bandgap reference voltage generation circuitry comprising a third diode-connected transistor and a second resistor that are powered by the clamping voltage, wherein the bandgap reference voltage is generated using the PTAT current to produce a voltage across the second resistor proportional to a ratio between the first resistor and the second resistor.

9. The apparatus of claim 8 wherein the input power supply voltage ranges from approximately 1.8 volts to approximately 5.5 volts.

10. The apparatus of claim 9 wherein the bandgap reference voltage is generated at a substantially stable voltage level throughout the range of the input power supply voltage.

11. The apparatus of claim 8 wherein the regulated power supply voltage is approximately 1.2 volts.

12. The apparatus of claim 8 wherein the clamping voltage is approximately 3 volts.

13. The apparatus of claim 12 wherein the clamping voltage level is substantially stable throughout the range of the input power supply voltage.

14. The apparatus of claim 8 further comprising negative feedback means that maintain the regulated power supply voltage at a substantially constant voltage level relative to the input power supply voltage, wherein the negative feedback means maintain the PTAT current proportional to temperature.

15. A bandgap voltage reference circuit with an input power supply voltage having a wide voltage range comprising:
a regulated power supply circuit that generates a regulated power supply voltage from the input power supply voltage and that maintains the regulated power supply voltage at a substantially constant voltage level relative to the input power supply voltage;
a proportional to absolute temperature (“PTAT”) current generating circuit that generates a PTAT current in a first resistor, wherein the PTAT current generating circuit comprises a first diode-connected transistor having a first voltage drop and a second diode-connected transistor having a second voltage drop that are powered by the regulated power supply, and wherein the PTAT current is proportional to a difference between the first and second voltage drops;
a clamping voltage generating circuit that generates a clamping voltage from the input power supply voltage that is greater than the regulated power supply voltage and less than the input power supply voltage and that maintains the clamping voltage at a substantially constant voltage level relative to the input power supply voltage; and
an output circuit that comprises a third diode-connected transistor and a second resistor that are powered by the clamping voltage, wherein the output circuit generates the bandgap reference voltage using the PTAT current to produce a voltage across the second resistor proportional to a ratio between the first resistor and the second resistor.

16. The bandgap voltage reference circuit of claim 15 wherein the input power supply voltage ranges from approximately 1.8 volts to approximately 5.5 volts.

17. The bandgap voltage reference circuit of claim 16 wherein the bandgap reference voltage is generated at a substantially stable voltage level throughout the range of the input power supply voltage.

18. The bandgap voltage reference circuit of claim 15 wherein the regulated power supply voltage is approximately 1.2 volts.

19. The bandgap voltage reference circuit of claim 15 wherein the clamping voltage is approximately 3 volts.

20. The bandgap voltage reference circuit of claim 19 wherein the clamping voltage level is substantially stable throughout the range of the input power supply voltage.

21. The bandgap voltage reference circuit of claim 15 further comprising a negative feedback loop that maintains the regulated power supply voltage at a substantially constant voltage level relative to the input power supply voltage, wherein the negative feedback loop maintains the PTAT current proportional to temperature.