# Patent

## Title
VLSI fabrication processes for introducing pores into dielectric materials

## Abstract

Porous dielectric layers are produced by introducing pores in pre-formed composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the conductive material is provided with a relatively smooth continuous surface on which to deposit.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation application claiming priority under 35 USC 120 from U.S. patent application Ser. No. 11/050,621 filed Jan. 31, 2005, now U.S. Pat. No. 7,166,531 titled “VLSI Fabrication Process for Introducing Pores into Dielectric Materials,” naming van den Hoek et al. as inventors. This application is related to the following U.S. patent applications and issued U.S. patents: U.S. Pat. No. 6,753,250, filed on Jun. 12, 2002, issued on Jun. 22, 2004, titled “Method of Fabricating Low Dielectric Constant Dielectric Films” by Hill et al., U.S. Pat. No. 6,995,439, filed on Mar. 17, 2004, issued on Feb. 7, 2006, titled “Method of Fabricating Low Dielectric Constant Dielectric Films” by Hill et al., U.S. patent application Ser. No. 10/785,235, filed on Feb. 23, 2004, titled “Plasma Detemplating and Silanol Capping of Porous Dielectric Films” by Wang et al., U.S. patent application Ser. No. 10/825,888, filed on Mar. 16, 2004, titled “Method to Improve Mechanical Strength of Low-K Dielectric Film Using Modulated UV Exposure” by Bandyopadhyay et al., U.S. patent application Ser. No. 10/789,103, filed on Feb. 27, 2004, titled “Methods for Producing Low-K CDO Films With Low Residual Stress” by Wu et al., and U.S. Pat. No. 7,094,713, filed Jun. 2, 2004, issued on Aug. 22, 2006, titled “Methods For Improving The Cracking Resistance Of Low-K Dielectric Materials” by Niu et al. Each of the above identified patents and patent applications is incorporated herein by reference for all purposes.


BACKGROUND
This invention relates to low dielectric constant layers for use in various applications. The invention also relates to methods of forming low dielectric constant layers and integrating them into a wide range of VLSI fabrication operations.
As the feature sizes of microelectronic integrated circuits devices are reduced, the electrical properties of the materials that constitute the devices will require change and improvement. One material that must be improved is the electrical insulator (“dielectric”) used between the wires, metal lines, and other elements of the circuit. Without improvement in the insulator material, there will be increased problems due to capacitive effects such as coupling (crosstalk) and propagation delay. The speed at which future circuits will operate will be limited by RC delay in the interconnect. These difficulties can be mitigated by preparing the circuit using an insulating layer that possesses a dielectric constant as low as possible (i.e., a “low-k” dielectric layer).
Earlier technology nodes (i.e., the sets of VLSI fabrication technologies associated with particular critical dimensions) employed dense materials such as silicon dioxide, silicon nitride, and cured silsesquioxanes as insulators. However, the dielectric constants of these materials range from 3.0-7.0. These values will be inadequate for future circuits. As yet the only fully dense (non-porous) materials with a dielectric constant less than about 2.4 are fluorinated polymers or fully aliphatic hydrocarbon polymers, but these have not met requirements for adhesion and thermal stability.
Thus, considerable effort has been directed towards the development of porous dielectric materials. These can be thought of as composite materials, with the value of their dielectric constants intermediate between that of air (dielectric constant of 1.0) and the fully dense phase. Several classes of porous dielectric films, including porous oxides and porous polymers have been described in the art. Pore in these materials typically have dimensions in the nanometer range (e.g., about 1 to 50 nanometers). The materials are sometimes referred to as “nanoporous” or “mesoporous.”
Nanoporous silica films are formed by a variety of techniques. In one example, a process deposits a monomeric precursor such as tetraethylorthosilicate or TEOS (a siloxane) onto a substrate using a solvent, and then cross-links the precursors to form a continuous porous solid network. The resultant films are dried by direct solvent evaporation or treatment with supercritical fluids. The films are then subjected to a high-temperature annealing step. See for example, Changming et al., Materials Research Society Bulletin, vol. 22, no. 10, pp. 39-42 (1997).
Other approaches involve forming a stable composite film (sometimes referred to herein as a “precursor film”) containing two components: a removable porogen and a structure former or dielectric material (e.g., a silicon containing material). After the composite film is formed on the substrate, the porogen component is removed, leaving a structurally intact porous dielectric matrix. Porogens are frequently organic compounds such as polyfunctional cyclic hydrocarbon compounds. Techniques for removing porogens from the composite film include, for example, thermal processes, e-beam exposure, ultra-violet radiation exposure, plasma treatments, and solvent extraction employing supercritical solutions.
In a related approach, a mesoporous dielectric matrix is formed using a block copolymer such as a polyethylene oxide (PEO)-polypropylene oxide (PPO) block copolymer. The polymer is deposited and the PEO and PPO blocks segregate into separate phases, with the PPO phase regions being more hydrophobic and the PEO phase regions being more hydrophilic. The two-phase polymer is sometimes referred to as a “template.” The dielectric matrix is created by infusing a dielectric precursor (e.g., TEOS) and a catalyst into the polymer template where one or both of them preferentially accumulate in one phase. In the favored phase, the catalyst promotes reaction of the dielectric precursor to form the dielectric. Thus, the dielectric matrix forms selectively in one phase of the template. The other phase (the “porogen”) can be removed subsequently by various techniques such as plasma treatment.
As used herein, the term porogen is intended to encompass any type of material that forms a removable second phase in a composite layer that serves as a precursor to the dielectric matrix. The porogen may be arranged in an ordered or non-ordered fashion within the dielectric matrix.
Another technique for producing porous low-k films employs inorganic-organic nanophase-separated hybrid polymer materials. These materials comprise organic polymers cast with silsesquioxane-based ladder-type polymeric structures. A casting solvent is used to dissolve the inorganic and organic polymer components. The materials are spin coated onto a substrate and upon application of high-temperature, the hybrid phase-separated polymer materials are formed. See for example, Miller et al., Materials Research Society Bulletin, vol. 22, no. 10, pp. 44-48 (1997).
Certain problems arise in VLSI processing of partially fabricated devices having a porous dielectric material. A first problem arises in porous “open cell” dielectric materials, in which the individual pores contact and open into one another. The pores of these materials provide long paths throughout the interior of the dielectric material. Gases and liquids contacting the outer surfaces of open cell dielectric materials can penetrate deep into the layer's interior. This gives rise to a particularly difficult problem during conformal depositions of conductive barrier layers or seed layers. Precursor gases or plasma for these processes penetrate deep into the open cell matrix where they deposit and form the conductive barrier or seed materials. This renders large portions of the dielectric layer unacceptably conductive. A similar problem is now encountered in closed cell dielectric materials, even where the pore sizes are significantly smaller than the VLSI feature dimensions.
Examples of extremely conformal deposition processes where the problem is most pronounced include certain forms of chemical vapor deposition (CVD) and atomic layer deposition (ALD). Less conformal processes such as physical vapor deposition (PVD) do not deposit conductive material within the pore network, but they do a poor job of covering the discontinuous porous side-walls of a trench or via.
Another problem arises because porous materials lack the mechanical strength of non-porous materials. As a consequence, when a planarization technique such as chemical mechanical polishing (CMP) is employed to remove excess copper or other material, the pressure applied to the wafer during that process can crack or crush the underlying dielectric material.
The current porous materials and associated processing techniques have thus far failed to meet the demands of next generation VSLI fabrication. Obviously, the problems will only increase as technologies move to smaller feature dimensions. Improved methodologies for integrating low-k dielectric materials into VLSI devices are required.
SUMMARY
The present invention overcomes these problems by providing a process in which voids are introduced in a layer of dielectric only after some or all process steps associated with creating conductive lines are completed. Thus, in one embodiment, the voids are produced only after the conductive lines have been formed and the material removal (planarization) process has been completed. As a consequence, in a damascene process flow for example, the dielectric etch, barrier deposition, metal deposition, and planarization steps are all performed on stable, non-porous materials. Only after these process steps are complete are the voids introduced in the dielectric layer. In this manner, the interior regions of the dielectric layer are protected from exposure to conductive barrier materials and metals. In addition, the barrier materials and seed metals are provided with non-porous dielectric surfaces for depositing as relatively smooth continuous thin films. Still further, because the voids are typically introduced after planarization/material removal, the more fragile porous dielectric layer is not directly exposed to the mechanical stress of planarization.
In one aspect, the invention is characterized as a method of forming conductive lines on a substrate (e.g., an electronic device such as a partially fabricated integrated circuit). This method includes the following sequence: (a) providing a layer of composite dielectric material on the substrate; (b) optionally treating the dielectric network in a manner that shrinks and/or strengthens the layer of dielectric material; (c) patterning the layer of composite dielectric material to define paths for the conductive lines; (d) filling the paths with conductive material; and (e) after filling the paths in (d), removing at least some of the porogen from the layer of composite dielectric material to produce a porous dielectric network. The composite dielectric material includes at least a dielectric network and a porogen.
Filling the paths with conductive material may include, for example, depositing a diffusion barrier layer, as well as filling the paths with a metal or other conductive material. The conductive material is formed by electroplating in the case of a conventional Damascene process. Further, the overall process may additionally require removing excess conductive material formed in (d) prior to removing the porogen in (e). This material removal operation typically forms an exposed pattern of conductive lines in the composite dielectric material.
In treating the dielectric network to cause shrinkage, the process may produce a side benefit of strengthening the dielectric network. For example, the process may increase the material's modulus, hardness, crack resistance and/or toughness (resistance to crack propagation). Examples of techniques for shrinking the material include exposing the dielectric network to at least one of the following: ultraviolet radiation, e-beam radiation, thermal treatment and a plasma. To remove porogen from the layer of composite dielectric material the process may involve exposing the composite dielectric material to at least one of the following: a supercritical solvent, a plasma, a thermal treatment, ultraviolet radiation, and e-beam radiation.
The conductive lines are frequently made from a metal such as copper and the dielectric is usually a non-porous material such as silicon oxide, silicon oxycarbide (also known as carbon doped silicon oxide or CDO), fluorinated silicate glass, silicon nitride, a spin-on organic material, a spin-on inorganic material, or a spin-on inorganic-hybrid material.
In another aspect, the invention involves forming a layer of conductive lines on a substrate according to the following sequence: (a) forming a layer of porous dielectric material on the substrate; (b) filling at least some pores in the dielectric material with a sealant; (c) patterning the layer of composite dielectric material to define paths for the conductive lines; (d) filling the paths with conductive material; and (e) after filling the paths in (d), removing at least some of the sealant from the dielectric material. In this approach, a sealant is first added to a pre-formed dielectric matrix and subsequently removed. In this aspect of the invention, operations (b) and (c) can be performed in either order.
The sealant serves much the same role as a porogen. It renders the porous surface of the dielectric relatively smooth and continuous surface to improve the quality of subsequently deposited layers such a barrier layers and seed layers. Examples of sealant materials include conventional photoresist materials, BARC (bottom anti-reflective coating) materials, and other materials such as benzocyclobutene (BCB). The sealant may be inserted into the porous dielectric material by a process such as spin on techniques, chemical vapor deposition, in situ polymerization techniques, liquid impregnation, vapor impregnation, and supercritical injection.
Yet another aspect of the invention pertains to other methods of forming layers of conductive lines on a substrate, according to the following sequence: (a) directly forming a dielectric layer comprising a dielectric network on the substrate; (b) patterning the dielectric layer to define paths for the conductive lines; (c) filling the paths with conductive material; and (d) after filling the paths in (c), removing porogen from the dielectric layer to produce a porous dielectric network. In this aspect of the invention, the as deposited dielectric network comprises a three-dimensional covalent network. It is formed without curing or polymerizing as deposited material. The porogen may be deposited together with the dielectric network or added at a later time.
These and other features and advantages of the present invention will be described in more detail below with reference to the associated drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a process flow chart depicting a general method of integrating a layer of low-k dielectric material in accordance with an embodiment of this invention.
FIG. 1B is a flow diagram depicting a process of this invention in which a composite dielectric layer is treated to shrink the layer prior to patterning.
FIG. 1C is a flow diagram depicting a process of this invention in which a dielectric layer that is initially porous is sealed prior to inlaying to form conductive lines.
FIG. 1D is a flow chart depicting a process of this invention in which the dielectric matrix is deposited directly, without curing.
FIG. 2A is a cross sectional diagram of a dielectric layer prior to a via etch in a damascene process.
FIG. 2B is a cross sectional diagram of the dielectric layer of FIG. 2A after a line etch has been performed.
FIG. 2C is a cross sectional diagram of the dielectric layer of FIGS. 2A and 2B after the etched regions have been filled with metal to form lines and vias.
FIG. 2D is a top view of a simplified version of the layer prepared as in FIG. 2C.



DETAILED DESCRIPTION
Introduction
This invention pertains to devices and methods of fabricating such devices by introducing voids into a dielectric layer, but preferably only after the dielectric material has been patterned and further processed to form conformal layers on its patterned surface. In typical embodiments, the voids are not introduced until after the dielectric material is deposited, etched, inlaid, and planarized. Exemplary methods for performing this invention will be presented below.
In many cases, the dielectric material serves as an intermetal dielectric in an integrated circuit and the patterning defines line paths and/or vias. Introducing the voids renders the dielectric layer porous and effectively reduces the dielectric constant of the layer, and thereby improves performance of the integrated circuit.
Frequently, the dielectric layer is initially a two-phase material comprising a dielectric network together with a porogen that occupies void regions within the dielectric network. The porogen is ultimately removed from the dielectric matrix to leave behind a porous structure having a lowered dielectric constant. But during early stages of dielectric processing (e.g., patterning, conformal deposition, planarization, etc.), the porogen remains in place to provide a composite dielectric substrate that presents a continuous non-porous surface onto which thin continuous layers may be deposited (e.g., diffusion barrier and seed layer layers). Further, the presence of the porogen during early stage processing lends additional strength to the dielectric layer to resist crushing during planarization processes.
In some cases, the porogen is present when the dielectric layer is formed on a substrate. In other cases, the porogen is inserted into the pores of a dielectric layer that was formed in a porous state or was rendered porous after deposition. In the former cases, the deposition conditions are tailored to form the porogen and dielectric matrix concurrently. Exemplary processes include chemical vapor deposition, spin on processes, and in situ formation of the dielectric matrix in a two-phase template. In the later cases, a specific infusion technique is employed to introduce the porogen as described below.
Using this invention, the significant difficulties encountered integrating the more conventional porous materials are reduced or eliminated. First, this invention reduces the problems specific to deposition of thin layers on porous surfaces. Specifically, conductive materials cannot penetrate to the dielectric interior regions when formed by conformal or partially conformal deposition processes. Second, the invention can reduce the porous material's susceptibility to damage during CMP or other planarization technique.
TERMINOLOGY
Throughout the specification, various terms are employed to describe the new concepts of this invention. Those terms may be well known to those skilled in the art. However, to ensure a consistent understanding of the terminology, the following explanations are provided.
In many cases, the dielectric materials employed at early and intermediate stages of fabrication processes described herein are characterized as “composite” dielectric materials. These possess at least two phases, a dielectric network and a porogen. Together they form a generally continuous condensed phase material. In one example, a composite dielectric layer includes a carbon doped silicon oxide as dielectric network and a polyfunctional hydrocarbon as a porogen.
When the porogen is removed, the dielectric network forms a porous structure having pores or voids distributed throughout its volume. The pores may define an open cell or a closed cell structure. Depending upon the application, the pores may have a particular mean or average size and size distribution. Typically, the mean pore size is significantly smaller than the line widths (e.g., at least about 2×). For IC fabrication employing 90 nanometer line widths, the mean size of pores is preferably between about 5 and 100 Angstroms. Note that all normal dielectric materials for IC applications are “porous” at some level. In carbon doped oxide films, for example, there “pores” within the dielectric network are generated by covalent “cages” or terminal methyl groups. These very small, molecular-scale voids are not considered pores within the meaning of this invention.
The porogen temporarily occupies the pore regions to provide (together with the dielectric matrix) a continuous nonporous surface on which materials such as diffusion barrier layers and conductive seed layers can be conformally deposited as smooth continuous films. Porous dielectric materials (which do not have porogen filling their voids) provide a rougher surface that can be difficult to cover with continuous thin layers that do not penetrate into interior regions of the dielectric material. In most processes described herein, the porogen is present only temporarily in the dielectric material. It is removed after, for example, formation of barrier films, deposition of conductive material and planarization to produce a porous low-k dielectric layer. Generally, composite dielectric materials are better able to withstand the pressures encountered in CMP and other processes employed in semiconductor device fabrication. However, strengthening the dielectric matrix by treatment with UV radiation or other appropriate stimulus, as described below, can greatly improve the ability of porous dielectrics to withstand aggressive processing.
The term “porogen” refers to any removable phase of a composite dielectric matrix. The term broadly refers to any condensed phase material that occupies regions of a dielectric matrix where the dielectric network material does not penetrate and voids can form. In some cases the porogen is randomly distributed throughout the composite film and other cases it is ordered in a repeating structure throughout the film. The porogen can be introduced into the dielectric at various times in a process sequence—e.g., together with formation of the porous dielectric network or after a porous network was already formed. In the later case, the porogen is sometimes referred to as a sealant.
One preferred class of porogen compounds is the polyfunctional non-aromatic compounds. Examples of such compounds are terpenines such as alpha terpenine (ATRP), norborenes such as 5-ethylidene-2-norbornene (ENB), limonene (C10H16), and other related compounds. An example of a different porogen of interest is benzocyclobutene (BCB). Certain polymeric materials such as photoresist and BARC materials can also be used as porogens. BARC (bottom anti-reflective coating) materials are strongly UV absorbing materials conventionally used beneath photoresist to absorb and thereby prevent reflection of UV radiation. Another class of porogen is one phase produced by template forming compounds such as certain block copolymer materials (e.g., polyethylene oxide (PEO)-polypropylene oxide (PPO) block copolymers) used to form ordered mesoporous films. The hydrophilic (e.g., PEO) and hydrophobic (e.g., PPO) components form separate phases within a polymer matrix (the template). In one approach, a silica-forming precursor is introduced to the template by, for example, supercritical infusion. Within the template, the precursor locates in its thermodynamically preferred phase and there reacts to produce the dielectric network. The reaction may be driven by introducing a catalyst.
A porogen may be removed from a composite dielectric matrix by thermal methods, treatment with plasma, supercritical extraction, UV-mediated techniques, electron beam treatment and the like. Various porogens and porogen-removal techniques are described below and in, for example, U.S. patent application Ser. No. 10/800,377, filed Mar. 11, 2004 (“METHOD AND APPARATUS FOR UV EXPOSURE OF LOW DIELECTRIC CONSTANT MATERIALS FOR POROGEN REMOVAL AND IMPROVED MECHANICAL PROPERTIES” by E. Srinivasan et al.), which is incorporated herein by reference for all purposes.
The term “dielectric network” describes the dielectric material that remains at the end of the process and serves as the porous dielectric matrix in accordance with methods of this invention. Spaces within the dielectric network are filled with porogen or vapor (e.g., air) at various stages of the process. The network itself is a condensed phase material, typically a solid. It forms an extended three-dimensional covalently bonded network of atoms such as silicon, oxygen, carbon, and hydrogen. Typically it exists as a cross-linked structure and as such a layer of the material may be viewed as a single molecule. A dielectric network of this invention is not comprised of small discrete molecules such as monomers. This does not mean the dielectric network cannot include dopant atoms and other relatively loosely affiliated elements and compounds. In many cases, the composite dielectric layer is formed under conditions that directly produce the dielectric network without the need for further polymerization or other network forming process.
Examples of materials that may serve as the dielectric network include silicon oxides (including silicon oxycarbides or carbon doped silicon oxides), fluorinated silicate glasses, silicon nitrides, spin-on materials (both organic and inorganic), and spin-on inorganic-hybrid materials. Carbon doped silicon oxides are preferred for many applications. These are composed of, at least, silicon, oxygen, hydrogen, and carbon. A typical chemical composition of as deposited CDO includes 10-25 atomic percentage silicon, 10-60 atomic percentage oxygen, 10-40 atomic percentage carbon and 20-40 atomic percentage of hydrogen. In certain embodiments, other elements may be present in the CDO films. Preferably the dielectric network has a relatively low intrinsic dielectric constant; e.g., below about 5. Examples include silicon dioxide ( ̃4.2), fluorinated silicate glass ( ̃3.6-3.7), and silicon oxycarbide ( ̃2.7-3.1).
Those of skill in the art understand that precursors are frequently employed to form the dielectric network. Different types of precursor are appropriate for different types of dielectric material and different types of deposition processes. In the case of silicon oxide films formed via a chemical vapor deposition technique (e.g., PECVD), examples of precursors include silanes, alkylsilanes (e.g., trimethylsilane and tetramethylsilane), alkoxysilanes (e.g., methyltriethoxysilane (MTEOS), methyltrimethoxysilane (MTMOS) diethoxymethylsilane (DEMS), methyldimethoxysilane (MDMOS), trimethylmethoxysilane (TMMOS) and dimethyldimethoxysilane (DMDMOS)), linear siloxanes and cyclic siloxanes (e.g. octamethylcyclotetrasiloxane (OMCTS) and tetramethylcyclotetrasiloxane (TMCTS)).
While the present invention may be used with conventional dielectric materials, it is by no means limited to them. Other dielectric materials such as CDO films containing unsaturated carbon-carbon bonds (i.e., double and triple bonds) may also be used. See U.S. patent application Ser. No. 10/789,103, filed on Feb. 27, 2004 by Wu, et al., and titled “Methods for Producing Low-K CDO Films with Low Residual Stress” which is incorporated in its entirety by reference herein for all purposes. Films that incorporate unsaturated bonds may have improved mechanical properties, specifically high mechanical strength and low intrinsic stress.
The term “electronic device” as used herein refers to any device employing circuitry on a substrate. Typically, an electronic device is formed on a semiconductor substrate or other structure possessing a semiconductor material. In many cases, an electronic device provides logic or memory. The term “electronic device” subsumes partially fabricated devices (such as partially fabricated integrated circuits) as well as completed devices available for sale or installed in particular apparatus. In short, an electronic device may exist at any state of manufacture that employs a method of this invention or possesses a structure of this invention.
Process Flow
The present invention may be embodied in a variety of distinct process sequences. As indicated above, the processes generally introduce voids or porosity into a dielectric layer relatively late in the fabrication process. And as indicated, typically that fabrication process is formation of a metallization layer in an integrated circuit. FIG. 1A depicts a general sequence of operations that is common to many embodiments of the present invention.
As depicted in FIG. 1A, the process begins with formation of a dielectric layer on a substrate. See block 103. Generally, the dielectric layer formed at this stage will include a porous dielectric network that may or may not have its pores filled with a porogen. If the porogen is not employed at this stage in the process, it will be introduced at a later stage as described in the text associated with FIG. 1C, for example.
The dielectric layer formed at 103 is subsequently patterned to define line paths associated with interconnects in a metallization layer of an integrated circuit. See block 105 in FIG. 1A. Typically, the patterning will be accomplished using a conventional process such as photolithography and etching, but other techniques can be used as well. For example, electron beam lithography may be suitable for certain applications.
Next in the process, conductive lines are formed in the previously defined line paths. See block 107. In many cases, this process involves deposition of a diffusion barrier and possibly a conductive seed layer (e.g., a thin copper layer). As explained with reference to the damascene process flow described below, the seed layer is employed to provide a conductive surface on which to electroplate bulk copper or other conductive material to form the current carrying lines in an electronic device.
Depending upon the process, it may be necessary to remove excess metal or other conductive material formed during operation 107. In a conventional example “overburden” (electroplated metal that extends out beyond the line paths and over the field regions) is removed by a planarization process such as chemical mechanical polishing). If this operation is required, it typically will be performed after operation 107 but before the point where voids are introduced into the dielectric layer (see block 109).
In operation 109, the voids are finally introduced into the dielectric layer to reduce the effective dielectric constant. This may be accomplished by various techniques, but generally involves removing the porogen from the composite dielectric layer.
As indicated, the general process flow depicted in FIG. 1A may be implemented in any one of many different specific embodiments. Three of these are depicted in other figures, FIGS. 1B-D. In FIG. 1B, the “as deposited” dielectric layer includes both the porogen and dielectric network. In FIG. 1C, the as deposited dielectric layer is initially porous. Subsequently, the pores are filled with a porogen, which is removed at a later stage in the process.
Turning first to FIG. 1B, the process begins at an operation 113 where a partially fabricated integrated circuit is made available for formation of a metallization layer in accordance with this embodiment of the invention. The partially fabricated integrated circuit may have an exposed pattern of interconnects in an underlying metallization layer or exposed active device contacts such as polysilicon gates in an underlying active device layer.
On this substrate, the process forms a layer of composite dielectric material having porogen and the dielectric matrix. See block 115. As indicated, this composite dielectric material should form a generally continuous solid or solid-like layer that is substantially void free. In a specific implementation, the composite dielectric material is formed by a chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) process that co-deposits the porogen and the dielectric network.
Frequently, the as deposited composite layer will shrink during subsequent processing to remove porogen and/or strengthen the dielectric matrix. If the dielectric layer was to shrink after the conductive lines were formed, it might create misaligned conductive paths and/or high levels of stress and concomitant damage to the materials in the metallization layer. To address this potential difficulty, the process of FIG. 1B employs a treatment that shrinks and optionally strengthens the composite dielectric layer. See block 117. As indicated below, this treatment may involve exposure to ultraviolet radiation in one example. Typically, this operation is conducted in a manner that does not remove porogen from the layer.
After the composite dielectric layer has been sufficiently strengthened and/or shrunk to a dimensionally stable level, it may be patterned and otherwise treated to form the conductive line paths necessary in the metallization layer. To this end, an operation 119 is depicted for patterning the composite layer to define line paths, and doing so without significantly removing porogen. In an alternative embodiment, the composite dielectric layer is patterned prior to the treatment to shrink/strengthen the layer. In other words, operations 117 and 119 are reversed.
With the porogen in place, relatively smooth continuous sidewalls and trench bottoms are available for receiving deposited conformal layers such as layers of diffusion barrier and seed layer. As indicated, the smooth surface provides for deposition of high quality conformal layers of diffusion barrier and seed metal. See block 121. This then allows deposition of high quality conductive material in the line paths of the patterned layer. See block 123. Again, a conventional damascene process may be employed in implementing the operations depicted in blocks 121 and 123.
The next operation in the process is depicted at block 125. It involves planarizing the substrate to produce an exposed pattern of conductive lines in the composite dielectric layer. In a normal damascene process flow, no further treatment of the dielectric would be required at this stage. In the present embodiment, however, a separate operation is employed to remove porogen from the composite dielectric material in a manner that leaves behind a low-k porous dielectric matrix. See block 127. Because the dielectric layer was previously treated to improve dimensional stability during subsequent process steps, operation 127 can be performed without significantly shrinking the dielectric matrix. Thus, the operation can be performed without significantly increasing internal stress in the layer.
From this point forward, conventional processing may be employed to complete formation of the metallization layer and prepare for creation of a next higher metallization layer (or for passivation if the current metallization layer is the last metallization layer required for the integrated circuit).
FIG. 1C depicts a separate embodiment of the present invention, one in which the “as deposited” dielectric layer is initially porous or made porous early in the process. The process begins, as before, with a partially fabricated integrated circuit as indicated at block 133. However, the process next involves formation of a porous dielectric layer on the integrated circuit as indicated at block 135. Presumably, this porous dielectric layer is dimensionally stable and requires no further treatment to ensure such stability. However, if the material does exhibit shrinkage, it may be appropriate to provide an appropriate treatment at this stage to ensure dimensional stability through subsequent process steps. Note that a porous dielectric material may be directly deposited by various techniques such as a spin-on process. It is also within the scope of this invention that the porous dielectric layer could be produced by one of the processes described herein that employ a composite dielectric layer of porogen and a dielectric network.
The next operation in the process involves infusing sealant (porogen) into the porous dielectric layer. See block 137. As indicated elsewhere herein, this may be accomplished by spin-on deposition, atomic layer deposition, chemical vapor deposition, in situ polymerization, liquid impregnation, vapor impregnation, or supercritical injection.
Next, the dielectric layer with infused sealant is patterned to define line paths in a manner that accomplishes this without removing the sealant from the pores of the dielectric layer. See block 139. Thereafter, the diffusion barrier and optionally the seed layer are conformally deposited on the patterned layer as indicated at block 141. From this point, the conductive material such as copper metal is deposited in the line paths of the patterned layer to form the current carrying lines of the metallization layer. See block 143. Note that operations 141 and 143 should be performed in a manner that ensures that little if any of the sealant is removed from the dielectric pores during these processes.
Next, the substrate is planarized to remove excess conductive material and produce an exposed pattern of the conductive lines in the dielectric layer. See block 145. Note that at this stage, the temporarily introduced sealant still remains in the dielectric layer. Thus, it is necessary to now remove the sealant to re-form the porous dielectric layer to give a low dielectric constant, as required for high performance applications. See block 147.
FIG. 1D is a process flow representing another aspect of the invention. In this aspect, the as deposited dielectric layer (which may or may not include porogen) comprises a dielectric network. The network is formed directly and therefore does not require curing or other post-deposition polymerization step.
As shown in FIG. 1D, the process is similar to that of FIG. 1B. The process begins with a partially fabricated integrated circuit on which a metallization layer or other layer of conductive lines is to be formed. Block 153. The process then directly forms a dielectric layer comprising a dielectric network on the substrate as indicated at block 155. This is accomplished without the need to cure or polymerize a deposited precursor to the dielectric network. Instead, the as-deposited dielectric layer comprises a dielectric network as described above (typically an extended three-dimensional covalent network). The porogen may be deposited together with the dielectric network or added at a later time, preferably before patterning.
As shown in FIG. 1D, the dielectric layer is patterned (157), covered with thin layers of diffusion barrier and seed (159), filled with a conductive material (161), and planarized (163). At the conclusion of this process, the porogen is removed to produce the final porous dielectric matrix.
For context, FIGS. 2A through 2D depict a dual damascene approach to operations 103, 105, and 107 of FIG. 1A. In a typical dual damascene process, first and second layers of composite dielectric are deposited in succession, possibly separated by deposition of an etch stop layer, such as a silicon nitride layer. These layers are depicted in FIG. 2A as first composite dielectric layer 203 and a second composite dielectric layer 205. These are formed on an adjacent portion of a substrate 209, which portion may be an underlying metallization layer or a gate electrode layer (at the device level). Note that in some damascene processes, the two layers 203, 205 may be formed as a single layer. Whether formed as a single layer or two layers, the resulting structure should be sufficiently thick to allow formation of both vias and trenches.
Each composite dielectric layer contains both a dielectric network 208 and porogen 204. In the case of the process depicted in FIG. 1C, the porogen (or sealant) is introduced in the layers after they formed, separately or after each layer is formed.
After the dielectric layer or layers have been deposited, operation 117 of the FIG. 1B process may be performed. In other words, the composite dielectric layers may be treated with ultraviolet radiation or other stimulus to shrink the composite dielectric to a dimensionally stable size. As mentioned, details of this process will be provided below.
After deposition of the second composite dielectric layer 205, the process forms a via mask 211 having openings where vias will be subsequently etched. Next, the vias are partially etched down to an intermediate level. Then via mask 211 is stripped off and replaced with a line mask 213 as depicted in FIG. 2B. A second etch operation is performed to remove sufficient amounts of dielectric to define line paths 215 in second dielectric layer 205. The etch operation also extends via holes 217 through first dielectric layer 203, down to contact the underlying substrate 209. See FIG. 2B. In alternative embodiments, the trenches are etched first and the vias second.
Next the process forms a thin layer of conductive barrier layer material 219 on the exposed surfaces (including sidewalls) of composite dielectric layers 203 and 205. Because copper frequently provides the conductive paths in the electronic device, the dielectric materials must be protected from diffusing metal (e.g., copper) that might otherwise diffuse or drift into the dielectric layer. Suitable materials for a copper diffusion barrier include tantalum, tantalum nitride, tungsten, titanium tungsten, titanium nitride, tungsten nitride, and the like. In a typical process, the barrier layer is formed by a physical vapor deposition (PVD) process such as sputtering, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.
On top of the barrier layer 219, the process deposits conductive metal (typically copper) in the via holes and line paths 217 and 215. Conventionally this deposition is performed in two steps: an initial deposition of a conductive seed layer followed by bulk deposition of copper by electroplating. The seed layer may be deposited by physical vapor deposition, chemical vapor deposition, electroless plating, etc. Note that the bulk deposition of copper not only fills line paths 215 but, to ensure complete filling, covers all the exposed regions on top of second dielectric layer 205.
Thus, it becomes necessary to remove the excess copper from the device. A planarization is often employed to planarize a wafer surface and removes material down to the level of the top of dielectric layer 205. This produces an exposed pattern of conductive lines 221 in dielectric layer 205 and vias in dielectric layer 203. See the cross-sectional view of FIG. 2C and the simplified top view of FIG. 2D. Note that the porogen 204 may be conveniently removed from dielectric matrix after the excess metal has been removed as indicated.
One widely used planarization process is chemical mechanical polishing (CMP). This process, or any process like it that applies downward pressure on the partially fabricated electronic device, can crack, crush, or otherwise destroy a highly porous low dielectric constant dielectric layer. One benefit of the present invention is that it allows a conventional pressure-based planarization technique in a fabrication technology employing a “porous” dielectric layer. It accomplishes this by introducing voids only after the pressure-based planarization technique has been completed. Note that the invention is not limited to use with planarization process that apply pressure to the underlying dielectric layer. Thus, it is not limited to CMP. It may also involve, for example, a combination of electropolishing, to remove most of the excess bulk copper, followed by CMP to remove the remaining copper down to the level of the top surface of dielectric layer 205.
Note that the present invention is not limited to dual damascene processes of the type depicted in FIGS. 2A-2D. It also applies to single damascene and various non-damascene processes for forming patterns of conductive features in dielectric layers.
Methods for Introducing Porogens in a Composite Layer
As indicated, the composite dielectric layer may be formed by co-depositing porogen and the dielectric network or it may be formed by infusing porogen into a pre-formed porous dielectric matrix. In the former case, deposition may be accomplished by providing the porogen together with a dielectric precursor to a CVD reactor. The deposition conditions are chosen so that the porogen coalesces in particular locations within the dielectric network as it forms by reaction of the precursors on the substrate surface. Appropriate conditions for co-depositing porogen and the dielectric network are well known in the art. See e.g., U.S. Pat. No. 6,312,793 (issued Nov. 6, 2001) to A. Grill et al., which is incorporated herein by reference for all purposes.
General template-based processes for creating the composite layer are known in the art. As indicated these processes involve initial formation of a template (e.g. a two-phase mesoporous block co-polymer), infusion of a dielectric precursor that preferentially localizes in one phase, and reaction of the precursor to produce a dielectric network. The phase where the dielectric did not form (the porogen) is subsequently removed. See for example, U.S. patent application Ser. No. 10/404,693 filed Mar. 31, 2003 by Humayun, et al., and titled “Method for Forming Porous Films by Porogen Removal Combined With In Situ Surface Modification,” and U.S. patent application Ser. No. 10/295,965 filed Nov. 15, 2002 by Schulberg, et al., and titled “System for Deposition of Mesoporous Materials,” both of which are incorporated herein by reference for all purposes.
In cases where the porogen or sealant is infused into a porous dielectric matrix, the infusion may be accomplished by spin-on, CVD, ALD, in situ polymerization, liquid impregnation, vapor impregnation, supercritical injection and the like. In another approach, porogen is formed by condensation of a porogen precursor and subsequent polymerization. In this approach, a vapor phase monomer is allowed to selectively condense on the substrate and there polymerize. To promote selective condensation, the substrate may be maintained at a lower temperature than a reactor walls.
Treatments for Shrinking and Improving Strength
The procedures for shrinking a composite dielectric layer to render it dimensionally stable in subsequent process steps (including porogen removal) include exposure to ultraviolet radiation, particularly modulated ultraviolet radiation. Modulated ultraviolet radiation treatments are described in U.S. patent application Ser. No. 10/825,888, which was previously incorporated by reference.
Preferably, the treatment has minimal impact on the porogen itself. For example, the treatment should not remove significant amounts of the porogen from the composite dielectric layer. In one embodiment, ultraviolet radiation is employed in two separate treatments: first to shrink/strengthen the dielectric matrix and second to remove the porogen. The porogen should be chosen that it is relatively immune to the first treatment. Preferably, the chosen porogen has a relatively narrow absorption band (e.g., 290-300 nanometers) that is well removed from an absorption edge (e.g., less than about 250 nanometers) where radiation can shrink and/or strengthen the dielectric matrix.
In preferred embodiments, the procedures employed to shrink the composite dielectric layer are sufficiently effective that during the subsequent porogen removal operation, the dielectric layer shrinks by no more than about 2%. As indicated, the treatment may also strengthen the dielectric matrix. The strengthening may be manifest by increasing its modulus, cracking threshold, toughness (resistance to crack propagation), etc.
Techniques for Removing Porogens
Techniques for removing porogen from the composite film include, for example, thermal processes in which the substrate is heated to a temperature sufficient for the breakdown and vaporization of the organic porogen, treatment with plasma, supercritical extraction, UV-mediated techniques, electron beam treatment, etc.
Thermal techniques for porogen removal involves heating the wafer to a temperature of approximately 400 C or greater for a period of time (e.g., several minutes to several hours) to thermally degrade and remove the porogen. During the process, the wafer is maintained in an environment where the thermal products (porogen vapor and/or decomposition products) are removed. Thus, the process may take place under flowing inert gas or in a vacuum.
Another technique involves exposing the wafer to a plasma treatment while heating the wafer. Specific plasma removal techniques and plasma conditions are described in U.S. patent application Ser. No. 10/785,235, filed on Feb. 23, 2004, titled “Plasma Detemplating and Silanol Capping of Porous Dielectric Films” by Wang et al., which was previously incorporated by reference. In some cases, the wafer may be treated with a capping agent to tie up silanol groups and dangling bonds produced during plasma treatment. Examples of capping agents include certain silane amines, alkyl alkoxysilanes, chlorosilanes, and aldehydes. Specific examples include hexamethyldisilazane, dimethyldimethoxysilane, trimethylchlorosilane, and an acetaldehyde. In some embodiments, the capping agent may be present in the reactor environment while the plasma processing takes place. In other embodiments, the capping takes place after the plasma treatment. Thus, porogen removal and silanol capping may be performed contemporaneously or sequentially. If performed sequentially, silanol capping is preferably performed without first exposing the dielectric matrix to moisture or ambient conditions.
UV-mediated porogen removal techniques are described in U.S. patent application Ser. No. 10/785,235, filed on Feb. 23, 2004, titled “Plasma Detemplating and Silanol Capping of Porous Dielectric Films” by Wang et al., which was previously incorporated by reference. Note that a preferred UV-mediated technique for removing porogen involves exposure to a modulated UV source in which the UV intensity on the wafer varies in a periodic fashion. Appropriate modulation frequencies, UV wavelength distributions, and source configurations are described in U.S. patent application Ser. No. 10/825,888, filed on Apr. 16, 2004, titled “Method to Improve Mechanical Strength of Low-K Dielectric Film Using Modulated UV Exposure” by Bandyopadhyay et al.
Other discussions of interest (UV-mediated porogen removal) are found in U.S. patent application Ser. No. 10/672,311, filed on Sep. 26, 2003, titled “Method of Porogen Removal from Porous Low-k Films Using UV Radiation,” by Adrianne Tipton et al., and U.S. patent application Ser. No. 10/404,693, filed on Mar. 31, 2003, titled “Method for Forming Porous Films by Porogen Removal Combined with In Situ Surface Modification,” by Raashina Humayun et al. Each of these patent applications is incorporated herein by reference for all purposes. A silanol capping agent (as discussed above) may be used in conjunction with the UV-mediated porogen removal.
Porogen extraction using supercritical extraction employs a supercritical or near supercritical solvent such as carbon dioxide to contact the composite dielectric layer and extract the porogen from within the small pores of the dielectric network. The excellent penetrating power of supercritical solvents allow them to effectively reach pores deep within the dielectric matrix. The supercritical fluid may contain one or more additives such as an oxidant that can oxidize the porogen and thereby facilitate its removal. In specific embodiments, the supercritical fluid contains between about 0.5% to 5% hydrogen peroxide by weight. Also in some embodiments, the supercritical fluid contains co-solvents to aid in the dissolution of the porogen and/or to increase the solubility of an oxidant. In some embodiments, the supercritical solution comprises a nitrile such as acetonitrile or benzonitrile. In a specific example, the solution comprises between about 5% and 15% acetonitrile. Suitable temperatures at which the precursor film is exposed to the supercritical fluid generally range between about 75 and 150 degrees Celsius. A silanol capping agent (as discussed above) may be used in conjunction with the supercritical extraction. Porogen extraction using supercritical extraction is describe in detail in U.S. patent application Ser. No. 10/672,305, filed on Sep. 26, 2003, titled “Method for Removal of Porogens from Porous Low-k Films Using Supercritical Fluids,” by Adrianne Tipton et al., which is incorporated herein by reference in its entirety for all purposes.
One side benefit sometimes associated with the porogen removal process is improved mechanical properties of the resulting porous dielectric layer. These mechanical properties include hardness, modulus, film residual stress, blanket film cracking threshold or limit, fracture toughness (i.e., resistance to crack propagation), etc. These properties are dependent on the strength of the atomic bonds and their binding energies. Under certain conditions, porogen removal and pre-treatment operations (e.g., operation 117 in the process of FIG. 1B) can modify the internal structure of the dielectric network and thereby improve these mechanical properties.
Dielectric materials with inferior mechanical properties will tend to have adhesive failures (delamination) and cohesive failures (cracking) during the copper-low k integration and packaging steps. These failures are exacerbated by the increasing complexity of integrated circuits and frequently manifest with growing numbers of metallization layers.
While the processes of this invention need not improve the mechanical properties of the resulting dielectric materials, it is generally desirable that materials have a modulus that is higher than about 3 GPa, more preferably higher than about 6 GPa. Measures of film modulus may be made with any suitable apparatus including a nano-indenter device.
The total residual stress of the dielectric layers produced in accordance this invention is preferably less than about 50 MPa tensile stress, and more preferably less than about 30 MPa tensile stress. If the film exhibits a net intrinsic compressive stress, the magnitude of that compressive stress is preferably less than about −30 MPa, and more preferably less than −20 MPa compressive. One suitable apparatus used to measure internal stress is the “Flexus” tool purchased from KLA-Tencor Corporation. But any tool that accurately measures bow or other deviation from planarity in a wafer can be employed.
One manifestation of residual tensile stress in a film is cracking. A film's cracking threshold is a measure of the thickness of the film on a blank substrate (e.g., a flat 200 mm wafer) that can be deposited without forming a crack. In a typical experiment, the dielectric film is deposited to various thicknesses using a single set of process conditions. The resulting wafer (with dielectric layer) is set aside without disturbance for a period of time (e.g., one day) and examined for cracks. The greatest thickness at which no crack is observed is the cracking threshold. For many processes, the cracking threshold is measured in μm. For the purposes of this invention, the cracking threshold is greater than about 3 μm. Most preferably, the cracking threshold is greater than about 5 μm.
OTHER EMBODIMENTS
While this invention has been described in terms of a few preferred embodiments, it should not be limited to the specifics presented above. Many variations on the above-described preferred embodiments may be employed. For example, while the invention has been described primarily in terms of preparing “porous” dielectrics in integrated circuits, it is not so limited. In some embodiments, the invention may be employed in non-semiconductor devices. Therefore, the invention should be broadly interpreted with reference to the following claims.

## Claims

1. A method of forming a layer comprising conductive lines on a substrate, the method comprising:
(a) providing a layer of composite dielectric material on the substrate, wherein the composite dielectric material comprises a dielectric network and a porogen;
(b) patterning the layer of composite dielectric material to define paths for the conductive lines;
(c) filling the paths with conductive material;
(d) after filling the paths in (c), removing at least some of the porogen from the layer of composite dielectric material to produce a porous dielectric network; and
(e) treating the porous dielectric network or the composite layer with a capping agent to chemically modify silanol groups and dangling bonds on a surface of the dielectric network.

2. The method of claim 1, wherein the capping agent is selected from the group consisting of a silane amine, an alkyl alkoxysilane, a chlorosilane, and an aldehyde.

3. The method of claim 1, wherein the capping agent is selected from the group consisting of hexamethyldisilazane, dimethyldimethoxysilane, trimethylchlorosilane and acetaldehyde.

4. The method of claim 1, wherein treating the composite layer or the porous dielectric network with the capping agent comprises plasma treating the layer or the network with the capping agent.

5. The method of claim 1, wherein removing at least some of the porogen from the layer of composite dielectric material to produce a porous dielectric network is performed by plasma treatment.

6. The method of claim 1, wherein operations (d) and (e) are performed concurrently by plasma treatment.

7. The method of claim 1, wherein operation (e) is performed after operation (d).

8. The method of claim 1, wherein removing at least some of the porogen from the layer of composite dielectric material comprises exposing the composite dielectric material to at least one of the following: a supercritical solvent, a plasma, a thermal treatment, ultraviolet radiation, and e-beam radiation.

9. The method of claim 1, further comprising removing excess conductive material formed in (c) prior to removing the porogen in (d), to thereby form an exposed pattern of conductive lines in the composite dielectric material.

10. The method of claim 9, wherein removing the excess conductive material also serves to produce a planarized surface.

11. The method of claim 1, wherein the dielectric network comprises a material selected from the group consisting of silicon oxide, a carbon doped silicon oxide, a fluorinated silicate glass, silicon nitride, a spin-on organic material, a spin-on inorganic material, and a spin-on inorganic-hybrid material.

12. The method of claim 1, wherein the conductive material is copper.

13. The method of claim 1, wherein filling the paths with a conductive material comprises plating the conductive material.