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                            Library & Multimedia
 Symbol Timing and Coarse Classification of Phase Modulated Signals on a Standalone SDR Platform
NCJ Number
              305972

Author(s)
          Gladstone Washington Marballie
Date Published

October 2010
Length
              102 pages
Annotation
              The Universal Classifier Synchronizer (UCS) is a Cognitive Radio system/sensor that can detect, classify, and extract the relevant parameters from a received signal to establish physical layer communications using the received signal's profile, with the current implementation being able to identify signals including AM, FM, MPSK, QAM, MFSK, and OFDM.
Abstract
              The system is constructed to run on a Universal Software Radio Peripheral (USRP) with the GNU Radio software toolkit and runs on an AnritsuTM signal analyzer. In both prototypes, the UCS system runs on a host computer's General Purpose Processor (GPP) and is constructed in MatlabTM. The aim is to then create a portable and standalone version of the UCS system as an intermediate step towards building a future commercial implementation. This application and particular implementation aims to run on a Lyrtech SFF SDR platform and uses its FPGA and DSP modules for implementation. This platform is one of the more advanced SDR platforms available, and the aim is to develop parts of the UCS system to run on this platform. The aim is to eventually develop the complete UCS cognitive radio system on the Lyrtech SFF SDR platform that can act as a standalone portable cognitive radio system. The modules created and implanted/implemented on the SDR hardware are the Bandwidth Estimation, and Symbol Timing & Coarse Classification modules. This is the system decision path towards classification, synchronization, and demodulation of digital phase modulated signals (QAM and MPSK signal types) and analog signals. The Digital Receiver Module (DRM) is implemented on the FPGA and takes care of all the digital down conversions, mixing, decimation, and low pass filtering. The FPGA is connected to the DSP module via a bus subsystem where the DSP receives real-time base-band complex IQ samples for further signal processing. The main UCS algorithm runs on the platform's DSP and is compiled from executable embedded C-code. Therefore, this system can then be implemented on virtually any setup that has an RF front end, digital receiver module, and processing module that will execute floating and fixed point C-code with minor changes. (Published abstract provided)
      
  
          Additional Details
Grant Number(s)
        2009-SQ-B9-K011


  
  
        
  Agencies
        NIJ-Sponsored


  
  
        
  Publication Type
        Thesis/Dissertation


  
  
        
  Award
        A Public Safety Cognitive Radio for Universal Interoperability: Transition to DSP Implementation for Manufacture
    
  
  
Date Published: October 1, 2010
    
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