# Patent

## Title
Temperature detector in an integrated circuit

## Abstract

A temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of the at least one temperature-dependent voltage. The timer is configured to generate a time-out signal, which is affected by one of the temperature-dependent voltage. The clock-driven recorder has a clock input terminal in response to the clock signal and time-out signal.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a temperature detector in an integrated circuit, and more particularly, to a highly sensitive temperature detector in an integrated circuit.
2. Description of the Related Art
Under certain circumstances, it is important to know the current temperature of an integrated circuit (IC) so as to respond accordingly. For example, a dynamic random access memory (DRAM) requires a refresh action at given times so as to maintain the data stored in the memory cells. The higher the ambient temperature, the more often the refresh action has to be performed because the leakage current of the memory cells is proportional to the ambient temperature. If a DRAM is not installed with a temperature detector, it has to operate at the fastest rate even at a cooler temperature to ensure correct operations, thus wasting power.
U.S. Pat. No. 5,691,661 discloses a pulse signal generating circuit including a ring oscillator and an internal voltage generating circuit. The internal voltage is low at a normal temperature and high at a high temperature. The inverters in the ring oscillator are driven by the internal voltage from the internal voltage generating circuit. As a result, the period of a pulse signal increases at a normal temperature, and decreases at a high temperature. Although U.S. Pat. No. 5,691,661 discloses a temperature detector in DRAM, its temperature-sensing mechanism is not accurate enough to satisfy the need to reduce power consumption in modern IC designs.
US 2006/0140037 A1 discloses an oscillator generating a temperature variable signal that has a frequency proportional to the ambient temperature. By means of a temperature invariant oscillator and an n-bit counter, the ambient temperature can be estimated. In other words, the faster the counter counts, the larger the count value at the end of a sense cycle initiated by the temperature invariant oscillator. A larger count value indicates a warmer temperature, and a smaller count value indicates a colder temperature. The disadvantage of US 2006/0140037 A1 is that the temperature reading is not accurate enough.
SUMMARY OF THE INVENTION
The above-mentioned problems are addressed by the present invention. The structure and method of the present invention will be understood according to the disclosure of the following specification and drawings.
According to one embodiment of the present invention, the temperature detector in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator, a timer and a clock-driven recorder. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of the at least one temperature-dependent voltage. The timer is configured to generate a time-out signal, which is affected by one of the temperature-dependent voltage. The clock-driven recorder has a clock input terminal in response to the clock signal and time-out signal.
According to one embodiment of the present invention, a dynamic random access memory (DRAM) comprises a memory array, a memory controller and a temperature detector. The memory array has a plurality of memory cells. The memory controller provides a refresh signal to maintain the content of the memory cells. The temperature detector is used to determine the rate of the refresh signal.
According to one embodiment of the present invention, a temperature-compensated charge pump in an integrated circuit comprises a temperature-dependent voltage generator, a ring oscillator and a charge pump. The temperature-dependent voltage generator is configured to generate at least one temperature-dependent voltage. The ring oscillator is configured to generate a clock signal, which is affected by one of the at least one temperature-dependent voltage. The charge pump is affected by one of the at least one temperature-dependent voltage and the clock signal.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described according to the appended drawings in which:
FIGS. 1(a) and 1(b) show temperature detectors in an integrated circuit in accordance with one embodiment of the present invention;
FIG. 2 shows an exemplary circuit of the temperature-dependent voltage generator;
FIG. 3 shows an exemplary circuit of the ring oscillator;
FIGS. 4(a) and 4(b) shows exemplary circuits of the shift register and D-flip flop;
FIGS. 5(a) and 5(b) show exemplary circuits of the timer;
FIG. 6 shows an exemplary DRAM;
FIG. 7 shows a symbol diagram of a charge pump; and
FIGS. 8(a) and 8(b) show the relationship between the pumping current and the period of the signal OSCP.



DETAILED DESCRIPTION OF THE INVENTION
FIG. 1(a) shows a temperature detector in an integrated circuit in accordance with one embodiment of the present invention. The temperature detector 10 includes a temperature-dependent voltage generator 11, a ring oscillator 12, a timer 13, a shift register 14 and a look-up table 15. The temperature-dependent voltage generator 11 is used to generate at least one temperature-dependent voltage. The ring oscillator 12 is configured to generate a clock signal OSCP, which is affected by the at least one temperature-dependent voltage. The timer 13 is configured to generate a time-out signal TO, which is affected by one of the temperature-dependent voltage. The shift register 14 has a clock input terminal in response to the clock signal OSCP and time-out signal TO. The look-up table 15 is used to decode an accurate ambient temperature in accordance with the content of the shift register 14. The look-up table 15 may be omitted if there are other easy ways to decode the content of the shift register 14. FIG. 1(b) shows a temperature detector 10′ in an integrated circuit in accordance with another embodiment of the present invention. The difference between it and the structure in FIG. 1(a) is that the shift register 14 is replaced by a counter 16. No matter it is the shift register 14 or the counter 16 that is selected, they are both clock-driven recorders which accumulate the number of input clocks. Please note that because the ring oscillator 12 and timer 13 are affected by the temperature-dependent voltage generated by the temperature-dependent voltage generator 11, the ring oscillator 12 and timer 13 are both temperature variable elements.
FIG. 2 shows an exemplary circuit of the temperature-dependent voltage generator 11. The voltage source VA is a temperature-independent voltage. The two input ends of the differential amplifier 21, VA and VRD, have the same voltage. A bipolar transistor pair 23 includes two bipolar transistors having the same size as the collectors coupled to their bases. Therefore the current flowing through the resistor R3 is the same as the current flowing through the resistor R4. Alternatively, a single resistor can be used to replace the resistors R3 and R4, and then connected to a single transistor which is used to replace the bipolar transistor pair 23.




  
    
      V
      ⁢
      
        
      
      ⁢
      A
    
    =
    
      VRD
      =
      
        
          
            R
            ⁢
            
              
            
            ⁢
            2
          
          
            
              R
              ⁢
              
                
              
              ⁢
              1
            
            +
            
              R
              ⁢
              
                
              
              ⁢
              2
            
          
        
        ×
        VR
      
    
  
  ,




which is a constant.





   
  
    
      
        
          PTDV
          =
          
          ⁢
          
            VBE
            +
            
              I
              ×
              R
              ⁢
              
                
              
              ⁢
              4
            
          
        
      
    
    
      
        
          =
          
          ⁢
          
            VBE
            +
            
              I
              ×
              R
              ⁢
              
                
              
              ⁢
              3
            
            +
            
              I
              ×
              
                (
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                  -
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                )
              
            
          
        
      
    
    
      
        
          =
          
          ⁢
          
            
              V
              ⁢
              
                
              
              ⁢
              A
            
            +
            
              I
              ×
              
                (
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                  -
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                )
              
            
          
        
      
    
    
      
        
          =
          
          ⁢
          
            
              V
              ⁢
              
                
              
              ⁢
              A
            
            +
            
              
                
                  
                    V
                    ⁢
                    
                      
                    
                    ⁢
                    A
                  
                  -
                  VBE
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              ×
              
                (
                
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    4
                  
                  -
                  
                    R
                    ⁢
                    
                      
                    
                    ⁢
                    3
                  
                
                )
              
            
          
        
      
    
    
      
        
          =
          
          ⁢
          
            
              
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  4
                
                
                  R
                  ⁢
                  
                    
                  
                  ⁢
                  3
                
              
              ×
              VA
            
            -
            
              
                (
                
                  
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      4
                    
                    
                      R
                      ⁢
                      
                        
                      
                      ⁢
                      3
                    
                  
                  -
                  1
                
                )
              
              ×
              VBE
            
          
        
      
    
  




Because




  
    
      R
      ⁢
      
        
      
      ⁢
      4
    
    
      R
      ⁢
      
        
      
      ⁢
      3
    
  
  ×
  V
  ⁢
  
    
  
  ⁢
  A




is constant, the signal PTDV varies as





  
    (
    
      
        
          R
          ⁢
          
            
          
          ⁢
          4
        
        
          R
          ⁢
          
            
          
          ⁢
          3
        
      
      -
      1
    
    )
  
  ×
  VBE




varies. The voltage VBE, which represents the base-emitter voltage of the bipolar transistor pair 23, is adversely proportional to the ambient temperature. In other words, the signal PTDV is proportional to the ambient temperature, and the parameter





  
    R
    ⁢
    
      
    
    ⁢
    4
  
  
    R
    ⁢
    
      
    
    ⁢
    3
  




can be used to adjust the factor of temperature variance to the signal PTDV. The two input ends of the differential amplifier 24, PTDV and VCX, have the same voltage. Because the signal PTDV is proportional to the ambient temperature, so is the signal VCX. The two input ends of the differential amplifier 26 and the signal PTDV1, which is divided by the signal PTDV and GP, have the same voltage. Because the signal PTDV is proportional to the ambient temperature, so is the signal GP.

FIG. 3 shows an exemplary circuit of the ring oscillator 12. The signal VCX acts as the voltage supply of the ring oscillator 12, and the signal EN activates the ring oscillator 12. The signal OSCP is the output clock signals of the ring oscillator 12. The higher temperature, the higher the clock rate of the signal OSCP.
FIG. 4(a) shows a symbol diagram of a D-flip flop (dff) 41, whose schematic diagram is shown in FIG. 4(b). The structure in FIG. 4(a) includes a shift register 14 with 50 D-flip flops 41 connected in series. The first D-flip flop has an input VCC, and its output is sent to the input terminal of the second D-flip flop. The output of the second D-flip flop is sent to the input terminal of the third D-flip flop, and so on. Two clock signals CK1 and CK2, which are generated by combining the signal OSCP and a time-out signal TO, are non-overlapping with each other.
FIG. 5(a) shows an exemplary circuit of the timer 13, where the power V2X is a temperature-independent voltage. The signal GP, which as mentioned above is proportional to the ambient temperature, controls the enablement of the PMOS transistors 51, and the temperature-independent voltage VR controls the enablement of the NMOS transistors. The signal TO, which represents the time-out signal, controls the enablement of the transmission gate 52. In FIG. 5(b), when the output AA of the timer 13 is at logic high, the time-out signal TO will turn to logic low, which means the time-out condition is fulfilled. In other words, the higher temperature is, the more the time-out point generated by the timer 13 will be postponed, which results in more sensitivity of the present invention.
As shown in Table 1, a lower temperature has a longer period of the signal OSCP but a shorter signal TO, and a higher temperature has a shorter period of the signal OSCP but a longer signal TO. Therefore, the sensitivity of actual temperature reading is improved at a high temperature, and power consumption can be effectively reduced at a low temperature.












TABLE 1







PTDV
GP
OSCP
TO




















 0° C.
1.54 V
0.77 V
16.9 ns
 94 ns


90° C.
1.96 V
0.98 V
13.2 ns
500 ns









As shown in Table 2, Q[n] means the output of the shift register 14, the state of which represents the ambient temperature. For example, Q[4:40] can be utilized to indicate the temperature between 0° C. and 90° C. It is evident that the temperature can be read by counting the number of logic 1 in Q[n] or by decoding it according to the look-up table 15.








TABLE 2







 0° C.
Q[0:3] = H, Q[4:49]


30° C.
Q[0:9] = H, Q[10:49]


60° C.
Q[0:18] = H, Q[19:49]


90° C.
Q[0:40] = H, Q[41:49]









FIG. 6 shows an exemplary DRAM. The DRAM 60 includes a memory array 61, a memory controller 62 and a temperature detector 10. The memory array 61 has a plurality of memory cells 63. The memory controller 62 provides a refresh signal to maintain the content of the memory cells 63. The temperature detector is used to determine the ambient temperature, which affects the rate of the refresh signal.
The temperature dependent OSCP can be used as the clock to a charge pump to save the consumption current. FIG. 7 shows a symbol diagram of a charge pump 71, e.g., a Jackson-type charge pump, where the signal CTL represents the enablement signal, and signal OSCP acts as the clock input of the charge pump 71.
Table 3 shows an exemplary relationship between the signals PTDV and OSCP, in which the smaller the signal PTDV the longer the period of the signal OSCP.










TABLE 3







PTDV
OSCP


















 0° C.
1.53 V
17.9 ns


90° C.
1.96 V
  14 ns









Please refer to FIGS. 8(a) and 8(b). The maximum pumping current under the condition of 90° C., 2.5V (VPP) occurs when the period of the signal OSCP is 14 ns. But under this condition (OSCP: 14 ns), the pumping current




  
    
      0.139
      ⁢
      
        
      
      ⁢
      mA
    
    
      0.127
      ⁢
      
        
      
      ⁢
      mA
    
  
  =
  1.094




is times than the current at 0° C., 2.5V. At 0° C., the period of the signal OSCP is 18 ns and gets the same pumping current as that at 90° C., but





  
    iVcc
    =
    
      
        
          2.5
          ⁢
          
            
          
          ⁢
          mA
          ⁢
          
            
          
          ⁢
          
            (
            
              18
              ⁢
              
                
              
              ⁢
              ns
              ⁢
              
                
              
              ⁢
              period
            
            )
          
        
        
          2.85
          ⁢
          
            
          
          ⁢
          mA
          ⁢
          
            
          
          ⁢
          
            (
            
              14
              ⁢
              
                
              
              ⁢
              ns
              ⁢
              
                
              
              ⁢
              period
            
            )
          
        
      
      =
      0.877
    
  
  ,




which means 13% power is saved. Another example is that at 0° C. and 3.6V,





  
    
      
        iVcc
        ⁢
        
          
        
        ⁢
        
          (
          
            at
            ⁢
            
              
            
            ⁢
            18
            ⁢
            
              
            
            ⁢
            ns
          
          )
        
      
      
        iVcc
        ⁢
        
          
        
        ⁢
        
          (
          
            at
            ⁢
            
              
            
            ⁢
            14
            ⁢
            
              
            
            ⁢
            ns
          
          )
        
      
    
    =
    
      
        5.1
        6.2
      
      =
      0.836
    
  
  ,




which means 14% power is saved.

The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.

## Claims

1. A temperature detector in an integrated circuit, comprising:
a temperature-dependent voltage generator configured to generate at least one temperature-dependent voltage;
a ring oscillator configured to generate a clock signal, wherein a clock rate of the clock signal is affected by one of the at least one temperature-dependent voltage;
a timer configured to generate a time-out signal, wherein the time-out signal is affected by one of the at least one temperature-dependent voltage; and
a clock-driven recorder having a clock input, wherein the clock input is in response to the clock signal and time-out signal, and the clock-driven recorder is used to estimate a temperature reading.

2. The temperature detector of claim 1, wherein the clock-driven recorder is a shift register.

3. The temperature detector of claim 1, wherein the clock-driven recorder is a counter.

4. The temperature detector of claim 1, further comprising a look-up table for use in decoding the content of the clock-driven recorder.

5. The temperature detector of claim 1, wherein the temperature-dependent voltage generator comprises only a bipolar transistor.

6. The temperature detector of claim 1, wherein the temperature-dependent voltage generator comprises a bipolar transistor pair which includes two bipolar transistors having the same size with the collectors of the transistors coupled to the base thereof.

7. The temperature detector of claim 1, wherein the ring oscillator has a voltage supply provided by one of the at least one temperature-dependent voltage.

8. The temperature detector of claim 1, wherein the timer has PMOS and/or NMOS transistors which are controlled by one of the temperature-dependent voltage.

9. The temperature detector of claim 7, wherein the temperature-dependent voltage is proportional to the ambient temperature.

10. The temperature detector of claim 1, wherein the time-out signal appears later as the temperature increases.

11. A dynamic random access memory (DRAM) comprising:
a memory array having a plurality of memory cells;
a memory controller providing a refresh signal to maintain the content of the memory cells; and
a temperature detector according to claim 1, wherein the temperature detector is used to determine the rate of the refresh signal.

12. The DRAM of claim 11, wherein the clock-driven recorder is a shift register.

13. The DRAM of claim 11, wherein the clock-driven recorder is a counter.

14. The DRAM of claim 11, further comprising a look-up table for use in decoding the content of the clock-driven recorder.

15. The DRAM of claim 11, wherein the ring oscillator has a voltage supply provided by one of the at least one temperature-dependent voltage.

16. The DRAM of claim 11, wherein the timer has PMOS and/or NMOS transistors which are controlled by one of the temperature-dependent voltage.

17. The DRAM of claim 15, wherein the temperature-dependent voltage is proportional to the ambient temperature.

18. The DRAM of claim 11, wherein the time-out signal appears later as the temperature increases.