# Patent

## Title
High voltage linear amplifier driving heavy capacitive loads with reduced power dissipation

## Abstract

A capacitive load drive circuit may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

## Background
RELATED CASES
The present application claims priority to U.S. Provisional Application No. 61/206,120, filed on Jan. 28, 2009, the disclosure of which is hereby incorporated by reference. This application is also related to U.S. patent application Ser. No. 12/571,352, filed on the same day as the present application, entitled A STEPPED VOLTAGE DRIVE FOR DRIVING CAPACITIVE LOADS, and assigned to the same assignee as the present application, the disclosure of which is hereby incorporated by reference.


FIELD
The present invention relates to high voltage capacitive load driving circuits, which may be such as a piezoelectric transducer, and more particularly a matrix of piezoelectric transducers, such as may be used in inkjet printer heads to actuate the production of an individual ink droplet in the respective actuated ink jet droplet making mechanism in an inkjet head of an inkjet printer.
BACKGROUND
Heavy capacitive loads are very common in industrial and commercial systems and equipment. A common example is a piezoelectric element which is used extensively in such applications as ink jet printers, speakers and motor drives. A piezoelectric element, formed by piezoelectric material sandwiched between two electrodes, is typically electrically modeled as a large capacitor, with the piezoelectric material acting as both a dielectric between the electrodes and an actuator under the influence of the electric field resulting from the application of a voltage across the electrodes. Indeed, an entire matrix of piezoelectric actuators for individual droplet making mechanisms in an inkjet printer head may be modeled as a single capacitive load. Throughout this application, unless otherwise expressly stated, discussion of a capacitive load in the form of a piezoelectric actuator will be understood to also include a matrix of such actuators producing a single capacitive load to which an output voltage is applied, and that this capacitive load also has typically resistive and inductive components to it.
The electrical drive to the capacitive load such as a piezoelectric actuator may be a controlled high voltage waveform delivered, as an example, once per cycle of printer head operation or the like. The shape, period and frequency of this waveform can be heavily dependent upon the application. Most piezoelectric element drive waveforms have fast switching transitions. There may also be a need for a portion of the waveform to exhibit finer linearity control and timing control, such as when the droplet is actually formed in the output of the respective ink jet printer ink jet nozzle and sized as it is ejected at a finely controlled time. Improvements in the ability to control these parameters are always in need to enhance such things as printer performance.
Therefore, typically a fast linear high voltage (HV) amplifier is used to deliver the waveform to the piezoelectric element. In such a fast linear high voltage (HV) amplifier, power dissipated while switching a load capacitor between a low voltage, such as a ground voltage GND (e.g., a zero voltage) to the high voltage VDD (as an example 50V) is given by:

Pdiss=CL×VDD2×·f  (1)

where CL=Load Capacitor capacitance, f=Frequency of drive waveform.

Existing linear capacitive load drives conform to equation 1. This relationship can result in limitations on attributes of the application or engineering system, such as maximum load capacitance and frequency of the waveform. This relationship can further limit the number of actuators that can be driven, such as in the piezoelectric inkjet printer print head application, the number of inkjets and thereby the resolution of the printing by the print head, as well as the speed of printing, i.e., cycles per second of actuation. Achieving higher resolution and higher frequency of the drive voltage waveform is generally desirable. In inkjet printer piezoelectric applications, faster operation is always a goal resulting in faster printing speed.
FIG. 3 is an example of a conventional high capacitive load drive circuit 140, utilizing a single amplifier, which may be like a PA78, PA79, PA86, PA69 or PA243 amplifier, available from applicants' assignee Cirrus Logic. The circuit 140 may have a class B gate drive amplifier 142 utilized to drive a load capacitor 132 (“CLOAD”), connected to ground 170. The amplifier 142 may have a negative input 152, which is connected to ground 170 through a resistor 156, such as a 1K ohm resistor and connected to the output through a resistor 169 such as a 9K resistor. The amplifier 142 may have a positive input 150 connected to an input voltage 153, which may be an arbitrary drive voltage waveform which is, in turn, connected to ground 170.
The amplifier 142 may have a HiGate output 178 connected to the gate of an external high power PFET 176, and a LoGate output 174 connected to the gate of an external high power NFET 172. The amplifier 142 may be implemented on an integrated circuit, and “external” means that the PFET and NFET may be, but need not necessarily be, implemented in a separate integrated circuit and packaged separately (“external”) to the amplifier 142, depending on the current drive required for the capacitive load. The source of the PFET 176 may be connected through a resistor 151, such as a 0.1 ohm resistor, to a high voltage source 180, such as a 50 V source V50, in which the high voltage source 180 is, in turn connected to ground 170. The source of the NFET 172 may be connected to ground 170 through a resistor 171, such as a 0.01 ohm resistor for current sense. The drains of the PFET 176 and NFET 172 are connected to the load capacitor CLOAD 132, such as a 527.4 nF capacitor. It will be understood that as high power integrated circuit technology advances, it may become possible to integrate more of or even all of the circuitry described in this application and related appropriate and necessary circuitry on a single integrated circuit so that “external” power FETs and the like need no longer be “external.”
The output node of the amplifier connected to the load capacitor 132 may also be feed back to the negative input 152 of the amplifier 142 through a parallel RC arrangement containing a resistor 169, such as a 9 K ohm resistor and a capacitor 168, such as a 40 pF compensation capacitor, in parallel with resistor 169. The closed loop gain of the amplifier 142 is set by the resistive divider network comprised of resistors 169 and 156.
The amplifier 142 may have a +VS connection 148 to a high voltage supply 150, such as a 50 V supply, which voltage supply 180 is also connected to ground 170. The voltage supply 180 is also connected to the source of the PFET 176 through the resistor 151. The amplifier 142 may also have a connection 149 to a voltage supply 144, such as a 12 V voltage supply, also connected to ground 170 to set the gate drive voltage. The amplifier 142 may also have a −VS connection 143 connected to ground 170 and a GND connection 145 connected to ground 170, along with a VG connection to a voltage supply 144, such as a 12 V voltage supply also connected to ground 170.
In operation, the HiGate output 178 of the amplifier 142, in response to the rising portion of the input 153, controls the voltage applied to the gate of the PFET 176 which controls the current flow through the PFET 176 to the load capacitor 132 and, in response to the falling portion of the input voltage 153, controls the gate of the NFET 172 to regulate the current flow from the CLOAD capacitor 132 as the CLOAD capacitor 132 discharges to ground during a ramp down period. The load capacitor CLOAD 132 thus charges up to from 0V to VS (e.g., 50 V) during the ramp up and discharges from 50V to 0V during the ramp down, assuming ground is 0V.
The disadvantages to such operation with a single amplifier 142 are as noted, namely, that the amplifier 142 exhibits high power dissipation and high cost. For piezoelectric inkjet printer applications, this disadvantage limits the resolution of printing and the speed of printing. Applicants have found that a better design according to aspects of the disclosed and present invention can reduce power dissipation in the drive circuit and save cost for the application.
Adiabatic switching (between rail high or low voltage and the other rail voltage in sequential rails) has been employed in digital circuits at low voltages as indicated in the following references. Indermaur et al., Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power CMOS Design, IEEE Symposium on Low Power Electronics (1994), relates to charge recovery through adiabatic switching for power reduction in CMOS integrated circuits. Gabara, Pulsed Power Supply CMOS-PPS CMOS, IEEE Symposium on Low Power Electronics (1994), relates to similar ramped driving and charge recovery, called “pulsed power” in CMOS circuits. Similarly Svensson et al., Driving a Capacitive Load Without Dissipating fCV2, IEEE Symposium on Low Power Electronics (1994), describes a similar “stepwise charging” in CMOS circuits.
FIG. 6 shows a schematic diagram of a circuit 310 useful in understanding energy dissipation while driving a capacitive load CLOAD 320. FIG. 6 shows two switches 322, 324 for charging and discharging the capacitor CLOAD 320. The circuit 310 includes a voltage supply 326, such as a 50 V DC power supply VDD, which when voltage controlled switch 322 is closed charges the load capacitor 320 through a resistor 328 that is modeling the on resistance of switch 322, and a voltage controlled switch 324, which, when closed, discharges the load capacitor 320 through a resistor 330 to ground. Each of the switches 322, 324 has a respective switch voltage supply 340, 342 to assist in the control of the timing and operation of the respective switches.
FIG. 6 shows switch 322, that when closed charges the load capacitor 320 with a charge Q=CLOAD×VDD. The energy from the supply 326 to provide this charge is ESUPPLY=Q×VDD=CLOAD·VDD2. The energy stored in the capacitor 320 is EC=CLOAD×VDD2/2.
These results can also be derived by integrating the instantaneous power over the period of interest.



  
    
      
        
          
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This analysis shows that half of the energy supplied by the voltage source is stored in the load capacitor while the other half is dissipated in switch 322 and resistor 328. During the discharge phase the charge is removed from CLOAD 320 and the energy is dissipated in switch 324 and resistor 330. Thus the energy dissipated during each switching cycle is given by:

Ediss=CLOAD·VDD2=2500·CLOAD(VDD=50V)  Equ (1)

While existing systems are of great benefit, there is need to improve performance of capacitive load drive systems, such as piezoelectric drive systems, including through energy savings, improved speed of operation, and the ability to drive more load elements, such as more piezoelectric elements. Advantageously the resolution of inkjet printers can be improved according to aspects of embodiments of the present invention present invention.
SUMMARY
In one aspect, a high load drive circuit according to a possible embodiment of the disclosed subject matter may comprise two amplifiers, such as a high current, high voltage gate drive amplifier for initial ramp up and final ramp down for each cycle and a floating voltage linear operational amplifier for finely tuning the transition at the top of the cycle waveform.
It will be understood that a capacitive load drive circuit is disclosed which may comprise a high current drive amplifier configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage; a low current drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and the high current drive amplifier configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the high current ramp up and the high current ramp down. The low current drive amplifier may comprise an amplifier having a linear response in the range of the low current ramp up. The capacitive load may comprise a piezoelectric element, which may comprise an element of an ink jet printer head ink droplet producing mechanism. The low current drive amplifier may comprise a floating low voltage amplifier.
It will also be understood that a capacitive load drive circuit and method of load driving is disclosed which may be utilized in lieu of the high voltage/high current drive amplifier during the high current ramp up and high current ramp down and may comprise a stepped voltage drive circuit configured to cyclically charge a capacitive load to a selected high voltage during a ramp up and configured to discharge the capacitive load to a selected low voltage during a ramp down, which may comprise a voltage supply circuit comprising a circuit configured to sequentially supply to the load a variable voltage varying between each of a plurality of rails, each rail having a rail high voltage and a rail low voltage with the rail low voltage of the sequentially next rail essentially equal to the rail high voltage of the sequentially preceding rail, during the ramp up, and configured to supply to the load a variable voltage varying between each of a plurality of rails, each having a rail high voltage and a rail low voltage, with the rail high voltage of the sequentially next rail essentially equal to the rail low voltage of the sequentially preceding rail during the ramp down.
In an illustrative embodiment, the rails may be equal and some fraction of a high voltage such as VDD/n where n is the number of separate rails. The rails could be VDD/n positive rails and VDD/n negative rails, such as 0V−(+VDD/4), +VDD/4−(+VDD/2), +VDD/2−(+3VDD/4), (+3VDD/4)−VDD and −VDD (−3VDD/4), −3VDD/4−(−VDD/2,)−VDD/2−(−VDD/4) and −VDD/4−0V assuming four positive and four negative rails of equal difference between the rail high voltage and the rail low voltage, i.e., VDD/4.
The drive circuit could also comprise a multi-stage stacked charging circuit configured to be electrically connected to the capacitive load and may comprise a first capacitor configured to be electrically connected to the capacitive load through a first switch during a first charging time period; a voltage supply configured to be electrically connected to the capacitive load through a second switch during a second charging time period; with the first capacitor configured to be electrically connected to the capacitive load through the first switch during a first discharging time period. The circuit may also comprise a third switch configured to electrically connect the capacitive load to the selected low voltage during a second discharging time period.
The voltage supply circuit could comprise an n-stage stacked voltage supply circuit, where n is an integer greater than or equal to 2, which may comprise n−1 capacitors and a voltage supply configured to each be sequentially electrically connected to the capacitive load through a respective first through nth switch during a respective first through nth charging time period; the n−1th capacitors configured to each be sequentially electrically connected to the capacitive load in reverse order during a first through n−1th discharging time period through the respective n−1th through first switches. The circuit may also comprise an n+1th switch configured to be electrically connected to the capacitive load to the selected low voltage during an nth discharging period. The drive circuit could comprise an amplifier selectively connected across a plurality of n sequential intermediate rails each with a rail high voltage V1 and a rail low voltage V2 with respective selected ranges having an increasing value of V1 during the ramp up and with the respective ranges having a decreasing value of V1 during the ramp down, each defining an output range of the amplifier. The amplifier could comprise an operational amplifier, and V1-V2 could be the same for each respective rail. The rails can extend between a positive circuit high voltage and a negative circuit low voltage. It will also be understood that the capacitive load drive circuit according to aspects of an embodiment of the present invention may comprise a stepped voltage drive circuit configured to cyclically charge a capacitive load to a selected high voltage during a high current ramp up and configured to discharge the capacitive load to a selected low voltage during a high current ramp down, which may comprise: a voltage supply circuit comprising a circuit configured to sequentially supply to the load a variable voltage varying between each of a plurality of rails, each rail having a rail high voltage and a rail low voltage with the rail low voltage of the sequentially next rail essentially equal to the rail high voltage of the sequentially preceding rail, during the high current ramp up, and configured to supply to the load a variable voltage varying between each of a plurality of rails, each having a rail high voltage and a rail low voltage, with the rail high voltage of the sequentially next rail essentially equal to the rail low voltage of the sequentially preceding rail during the high current ramp down; and may comprise a low current linear drive amplifier configured to be connected to the capacitive load during a low current ramp up of the voltage to the capacitive load, intermediate the high current ramp up and high current ramp down.



BRIEF DESCRIPTION OF THE DRAWINGS
The features, functions, and advantages that are disclosed can be achieved independently in various embodiments of the present disclosure or may be combined in yet other embodiments, further details of which can be seen with reference to the following description and drawings, wherein like numerals depict like parts, and wherein:
FIG. 1 shows a schematic block diagram of a high capacitive load drive circuit 20 according to aspects of an embodiment of the present invention;
FIG. 2 shows an example of a waveform used to drive capacitive loads such as piezoelectric elements in an inkjet printer head droplet producing mechanism which applicants have used to simulate the operation of the circuit of FIG. 1;
FIG. 3 shows a schematic block diagram of an example of a conventional high capacitive load drive circuit;
FIG. 4 shows a simulated wave form for the output of the circuit of FIG. 1;
FIG. 5 shows schematically a transducer actuator for an ink droplet producing mechanism as part of an ink jet printer head in an ink jet printer according to aspects of an embodiment of the present invention;
FIG. 6 shows a conventional voltage drive circuit;
FIG. 7 shows a schematic circuit diagram of a drive circuit according to aspects of an embodiment of the present invention;
FIG. 8 shows schematically an example of a timing of the operation of the circuit of FIG. 7.
FIG. 9 shows a schematic circuit diagram of a drive circuit according to aspects of an embodiment of the present invention;
FIG. 10 shows an example of a simulation of the operation of the circuit of FIG. 9;
FIG. 11 shows a graph of normalized energy dissipation for given values of a step voltage; and
FIG. 12 shows in schematic and block diagram form a variable voltage staged capacitive load drive circuit with a circuit such as is illustrated in FIG. 9 replacing an amplifier as illustrated in FIG. 1.



DETAILED DESCRIPTION
A novel linear amplifier drive according to aspects of the present invention can be utilized to reduce a substantial amount of power dissipation in piezoelectric systems or like systems involving driving large capacitive loads. As an example, aspects of the present invention can greatly improve performance of piezoelectric drive systems including through energy savings, improved speed of operation, ability to drive more piezoelectric elements, as an example allowing increased resolution of inkjet printing and reduced costs. Also an improvement according to aspects of the present invention is the uniformity of the response of the overall drive circuit to the input, especially at the top of the cyclic driving waveform.
A simplified schematic block diagram shown in FIG. 1 is a high capacitive load drive circuit 20 according to aspects of an embodiment of the present invention. The illustrative circuit 20 has two amplifiers 22, 34 driving a load capacitor CL 32, such as a 527.4 nF capacitor. Amplifier 22 may be a high voltage—high current output amplifier, such as a class B, C or D gate driver amplifier, capable of driving large currents on the order of as an example 30-50 amps. The amplifier 22 is selected to be able to drive fast HV transitions and handle the high peak currents, such as a model one of the Cirrus Logic amplifiers noted above. Amplifier 34 may be a floating low voltage linear amplifier with lower current drive capability than amplifier 22 and at the same time having better linearity over its output voltage range.
Amplifier 34 may be selected to have a very linear output voltage in the range in which it is used to form part of the drive output voltage waveform, such as is shown in FIG. 2 in each given actuation cycle, i.e., from the peak voltage generated by amplifier 22 to the peak voltage of the entire drive circuit 20. Amplifier 34 thus acts as a linear amplifier for the slow transitions at high voltage with high gain accuracy over a relatively shorter range of output voltages.
It will be understood by those skilled in the art, that this portion of the output voltage waveform is most important to delivering a finely timed and tuned output of the drive circuit 20. In the example of an individual ink jet printer head ink jet producing mechanism piezoelectric actuator, a droplet of the right size and with the right timing is very dependent on the accuracy of this portion of the drive circuit output waveform. This aids in, among other things, the accuracy of the image being reproduced on the surface being printed upon by the inkjet printer. Those skilled in the art will understand that there are other applications for such a drive circuit.
The capacitive load driver circuit 20 can have high voltage/high current amplifier 22, similar to or the same as the amplifier 142 of FIG. 3, connected between a voltage supply VS 24, which may be at 40-50 volts, as an example, and ground 26. This connection defines the range of the output of the amplifier 22. The output of the amplifier 22 may be connected to the load capacitor 32 through a voltage controlled switch 30 in the high current path to the load capacitor 32. This connection, through voltage controlled switch 30, as with amplifier 142 in FIG. 3 connects a high voltage, such as a 40 V VS when the HiGate output 52 of the amplifier 22 is controlling the PFET 60 during a ramping up period as the drive circuit output waveform illustrated by way of example in FIG. 2 goes from a low voltage, such as 0V, to a high voltage, such as VS (e.g., 40 V) and connects to the load capacitance CLOAD 32. When the LowGate output 54 of the amplifier 22 is controlling the gate of the NFET 62 during the discharge of the load capacitor CLOAD 32 from, as illustrated in FIG. 2, a high voltage of VS, as an example, to a low voltage, such as ground 26, once again, while switch 30 is also closed.
The output node (“OUT2”) of the amplifier 22, connected to the load capacitor 32 may be fed back to the negative input 58 of the amplifier 22, through an RC network containing a capacitor 66, such as a 40 pF compensation capacitor, and a resistor 64, such as a 9K ohm resistor in order to set closed loop gain.
The low voltage floating linear amplifier 34 may be connected through a similar switch 36 to the load capacitor 32 in a low current path. The amplifier 34 may be connected across a higher voltage supply 38 (VS+VDD) through a VDD connection 41 and supply voltage VS, through a VSS connection 43, such as with VDD equal to in the range of about ten volts or so, such that VS+VDD equals 50V in the exemplary circuit of FIG. 1 and 48V in the exemplary waveform of FIG. 2. This connection defines the range of output from the amplifier 34 to between VS and VS+VDD. A VS level translator 40 may be connected between a drive circuit input 50 and the positive input 62 of amplifier 34, with the input 50 connected directly to the positive input 56 of the amplifier 22. Voltage supply VS may also be connected to the negative input 60 of the amplifier 34 through resistor 64. The output of the amplifier 34 may be fed back to the negative input 60 of the amplifier 34 through a resistor 66, such as a 1K resistor.
Amplifier 34 can operate as a floating low voltage linear operational amplifier, using a floating VDD supply (with respect to VS) as a positive voltage supply. The return for amplifier 34 in the illustrative circuit 20 is the high voltage supply Vs. The input to the floating amplifier is level translated by the level translator block 40. The timing of the switches 30, 36 are controlled by the two comparators (not shown in the figure).
FIG. 2 shows an example of an ideal waveform used to drive capacitive loads such as piezoelectric elements in an inkjet printer which applicants have used to simulate the operation of the circuit of FIG. 1. As shown in the FIG. 2, region 1 uses amplifier 22 as a switching amplifier and drives peak current of 36 A for a 0.8 μF load for an exemplary 0.9 μs duration which defines a ramping up period from the low voltage of 0V to a high voltage of 40 V. During this ramp up phase in the exemplary circuit of FIG. 1, the HiGate output 52 of the amplifier 22 is controlling the current flow through the PFET 60 and the drain of the PFET 60 is connected to the load capacitance 32 through switch 30.
The simulation results for the exemplary circuit of FIG. 1 are shown in FIG. 4. The input to the amplifier 34 can be ramping up relatively slowly during the illustrated period of time in FIG. 4 from about 5 μs to around 10 μs, corresponding to the period 2 in the illustration of FIG. 2. Thus, the output (“OUT1”) of the amplifier 34 ramps up from a voltage of VS to approximately VS+10V, while, as illustrated in FIG. 4, the input voltage on input 62 of the amplifier 34 is not ramping up between about 10 μs and about 14 μs, so that the output of amplifier 34 does not increase during that period of time corresponding generally to the period marked 2′ in FIG. 2.
Region 2 uses a floating linear amplifier 34 that drives 3.3 A of current in region 2 for the exemplary 1.94 μs. Switch 30 is open and switch 36 is closed. The amplifier 34 is responding to an input on positive input 62, which, as noted, may have a waveform as shown as curve 90 in the simulated operating curves of FIG. 4, curve 92 corresponding to the ramp up period of amplifier 22.
The drive circuit 20 in regions 3 and 4 goes back to switching amplifier 22, with switch 36 open and switch 30 closed and drives peak current of 37 A for 1.04 μs, including in region 3, a 0.17 μs period between a peak voltage, shown as an example to be 48 V, and a lower voltage, e.g., matching the peak voltage output of the amplifier 22 in region 1, i.e., 40 V, and a 0.87 period between 40 V and 0 V. With switch 30 closed, the amplifier 22 is controlling the discharge of the load capacitor 32 to ground 26 through the NFET 62, by applying a variable voltage to the gate of the NFET 62. The discharge follows the simulation curve 92′ of FIG. 4 in response to the input signal curve 90 shown in the simulation of FIG. 4, responsive to the input signal relatively rapidly ramping down after about the 14 μs time until about the 19 μs time. The ramp up and ramp down times are different between the waveform in FIG. 2. and simulated wave in FIG. 4. Thus, the peak currents drawn will be different between FIG. 2 and FIG. 4 for the same capacitive load.
During the amplification carried out by amplifier 22 in region 2 of FIG. 2 (between about 5 μs and 11 μs is as illustrated in the simulation curves shown in FIG. 4), very fine control can be exerted over and actuator such as the piezoelectric unit 130 in FIG. 5, squeezing an ink drop out of an ink jet printer head in an ink jet printer head ink droplet producing mechanism.
It will be understood that various ways may be utilized to control the timing of the operation of certain aspects of the drive circuit according to embodiments of the present invention. For example, the circuit could be controlled by switching control, such as, with voltage controlled switches, such as 30, 36 as discussed above. These switches 30, 36 could be controlled by a controller (not shown) setting voltage signals to the V+, V− terminals of the voltage controlled switches, according to some desired waveform similar to the ones illustrated as examples in FIGS. 2 and 4. The specific timing and shape of the waveforms as exemplified in FIGS. 2 and 4 depend heavily on the particular application. As an example, the droplet producing mechanism 120 illustrated schematically in FIG. 5 may need a rapid application of pressure or force to the channel 124 to initiate droplet production within some time for a cycle of the droplet production mechanism 120 from producing a droplet to relaxing in preparation for a next droplet production, if necessary in the next inkjet printer head cycle. Thus, there exists the need for the rise in voltage applied to the load from 0 to 40 V relatively rapidly.
The controller, under programmed control and with appropriate data and memory, and in response to signals received as to the ink production mechanisms that need to be actuated, cycle to cycle, the type of droplet production mechanism being used and the details of its actuation to produce a droplet, and the like, can determine what the ramp up is needed for the transient 0V-40V, and the voltage supply circuit is driven accordingly.
With particular details being addressed, such as the size (and perhaps even the shape) and precise timing of production of a droplet in the exemplary application, and thus the needed application wave form for the actuator actuation, such as by piezoelectric actuator, the controller may select such things as the voltage to which the low voltage floating linear amplifier will take its output, the ramp transient used (slope, shape, etc.). The controller may therefore be able to control the more finely linear amplifier 34 in this region (2 in FIG. 2) to achieve the desired results. The portion of the waveform where there is little or no change of the output voltage from the amplifier 34 (region 2′ in FIG. 2) may be used to give the controller some flexibility as to high voltage selected and ramp used in region 2. That is, as an example, some flexibility in timing of the turn off of switch 36 and turn on of switch 30, to begin the high current ramp down.
As illustrated in the simulation curves of FIG. 4, the low voltage floating linear amplifier input signal could drive the voltage on the output OUT1 back to 40 V and the amplifier 22 could take over at that point by closing switch 30 and opening switch 36.
Other various means of control are also possible. As an example, the timing of the opening and closing of the switches 30, 36 may be controlled by voltage comparators, such as the comparison of the voltage on OUT1 or OUT2 to some fixed or variable reference voltages, such as VS or VDD or other reference voltage(s) to control the switches 30, 36. The voltage controlled switches 30 and 36 could respond to fixed inputs of variable voltage selected and timed to a particular waveform and cycle period, and always open and close switches 30, 36 at a particular time relative to each other and the cycle time for the application, such as ink jet droplet generation.
Applicants have examined the energy drawn from voltage supply VS=ESUPPLY, with VS=50 in the sample solution of FIG. 3. The value for VS could be set to another value, such as 40V in the architecture shown in FIGS. 1 and 2. For the sample solution, energy stored in capacitor CL32=Ec, and energy dissipated=Ediss, which amounts to ESUPPLY-EC. The following can be derived.



  
    
      
        
          
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              ⁢
              
                d
                t
              
            
          
        
      
    
    
      
        
          =
          
            
              C
              L
            
            ·
            
              V
              DD
            
            ·
            
              
                ∫
                0
                ∞
              
              ⁢
              
                
                  
                    d
                    
                      V
                      OUT
                    
                  
                  ·
                  
                    d
                    t
                  
                
                
                  d
                  t
                
              
            
          
        
      
    
    
      
        
          =
          
            
              C
              L
            
            ·
            
              V
              DD
            
            ·
            
              
                ∫
                0
                40
              
              ⁢
              
                d
                
                  V
                  OUT
                
              
            
          
        
      
    
    
      
        
          =
          
            
              
                C
                L
              
              ×
              50
              ×
              40
            
            =
            
              2000
              ·
              
                C
                L
              
            
          
        
      
    
  




  
    
      
        
          
            E
            C
          
          =
          
            
              ∫
              0
              ∞
            
            ⁢
            
              
                
                  i
                  dd
                
                ⁡
                
                  (
                  t
                  )
                
              
              ·
              
                
                  v
                  OUT
                
                ⁡
                
                  (
                  t
                  )
                
              
              ·
              
                
              
              ⁢
              
                d
                t
              
            
          
        
      
    
    
      
        
          =
          
            
              C
              L
            
            ·
            
              
                ∫
                0
                ∞
              
              ⁢
              
                
                  
                    d
                    
                      
                        v
                        OUT
                      
                      ⁡
                      
                        (
                        t
                        )
                      
                    
                  
                  
                    d
                    t
                  
                
                ·
                
                  
                    v
                    OUT
                  
                  ⁡
                  
                    (
                    t
                    )
                  
                
                ·
                
                  
                
                ⁢
                
                  d
                  t
                
              
            
          
        
      
    
    
      
        
          =
          
            
              
                C
                L
              
              ·
              
                
                  [
                  
                    
                      v
                      
                        OUT
                        2
                      
                    
                    2
                  
                  ]
                
                0
                40
              
            
            =
            
              800
              ·
              
                C
                L
              
            
          
        
      
    
  




  
    
      E
      
        diss
        ⁢
        
          
        
        ⁢
        1
      
    
    =
    
      1200
      ·
      
        C
        L
      
    
  



Assuming a 40 V value for VS and 10V for VDD in the circuit of FIG. 1, the following applies:

Ediss1=800·CL since ESUPPLY=1600×CL and EC=800×CL.

In regions 2 and 3, Ediss2=Ediss3=48 CL, since ES=CL×50×8=400 CL and




  
    E
    C
  
  =
  
    
      
        C
        L
      
      ·
      
        
          [
          
            
              v
              
                OUT
                2
              
            
            2
          
          ]
        
        40
        48
      
    
    =
    
      352
      ·
      
        
          C
          L
        
        .
      
    
  




In region 4, Ediss4=1200×CL, as shown above for region 1. With VDD=40, Ediss4=800×CL, also as shown above.
Therefore, Ediss×(VDD=50V)=2496×·CL, for a single amplifier using a single VS equals 50 V voltage supply of FIG. 3, and Ediss×(VDD=40V)=1696×CL for the two amplifier arrangement of FIG. 1. According to aspects of an embodiment of the present invention, an improvement of 32% (reduction) in the amount of energy dissipated is achieved. The architecture for the capacitive load drive circuit of FIG. 1 was modeled against a circuit with the single class B gate driver as illustrated in FIG. 3, with high gain and low gain outputs connected to the gates of an external PFET and external NFET respectively and the load connected to the drains of the PFET and NFET in the conventional manner illustrated in FIG. 3. The simulation was for a 50 V linear amplifier driving a 0.527 μF load capacitor.
The amplifier used according to an aspect of an embodiment of the present invention has the following differences or advantages over traditional class G amplifiers. Class G amplifiers have global feedback to maintain linearity over the entire voltage range. In the intended application for the amplifier circuit 20 according to the present invention, linearity is not required over the entire voltage range. Hence, only amplifier 22 will require feedback while amplifier 34 can be a class D switching amplifier. Class G amplifiers also typically have a single output stage capable of driving the load current in, e.g., a piezoelectric application, where load current is high during fast switching and it is low during slow linear transitions. Only amplifier 22, therefore, needs to drive high currents.
The simulation was performed with respect to comparing the prior art single 50 V class B high voltage linear amplifier system driving to a peak 50 V and returning to 0 V per cycle, driving a 0.527 μF capacitive load, with a rise from 0 V to around 40 V over about a 5 μs period, a rise from around 40 V to about 50 V over an approximately 4 μs period, steady state for about a 5.5 μs period followed by a reduction in output voltage from 50 V to 0 V over about a 5.5 μs period. The average current drawn was found to be 3.56 A and power dissipation 178 W.
Using a circuit according to an embodiment of the present invention, with the same load tied to the outputs of two amplifiers 22, 34, as described above, the transients shown in FIG. 4 were modeled and simulated, and the average current drawn from the floating 10 V supply was found to be 0.437 A and power dissipation of 4.37 W. At the same time, the average current for a 40 V high voltage linear amplifier was shown to be 2.5 A, resulting in a 100 W power dissipation.
Therefore, the difference in power dissipation is between 178 W in the prior art circuit and 104.37 W, i.e., a 41% difference. This matches closely with the theoretical 32% energy dissipation reduction noted above.
It will be understood by those skilled in the art that “high” capacitive loads vary with a given application and that the difference between the voltage and current that can be handled by the “high voltage, high current operational amplifier” 22 vis-à-vis the floating low voltage linear amplifier 34 also varies with application. As used herein, those skilled in the art will understand high and low to be distinctive of the operation of the high voltage/high current amplifier 22 in those applications requiring relatively high current to the load over a relatively short period of time during a ramp up of, as an example, the charging of a relatively large capacitive load, and the similar relatively large and rapid current flow from the load, such as to discharge the capacitive load during a steep ramp down period. This is as opposed to a relatively slower transient at the top of the drive circuit waveform from a starting voltage (generally at the voltage at which the high voltage/high current amplifier left off), to a maximum voltage relatively closed to the starting voltage for the low voltage/low current amplifier 34. Examples here have been given circuits where “high” voltage is 40-50 V and high current is in the range of tens of amps. The voltage and current ranges in which the exemplary low current/low voltage portions of the circuits described herein operate are on the order of 8-10 V and 3-5 amps. The high voltage/high current amplifiers currently on the market can handle much higher voltage, on the order of hundreds of volts and tens of amps. For purposes of this application, however, the difference between “high” and “low” means that the “low” value of voltage or current is in a range of about 0.1-20% of the high value, and most often 0.1-10%.
It will be understood that a high capacitive load drive circuit for driving external capacitive loads is disclosed which may comprise a high current drive amplifier, such as amplifier 22 of FIG. 1 configured to be coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage, such as the period/portion 1 of time in FIG. 2 and the ramp up transient labeled as 92 in FIG. 4. A low current drive amplifier, such as amplifier 34 in FIG. 1, may be configured to be connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load, such as the ramp up illustrated during the period 2 in FIG. 2 and the ramp up time period of curve 94 in FIG. 4. The high current drive amplifier may be configured to be connected to the capacitive load during a high current ramp down of the voltage across the capacitive load, such as the time periods 3 and 4 in FIG. 2 and the ramp down curve 92′ in FIG. 4. The low current drive amplifier may be connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down, such as the period labeled 2′ in FIG. 2. During this period, the output signal connected to the capacitive load may require high gain accuracy and hence linearity. The low current drive amplifier may comprise an amplifier having a linear response in the range of the low current ramp up, such as between a cut off voltage for the high current ramp up, for example, 40 V and 48V. The capacitive load may comprise a piezoelectric element, which may comprise an element of an ink jet printer head ink droplet producing mechanism such as is shown schematically in FIG. 5.
FIG. 7 shows a schematic circuit diagram of a capacitive load drive circuit 310′ having a multi-supply arrangement, in the specific example, a two stage stepped voltage supply. The circuit 310′ contains the elements of the circuit 310 of FIG. 6 for charging CLOAD 320 to VDD during the ramp up and discharged during ramp down. In a stepped voltage drive with n steps, such as n=2 as illustrated in FIG. 2, there can be a number (n) of intermediate rails with specific voltage levels between the rails, which may be, but need not necessarily be equal, as in the example where the incremental values are equal to VDD/n. In addition there can be a number (n) of switches controlling current flow, as an example for either the charging or discharging of the load, as the case may be, during such charging and discharging of the capacitor 320 by (VDD·CLOAD) amounts.
In addition to the elements of FIG. 7, the circuit 310′ of FIG. 7 contains, by way of example, a current supply, which may comprise a charge storage device, such as capacitor CBIG 354. The capacitor 354 may be connected to the load capacitor 320 through a resistor 352 which models the ON resistance of the switch when switch 350 is closed. The timing of the closing of switch 350 may be done by a voltage supply 356, which may provide a time varying closure signal, such as a saw tooth time varying signal to the V+ and V− terminals of the voltage controlled switch 350.
FIG. 8 illustrates an output voltage waveform 360 for the circuit 310′ of FIG. 3 illustrating a timing of operation of the circuit. The control of the timing of the closing of the switches 322, 324 and 350 by the respective switch control signals 342, 340 and 356 can be set up so that during a first charging time period switch 350 is closed and a portion 362 of the output waveform 360 of the voltage supply circuit 310′ is generated during a first charging time period as illustrated in FIG. 8. In an exemplary embodiment, where the output waveform serves to charge a capacitive load, such as actuation of a piezoelectric element, the portion 362 of the output waveform 360 initiates the actuation of the piezoelectric element 130 shown in FIG. 5. Also in an exemplary embodiment, this can begin to squeeze a channel 124 (or the liquid in a channel 124) in an inkjet printer inkjet droplet producing mechanism 120, or a nozzle 122 in such a channel 124, to begin to force out ink from the individual inkjet nozzle 122 in an inkjet printer print head (not shown). During the first charging time period 362, the output waveform can provide an output voltage varying from 0 to VDD/2, which in the exemplary embodiment is the value of the voltage on CBIG 354.
Thereafter, with switch 324 closed, and switch 322 having been reopened (it being understood that throughout this application, unless expressly noted otherwise, all other switches, including ones previously noted as being closed, remain open while the switches under discussion are closed) the voltage supply VDD is connected to the load, and in the exemplary embodiment a capacitive load such as a piezoelectric element in an inkjet printer print head, increases the output voltage applied to the load CLOAD from VDD/2 to VDD during a second charging time period 364. During a subsequent time period 366 the output voltage may be maintained at VDD. Thereafter, with switch 350 closed, the charge storage element, such as capacitor CBIG 354 may be charged to VDD/2 from the charge storage device CLOAD 320 during a first discharging time period 368, wherein the load goes from VDD to VDD/2. In other words, the charge that was initially provided by the VDD/2 supply during ramp up is dumped back into CBIG 354.
In the exemplary embodiment, this reduction in voltage applied to the load can begin to relax the piezoelectric element 130 squeeze on the channel 124 (or the liquid in the channel 124) in an inkjet printer ink droplet producing mechanism 120, by relaxing the deformation the piezoelectric element or transducer 130 under the influence of the electric field created by the voltage across the electrodes of the piezoelectric element 130, to begin to draw ink into the individual inkjet nozzle channel 124 from a reservoir (not shown) in an inkjet printer print head (not shown), through an ink supply line 126. It will be understood that other means may be used, alone or in combination with such relaxation of the piezoelectric element to resupply the channel 124 of the given nozzle 122, such as a pressure applied to the reservoir (not shown).
Finally, switch 322 may be closed to connect the load 320 to ground thereby discharging the load capacitor CLOAD 320 through switch 322 and resistor 328 during a second discharging time period 370 and the output waveform thus provides an output voltage varying from VDD/2 to 0. In the exemplary embodiment, the reduction in voltage to the load can completely relax the piezoelectric element 130 pressure exerted on ink in the inkjet channel in preparation for a subsequent actuation of the piezoelectric element 130 at a later time by the application of another output voltage waveform 360 to the load. The following analysis of energy dissipation Ediss during such charging of the load 320 applies with the switch 350 closed.



  
    
      
        
          
            E
            CBIG
          
          -
          
          ⁢
          
            
              ∫
              0
              ∞
            
            ⁢
            
              
                
                  
                    i
                    CBIG
                  
                  ⁡
                  
                    (
                    t
                    )
                  
                
                ·
                
                  
                    v
                    CBIG
                  
                  ⁡
                  
                    (
                    t
                    )
                  
                
              
              ⁢
              
                d
                t
              
            
          
        
      
    
    
      
        
          =
          
          ⁢
          
            
              C
              L
            
            ·
            
              
                V
                DD
              
              2
            
            ·
            
              
                ∫
                0
                ∞
              
              ⁢
              
                
                  
                    d
                    
                      V
                      OUT
                    
                  
                  ·
                  
                    d
                    t
                  
                
                
                  d
                  t
                
              
            
          
        
      
    
    
      
        
          =
          
          ⁢
          
            
              C
              L
            
            ·
            
              
                V
                DD
              
              2
            
            ·
            
              
                ∫
                0
                
                  
                    V
                    DD
                  
                  2
                
              
              ⁢
              
                d
                
                  V
                  OUT
                
              
            
          
        
      
    
    
      
        
          =
          
          ⁢
          
            
              
                C
                L
              
              ×
              
                
                  V
                  DD
                
                2
              
              ×
              
                
                  V
                  DD
                
                2
              
            
            =
            
              
                25
                2
              
              ·
              
                C
                L
              
            
          
        
      
    
  




  
    
      
        
          
            E
            CLoad
          
          =
          
            
              ∫
              0
              ∞
            
            ⁢
            
              
                
                  i
                  CLoad
                
                ⁡
                
                  (
                  t
                  )
                
              
              ·
              
                
                  v
                  OUT
                
                ⁡
                
                  (
                  t
                  )
                
              
              ·
              
                
              
              ⁢
              
                d
                t
              
            
          
        
      
    
    
      
        
          =
          
            
              C
              L
            
            ·
            
              
                ∫
                0
                ∞
              
              ⁢
              
                
                  
                    d
                    
                      
                        v
                        OUT
                      
                      ⁡
                      
                        (
                        t
                        )
                      
                    
                  
                  
                    d
                    t
                  
                
                ·
                
                  
                    v
                    OUT
                  
                  ⁡
                  
                    (
                    t
                    )
                  
                
                ·
                
                  
                
                ⁢
                
                  d
                  t
                
              
            
          
        
      
    
    
      
        
          =
          
            
              
                C
                L
              
              ·
              
                
                  [
                  
                    
                      V
                      
                        OUT
                        2
                      
                    
                    2
                  
                  ]
                
                0
                
                  
                    V
                    DD
                  
                  2
                
              
            
            =
            
              
                
                  25
                  2
                
                2
              
              ·
              
                C
                L
              
            
          
        
      
    
  




  
    
      E
      
        diss
        ⁢
        
          
        
        ⁢
        1
      
    
    =
    
      
        
          E
          CBIG
        
        -
        
          E
          CLoad
        
      
      =
      
        
          
            25
            2
          
          2
        
        ·
        
          C
          L
        
      
    
  



It will be understood that, with the intermediate voltage set to an arbitrary voltage V1 between V and VDD, Ediss1 will equal (CL×V12)/2.
Later, with switch 324 closed, during the charging from V1 to VDD, i.e., from VDD/2 to VDD, where V1=VDD/2, the following applies:



  
    
      
        
          
            E
            SUPPLY
          
          =
          
            
              ∫
              0
              ∞
            
            ⁢
            
              
                
                  
                    i
                    VDD
                  
                  ⁡
                  
                    (
                    t
                    )
                  
                
                ·
                
                  
                    V
                    DD
                  
                  ⁡
                  
                    (
                    t
                    )
                  
                
              
              ⁢
              
                d
                t
              
            
          
        
      
    
    
      
        
          =
          
            
              C
              L
            
            ·
            
              V
              DD
            
            ·
            
              
                ∫
                0
                ∞
              
              ⁢
              
                
                  
                    d
                    
                      V
                      OUT
                    
                  
                  ·
                  
                    d
                    t
                  
                
                
                  d
                  t
                
              
            
          
        
      
    
    
      
        
          =
          
            
              C
              L
            
            ·
            
              V
              DD
            
            ·
            
              
                ∫
                25
                50
              
              ⁢
              
                d
                
                  V
                  OUT
                
              
            
          
        
      
    
    
      
        
          =
          
            
              C
              L
            
            ×
            50
            ×
            25
          
        
      
    
  




  
    
      
        
          
            E
            C
          
          =
          
            
              ∫
              0
              ∞
            
            ⁢
            
              
                
                  i
                  dd
                
                ⁡
                
                  (
                  t
                  )
                
              
              ·
              
                
                  v
                  OUT
                
                ⁡
                
                  (
                  t
                  )
                
              
              ·
              
                
              
              ⁢
              
                d
                t
              
            
          
        
      
    
    
      
        
          =
          
            
              C
              L
            
            ·
            
              
                ∫
                0
                ∞
              
              ⁢
              
                
                  
                    d
                    
                      
                        v
                        out
                      
                      ⁡
                      
                        (
                        t
                        )
                      
                    
                  
                  
                    d
                    t
                  
                
                ·
                
                  
                    v
                    OUT
                  
                  ⁡
                  
                    (
                    t
                    )
                  
                
                ·
                
                  
                
                ⁢
                
                  d
                  t
                
              
            
          
        
      
    
    
      
        
          =
          
            
              
                C
                L
              
              ·
              
                
                  [
                  
                    
                      v
                      
                        OUT
                        2
                      
                    
                    2
                  
                  ]
                
                25
                50
              
            
            =
            
              
                C
                L
              
              ·
              
                [
                
                  
                    
                      50
                      2
                    
                    2
                  
                  -
                  
                    
                      25
                      2
                    
                    2
                  
                
                ]
              
            
          
        
      
    
  







  
    E
    
      diss
      ⁢
      
        
      
      ⁢
      2
    
  
  =
  
    
      
        E
        SUPPLY
      
      -
      
        E
        C
      
    
    =
    
      
        
          25
          2
        
        2
      
      ·
      
        C
        L
      
    
  




The total energy dissipated for the 0-VDD transition is:

Ediss—RampUP=Ediss1+Ediss2=252×CLOAD  Equ (2)

It will be seen that the energy dissipated in a discharging transition of the load from VDD−0 Ediss—RampDwn will also equal 252×CLOAD.
The total energy dissipated during one switching cycle therefore is:

Ediss2—=2×252×CLOAD  Equ (3)

Comparing equations 1 and 3 one can conclude that the energy savings factor with a two stage voltage drive as opposed to a one stage voltage drive is equal to 2. In a similar fashion it can be shown that in theory energy dissipated for an n-step voltage drive during one switching cycle is:

Ediss—n=n×(VDD/n)2×CLOAD  Equ (4)

The energy savings factor for an n-step drive is given by:




  
    
      
        
          S
          n
        
        =
        
          
            
              
                V
                
                  DD
                  2
                
              
              ·
              
                C
                LOAD
              
            
            
              [
              
                
                  C
                  LOAD
                
                ·
                
                  
                    V
                    
                      DD
                      2
                    
                  
                  
                    n
                    2
                  
                
                ·
                n
              
              ]
            
          
          =
          n
        
      
    
    
      
        Equ
        ⁢
        
          
        
        ⁢
        
          (
          5
          )
        
      
    
  




With the intermediate voltage set to the arbitrary V1, Ediss2 will equal CLOAD·[V12+(VDD−V1)2] and the total energy dissipated will equal Ediss1+Ediss2 and the normalized total dissipation Ediss<n> will be [V12+(VDD−V1)2]/VDD2 which forms the parabola shown in FIG. 11, which can be utilized to select optimal values for the voltage steps, in an adiabatically driven output voltage, such as, for driving high capacitive loads in piezoelectric drive actuators in ink jet printer head droplet production mechanisms. For example on the left side of the curve the normalized energy dissipation drops significantly down to about 10 or so steps and then more or less levels off so that the problems (such as greater complexity of circuitry), overtake any advantage in continued reductions in energy dissipation at smaller incremental changes.
In FIG. 9 there is shown a multi-supply capacitive load drive circuit 380, which may include an output connected to a load, such as a capacitive load CLOAD 320 such as a 0.8 μF capacitance. The circuit 380 may include a multi-supply stacked (stepped) voltage supply to the load 320, which may comprise a switch 382, which when closed connects a capacitor 382C to the load 320 through a resistor 382R. The stacked supply 380 may further include a switch 384, through which a capacitor 384C is connected to the load 320 through a resistor 384R. In similar fashion the remaining stages including switch 386, capacitor 386C and resistor 386R, switch 388, capacitor 388C and resistor 388R, switch 390, capacitor 390C, resistor 390R, switch 392, capacitor 392C and resistor 392R, switch 394, capacitor 394C and resistor 394R, switch 396, capacitor 396C and resistor 396R, switch 398, capacitor 398C and resistor 398R, may serve to connect the respective capacitors to the output and thus to the load 320.
A switch 400, when closed, may serve to connect a high voltage, such as VDD 326, to the load 320 through a resistor 400R. A further switch 402 may serve to connect the load to ground through a resistor 402R.
In operation, as simulated in FIG. 10 the switches 382, 384, 386, 388, 390, 392, 394, 396, 398 and 400 may be sequentially closed to step the voltage at the output (“OUT”) by selected sequential amounts, such as regular intervals of, by way of example, 5 V intervals, for an exemplary ten stage/step circuit with VDD equal to 50 V. It will be understood that the steps need not be identical rail to rail, such as, each being a specific fraction of VDD, such as VDD/n, as in the Example of FIG. 9.
As shown in FIG. 10 this sequentially switching in of different capacitive elements, applies at the output, and thus to the load 320, increasing voltage steps from 0-VDD, in the exemplary embodiment, 10 steps of voltage output varying in 5 V intervals from 0-VDD. As with the exemplary two stage circuit of FIG. 2, the source of the current to the load, applied in an exemplary embodiment in charging a capacitive load, is the high voltage source VDD. The remaining voltage sources are formed in the exemplary embodiment by the respective capacitors 382C, 384C, 386C, 388C, 390C, 392C, 394C, 396C and 398C. This increase in voltage to the load during each of a respective ten successive charging time periods with all but the tenth charging time period causing the output to provide current flow to the load 320 from a respective charge storage device 382C, 384C, 386C, 388C, 390C, 392C, 394C, 396C and 398C. The tenth charging time period results in current flow generated by applying the voltage source VDD to the load 320.
Also as illustrated in the simulated waveform of FIG. 10, in a discharging sequence, each of the switches 398, 396, 394, 392, 390, 388, 386, 384 and 382 are sequentially closed, in that order, in the exemplary embodiment, charging the respective capacitors 398C, 396C, 394C, 392C, 390C, 388C, 386C, 384C and 382C in decreasing amounts, as an example, in 5 V intervals, from VDD−5 to VDD−45, with the exemplary ten stage circuit and VDD=50, and equally sized decrements. Finally switch 402 is closed taking the output and the voltage across the load 320 from VDD−45 to 0 in the exemplary embodiment. It will be understood that as used herein, ground is simply a common voltage below VDD and need not be zero volts and could even be a negative voltage.
The simulation of FIG. 10 compares a waveform 310 for a single stage 50 V VDD supply as exemplified by the circuit of FIG. 6 to the simulated waveform 312 created during the simulation of the operation of the circuit of FIG. 9.
In generating FIG. 10, a simulation of the circuit of FIG. 9 was modeled to simulate a 10 step voltage drive for a 50 V switched driving a load equal to a 0.8 μF capacitive load. The large capacitors for the 5 V steps C5V-C45V, are the capacitors 382C, 384C, 386C, 388C, 390C, 392C, 394C, 396C and 398C and were assumed to be 1 F for simulation purposes only. The nodes 5V-45V, corresponding to capacitors 382C, 384C, 386C, 388C, 390C, 392C, 394C, 396C and 398C, in that order, were initialized to the corresponding voltage using an .ic statement in a Spice simulator. The switches 382, 384, 386, 388, 390, 392, 394, 396, 398, 400 and 402 were assumed to be ideal switches.
The results of this simulation were compared with a single 50 V step linear drive to determine energy savings. Current through the load 320 was simulated for the sequential closure of each of the switches 382, 384, 386, 388, 390, 392, 394, 396, 398, 400 and 402 during the respective charging time periods shown in FIG. 10, and charge recovery for each of the capacitors 398C, 396C, 394C, 392C, 390C, 388C, 386C, 384C and 382C was also simulated for each of the respective discharging time periods associated with the closure sequentially of the switches 398, 396, 394, 392, 390, 388, 386, 384, 382 and 402 in that order. The average power dissipation can be approximated by looking at the energy lost by the 50 V supply with ground return since there is no charge recovery for the 50 V supply.
For a single stage voltage supply also simulated, the average current drawn was 2.667 amps. The average power dissipation was 133.35 W. The simulation also showed that the current drawn from the 50 V VDD supply was 0.628 amps and power dissipation was 13.4 W, which matches very closely with the theoretical power dissipation savings for an n stage supply circuit with n=10 as equaling 133.35/13.4=9.95, which is very nearly equal to n=10.
Those skilled in the art will understand that voltage drive circuit, such as a capacitive load drive circuit and method of operation of the same is disclosed and may include a multi-stage stacked charging circuit such as the circuit of FIG. 7, electrically connected to the capacitive load 20, which may include a first capacitor, such as the capacitor CBIG 354, electrically connected to the capacitive load 320 through a first switch 350 during a first charging time period, i.e., charging time period 362 of waveform 360 as shown in FIG. 8. The circuit may also include a voltage supply, such as VDD 326 electrically connected to the capacitive load 320 through a second switch 324 during a second charging time period 364 as shown in FIG. 8. The first capacitor 354 may be electrically connected to the capacitive load 320 through the first switch 350 during a first discharging time period 368 as illustrated in FIG. 8.
The system and method in an exemplary embodiment may comprise a third switch 322 electrically connecting the capacitive load 320 to ground during a second discharging time period 370 as illustrated in FIG. 8. The capacitive load 320 may comprise a piezoelectric element 130, such as illustrated in FIG. 5 which may comprise an inkjet printer head ink droplet production mechanism 120 inkjet actuator 130.
The system and method by way of an exemplary embodiment may comprise an n-stage stacked charging circuit such as the ten stage circuit of FIG. 9, which may comprise n−1 capacitors, and a voltage supply, by way of example the nine capacitors 382C, 384C, 386C, 388C, 390C, 392C, 394C, 396C and 398C and a voltage supply VDD, each electrically connected in sequence to the capacitive load 320 through a respective first through nth switch, such as switches 382, 384, 386, 388, 390, 392, 394, 396, 398 and 400 during a respective first through nth charging time period, such as is illustrated by way of example in FIG. 10 for the respective closure of the switches 382, 384, 386, 388, 390, 392, 394, 396, 398 and 400; the n−1th capacitors 398C, 396C, 394C, 392C, 390C, 388C, 386C, 384C and 382C may each be sequentially electrically connected to the capacitive load 320 in reverse order during a first through n−1th discharging time periods through the respective n−1th through first switches, as illustrated in FIG. 9 for the discharge time periods associated with the closure of each switch 398, 396, 394, 392, 390, 388, 386, 384 and 382 sequentially.
The system and method may comprise an n+1th switch, such as, switch 402, electrically connecting the capacitive load to ground during an nth discharging period as is also illustrated in FIG. 10. The capacitive load 320 may comprise a piezoelectric element, such as piezoelectric transducer 130 illustrated by way of example in FIG. 5, which may comprise an inkjet printer head 120 inkjet droplet production mechanism actuator.
FIG. 5 illustrates schematically the principal elements of a printer head ink droplet production mechanism 120, such as in an inkjet printer head (not shown), with which the present invention may be used. The inkjet printer head ink droplet production mechanism 120 typically includes a nozzle 122 fed by a feed channel 124, which may receive ink from a supply reservoir (not shown) through an ink supply passage 126. A piezoelectric transducer 130, which may be the capacitive load 320 illustrated in FIGS. 6, 7 and 9, or a part of that load, may be connected to the output of a drive circuit, such as those illustrated in FIG. 6, 7 or 9 by a voltage supply connector 132 and to ground by a connector 134, appearing, as noted above, as a high capacitance load to the drive circuits as shown in FIG. 6, 7 or 9.
It will also be understood that the drive circuit 310 or 380 or the like can be employed with the low current linear amplifier 34 such as illustrated in FIG. 1, to generate the high current ramp up and high current ramp down portions of the cyclical wave form of the drive circuit output, to provide a relatively linear ramp up and a relatively linear ramp down. Such a circuit is illustrated by way of example in FIG. 12. In FIG. 12, there is shown a multi-supply capacitive load drive circuit 420, with the circuit 380 of FIG. 9 in place of the amplifier 22 in FIG. 1, connected to the capacitive load 32 through a switch 30 during ramp up and ramp down. The circuit as explained in regard to FIG. 9 selectively sequentially connects ground and then the capacitors 382C, 384C, 386C, 388C, 390C 392C, 394C, 396C and 398C, and then voltage supply VS to the capacitive load 32 increasing the voltage on the load in 5V increments from 0 volts to 50 volts. Subsequently, after amplifier 34 has been connected to the capacitive load 32 through switch 36, switch 36 is opened and switch 30 is again closed and the voltage on the capacitive load 32 sequentially charges the capacitors 382C, 384C, 386C, 388C, 390C 392C, 394C, 396C and 398C in reverse order during a ramp down, with the ramp down being completed by switch 402 being closed to connect the load 32 to ground.
It will be understood that in a portion of the drive circuit output to the capacitive load, such as an ink droplet production mechanism actuator, linearity is not at a premium, and the savings in power dissipation may overcome any lack of linearity. Using the same quantitative techniques shown above, the energy dissipated using drive circuit 380 in FIG. 9 in place of amplifier 20 in FIG. 1 can be derived as 256×CL. The energy savings in comparison to exemplary existing solution of FIG. 3. is 89.75%.
In operation, the transducer 130 deforms as voltage is applied across the connectors 132 and 134 and either bends or bulges in the direction of the channel 124 or bulges out on both sides, including in the direction of the channel 124, serving to squeeze a droplet of ink out of the nozzle each time the transducer is so actuated. In some printer heads, the relaxation of the transducer, as voltage is removed, may also serve to suck ink into the channel 124 through the supply line 126. It will be understood also that the piezoelectric transducer 130 may force ink out of the ink jet droplet producing mechanism 120 by other means, such as squeezing the channel 124 or the nozzle 122 or both, and more than one piezoelectric element 130 may be used per droplet production mechanism 120.
Distinct from the adiabatic computing circuits, embodiments of the present invention including adiabatic stepping and voltage control circuits are used to control the output of a high capacitive load driver circuit such as a step voltage amplifier by defining the output range for each step. Also distinct from adiabatic computing circuits, embodiments of the present invention are for an analog application with a portion or all of the output waveform requiring gain and linearity. Creating a floating rail according to aspects of embodiments of the present invention provides several advantages. In certain embodiments, there can be created an inductor based floating rail. Circuits according to aspects of embodiments of the present invention can generate a ramp that drives a drive circuit amplifier based upon the signal level, i.e., output signal range of the amplifier.
It should be apparent that the scope and content of the present disclosure are not limited to the above embodiments but should be considered in scope and content taking into account the manner in which the disclosed embodiments may be changed and modified without departing from the scope and spirit of the disclosed subject matter and claims, some of which changes and modifications have been noted above.

## Claims

1. A capacitive load drive circuit comprising:
a high current drive amplifier configured to be selectively coupled to a capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage;
a low current drive amplifier configured to be selectively connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and
the high current drive amplifier configured to be selectively connected to the capacitive load during a high current ramp down of the voltage across the capacitive load.

2. The drive circuit of claim 1 further comprising:
the low current drive amplifier selectively connected to the capacitive load during a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

3. The drive circuit of claim 1 wherein the low current drive amplifier comprises an amplifier having a linear response in the range of the low current ramp up.

4. The drive circuit of claim 1 wherein the capacitive load comprises a piezoelectric element.

5. The drive circuit of claim 2 wherein the capacitive load comprises a piezoelectric element.

6. The drive circuit of claim 3 wherein the capacitive load comprises a piezoelectric element.

7. The drive circuit of claim 4 wherein the piezoelectric element comprises an element of an ink jet print head ink droplet producing mechanism.

8. The drive circuit of claim 5 wherein the piezoelectric element comprises an element of an ink jet print head ink droplet producing mechanism.

9. The drive circuit of claim 6 wherein the piezoelectric element comprises an element of an ink jet print head ink droplet producing mechanism.

10. The drive circuit of claim 1 wherein the low current drive amplifier comprises a floating low voltage amplifier.

11. The drive circuit of claim 2 wherein the low current drive amplifier comprises a floating low voltage amplifier.

12. The drive circuit of claim 1 wherein the high current and low current drive amplifiers are contained in one or more integrated circuits.

13. A method of driving high capacitive loads comprising:
utilizing a high current drive amplifier configured to be selectively coupled to the capacitive load during a high current ramp up of the voltage across the capacitive load to a cut off voltage;
utilizing a low current drive amplifier configured to be selectively connected to the capacitive load during a low current ramp up of the voltage across the capacitive load, from the cut off voltage to a maximum voltage across the capacitive load; and
utilizing the high current drive amplifier configured to be selectively connected to the capacitive load during a high current ramp down of the voltage across the capacitive load.

14. The method of claim 13 further comprising:
allowing for a period of steady state of the voltage across the capacitive load, intermediate the low current ramp up and the high current ramp down.

15. The method of claim 13 wherein the low current drive amplifier comprises an amplifier having a linear response in the range of the low current ramp up.

16. The method of claim 13 wherein the capacitive load comprises a piezoelectric element.

17. The method of claim 14 wherein the capacitive load comprises a piezoelectric element.

18. The method of claim 15 wherein the capacitive load comprises a piezoelectric element.

19. The method of claim 16 wherein the piezoelectric element comprises an element of an ink jet print head ink droplet producing mechanism.

20. The method of claim 17 wherein the piezoelectric element comprises an element of an ink jet print head ink droplet producing mechanism.

21. The drive circuit of claim 18 wherein the piezoelectric element comprises an element of an ink jet print head ink droplet producing mechanism.

22. The method of claim 13 wherein the low current drive amplifier comprises a floating low voltage amplifier.

23. The method of claim 14 wherein the low current drive amplifier comprises a floating low voltage amplifier.

24. The method of claim 13 wherein the high current and low current drive amplifiers are contained in one or more integrated circuits.

25. The method of claim 14 wherein the high current and low current drive amplifiers are contained in one or more integrated circuits.