# Patent

## Title
Driving method for organic electroluminescence light emitting section

## Abstract

A driving method for an organic EL light emitting section achieves optimization of mobility correction for a transistor of a driving circuit in response to luminance. In a driving circuit formed from a driving transistor, an image signal writing transistor and a capacitor section having a pair of electrodes, a driving method carries out a pre-process, a threshold voltage cancellation process and a writing process. A variable correction voltage which relies upon the image signal voltage is applied to a first node of the capacitor and a voltage which is higher than a potential of the second node of the capacitor in the threshold voltage cancellation process is applied to the drain electrode of the driving transistor, between the threshold voltage cancellation process and the writing process, to raise the potential of the second node in response to a characteristic of the driving transistor.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This is a Continuation Application of U.S. patent application Ser. No. 12/450,266, filed Sep. 18, 2009, which is based on a National Stage Application of PCT/JP08/055,045, filed Mar. 19, 2008, which in turn claims priority from Japanese Application No. 2007-098465, filed on Apr. 4, 2007, the entire contents of which are incorporated herein by reference.


TECHNICAL FIELD
This invention relates to a driving method for an organic electroluminescence light emitting section.
BACKGROUND ART
In an organic electroluminescence display apparatus (hereinafter referred to simply as organic EL display apparatus) which uses an organic electroluminescence element (hereinafter referred to simply as organic EL element) as a light emitting element, the luminance of the organic EL element is controlled with the value of current flowing through the organic EL element. And similarly as in a liquid crystal display apparatus, also in the organic EL display apparatus, a simple matrix type and an active matrix type are known as driving methods. Although the active matrix type has such a drawback that it is complicated in structure in comparison with the simple matrix type, it has such various advantages as an advantage that an image can be displayed with high luminance.
As a circuit for driving an organic electroluminescence light emitting section (hereinafter referred to simply as light emitting section) which forms an organic EL element, a driving circuit (called 5Tr/1C driving circuit) composed of five transistors and one capacitor is commonly known, for example, from Japanese Patent Laid-Open No. 2006-215213. This conventional 5Tr/1C driving circuit includes, as shown in FIG. 1, five transistors of, as shown in FIG. 1, an image signal writing transistor TSig, a driving transistor TDrv, a light emission controlling transistor TEL—C, a first node initializing transistor TND1 and a second node initializing transistor TND2 and further includes one capacitor section C1. Here, the other one of the source/drain regions of the driving transistor TDrv forms a second node ND2 and the gate electrode of the driving transistor TDrv forms a first node ND1.
It is to be noted that the transistors and the capacitor are hereinafter described in detail.
Further, as shown in a timing chart of FIG. 24, within a [period TP (5)1], a pre-process for carrying out a threshold voltage cancellation process is executed. In particular, when the first node initializing transistor TND1 and the second node initializing transistor TND2 are placed into an on state, the potential of the first node ND1 becomes VOfs (for example, 0 volts). Meanwhile, the potential of the second node ND2 becomes VSS (for example, −10 volts). As a result, the potential difference between the gate electrode and the other one (for the convenience of description, hereinafter referred to as source region) of the source/drain electrodes of the driving transistor TDrv becomes higher than Vth and the driving transistor TDrv is placed into an on state.
Then, within a [period TP (5)2], a threshold voltage cancellation process is carried out. In particular, while the on state of the first node initializing transistor TND1 is maintained, the light emission controlling transistor TEL—C is placed into an on state. As a result, the potential of the second node ND2 changes toward a potential difference of the threshold voltage Vth of the driving transistor TDrv from the potential of the first node ND1. In other words, the potential of the second node ND2 which is in a floating state rises. Then, when the potential difference between the gate electrode and the source electrode of the driving transistor TDrv reaches Vth, the driving transistor TDrv is placed into an off state. In this state, the potential of the second node is substantially (VOfs−Vth). Thereafter, within a [period TP (5)3], while the on state of the first node initializing transistor TND1 is maintained, the light emission controlling transistor TEL—C is placed into an off state. Then, within a [period TP (5)4], the first node initializing transistor TND1 is placed into an off state.
Then, within a [period TP (5)5′], a kind of writing process into the driving transistor TDrv is executed. In particular, while the off state of the first node initializing transistor TND1, second node initializing transistor TND2 and light emission controlling transistor TEL—C is maintained, the potential of a data line DTL is set to a voltage corresponding to an image signal [image signal (driving signal, luminance signal) VSig for controlling the luminance of the light emitting section ELP] and then a scanning line SCL is set to the high level to place the image signal writing transistor TSig into an on state. As a result, the potential of the first node ND1 rides to VSig. Charge based on the variation of the potential of the first node ND1 is distributed to the capacitor section C1, the parasitic capacitance CEL of the light emitting section ELP and the parasitic capacitance between the gate electrode and the source electrode of the driving transistor TDrv. Accordingly, if the potential of the first node ND1 varies, then also the potential of the second node ND2 varies. However, as the capacitance value of the parasitic capacitance CEL of the light emitting section ELP has an increasing value, the variation of the potential of the second node ND2 decreases. Generally, the capacitance of the parasitic capacitance CEL of the light emitting section ELP is higher than the capacitance value of the capacitor section C1 and the value of the parasitic capacitance of the driving transistor TDrv. Therefore, if it is assumed that the potential of the second node ND2 little varies, then the potential difference Vgs between the gate electrode and the other one of the source/drain regions of the driving transistor TDrv is given by the expression (A) given below. It is to be noted that an enlarged timing chart within a [period TP (5)5′] and a [period TP (5)6′] is shown in (A) of FIG. 25.

Vgs≈VSig−(VOfs−Vth)  (A)

Thereafter, within the [period TP (5)6′], correction (mobility correction process) of the potential of the source region (second node ND2) of the driving transistor TDrv based on the magnitude of the mobility μ of the driving transistor TDrv is carried out. In particular, while the on state of the driving transistor TDrv is maintained, the light emission controlling transistor TEL—C is placed into an on state, and then when predetermined time (tCor) elapses, the image signal writing transistor TSig is placed into an off state to place the first node ND1 (gate electrode of the driving transistor TDrv) into a floating state. As a result, where the value of the mobility μ of the driving transistor TDrv is high, the rise amount ΔV of the potential (potential correction value) in the source region of the driving transistor TDrv is great, but where the value of the mobility μ of the driving transistor TDrv is low, the rise amount ΔV of the potential (potential correction value) in the source region of the driving transistor TDrv is small. Here, the potential difference Vgs between the gate electrode and the source electrode of the driving transistor TDrv is transformed from the expression (A) into the expression (B) given below. It is to be noted that the predetermined time for executing the mobility correction process (total time (tCor) of the [period TP (5)6′]) may be determined in advance as a design value upon designing of the organic EL display apparatus.

Vgs≈VSig−(VOfs−Vth)−ΔV  (B)

By the foregoing operation, the threshold voltage cancellation process, writing process and mobility correction process are completed. Within a later [period TP (5)7], the image signal writing transistor TSig is placed into an off state and the first node ND1, that is, the gate electrode of the driving transistor TDrv, is placed into a floating state while the light emission controlling transistor TEL—C maintains the on state and one (for the convenience of description, hereinafter referred to as drain region) of the source/drain regions of the light emission controlling transistor TEL—C is in a state wherein it is connected to a current supplying section (voltage VCC, for example, 20 volts) for controlling the light emission of the light emitting section ELP. Accordingly, as a result of the foregoing, the potential of the second node ND2 rises, and a phenomenon similar to that which occurs with a so-called bootstrap circuit occurs with the gate electrode of the driving transistor TDrv and also the potential of the first node ND1 rises. As a result, the potential difference Vgs between the gate electrode and the source electrode of the driving transistor TDrv maintains the value of the expression (B). Meanwhile, since the current flowing through the light emitting section ELP is drain current Ids which flows from one (for the convenience of description, hereinafter referred to as drain region) of the source/drain regions to the source region of the driving transistor TDrv, it can be represented by the expression (C). It is to be noted that the coefficient k is hereinafter described.




  
    
      
        
          
            
              
                I
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                k
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                μ
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                    (
                    
                      
                        V
                        gs
                      
                      -
                      
                        V
                        th
                      
                    
                    )
                  
                  2
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                k
                ·
                μ
                ·
                
                  
                    (
                    
                      
                        V
                        sig
                      
                      -
                      
                        V
                        Ofs
                      
                      -
                      
                        Δ
                        ⁢
                        
                          
                        
                        ⁢
                        V
                      
                    
                    )
                  
                  2
                
              
            
          
        
      
    
    
      
        (
        C
        )
      
    
  




Also driving and so forth of the 5Tr/1C driving circuit whose outline is described above are hereinafter described in detail.
Incidentally, in the mobility correction process, the voltage of the source region of the driving transistor TDrv relies upon the image signal (driving signal, luminance signal) VSig as apparent also from the expression (B) and is not fixed. And, since, in order to raise the luminance of the organic EL element, high current flows through the driving transistor TDrv, the rising speed of the rise amount ΔV of the potential in the source region of the driving transistor TDrv is accelerated.
In other words, since the predetermined time for executing the mobility correction process (total time (tCor) of the [period TP (5)6′]) is a fixed design value, where “white display” is to be carried out on the organic EL display apparatus, that is, where the organic EL element displays high luminance, the rise amount ΔV (potential correction value) of the potential in the source region of the driving transistor TDrv exhibits a quick rise as indicated by a solid line ΔV1 in (B) of FIG. 25. On the other hand, where “black display” is to be carried out, that is, where the organic EL element displays low luminance, the rise amount ΔV (potential correction value) of the potential in the source region of the driving transistor TDrv exhibits a slow rise as indicated by a solid line ΔV2 in (B) of FIG. 25. In particular, where the value of ΔV required where “white display” is carried out is represented by ΔVH, the rise amount ΔV reaches ΔVH in time (tH-Cor) shorter than tCor. On the other hand, where the value of ΔV required where “black display” is carried out is represented by ΔVL, ΔVL is not reached if time (tL-Cor) longer than tCor does not elapse. Accordingly, where “white display” is carried out, the rise amount ΔV becomes excessively great, but where “black display” is carried out, the rise amount ΔV becomes excessively small. As a result, such a problem that the display quality of the organic EL display apparatus is deteriorated occurs.
Accordingly, the object of the present invention resides in provision of a driving method for an organic electroluminescence light emitting period of an organic electroluminescence display apparatus which makes it possible to achieve optimization of a mobility correction process of a transistor which composes a driving circuit in response to an image to be displayed.
DISCLOSURE OF INVENTION
In order to achieve the object described above, according to the present invention, there is provided a driving method for an organic electroluminescence light emitting section which uses a driving circuit including
(A) a driving transistor having source/drain regions, a channel formation region and a gate electrode,
(B) an image signal writing transistor including source/drain regions, a channel formation region and a gate electrode, and
(C) a capacitor section including a pair of electrodes,
the driving transistor
(A-1) being connected at one of the source/drain regions thereof to a current supplying section,
(A-2) being connected at the other one of the source/drain regions thereof to the organic electroluminescence light emitting section and also to one of the electrodes of the capacitor section so as to form a second node, and
(A-3) being connected at the gate electrode thereof to the other one of the source/drain regions of the image signal writing transistor and the other one of the electrodes of the capacitor section so as to form a first node,
the image signal writing transistor
(B-1) being connected at one of the source/drain regions thereof to a data line, and
(B-2) being connected at the gate electrode thereof to a scanning line.
And, the driving method includes the steps of:
(a) carrying out a pre-process of applying a first node initialization voltage to the first node and applying a second node initialization voltage to the second node so that the potential difference between the first and second nodes exceeds a threshold voltage of the driving transistor and the potential difference between a cathode electrode of the organic electroluminescence light emitting section and the second node does not exceed a threshold voltage of the organic electroluminescence light emitting section;
(b) carrying out a threshold voltage cancellation process of varying the potential of the second node toward a potential of the difference of the threshold voltage of the driving transistor from the potential of the first node in a state wherein the potential of the first node is maintained;
(c) carrying out a writing process of applying an image signal from the data line to the first node through the image signal writing transistor which has been placed into an on state with a signal from the scanning line; and
(d) placing the image signal writing transistor into an off state with a signal from the scanning line to place the first node into a floating state thereby to allow current corresponding to the value of the potential difference between the first and second nodes to be supplied from the current supplying section to the organic electroluminescence light emitting section through the driving transistor to drive the organic electroluminescence light emitting section.
The driving method further includes the step of
carrying out, between the steps (b) and (c), a mobility correction process of applying a correction voltage to the first node from the data line through the image signal writing transistor which has been placed into an on state with the signal from the scanning line and applying a voltage higher than the potential of the second node at the step (b) from the current supplying section to the one of the source/drain regions of the driving transistor to raise the potential of the second node in response to a characteristic of the driving transistor;
the value of the correction voltage being a value which relies upon the image signal applied from the data line to the first node at the step (c) and is lower than the image signal.
It is to be noted that, in order to vary, at the step (b) described above, the potential of the second node toward the potential of the difference of the threshold voltage of the driving transistor from the potential of the first node in the state wherein the potential of the first node is maintained, a voltage exceeding the voltage of the sum of the potential of the second node at the step (a) and the threshold voltage of the driving transistor may be applied from the current supplying section to the one of the source/drain regions of the driving transistor.
In the driving method for an organic electroluminescence light emitting section (hereinafter referred to simply as driving method of the present invention), the following parameters are used:
value of the image signal: VSig 
value of the correction voltage: VCor 
minimum value of the image signal: VSig-Min 
maximum value of the image signal: VSig-Max 
In this instance, the driving method may have such a form that VCor is represented by a quadratic function of VSig [this can be represented, where a2, a1 and a0 (where a2<0) are coefficients, as VCor=a2·VSig2+a1·VSig+a0 wherein the coefficient of a quadratic term is a negative value.
Or, the driving method may have such a form that, where α1 and β2 are constants higher than 0 and β1 is a constant,

VCor=α1×VSig+β1 [where VSig-Min≦VSig≦VSig-0]

VCor=β2 [where VSig-0≦VSig≦VSig-Max]

are satisfied. It is to be noted, however, that

α1×VSig-0+β1=β2 

Or else, the driving method may have such a form that, where α1 is a constant higher than 0 and β1 is a constant,

VCor=α1×VSig+β1 [where VSig-Min≦VSig≦VSig-Max]

is satisfied.

Or else, the driving method may have such a form that, where α1 and β1 are constants higher than 0,

VCor=−α1×VSig+β1 [where VSig-Min≦VSig≦VSig-Max]

is satisfied.

Or else, the driving method may have such a form that, where α1, α2 and β1 are constants higher than 0 and β2 is a constant,

VCor=−α1×VSig+β1 [where VSig-Min≦VSig≦VSig-0]

VCor=α2×VSig+β2 [where VSig-0≦VSig≦VSig-Max]

are satisfied.

It is to be noted, however, that

−α1×VSig-0+β1=α1×VSig-0β1 

It is to be noted that whether one of the forms should be adopted or a form other than the forms should be adopted may be determined based on time (mobility correction processing time) tCor for the mobility correction process and time (writing processing time) tSig for the writing process. Further, the control of the correction voltage is not limited but can be carried out based on a combination of passive elements such as resistors or capacitors and discrete parts provided in an image signal outputting circuit hereinafter described, or can be carried out by storing a table, which defines a relationship between the image signal and the correction voltage using the image signal as a parameter, in the image signal outputting circuit.
Although details of the driving circuit are hereinafter described, the driving circuit can be formed from a driving circuit composed of five transistors and one capacitor section (5Tr/1C driving circuit), a driving circuit composed of four transistors and one capacitor section (4Tr/1C driving circuit), a driving circuit composed of three transistors and one capacitor section (3Tr/1C driving circuit) or a driving circuit composed of two transistors and one capacitor section (2Tr/1C driving circuit).
In an organic electroluminescence display apparatus (organic EL display apparatus) according to the driving method of the present invention, the configuration and the structure of the current supplying section, the scanning circuit connected to the scanning line, the image signal outputting circuit to which the data line is connected, the scanning line, the data line and the organic electroluminescence light emitting section (hereinafter referred to sometimes merely as light emission section) may be a well-known configuration and structure. In particular, the light emitting section can be formed, for example, from an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer, a cathode electrode and so forth.
In the organic EL display apparatus for color display in the driving method of the present invention, one pixel is formed from a plurality of subpixels. Particularly, however, one pixel may have a form that it is formed from three subpixels of a red light emitting subpixel, a green light emitting subpixel and a blue light emitting subpixel. Or one pixel may be formed from a set of subpixels including one or a plurality of different sub pixels in addition to the three different subpixels (for example, a set including an additional subpixel for emitting white light for enhancing the luminance, another set including additional subpixels for emitting light of complementary colors for expanding the color reproduction range, a further set including an additional subpixel for emitting light of yellow for expanding the color reproduction range or a still further set including additional subpixels for emitting light of yellow and cyan for expanding the color reproduction range).
Although a thin film transistor (TFT) of the n channel type can be used for the transistors for forming the driving circuit, according to circumstances, it is possible to use, for example, a thin film transistor of the p channel type for a light emission controlling transistor hereinafter described or use a thin film transistor of the p channel type for the image signal writing transistor. Also it is possible to form the driving circuit from a field effect transistor (for example, a MOS transistor) formed on a silicon semiconductor substrate. The capacitor section can be formed from one electrode, the other electrode, and a dielectric layer (insulating layer) sandwiched between the electrodes. The transistors and the capacitor section which form the driving circuit are formed in a certain plane (for example, formed on a substrate), and the light emitting section is formed above the transistors and the capacitor section which form the driving circuit with an interlayer insulating layer interposed therebetween. Meanwhile, the other one of the source/drain regions of the driving transistor is connected to the anode electrode provided on the light emitting section, for example, through a contact hole.
The organic EL display apparatus to which the driving method of the present invention is applied includes
(a) a scanning circuit,
(b) an image signal outputting circuit,
(c) totaling N×M organic electroluminescence elements arrayed in a two-dimensional matrix including N organic electroluminescence elements arrayed in a first direction and M organic electroluminescence elements arrayed in a second direction different from the first direction,
(d) M scanning lines connected to a scanning circuit and extending in the first direction,
(e) N data lines connected to an image signal outputting circuit and extending in the second direction, and
(f) a current supplying section. Each of the organic electroluminescence elements (referred to simply as organic EL element) includes
a driving circuit including a driving transistor, an image signal writing transistor and a capacitor section, and
an organic electroluminescence light emitting section (light emitting section).
As described hereinabove, in the prior art, the image signal VSig is applied, in the mobility correction process, to the gate electrode of the driving transistor TDrv. Accordingly, since, in order to raise the luminance of the organic EL element, high current flows to the driving transistor TDrv, in the mobility correction process, the rising speed of the rise amount ΔVCor of the potential (potential correction value) in the source region of the driving transistor TDrv increases. Then, since the mobility correction processing time tCor is fixed, even if organic EL elements have the same mobility, the rise amount ΔVCor (potential correction value) is great with the organic EL element which displays high luminance. Therefore, from the expression (C) given hereinabove, in the organic EL element which should display high luminance, the current flowing to the light emitting section is reduced, and after all, the luminance of the light emitting section becomes lower than desired luminance. On the other hand, the rise amount ΔVCor (potential correction value) is small conversely with the organic EL display element which should display low luminance. Therefore, from the expression (C) given hereinabove, the current to flow to the light emitting section increases in the organic EL element which should display low luminance, and after all, the luminance of the light emitting section becomes higher than desired luminance.
In contrast, in the present invention, the variable correction voltage which has a value which relies upon the image signal VSig and is lower than the image signal VSig is applied to the gate electrode of the driving transistor TDrv. Accordingly, the influence of the magnitude of the image signal VSig upon the mobility correction process (influence on the rise amount ΔVCor) can be reduced, and the luminance of the light emitting section can be set to the desired luminance or the luminance of the light emitting section can be varied further closer to the desired luminance. As a result, enhancement of the display quality of the organic EL display apparatus can be achieved.



BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is an equivalent circuit diagram of a driving circuit of an embodiment 1 basically formed from a 5-transistor/1-capacitor section.
FIG. 2 is a conceptual view of the driving circuit of the embodiment 1 basically formed from the 5-transistor/1-capacitor section.
FIG. 3 is a view schematically showing a timing chart of driving of the driving circuit of the embodiment 1 basically formed from the 5-transistor/1-capacitor section.
(A) and (B) of FIG. 4 are views wherein part of the timing chart of driving shown in FIG. 3 (portions of a [period TP (5)5] and a [period TP (5)6] is enlarged.
(A) to (D) of FIG. 5 are views schematically showing on/off states and so forth of the transistors which compose the driving circuit of the embodiment 1 basically formed from the 5-transistor/1-capacitor section.
(A) to (E) of FIG. 6 are views schematically showing on/off states and so forth of the transistors which compose the driving circuit of the embodiment 1 basically formed from the 5-transistor/1-capacitor section following (D) of FIG. 5.
FIG. 7 is an equivalent circuit diagram of a driving circuit of an embodiment 2 basically formed from a 4-transistor/1-capacitor section.
FIG. 8 is a conceptual view of the driving circuit of the embodiment 2 basically formed from the 4-transistor/1-capacitor section.
FIG. 9 is a view schematically showing a timing chart of driving of the driving circuit of the embodiment 2 basically formed from the 4-transistor/1-capacitor section.
(A) to (D) of FIG. 10 are views schematically showing on/off states and so forth of the transistors which compose the driving circuit of the embodiment 2 basically formed from the 4-transistor/1-capacitor section.
(A) to (D) of FIG. 11 are views schematically showing on/off states and so forth of the transistors which compose the driving circuit of the embodiment 2 basically formed from the 4-transistor/1-capacitor section following (D) of FIG. 10.
FIG. 12 is an equivalent circuit diagram of a driving circuit of an embodiment 3 basically formed from a 3-transistor/1-capacitor section.
FIG. 13 is a conceptual view of the driving circuit of the embodiment 3 basically formed from the 3-transistor/1-capacitor section.
FIG. 14 is a view schematically showing a timing chart of driving of the driving circuit of the embodiment 3 basically formed from the 3-transistor/1-capacitor section.
(A) to (D) of FIG. 15 are views schematically showing on/off states and so forth of the transistors which compose the driving circuit of the embodiment 3 basically formed from the 3-transistor/1-capacitor section.
(A) to (E) of FIG. 16 are views schematically showing on/off states and so forth of the transistors which compose the driving circuit of the embodiment 3 basically formed from the 3-transistor/1-capacitor section following (D) of FIG. 15.
FIG. 17 is an equivalent circuit diagram of a driving circuit of an embodiment 4 basically formed from a 2-transistor/1-capacitor section.
FIG. 18 is a conceptual view of the driving circuit of the embodiment 4 basically formed from the 2-transistor/1-capacitor section.
FIG. 19 is a view schematically showing a timing chart of driving of the driving circuit of the embodiment 4 basically formed from the 2-transistor/1-capacitor section.
(A) to (D) of FIG. 20 are views schematically showing on/off states and so forth of the transistors which compose the driving circuit of the embodiment 4 basically formed from the 2-transistor/1-capacitor section.
(A) to (C) of FIG. 21 are views schematically showing on/off states and so forth of the transistors which compose the driving circuit of the embodiment 4 basically formed from the 2-transistor/1-capacitor section following (D) of FIG. 20.
FIG. 22 is a schematic partial sectional view of part of an organic electroluminescence element.
(A), (B) and (C) of FIG. 23 are equivalent circuit diagrams suitable to carry out control of a correction voltage in the embodiments.
FIG. 24 is an equivalent circuit diagram of a conventional driving circuit basically formed from a 5-transistor/1-capacitor section.
FIG. 25 is a timing chart wherein a [period TP (5)5′] and a [period TP (5)6′] in the equivalent circuit diagram of the conventional driving circuit basically formed from the 5-transistor/1-capacitor section shown in FIG. 24 are enlarged.



BEST MODE FOR CARRYING OUT THE INVENTION
In the following, the present invention is described based on embodiments with reference to the drawings. However, prior to the description, an outline of an organic EL display apparatus which is used in the embodiment is described.
An organic EL display apparatus suitable for use with the embodiments is an organic EL display apparatus which includes a plurality of pixels. And, one pixel is composed of a plurality of sub pixels (in the embodiments, three sub pixels including a red light emitting sub pixel, a green light emitting sub pixel and a blue light emitting sub pixel), and each of the sub pixels is composed of an organic electroluminescence element (organic EL element) 10 having a structure wherein a driving circuit 11 and an organic electroluminescence light emitting element (light emitting section ELP) connected to the driving circuit 11 are laminated. Equivalent circuit diagrams of the organic EL display apparatus in embodiments 1, 2, 3 and 4 are shown in FIGS. 1, 7, 12 and 17, respectively. Conceptual views of the organic EL display apparatus in embodiments 1, 2, 3 and 4 are shown in FIGS. 2, 8, 13 and 18, respectively. It is to be noted that FIGS. 1 and 2 show a driving circuit basically formed from a 5-transistor/1-capacitor section; FIGS. 7 and 8 show a driving circuit basically formed from a 4-transistor/1-capacitor section; FIGS. 12 and 13 show a driving circuit basically formed from a 3-transistor/1-capacitor section; and FIGS. 17 and 18 show a driving circuit basically formed from a 2-transistor/1-capacitor section.
Here, the organic EL display apparatus in each embodiment includes:
(a) a scanning circuit 101;
(b) an image signal outputting circuit 102;
(c) totaling N×M organic EL elements 10 arrayed in a two-dimensional matrix wherein N organic EL elements 10 are arrayed in a first direction and M organic EL elements 10 are arrayed in a second direction different from the first direction (in particular, in a direction perpendicular to the first direction);
(d) M scanning lines SCL connected to the scanning circuit 101 and extending in the first direction;
(e) N data lines DTL connected to the image signal outputting circuit 102 and extending in the second direction; and
(f) a current supplying section 100.
It is to be noted that, while, in FIGS. 2, 8, 13 and 18, 3×3 organic EL elements 10 are shown, this is a mere illustration to the end.
The light emitting section ELP has a well-known configuration and structure including, for example, an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer, a cathode layer and so forth. Further the scanning circuit 101 is provided at one end of the scanning lines SCL. The configuration and structure of the scanning circuit 101, image signal outputting circuit 102, scanning lines SCL, data lines DTL and current supplying section 100 may be any well-known configuration and structure.
Where minimum components of the driving circuit are listed, the driving circuit is composed at least of a driving transistor TDrv, an image signal writing transistor TSig and a capacitor section C1 having a pair of electrodes. The driving transistor TDrv is formed from an n-channel TFT having source/drain regions, a channel formation region and a gate electrode. Also the image signal writing transistor TSig is formed from an n-channel TFT having source/drain regions, a channel formation region and a gate electrode.
Here, in the driving transistor TDrv,
(A-1) one (hereinafter referred to as drain region) of the source/drain regions is connected to the current supplying section 100;
(A-2) the other one (hereinafter referred as source region) of the source/drain regions is connected to the anode electrode provided on the light emitting section ELP and connected to one of the electrodes of the capacitor section C1 and forms a second node ND2; and
(A-3) the gate electrode is connected to the other one of the source/drain regions of the driving transistor TDrv and connected to the other electrode of the capacitor section C1 and forms a first node ND1.
Further, the image signal writing transistor TSig 
(B-1) is connected at the one of the source/drain regions thereof to a data line DTL, and
(B-2) is connected at the gate electrode thereof to a scanning line SCL.
More particularly, as shown in a schematic partial sectional view of part in FIG. 22, the transistors TSig and TDrv and the capacitor section C1 which compose the driving circuit are connected to a substrate, and the light emitting section ELP is formed above the transistors TSig and TDrv and the capacitor section C1, which compose the driving circuit, for example, with an interlayer insulating layer 40 interposed therebetween. Further, the driving transistor TDrv is connected at the other one of the source/drain regions thereof to the anode electrode provided for the light emitting section ELP through a contact hole. It is to be noted that, in FIG. 22, only the driving transistor TDrv is shown. The image signal writing transistor TSig and the other transistors are hidden and cannot be observed.
More particularly, the driving transistor TDrv is formed from a gate electrode 31, a gate insulating layer 32, source/drain regions 35 provided in a semiconductor layer 33, and a channel formation region 34 which corresponds to a portion of the semiconductor layer 33 between the source/drain regions 35. Meanwhile, the capacitor section C1 is formed from the other electrode 36, a dielectric layer formed from an extension of the gate insulating layer 32 and the one electrode 37 (which corresponds to the second node ND2). The gate electrode 31, part of the gate insulating layer 32 and the electrode 36 which composes the capacitor section C1 are formed on a substrate 20. The driving transistor TDrv is connected at the one of the source/drain regions 35 to a wiring line 38 and at the other one of the source/drain regions 35 to the one electrode 37 (which corresponds to the second node ND2). The driving transistor TDrv, capacitor section C1 and so forth are covered with the interlayer insulating layer 40, and the light emitting section ELP formed from an anode electrode 51, the hole transport layer, the light emitting layer, the electron transport layer and a cathode electrode 53 is provided on the interlayer insulating layer 40. It is to be noted that, in the drawings, the hole transport layer, light emitting layer and electron transport layer are represented by one layer 52. A second interlayer insulating layer 54 is provided at a portion of the interlayer insulating layer 40 at which the light emitting section ELP is not provided, and a transparent substrate 21 is disposed on the second interlayer insulating layer 54 and the cathode electrode 53 such that light emitted from the light emitting layer passes through the substrate 21 and goes out to the outside. It is to be noted that the one electrode 37 (second node ND2) and the anode electrode 51 are connected to each other through a contact hole formed in the interlayer insulating layer 40. Further, the cathode electrode 53 is connected to a wiring line 39 provided on the extension of the gate insulating layer 32 through contact holes 56 and 55 formed in the interlayer insulating layer 40.
The organic EL display apparatus is formed from pixels arrayed in an (N/3)×M two-dimensional matrix. And, the organic EL elements 10 which form the pixels are line-sequentially driven, and the display frame rate is FR (times/second). In particular, the organic EL elements 10 which form the N/3 pixels (N sub pixels) arrayed in the mth row (where m=1, 2, 3, . . . , M) are driven simultaneously. In other words, in the organic EL elements 10 which form one row, the light emission/no-light emission timings are controlled in a unit of a row to which the organic EL elements 10 belong. It is to be noted that the process of writing an image signal into the pixels which form one row may be a process of writing an image signal simultaneously into all of the pixels (the process is hereinafter referred to sometimes merely as simultaneous writing process) or may be a process of writing an image signal successively for each of the pixels (the process is hereinafter referred to sometimes merely as successive writing process). Which one of the writing processes should be used may be selected suitably in response to the configuration of the driving circuit.
Here, driving and operation relating to an organic EL element 10 which forms one sub pixel in the pixel which is positioned in the mth row and the nth column (where n=1, 2, 3, . . . , N) is described in principle, and such a subpixel or an organic EL element 10 is hereinafter referred to as (n, m)th sub pixel or (n, m)th organic EL element 10. And, before a horizontal scanning period of the organic EL elements 10 arrayed in the mth row (mth horizontal scanning period) ends, various processes (threshold voltage cancellation process, writing process and mobility correction process hereinafter described) are carried out. It is to be noted that, although the writing process and the mobility correction process are carried out within the mth horizontal scanning period, according to circumstances, they are sometimes carried out over the (m−m′′)th horizontal scanning period to the mth horizontal scanning period. On the other hand, depending upon the type of the driving circuit, the threshold voltage cancellation process and an associated pre-process can be carried out prior to the mth horizontal scanning period.
Then, after all of the various processes described above end, the light emitting sections which compose the organic EL elements 10 arrayed in the mth row are driven to emit light. It is to be noted that the light emitting sections may be driven to emit light immediately after all of the processes described above end, or the light emitting sections may be driven to emit light after a predetermined period (for example, a predetermined horizontal scanning period for a predetermined number of rows). The predetermined period mentioned can be set suitably depending upon the specifications of the organic EL display apparatus, the configuration of the driving circuit and so forth. It is to be noted that, for the convenience of description, it is assumed in the following description that the light emitting section is driven to emit light immediately after the various processes end. And, emission of light of the light emitting sections which form the organic EL elements 10 arrayed in the mth row is continued till a point of time immediately before starting of a horizontal scanning period of the organic EL elements 10 arrayed in the (m+m′)th row. Here, “m′” depends upon the design specifications of the organic EL display apparatus. In particular, emission of light of the light emitting section which composes the organic EL elements 10 arrayed in the mth row of a certain display frame is continued till the (m+m′−1)th horizontal scanning period. Meanwhile, the light emitting section which composes the organic EL elements 10 arrayed in the mth row maintains a no-light emitting state after the start of the (m+m′)th horizontal scanning period until the writing process and the mobility correction process are completed within the mth horizontal scanning period in a next display frame. By the provision of the period of the no-light emission state described hereinabove (the period is hereinafter referred to sometimes simply as no-light emitting period), after-image blurring caused by active Matrix driving is reduced, and the dynamic picture quality can be made more superior. However, the light emission/no-light emission states of each sub pixel (organic EL element 10) are not limited to the states described above. Further, the time length of the horizontal scanning period is time length shorter than (1/FR)×(1/M). Where the value of (m+m′) exceeds M, the exceeding portion of the horizontal scanning period is processed in a next display frame.
The term “one of the source/drain regions” in regard to two source/drain regions which one transistor has is sometimes used to signify one of the source/drain regions on the side connected to a power supply section. Meanwhile, that a transistor is in an on state signifies a state wherein a channel is formed between the source/drain regions. It does not matter whether or not current flows from one of the source/drain regions to the other one of the source/drain regions of the transistor. On the other hand, that the source/drain regions of a certain transistor are connected to the source/drain regions of another transistor includes a form wherein the source/drain regions of the certain transistor and the source/drain regions of the other transistor occupy the same region. Further, the source/drain regions not only can be formed from a conductive material such as polycrystalline silicon or amorphous silicon containing impurities but also can be formed from a layer formed from a metal, an alloy, conductive particles, a laminate structure of them, or an organic material (conductive high molecules). Further, in timing charts used in the following description, the length (time length) of the axis of abscissa indicating various periods is a schematic one, and a ratio in time length between periods is not indicated.
In the following, a driving method for the light emitting section ELP which uses a 5Tr/1C driving circuit, a 4Tr/1C driving circuit, a 3Tr/1C driving circuit and a 2Tr/1C driving circuit is described based on embodiments.
Embodiment 1
The embodiment 1 relates to a driving method for an organic electroluminescence light emitting section of the present invention. In the embodiment 1, the driving circuit is formed from a 5Tr/1C driving circuit.
An equivalent circuit diagram of the 5Tr/1C driving circuit is shown in FIG. 1; a conceptual view is shown in FIG. 2; a timing chart of driving is schematically shown in FIG. 3; and on/off states and so forth of the transistors are schematically shown in (A) to (D) of FIG. 5 and (A) to (E) of FIG. 6. Further, an example of a figure wherein part of the timing chart of driving shown in FIG. 3 ([period TP (5)5] and [period TP (5)6]) is enlarged is shown in (A) and (B) of FIG. 4.
This 5Tr/1C driving circuit includes five transistors including a image signal writing transistor TSig, a driving transistor TDrv, a light emission controlling transistor TEL—C, a first node initializing transistor TND1 and a second node initializing transistor TND2 and further includes one capacitor section C1.
[Light Emission Controlling Transistor TEL—C]
The light emission controlling transistor TEL—C is connected at one of the source/drain regions thereof to the current supplying section 100 (voltage VCC) and at the other one of the source/drain regions thereof to one of the source/drain regions of the driving transistor TDrv. Meanwhile, on/off operation of the light emission controlling transistor TEL—C is controlled by a light emission controlling transistor control line CLEL—C connected to the gate electrode of the light emission controlling transistor TEL—C. It is to be noted that the current supplying section 100 is provided in order to supply current to the light emitting section ELP of the organic EL element 10 to control light emission of the light emitting section ELP. Further, the light emission controlling transistor control line CLEL—C is connected to a light emission controlling transistor control circuit 103.
[Driving Transistor TDrv]
The driving transistor TDrv is connected at the one of the source/drain regions thereof to the other one of the source/drain regions of the light emission controlling transistor TEL—C as described hereinabove. In particular, the driving transistor TDrv is connected at the one of the source/drain regions thereof to the current supplying section 100 through the light emission controlling transistor TEL—C. Meanwhile, the driving transistor TDrv is connected at the other of the source/drain regions thereof to

    [1] the anode electrode of the light emitting section ELP,
    [2] the other one of the source/drain regions of the second node initializing transistor TND2, and
    [3] one of the electrodes of the capacitor section C1 and forms the second node ND2. Further, the driving transistor TDrv is connected at the gate thereof to [1] the other one of the source/drain regions of the image signal writing transistor TSig, [2] the other one of the source/drain regions of the first node initializing transistor TND1, and
    [3] the other electrode of the capacitor section C1 and forms the first node ND1.


Here, in the light emitting state of the organic EL element 10, the driving transistor TDrv is driven to supply drain current Ids in accordance with the expression (1) given below. In the light emitting state of the organic EL element 10, the one of the source/drain regions of the driving transistor TDrv acts as a drain region and the other one of the source/drain regions acts as a source region. For the convenience of description, in the following description, the one of the source/drain regions of the driving transistor TDrv is sometimes referred to simply as drain region, and the other of the source/drain regions is sometimes referred to merely as source region. It is to be noted that

    μ: effective mobility
    L: channel length
    W: channel width
    Vgs: potential difference between the gate electrode and the source region
    Vth: threshold voltage
    Cox: (relative electric constant of the gate insulating layer)×(dielectric constant of vacuum)/(thickness of the gate insulating layer)

k≡(1⁄2)·(W/L)·Cox 

Ids=k·μ·(Vgs−Vth)2  (1)



Since this drain current Ids flows to the light emitting section ELP of the organic EL element 10, the light emitting section ELP of the organic EL element 10 emits light. Further, the light emitting state (luminance) of the light emitting section ELP of the organic EL element 10 is controlled by the magnitude of the value of the drain current Ids.
[Image Signal Writing Transistor TSig]
The image signal writing transistor TSig is connected at the other one of the source/drain regions thereof to the gate electrode of the driving transistor TDrv as described above. Meanwhile, the image signal writing transistor TSig is connected at the one of the source/drain regions thereof to a data line DTL. And, an image signal (driving signal, luminance signal) VSig for controlling the luminance of the light emitting section ELP, and a variable correction voltage VCor, is connected to the one of the source/drain regions of the image signal writing transistor TSig through a data line DTL from the image signal outputting circuit 102. It is to be noted that various signals and voltages (a signal for precharge driving, various reference potentials and so forth) other than VSig and the correction voltage VCor may be supplied to the one of the source/drain regions through the data line DTL. Further, the on/off operation of the image signal VSig is controlled through the scanning line SCL connected to the gate electrode of the image signal writing transistor TSig.
[First Node Initializing Transistor TND1]
The first node initializing transistor TND1 is connected at the other one of the source/drain regions thereof to the gate electrode of the driving transistor TDrv as described above. Meanwhile, a voltage VOfs for initializing the potential of the first node ND1 (that is, the potential of the gate electrode of the driving transistor TDrv) is supplied to the one of the source/drain regions of the first node initializing transistor TND1. Further, the on/off operation of the first node initializing transistor TND1 is controlled through a first node initializing transistor control line AZND1 connected to the gate electrode of the first node initializing transistor TND1. The first node initializing transistor control line AZND1 is connected to a first node initializing transistor control circuit 104.
[Second Node Initializing Transistor TND2]
The second node initializing transistor TND2 is connected at the other one of the source/drain regions thereof to the source electrode of the driving transistor TDrv as described above. Meanwhile, a voltage VSS for initializing the potential of the second node ND2 (that is, the potential of the source region of the driving transistor TDrv) is supplied to the one of the source/drain regions of the second node initializing transistor TND2. Further, the on/off operation of the second node initializing transistor TND2 is controlled through a second node initializing transistor control line AZND2 connected to the gate electrode of the second node initializing transistor TND2. The second node initializing transistor control line AZND2 is connected to a second node initializing transistor control circuit 105.
[Light Emitting Section ELP]
The light emitting section ELP is connected at the anode electrode thereof to the source region of the driving transistor TDrv as described above. Meanwhile, a voltage VCat is applied to the cathode electrode of the light emitting section ELP. The parasitic capacitance of the light emitting section ELP is represented by reference character CEL. Further, the threshold voltage required for emission of light of the light emitting section ELP is represented by Vth-EL. In particular, if a voltage higher than Vth-EL is applied between the anode electrode and the cathode electrode of the light emitting section ELP, then the light emitting section ELP emits light.
In the following description, the values of voltages or potentials are such as given below. However, they are values for description to the upmost and are not limited to the specific values.

    VSig: image signal for controlling the luminance of the light emitting section ELP
    
        0 volts to 14 volts
        Maximum value VSig-Max of the image signal=14 volts
        Minimum value VSig-Min of the image signal=0 volts
    
    
    VCC: voltage of the current supplying section for controlling emission of light of the light emitting section ELP
    
        20 volts
    
    
    VOfs: voltage for initializing the potential of the gate voltage of the driving transistor TDrv (potential of the first node ND1)
    
        0 volts
    
    
    VSS: voltage for initializing the potential of the source region of the driving transistor TDrv (potential of the second node ND2)
    
        −10 volts
    
    
    Vth: threshold voltage of the driving transistor TDrv 
    
        3 volts
    
    
    VCat: voltage applied to the cathode electrode of the light emitting section ELP
    
        0 volts
    
    
    Vth-EL: threshold voltage of the light emitting section ELP
    
        3 volts
    
    


In the following, operation of the 5Tr/1C driving circuit is described. It is to be noted that while it is described that the light emitting state starts immediately after the various processes (threshold voltage cancellation process, writing process and mobility correction process) are completed as described above, the starting of the light emitting state is not limited to this. This similarly applies also to description of the embodiments 2 to 4 (4Tr/1C driving circuit, 3Tr/1C driving circuit and 2Tr/1C driving circuit) hereinafter described.
[Period TP (5)−1] (Refer to (A) of FIG. 5)
This [Period TP (5)−1] relates to operation, for example, for a preceding display frame and is a period within which the (n, m)th organic EL element 10 remains in a light emitting state after completion of the various processes in the preceding operation cycle. In particular, drain current I′ds based on the expression (5) hereinafter given flows to the light emitting section ELP of the organic EL element 10 which forms the (n, m)th sub pixel, and the luminance of the organic EL element 10 which forms the (n, m)th sub pixel has a value corresponding to such drain current I′ds. Here, the image signal writing transistor TSig, first node initializing transistor TND1 and second node initializing transistor TND2 are in an off state, and the light emission controlling transistor TEL—C and the driving transistor TDrv are in an on state. The light emitting state of the (n, m)th organic EL element 10 is continued till a point of time immediately before a horizontal scanning period of the organic EL elements 10 arrayed in the (m+m′)th row.
The [period TP (5)0] to [period TP (5)4] illustrated in FIG. 3 are an operation period after the light emitting state after completion of the various processes in the preceding operation cycle ends till a point of time immediately before a next writing process is carried out. In particular, the [period TP (5)0] to [period TP (5)4] are a period of a certain time length from a start timing of the (m+m′)th horizontal scanning period in a preceding display frame till an end timing of the (m−1)th horizontal scanning period in the current display frame. It is to be noted that the [period TP (5)1] to the [period TP (5)4] can be configured so as to be included in the mth horizontal scanning period in the current display frame.
And within the [period TP (5)0] to the [period TP (5)4], the (n, m)th organic EL element 10 is in a no-light emitting state. In particular, within the [period TP (5)0] to [period TP (5)1] and the [period TP (5)3] to [period TP (5)4], the light emission controlling transistor TEL—C is in an off state, and therefore, the organic EL element 10 does not emit light. It is to be noted that, within the [period TP (5)2], the light emission controlling transistor TEL—C becomes an on state. However, within this period, the threshold voltage cancellation process hereinafter described is carried out. While detailed description is given in the description of the threshold voltage cancellation process, if it is presupposed that the expression (2) hereinafter given is satisfied, then the organic EL element 10 does not emit light.
In the following, the periods from the [period TP (5)0] to [period TP (5)4] are described first. It is to be noted that the start timing of the [period TP (5)1] and the length of each of the periods of the [period TP (5)1] to [period TP (5)4] may be set suitably in accordance with the design of the organic EL display apparatus.
[Period TP (5)0]
As described hereinabove, within this [period TP (5)0], the (n, m)th organic EL element 10 is in a no-light emitting state. The image signal writing transistor TSi, first node initializing transistor TND1 and second node initializing transistor TND2 are in an off state. Further, at a point of time of transition from the [period TP (5)−1] to the [period TP (5)0], the light emission controlling transistor TEL—C is placed into an off state. Therefore, the potential of the second node ND2 (source region of the driving transistor TDrv or anode electrode of the light emitting section ELP) drops to (Vth-EL−VCor), and the light emitting section ELP enters a no-light emitting state. Further, also the potential of the first node ND1 in the floating state (gate electrode of the driving transistor TDrv) drops in such a manner as to follow up the potential drop of the second node ND2.
[Period TP (5)1] (Refer to (B) and (C) of FIG. 5)
Within this [Period TP (5)1], a pre-process for carrying out the threshold voltage cancellation process hereinafter described is carried out. In particular, a first node initialization voltage is applied to the first node ND1 such that the potential difference between the first node ND1 and the second node ND2 exceeds the threshold voltage Vth of the driving transistor TDrv and the potential difference between the cathode electrode of the light emitting section ELP and the second node does not exceed the threshold voltage Vth-EL of the light emitting section ELP, and besides a second node initialization voltage is applied to the second node ND2. In particular, upon starting of the [period TP (5)1], the first node initializing transistor control line AZND1 and the second node initializing transistor control line AZND2 are set to the high level based on operation of the first node initializing transistor control circuit 104 and the second node initializing transistor control circuit 105 to place the first node initializing transistor TND1 and the second node initializing transistor TND2 into an on state. As a result, the potential of the first node ND1 becomes VOfs (for example, 0 volts). Meanwhile, the potential of the second node ND2 becomes VSS (for example, −10 volts). Then, before completion of the [period TP (5)1], the second node initializing transistor control line AZND2 is set to the low level based on operation of the second node initializing transistor control circuit 105 to place the second node initializing transistor TND2 into an off state. It is to be noted that the first node initializing transistor TND1 and the second node initializing transistor TND2 may be placed into an on state at the same time, or the first node initializing transistor TND1 may be placed into an on state first.
By the process described above, the potential difference between the gate electrode and the source region of the driving transistor TDrv becomes higher than Vth, and the driving transistor TDrv is placed into an on state.
[Period TP (5)2] (Refer to (D) of FIG. 5)
Then, in a state wherein the potential of the first node ND1 is maintained, more particularly by applying a voltage exceeding the sum potential of the threshold voltage Vth of the driving transistor TDrv and the potential of the second node ND2 within the [period TP (5)1] to the one of the source/drain regions (drain region) of the driving transistor TDrv from the current supplying section 100, a threshold voltage cancellation process of varying the potential difference between the first node ND1 and the second node ND2 toward the threshold voltage Vth of the driving transistor TDrv (in particular, of raising the potential of the second node ND2) is carried out. More particularly, while the on state of the first node initializing transistor TND1 is maintained, the light emission controlling transistor control line CLEL—C is set to the high level based on the operation of the light emission controlling transistor control circuit 103 to place the light emission controlling transistor TEL—C into an on state. As a result, although the potential of the first node ND1 does not vary (VOfs=0 volts is maintained), the potential of the second node ND2 varies toward the difference potential of the threshold voltage Vth of the driving transistor TDrv from the potential of the first node ND1. In particular, the potential of the second node ND2 in the floating state rises. Then, when the potential difference between the gate electrode and the source region of the driving transistor TDrv reaches Vth, the driving transistor TDrv is placed into an off state. More particularly, the potential of the second node ND2 in the floating state approaches (VOfs−Vth=−3 volts>VSS) and finally becomes (VOfs−Vth). Here, if the expression (2) given below is assured, or in other words, if the potential is selected and determined so as to satisfy the expression (2), then the light emitting section ELP does not emit light at all. It is to be noted that, qualitatively, the degree by which the potential difference between the first node ND1 and the second node ND2 (in other words, the potential difference between the gate electrode and the source region of the driving transistor TDrv) approaches the threshold voltage Vth of the driving transistor TDrv in the threshold voltage cancellation process depends upon the time for the threshold voltage cancellation process. Accordingly, for example, if the time for the threshold voltage cancellation process is assured sufficiently long, then the potential difference between the first node ND1 and the second node ND2 reaches the threshold voltage Vth and the driving transistor TDrv is placed into an off state. On the other hand, for example, if the time for the threshold voltage cancellation process is set short, then the potential difference between the first node ND1 and the second node ND2 is greater than the threshold voltage Vth of the driving transistor TDrv, and the driving transistor TDrv does not sometimes enter an off state. In other words, as a result of the threshold voltage cancellation process, it is not necessarily required that the driving transistor TDrv enters an off state.

(VOfs−Vth)<(Vth-EL+VCat)  (2)

Within this [period TP (5)2], the potential of the second node ND2 finally becomes, for example, (VOfs−Vth). In particular, the potential of the second node ND2 relies only upon the threshold voltage Vth of the driving transistor TDrv and the voltage VOfs for initializing the gate electrode of the driving transistor TDrv. In other words, the potential of the second node ND2 does not rely upon the threshold voltage Vth-EL of the light emitting section ELP.
[Period TP (5)3] (Refer to (A) of FIG. 6)
Thereafter, while the on state of the first node initializing transistor TND1 is maintained, the light emission controlling transistor control line CLEL—C is placed to the low level state based on the operation of the light emission controlling transistor control circuit 103 to place the light emission controlling transistor TEL—C into an off state. As a result, the potential of the first node ND1 does not vary (VOfs=0 volts is maintained), and the potential of the second node ND2 in the floating state does not vary either but (VOfs−Vth=−3 volts) is maintained.
[Period TP (5)4] (Refer to (B) of FIG. 6)
Then, the first node initializing transistor control line AZND1 is set to the low level based on operation of the first node initializing transistor control circuit 104 to place the first node initializing transistor TND1 into an off state. The potential of the first node ND1 and the second node ND2 does not vary (actually, potential differences can possibly be caused by an electrostatic coupling of the parasitic capacitance or the like, but usually they can be ignored).
Now, the periods from the [period TP (5)5] to the [period TP (5)7] are described. It is to be noted that, as hereinafter described, within the [period TP (5)5], a mobility correction process is carried out, and within the [period TP (5)6], a writing process is carried out. As described above, the processes mentioned may be carried out within the mth horizontal scanning period. However, as occasion demands, the processes may be carried out over a plurality of horizontal scanning periods. This similarly applies also to the embodiments 2 to 4 hereinafter described. However, in the embodiment 1, it is assumed for the convenience of description that the start timing of the [period TP (5)5] and the end timing of the [period TP (5)6] coincide with the start timing and the end timing of the mth horizontal scanning period, respectively.
Generally, where the driving transistor TDrv is formed from a polycrystalline silicon thin film transistor or the like, it cannot be avoided that a dispersion appears in the mobility μ between transistors. Accordingly, even if the image signal VSig of an equal value is applied to the gate electrodes of a plurality of driving transistors TDrv having a difference in the mobility μ therebetween, a difference appears between the drain current Ids flowing to the driving transistor TDrv having a higher mobility μ and the drain current Ids flowing to the driving transistor TDrv having a lower mobility μ. If such a difference appears, then the uniformity of the screen image of the organic EL display apparatus is damaged.
[Period TP (5)6] (refer to (C) of FIG. 6)
Accordingly, correction (mobility correction process) of the potential of the source region (second node ND2) of the driving transistor TDrv based on the magnitude of the mobility μ of the driving transistor TDrv is carried out thereafter. In particular, the variable correction voltage VCor is applied from the data line DTL to the first node ND1 through the image signal writing transistor TSig which has been placed into an on state by the signal from the scanning line SCL and a voltage higher than the potential of the second node ND2 within the [period TP (5)2] is applied from the current supplying section 100 to the one of the source/drain regions (drain region) of the driving transistor TDrv to carry out a mobility correction process of raising the potential of the second node ND2 in response to the characteristic of the driving transistor TDrv.
In particular, while the off state of the first node initializing transistor TND1, second node initializing transistor TND2 and light emission controlling transistor TEL—C is maintained, the potential of the data line DTL is set to the correction voltage VCor based on operation of the image signal outputting circuit 102. Then, the scanning line SCL is set to the high level based on operation of the scanning circuit 101 to place the image signal writing transistor TSig into an on state. Simultaneously, the light emission controlling transistor control line CLEL—C is place into a high level state based on operation of the light emission controlling transistor control circuit 103 to place the light emission controlling transistor TEL—C into an on state. As a result, the potential of the first node ND1 (potential of the gate electrode of the driving transistor TDrv) rises to the correction voltage VCor while the potential of the one of the source/drain regions (drain region) of the driving transistor TDrv rises toward VCC.
Here, the value of the correction voltage VCor depends upon the image signal VSig applied to the first node ND1 from the data line DTL within the next [period TP (5)6] and is lower than the image signal VSig. It is to be noted that the relationship between the correction voltage VCor and the image signal VSig is hereinafter described.
As a result of the foregoing, if the value of the mobility μ of the driving transistor TDrv is high, then the rise amount ΔVCor (potential correction value) of the potential at the source region of the driving transistor TDrv is great, but where the value of the mobility μ is low, the rise amount ΔVCor (potential correction value) of the potential at the source region of the driving transistor TDrv is small. Further, where the luminance of the organic EL element is to be raised, the value of the image signal VSig is set high and high current flows to the driving transistor TDrv, but where the luminance is to be lowered, the value of the image signal VSig is set low and low current flows to the driving transistor TDrv. Here, if a case wherein the value of the mobility μ of the driving transistor TDrv is equal in the organic EL elements is considered, the value of the correction voltage VCor in the mobility correction process depends upon the image signal VSig and is lower than the image signal VSig. Accordingly, even if the mobility correction processing time tCor is fixed, the rise amount ΔVCor (potential correction amount) of the potential in the source region of the driving transistor TDrv in the organic EL display elements can be suppressed from being displaced from a desired value. Here, the potential difference between the first node ND1 and the second node ND2, that is, the potential difference Vgs between the gate electrode and the source region of the driving transistor TDvr, can be represented by the following expression (3).

Vg=VCor 

Vs≈VOfs−Vth+ΔVCor 

Vgs≈VCor−[(VOfs−Vth)+ΔVCor]  (3)

It is to be noted that the predetermined time for executing the mobility correction process (total time (tCor) within the [period TP (5)5]) should be determined in advance as a design value upon designing of the organic EL display apparatus. Further, the total time tCor within the [period TP (5)5] is determined such that the potential (VOfs−Vth+ΔVCor) in the source region of the driving transistor TDrv at this time may satisfy the expression (2′) given below is satisfied. And, by this, the light emitting section ELP does not emit light within the [period TP (5)5]. Further, also correction of the dispersion of the coefficient k (≡(1⁄2)·(W/L)·Cox) is carried out simultaneously by the mobility correction process.

(VOfs−Vth+ΔVCor)<(Vth-EL+VCat)  (2′)

[Period TP (5)6] (Refer to (D) of FIG. 6)
Thereafter, a writing process of applying an image signal VSig [image signal VSig (driving signal, luminance signal) for controlling the luminance of the light emitting section ELP] from the data line DTL to the first node ND1 through the image signal writing transistor TSig which has been placed into an on state with a signal from the scanning line SCL is carried out. In particular, while the off state of the first node initializing transistor TND1 and the second node initializing transistor TND2 is maintained and the on state of the image signal writing transistor TSig and the light emission controlling transistor TEL—C is maintained, the potential of the data line DTL is set to the image signal VSig for controlling the luminance of the light emitting section ELP from the correction voltage VCor based on operation of the image signal outputting circuit 102. As a result, the potential of the first node ND1 rises to VSig. Also the potential of the second node ND2 rises following up the rise of the potential of the first node ND1. The rise amount of the potential of the second node ND2 from ΔVCor is represented by ΔVSig. As a result of the foregoing, the potential difference between the first node ND1 and the second node ND2, that is, the potential difference Vgs between the gate electrode and the source electrode of the driving transistor TDrv, is transformed from the expression (3) into the expression (4) given below. The time for the writing process (writing processing time) is TSig.

Vg=VSig 

Vs≈VOfs−Vth+ΔVCor+ΔVSig 

Vgs≈VSig−[VOfs−Vth+ΔVCor+ΔVSig)  (4)

In particular, Vg, obtained by the writing process into the driving transistor TDrv relies only upon the image signal VSig for controlling the luminance of the light emitting section ELP, the threshold voltage Vth of the driving transistor TDrv the voltage VOfs for initializing the gate electrode of the driving transistor TDrv and the correction voltage VCor. Here, ΔVCor and ΔVSig rely only upon VSig, Vth, VOfs and VCor. This similarly applies also to the embodiments 2 to 4 hereinafter described. Further, they are independent of the threshold voltage Vth-EL of the light emitting section ELP.
[Period TP (5)7] (Refer to (E) of FIG. 6)
Since the threshold voltage cancellation process, writing process and mobility correction process are completed by the operations described above, the image signal writing transistor TSig is placed into an off state with a signal from the scanning line SCL to place the first node ND1 into a floating state thereby to supply current corresponding to the value of the potential difference between the first node ND1 and the second node ND2 from the current supplying section 100 to the light emitting section ELP through the driving transistor TDrv to drive the light emitting section ELP. In other words, the light emitting section ELP is caused to emit light.
In particular, after the predetermined time (tSig) elapses, the scanning line SCL is placed into a low level state based on operation of the scanning circuit 101 to place the image signal writing transistor TSig into an off state thereby to place the first node ND1 (gate electrode of the driving transistor TDrv) into a floating state. Meanwhile, the light emission controlling transistor TEL—C maintains the on state, and the drain region of the light emission controlling transistor TEL—C is in a state wherein it is connected to the current supplying section 100 (voltage VCC, for example, 20 volts) for controlling the emission of light of the light emitting section ELP. Accordingly, as a result of the foregoing, the potential of the second node ND2 rises. Here, since the gate electrode of, the driving transistor TDrv is in a floating state as described hereinabove and besides the capacitor section C1 exists, a phenomenon similar to that which occurs with a so-called bootstrap circuit occurs with the gate electrode of the driving transistor TDrv, and also the potential of the first node ND1 rises. As a result, the potential difference Vgs between the gate electrode and the source region of the driving transistor TDrv maintains the value of the expression (4). Further, since the potential of the second node ND2 rises and exceeds (Vth-EL+VCat), the light emitting section ELP starts emission of light. At this time, since the current flowing to the light emitting section ELP is drain current Ids flowing from the drain region to the source region of the driving transistor TDrv, it can be represented by the expression (1). Here, from the expressions (1) and (4), the expression (1) can be transformed in such a manner as given by the following expression (5).

Ids=k·μ·(VSig−VOfs−ΔVCorΔVSig)2  (5)

Accordingly, the current Id, flowing through the light emitting section ELP increases in proportion to the square of a value obtained by subtracting, for example, where VOfs is set to 0 volts, the value of the potential correction value ΔVCor at the second node ND2 (source region of the driving transistor TDrv) originating from the mobility μ of the driving transistor TDrv and ΔVSig which relies upon the value of the image signal VSig from the value of the image signal VSig for controlling the luminance of the light emitting section ELP. In other words, the drain current Ids flowing through the light emitting section ELP does not rely upon any of the threshold voltage Vth-EL of the light emitting section ELP and the threshold voltage Vth of the driving transistor TDrv. In other words, the light emission amount (luminance) of the light emitting section ELP is not influenced by any of the threshold voltage Vth-EL of the light emitting section ELP and the threshold voltage Vth of the driving transistor TDrv. And, the luminance of the (n, m)th organic EL element 10 has a value corresponding to the drain current Ids.
Besides, as the mobility μ of the driving transistor TDrv increases, the potential correction value ΔVCor increases, and therefore, the value of Vgs on the left side of the expression (4) decreases. Accordingly, in the expression (5), even if the value of the mobility μ is high, the value of (VSig−VOfs−ΔVCor−ΔVSig)2 is low, and as a result, the drain current Ids can be corrected. In particular, even where the driving transistors TDrv have different values of the mobility μ, if the values of the image signal VSig are equal to each other, then the values of drain current Ids are substantially equal to each other. As a result, the drain current Ids which flows through the light emitting sections ELP and controls the luminance of the light emitting sections ELP is uniformed. In particular, a dispersion of the luminance of the light emitting section arising from a dispersion of the mobility μ (further from a dispersion of k) can be corrected.
Further, in the mobility correction process, the correction voltage VCor which depends upon the image signal VSig and is lower than the image signal VSig is applied to the gate electrode of the driving transistor TDrv. Accordingly, the influence of the luminance of the image signal VSig on the mobility correction process can be reduced, and the luminance of the light emitting section can be controlled to a desired luminance. As a result, improvement of the display quality of the organic EL display apparatus can be achieved.
An example of a view where part of the timing chart of driving shown in FIG. 3 (portions represented as [period TP (5)5] and [period TP (5)6]) is shown in (A) and (B) of FIG. 4. Here, in the example shown in (A) and (B) of FIG. 4, potential variation of the first node ND1 and the second node ND2 within the [period TP (5)5] and the [period TP (5)6] are indicated by solid lines. Further, potential variations of the first node ND1 and the second node ND2 within the [period TP (5)5′] when the prior art is applied are indicated by broken lines. Further, while the time until the value of (ΔVCor+ΔVSig) becomes a desired value is represented by t, in the example shown in (A) of FIG. 4, the value of t when the prior art is applied is shorter than the value of t in the embodiment 1. Meanwhile, in the example shown in (B) of FIG. 4, the value of t when the prior art is applied is longer than the value of t in the embodiment 1.
The light emitting state of the light emitting section ELP continues till the (m+m′−1)th horizontal scanning period. This point of time corresponds to the end of the [period TP (5)−1].
By the foregoing, the light emitting operation of the organic EL element 10 [(n, m)th subpixel (organic EL element 10)] is completed.
In the following, a relationship between the correction voltage VCor and the image signal VSig is described.
It is assumed now that the optimum mobility correction time for gradations of white, gray and black (more accurately, including gray nearer to black) is 3, 5 and 7 microseconds. Meanwhile, the mobility correction processing time tCor is assumed to be 4 microseconds, and the writing processing time tSig is assumed to be 3 microseconds. And, in such time settings, an optimum correction voltage VCor is examined for each gradation.
First, where the organic EL display element displays a gradation of the black for which the image signal VSig is, for example, lower than 3 volts (more accurately, a gradation including gray nearer to the black. This similarly applies also to the following description), the optimum mobility correction time of the gradation of the black (for example, image signal VSig=3 volts) is 7 microseconds. On the other hand, since tCor+tSig=7 microseconds, where the gradation of the black is displayed by the organic EL element, the correction voltage VCor of a very high value need not be applied. The relationship between the correction voltage VCor and the image signal VSig is, according to various tests, for example, such as given below.














Image signal VSig
Correction voltage VCor









0 (V)
0 (V)



3 (V)
3 (V)










Then, when the gradation of gray (image signal VSig is, for example, 6 to 8 volts or less) is displayed by the organic EL element, the optimum mobility correction time of the gradation of the gray (for example, image signal VSig=8 volts) is 5 microseconds. However, since the mobility correction processing time tCor is 4 microseconds, the optimum mobility correction time of the gradation of the gray (for example, image signal VSig=8 volts) exceeds the mobility correction processing time tCor. Accordingly, it is necessary to set the value of the correction voltage VCor so that the optimum mobility correction time may not exceed the mobility correction processing time tCor. The relationship between the correction voltage VCor and the image signal VSig is, as a result of various tests, for example, such as given below.














Image signal VSig
Correction voltage VCor









6 (V)
  4 (V)



8 (V)
6.7 (V)










Then, for example, when the gradation of the white (the image signal VSig is, for example, lower than 14 volts) is displayed by the organic EL element, the optimum mobility correction time of the gradation of the white (for example, image signal VSig=14 volts) is 3 microseconds. And, since the mobility correction processing time tCor is 4 microseconds, the optimum mobility correction time of the gradation of the white (for example, image signal VSig=14 volts) is within the range of the mobility correction processing time tCor. Accordingly, where the gradation of the white is displayed by the organic EL element, the correction voltage VCor of a very high value need not be applied. The relationship between the correction voltage VCor and the image signal VSig is, as a result of various tests, for example, such as given below.














Image signal VSig
Correction voltage VCor









10 (V)
0 (V)



12 (V)
0 (V)



14 (V)
0 (V)










As a result of the foregoing, and further, from a test wherein a finer relationship between the correction voltage VCor and the image signal VSig was examined, if an optimum correction voltage VCor is considered for each gradation in the timing settings described hereinabove, then the correction voltage VCor was represented by a quadratic function of VSig wherein the coefficient of a quadratic term is a negative value. In particular, where a2, al and a0 are coefficients (however, where a2<0), the correction voltage VCor was able to be represented as VCor=a2·VSig2+a1·VSig+a0.
If the relationship between the correction voltage VCor and the image signal VSig is set based on a quadratic function in this manner, then by assembling a logic circuit conforming to the function in the organic EL display apparatus, the optimum correction voltage VCor can be determined finely for each image signal VSig and outputted to the driving circuit 11.
Alternately, it is assumed that the optimum mobility correction time for gradations of white, gray and black (more accurately, including gray nearer to black) is 3, 5 and 7 microseconds. On the other hand, different from the foregoing, the mobility correction processing time tCor is set to 5.5 microseconds, and the image signal writing transistor TSig is set to 1.5 microseconds. And, in such time settings, an optimum correction voltage VCor is considered for each gradation.
First, where the organic EL display element displays a gradation of the black (the image signal VSig is, for example, lower than 3 volts, the optimum mobility correction time of the gradation of the black (for example, image signal VSig=3 volts) is 7 microseconds. On the other hand, since tCor+tSig=7 microseconds, where the gradation of the black is displayed by the organic EL element, the correction voltage VCor of a very high value need not be applied. The relationship between the correction voltage VCor and the image signal VSig is, according to various tests, for example, such as given below.














Image signal VSig
Correction voltage VCor









0 (V)
0 (V)



3 (V)
3 (V)










Then, when the gradation of gray (image signal VSig is, for example, 6 to 8 volts or less) is displayed by the organic EL element, the optimum mobility correction time of the gradation of the gray (for example, image signal VSig=8 volts) is 5 microseconds. However, since the mobility correction processing time tCor is 1.5 microseconds, the optimum mobility correction time of the gradation of the gray (for example, image signal VSig=6 to 8 volts) exceeds the mobility correction processing time tCor. Accordingly, it is necessary to set the value of the correction voltage VCor so that the optimum mobility correction time may not exceed the mobility correction processing time tCor. The relationship between the correction voltage VCor and the image signal VSig is, as a result of various tests, for example, such as given below.














Image signal VSig
Correction voltage VCor









6 (V)
6.5 (V)



8 (V)
6.5 (V)










Then, for example, when the gradation of the white (the image signal VSig is, for example, lower than 14 volts) is displayed by the organic EL element, the optimum mobility correction time of the gradation of the white (for example, image signal VSig=14 volts) is 3 microseconds. And, since the mobility correction processing time tCor is 1.5 microseconds, the optimum mobility correction time of the gradation of the white (for example, image signal VSig=14 volts) exceeds the mobility correction processing time tCor. Accordingly, it is necessary to set the correction voltage VCor so as not to exceed the mobility correction processing time tCor. The relationship between the correction voltage VCor and the image signal VSig is, as a result of various tests, for example, such as given below.














Image signal VSig
Correction voltage VCor









10 (V)
6.5 (V)



12 (V)
6.5 (V)



14 (V)
8.5 (V)










As a result of the foregoing, and further, from a test wherein a finer relationship between the correction voltage VCor and the image signal VSig was examined, if an optimum correction voltage VCor is considered for each gradation in the timing settings described hereinabove, then where α1 and β2 are constants higher than 0 and β1 is a constant,

VCor=α1×VSig+β1 [where VSig-Min≦VSig≦VSig-0]

VCor=β2 [where VSig-0≦VSig≦VSig-Max]

are satisfied. Here, α1×VSig-0+β1=β2.

If the relationship between the correction voltage VCor and the image signal VSig is set based on a linear function in this manner, then by assembling a logic circuit conforming to the function in the organic EL display apparatus, the optimum correction voltage VCor can be determined finely for each image signal VSig and outputted to the driving circuit 11.
As described above, it may be determined based on the mobility correction processing time tCor and the writing processing time tSig what relationship (for example, function) should be adopted as a relationship between the correction voltage VCor and the image signal VSig. For example, where the mobility correction processing time tCor is longer than the writing processing time tSig, although it depends upon the values of tCor and tSig, where α1 is a constant higher than 0 and β1 is a constant, a monotonously increasing linear function which satisfies

VCor=α1×VSig+β1 [where VSig-Min≦VSig≦VSig-Max]

may be used for the relationship described above. For example, where the mobility correction processing time tCor is shorter than the writing processing time tSig, although it depends upon the values of tCor and tSig, where α1 and β1 are constants higher than 0, a monotonously decreasing linear functions which satisfies

VCor=−α1×VSig+β1 [where VSig-Min≦VSig≦VSig-Max]

may be used for the relationship described above. Further, although it depends upon the values of tCor and tSig, where α1, α2 and β1 are constants higher than 0 and β2 is a constant,

VCor=−α1×VSig+β1 [where VSig-Min≦VSig≦VSig-0]

VCor=α2×VSig+β2 [where VSig-0≦VSig≦VSig-Max]

are satisfied. Here, −α1×VSig-0+β1=α2×VSig-0+β2.

Although it depends upon the relationship between the correction voltage VCor and the image signal VSig, a table which defines the relationship between the image signal VSig and the correction voltage VCor using the image signal VSig as a parameter may be stored in the image signal outputting circuit 102 such that a correction voltage VCor is determined based on the image signal VSig to be outputted from the image signal outputting circuit 102 and is then outputted from the image signal outputting circuit 102.
Alternatively, control of the correction voltage VCor can be carried out based on a combination of passive elements such as resistors and capacitors, discrete parts and so forth provided in the image signal outputting circuit 102. In particular, where the relationship between the correction voltage VCor and the image signal VSig are set as a monotonously increasing linear function, the image signal outputting circuit 102 includes, for example, a digital-analog converter DAC, resistors RT1 and RT2 and switches SWA and SWB as shown in (A) of FIG. 23. Then, an image signal VSig is outputted from the digital-analog converter DAC. Within the [period TP (5)5], the switch SWB is placed into an off state and the switch SWA is placed into an on state. As a result, the value of the potential at a node NDA, that is, the correction voltage VCor, becomes such as given by an expression given below based on the resistance value (rt1) of the resistor RT1 and the resistance value (rt2) of the resistor RT2, and the correction voltage VCor is outputted to the data line DTL.

VCor=VSig×rt2/(rt1+rt2)

Thereafter, within the [period TP (5)6], the switch SWB is placed into an on state and the switch SWA is placed into an off state. As a result, an image signal VSig is outputted to the data line DTL. By varying the resistance value (rt1) of the resistor RT1 and the resistance value (rt2) of the resistor RT2 as described above, that is, by a simple resistance dividing method, the relationship between the correction voltage VCor and the image signal VSig can be varied readily.
Alternatively, where the relationship between the correction voltage VCor and the image signal VSig is set to a monotonously increasing linear function, the image signal outputting circuit 102 is formed, for example, from a digital-analog converter DAC, capacitors CS1 and CS2 and switches SWA, SWB and SWC as shown in (B) of FIG. 23. Then, an image signal VSig is outputted from the digital-analog converter DAC. Within the [period TP (5)5], the switches SWB and SWC are placed into an off state and the switch SWA is placed into an on state. As a result, the value of the potential at the node NDA, that is, the correction voltage VCor, becomes such as given by the expression given below by coupling of the capacitors CS1 (capacitance cs1) and CS2 (capacitance cs2), and a correction voltage VCor is outputted to the data line DTL.

VCor=VSig×cs1/(cs1+cs2)

Thereafter, within the [period TP (5)6], the switches SWB and SWC are placed into an on state and the switch SWA is placed into an off state. As a result, an image signal VSig is outputted to the data line DTL. By varying the capacitance cs1 of the capacitor CS1 and the capacitance cs2 of the capacitor CS2 as described above, that is, by a simple resistance dividing method, the relationship between the correction voltage VCor and the image signal VSig can be varied readily.
Alternatively, where the relationship between the correction voltage VCor and the image signal VSig is set to a monotonously decreasing linear function, the image signal outputting circuit 102 is formed, for example, from a digital-analog converter DAC, a transistor TR, a resistor RT, a capacitor CS and switches SWA, SWB and SWC as shown in (C) of FIG. 23. Then, an image signal VSig is outputted from the digital-analog converter DAC. Within the [period TP (5)5], the switch SWA is placed into an on state and the switches SWB and SWC are placed into an on state.
Here, where the value of the image signal VSig is high, that is, where the organic EL element displays the gradation of the white, the voltage drop by the transistor TR is small and the potential VA at the node NDA is high. Further, the value of the potential at the node NDB, that is, the correction voltage VCor, becomes VCor=Vdd−VA by coupling of the capacitor CS. As described above, where the value of the image signal VSig is high, since the potential VA at the node NDA is high, the value of the correction voltage VCor is low after all. Then, this correction voltage VCor is outputted to the data line DTL.
Meanwhile, where the value of the image signal VSig is low, that is, where the organic EL element displays the gradation of the black, the voltage drop by the transistor TR is great and the potential VA at the node NDA is low. Further, the value of the potential at the node NDB, that is, the correction voltage VCor, becomes VCor=Vdd−VA by coupling of the capacitor CS. As described above, where the value of the image signal VSig is low, since the potential VA at the node NDA is low, the value of the correction voltage VCor is high after all. Then, this correction voltage VCor is outputted to the data line DTL.
Thereafter, within the [period TP (5)6], the switches SWB and SWC are placed into an on state and the switch SWA is placed into an off state. As a result, an image signal VSig is outputted to the data line DTL. By varying the resistance value of the transistor TR in the on state, the resistance value of the resistor RT and the capacitance of the capacitor CS as described above, the relationship between the correction voltage VCor and the image signal VSig can be varied readily.
The foregoing argument and circuit configuration can be applied also to the embodiments 2 to 4 described below.
Embodiment 2
The embodiment 2 is a modification to the embodiment 1. In the embodiment 2, the driving circuit is formed from a 4Tr/1C driving circuit. An equivalent circuit diagram of the 4Tr/1C driving circuit is shown in FIG. 7; a conceptual view is shown in FIG. 8; a timing chart of driving is schematically shown in FIG. 9; and on/off states and so forth of the transistors are schematically shown in (A) to (D) of FIG. 10 and (A) to (D) of FIG. 11.
In this 4Tr/1C driving circuit, the first node initializing transistor TND1 is omitted from the 5Tr/1C driving circuit described hereinabove. In particular, the present 4Tr/1C driving circuit is composed of four transistors of an image signal writing transistor TSig, a driving transistor TDrv, a light emission controlling transistor TEL—C and a second node initializing transistor TND2 and further includes one capacitor section C1.
[Light Emission Controlling Transistor TEL—C]
The configuration of the light emission controlling transistor TEL—C is same as that of the light emission controlling transistor TEL—C described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
[Driving Transistor TDrv]
The configuration of the driving transistor TDrv is same as that of the driving transistor TDrv described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
[Second Node Initializing Transistor TND2.]
The configuration of the second node initializing transistor TND2 is same as that of the second node initializing transistor TND2 described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
[Image Signal Writing Transistor TSig]
The configuration of the image signal writing transistor TSig is same as that of image signal writing transistor TSig described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted. It is to be noted, however, that, although the image signal writing transistor TSig is connected at the one of the source/drain regions thereof to a data line DTL, not only the image signal VSig and the correction voltage VCor for controlling the luminance of the light emitting section ELP but also a voltage VOfs for initializing the gate electrode of the driving transistor TDrv are supplied from the image signal outputting circuit 102. In this regard, the operation of the image signal writing transistor TSig is different from that of the image signal writing transistor TSig described hereinabove in connection with the 5Tr/1C driving circuit. It is to be noted that, from the image signal outputting circuit 102, a signal or voltage (for example, a signal for precharge driving) other than VSig, VCor and VOfs may be supplied to the one of the source/drain regions of the image signal writing transistor TSig.
[Light Emitting Section ELP]
The configuration of the light emitting section ELP is same as that of the light emitting section ELP described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
In the following, operation of the 4Tr/1C driving circuit is described.
[Period TP (4)−1] (Refer to (A) of FIG. 10)
Operation within this [period TP (4)−1] is operation, for example, in a preceding display frame and is same as that within the [period TP (5)−1] described hereinabove in connection with the 5Tr/1C driving circuit.
The [period TP (4)0] to the [period TP (4)4] shown in FIG. 9 are a period corresponding to the [period TP (5)0] to the [period TP (5)4] shown in FIG. 3 and is an operation period till a point of time immediately before a next writing process is carried out. Moreover, similarly as in the 5Tr/1C driving circuit, within the [period TP (4)0] to the [period TP (4)4], the (n, m)th organic EL element 10 is in a no-light emitting state. However, the operation of the 4Tr/1C driving circuit is different from the operation of the 5Tr/1C driving circuit in that not only the [period TP (4)5] to the [period TP (4)6] but also the [period TP (4)2] to the [period TP (4)4] are included in the mth horizontal scanning period. It is to be noted that, for the convenience of description, it is described that the start timing of the [period TP (4)2] and the end timing the [period TP (4)6] coincide with the start timing and the end timing of the mth horizontal scanning period, respectively.
In the following, the [period TP (4)0] to the [period TP (4)4] are described individually. It is to be noted that, similarly as in the description of the 5Tr/1C driving circuit, the start timing of the [period TP (4)1] and the length of each of the periods of the [period TP (4)1] to [period TP (4)4] may be set suitably in accordance with the design of the organic EL display apparatus.
[Period TP (4)0]
Operation within this [period TP (4)0] is operation, for example, in a current display frame from a preceding display frame and is substantially same operation as that within the [period TP (5)0] described hereinabove in connection with the 5Tr/1C driving circuit.
[Period TP (4)1] (Refer to (B) of FIG. 10)
This [period TP (4)1] corresponds to the [period TP (5)1] described hereinabove in connection with the 5Tr/1C driving circuit. Within this [period TP (4)1], a pre-process for carrying out a threshold voltage cancellation process hereinafter described is carried out. Upon starting of the [period TP (4)1], the second node initializing transistor control line AZND2 is placed into a high level state based on operation of the second node initializing transistor control circuit 105 to place the second node initializing transistor TND2 into an on state. As a result, the potential of the second node ND2 becomes VSS (for example, −10 volts). Also the potential of the first node ND1 (gate electrode of the driving transistor TDrv) in a floating state drops in such a manner as to follow up the potential drop of the second node ND2. It is to be noted that the potential of the first node ND1 within the [period TP (4)1] depends upon the potential of the first node ND1 (which depends upon the value of VSig in the preceding frame) within the [period TP (4)−1] and therefore does not assume a fixed value.
[Period TP (4)2] (Refer to (C) of FIG. 10)
Thereafter, the potential of the data line DTL is set to VOfs based on operation of the image signal outputting circuit 102 and the scanning line SCL is placed into a high level state based on operation of the scanning circuit 101 to place the image signal writing transistor TSig into an on state. As a result, the potential of the first node ND1 becomes VOfs (for example, 0 volts). The potential of the second node ND2 maintains VSS (for example, −10 volts). Thereafter, the second node initializing transistor control line AZND2 is placed into a low level state based on operation of the second node initializing transistor control circuit 105 to place the second node initializing transistor TND2 into an off state.
It is to be noted that the image signal writing transistor TSig may be placed into an on state simultaneously with the starting of the [period TP (4)1] or midway of the [period TP (4)1].
By the processes described above, the potential difference between the gate electrode and the source region of the driving transistor TDrv becomes greater than Vth and the driving transistor TDrv is placed into an on state.
[Period TP (4)3] (Refer to (D) of FIG. 10)
Then, a threshold voltage cancellation process is carried out. In particular, while the on state of the image signal writing transistor TSig is maintained, the light emission controlling transistor control line CLEL—C is placed into a high level state based on operation of the light emission controlling transistor control circuit 103 to place the light emission controlling transistor TEL—C into an on state. As a result, although the potential of the first node ND1 does not vary (VOfs=0 volts are maintained), the potential of the second node ND2 varies toward a potential difference of the threshold voltage Vth of the driving transistor TDrv from the potential of the first node ND1. In other words, the potential of the second node ND2 in a floating state rises. Then, if the potential difference between the gate electrode and the source region of the driving transistor TDrv reaches Vth, then the driving transistor TDrv is placed into an off state. In particular, the potential of the second node ND2 in the floating state varies toward (VOfs−Vth=−3 volts) and finally becomes (VOfs−Vth). Here, if the expression (2) given hereinabove is assured, or in other words, if the potential is selected and determined so as to satisfy the expression (2), then the light emitting section ELP does not emit light at all.
Within this [period TP (4)3], the potential of the second node ND2 finally becomes, for example, (VOfs−Vth). In particular, the potential of the second node ND2 depends only upon the threshold voltage Vth of the driving transistor TDrv and the voltage VOfs for initializing the gate electrode of the driving transistor TDrv. Moreover, the potential of the second node ND2 is independent of the threshold voltage Vth-EL of the light emitting section ELP.
[Period TP (4)4] (Refer to (A) of FIG. 11)
Thereafter, while the on state of the image signal writing transistor TSig is maintained, the light emission controlling transistor control line CLEL—C is placed into a low level state based on operation of the light emission controlling transistor control circuit 103 to place the light emission controlling transistor TEL—C into an off state. As a result, the potential of the first node ND1 does not vary (VOfs=0 volts are maintained) and also the potential of the second node ND2 in the floating state does not substantially vary (while actually potential variations may possibly be caused by electrostatic coupling of the parasitic capacitance and so forth, normally they can be ignored) but maintains (VOfs−Vth=3 volts).
Now, periods from the [period TP (4)5] to the [period TP (4)7] are described. Operation in the periods is substantially same operation as that in the [period TP (5)5] to the [period TP (5)7] described hereinabove in connection with the 5Tr/1C driving circuit.
[Period TP (4)5] (Refer to (B) of FIG. 11)
Then, correction (mobility correction process) of the potential of the source region of the driving transistor TDrv (second node ND2) based on the magnitude of the mobility μ of the driving transistor TDrv is carried out. In particular, operation same as that in the [period TP (5)5] described hereinabove in connection with the 5Tr/1C driving circuit may be carried out. In particular, while the off state of the second node initializing transistor TND2 and the light emission controlling transistor TEL—C is maintained, the potential of the data line DTL is changed over from VOfs to the correction voltage VCor based on operation of the image signal outputting circuit 102 to place the image signal writing transistor TSig and the light emission controlling transistor TEL—C into an on state. As a result, the potential of the first node ND1 rises to the correction voltage VCor and the potential of the second node ND2 rises to ΔVCor. It is to be noted that the predetermined time for executing the mobility correction process (total time (tCor) within the [period TP (4)5] may be determined as a design value in advance upon designing of the organic EL display apparatus.
By this, similarly as in the description of the 5Tr/1C driving circuit, the value described in connection with the expression (3) can be obtained as the potential difference between the first node ND1 and the second node ND2, that is, as the potential difference Vas between the gate electrode and the source region of the driving transistor TDrv.
[Period TP (4)6] (Refer to (C) of FIG. 11)
Thereafter, a writing process for the driving transistor TDrv is executed. In particular, the potential of the data line DTL is changed over from VCors to the image signal VSig for controlling the luminance of the light emitting section ELP based on operation of the image signal outputting circuit 102. As a result, the potential of the first node ND1 rises to VSig and the potential of the second node ND2 rises almost to (VOfs−Vth+ΔVCor+ΔVSig). Consequently, similarly as in the description given hereinabove in connection with the 5Tr/1C driving circuit, the value described hereinabove in connection with the expression (4) can be obtained as the potential difference between the first node ND1 and the second node ND2, that is, as the potential difference Vgs between the gate electrode and the source region of the driving transistor TDrv.
In particular, also in the 4Tr/1C driving circuit, Vgs obtained in the writing process into the driving transistor TDrv relies only upon the image signal VSig for controlling the luminance of the light emitting section ELP, the threshold voltage Vth of the driving transistor TDrv, the voltage VOfs for initializing the gate electrode of the driving transistor TDrv and the correction voltage VCor. Moreover, Vgs is independent of the threshold voltage Vth-EL of the light emitting section ELP.
[Period TP (4)7] (Refer to (D) of FIG. 11)
By the foregoing operation, the threshold voltage cancellation process, writing process and mobility correction process are completed. Then, a process same as that in the [period TP (5)7] described hereinabove in connection with the 5Tr/1C driving circuit is carried out, and the potential of the second node ND2 rises and exceeds (Vth-EL+VCat). Therefore, the light emitting section ELP starts emission of light. At this time, since the current flowing through the light emitting section ELP can be obtained using the expression (5) given hereinabove, the drain current Ids flowing through the light emitting section ELP does not rely upon any of the threshold voltage Vth-EL of the light emitting section ELP and the threshold voltage Vth of the driving transistor TDrv. In other words, the light emission amount (luminance) of the light emitting section ELP is not influenced by any of the threshold voltage Vth-EL of the light emitting section ELP and the threshold voltage Vth of the driving transistor TDrv. In addition, occurrence of a dispersion in drain current Ids arising from a dispersion in mobility μ of the driving transistor TDrv can be suppressed.
Then, the light emitting state of the light emitting section ELP continues till the (m+m′−1)th horizontal scanning period. This point of time corresponds to the end of the [period TP (4)−1].
By the operation described above, the light emitting operation of the organic EL element 10 [(n, m)th sub pixel (organic EL element 10)] is completed.
Embodiment 3
The embodiment 3 is a modification to the embodiment 1. In the embodiment 3, the driving circuit is formed from a 3Tr/1C driving circuit. An equivalent circuit diagram of the 3Tr/1C driving circuit is shown in FIG. 12, a conceptual view is shown in FIG. 13, a timing chart of driving is schematically shown in FIG. 14, and on/off states and so forth of the transistors are shown in (A) to (D) of FIG. 15 and (A) to (E) of FIG. 16.
In this 3Tr/1C driving circuit, two transistors of the first node initializing transistor TND1 and the second node initializing transistor TND2 are omitted from the 5Tr/1C driving circuit described hereinabove. In particular, the present 3Tr/1C driving circuit is composed of three transistors of an image signal writing transistor TSig, a light emission controlling transistor TEL—C and a driving transistor TDrv and further includes one capacitor section C1.
[Light Emission Controlling Transistor TEL—C]
The configuration of the light emission controlling transistor TEL—C is same as that of the light emission controlling transistor TEL—C described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
[Driving Transistor TDrv]
The configuration of the driving transistor TDrv is same as that of the driving transistor TDrv described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
[Image Signal Writing Transistor TSig]
The configuration of the image signal writing transistor TSig is same as that of image signal writing transistor TSig described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted. It is to be noted, however, that, although the image signal writing transistor TSig is connected at the one of the source/drain regions thereof to a data line DTL, not only the image signal VSig and the correction voltage VCor for controlling the luminance of the light emitting section ELP but also the voltage VOfs-H and the voltage VOfs-L for initializing the gate electrode of the driving transistor TDrv are supplied from the image signal outputting circuit 102. In this regard, the operation of the image signal writing transistor TSig is different from that of the image signal writing transistor TSig described hereinabove in connection with the 5Tr/1C driving circuit. It is to be noted that, from the image signal outputting circuit 102, a signal or voltage (for example, a signal for precharge driving) other than VSig, the correction voltage VCor and VOfs-H/VOfs-L may be supplied to the one of the source/drain regions of the image signal writing transistor TSig. Although the value of the voltage VOfs-H and the voltage VOfs-L is not limited, for example, VOfs-H=approximately 30 volts and VOfs-L=approximately 0 volts can be given as an example.
[Relationship Between Values of CEL and C1]
As hereinafter described, in the 3Tr/1C driving circuit, it is necessary to vary the potential of the second node ND2 utilizing the data line DTL. The foregoing description of the 5Tr/1C driving circuit and the 4Tr/1C driving circuit is given assuming that the capacitance value cEL of the parasitic capacitance CEL of the light emitting section ELP has a sufficiently high value in comparison with the capacitance value of the capacitor section C1 and the value cgs of the parasitic capacitance between the gate electrode and the source electrode of the driving transistor TDrv and without taking the variation of the potential of the source region of the driving transistor TDrv (second node ND2) based on the variation amount of the potential of the gate electrode of the driving transistor TDrv into consideration (this similarly applies also to a 2Tr/1C driving circuit hereinafter described). On the other hand, in the 3Tr/1C driving circuit, the value capacitor section C1 is set to a value higher than those of the other driving circuits upon designing (for example, the value c1 is set to approximately 1⁄4 to 1⁄3 of the value cEL). Accordingly, the degree of the potential variation of the second node ND2 which is caused by a potential variation of the first node ND1 is higher than that of the other driving circuits. Therefore, the description of the 3Tr/1C driving circuit is given taking the potential variation of the second node ND2 caused by the potential variation of the first node ND1 into consideration. It is to be noted that also the timing chart of driving shown in the drawings is given taking the potential variation of the second node ND2 caused by the potential variation of the first node ND1 into consideration.
[Light Emitting Section ELP]
The configuration of the light emitting section ELP is same as that of the light emitting section ELP described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
In the following, operation of the 3Tr/1C driving circuit is described.
[Period TP (3)−1] (Refer to (A) of FIG. 15)
Operation within this [period TP (3)−1] is operation of, for example, in a preceding display frame and is substantially same as that within the [period TP (5)−1] described hereinabove in connection with the 5Tr/1C driving circuit.
The [period TP (3)0] to the [period TP (3)4] shown in FIG. 14 are a period corresponding to the [period TP (5)0] to the [period TP (5)4] shown in FIG. 3 and is an operation period till a point of time immediately before a next writing process is carried out. Similarly as in the 5Tr/1C driving circuit, within the [period TP (3)0] to the [period TP (3)4], the (n, m)th organic EL element 10 is in a no-light emitting state. However, the operation of the 3Tr/1C driving circuit is different from the operation of the 5Tr/1C driving circuit in that not only the [period TP (3)5] to the [period TP (3)6] but also the [period TP (5)1] to the [period TP (3)4] are included in the mth horizontal scanning period. It is to be noted that, for the convenience of description, it is described that the start timing of the [period TP (3)1] and the end timing the [period TP (3)6] coincide with the start timing and the end timing of the mth horizontal scanning period, respectively.
In the following, each of the [period TP (3)0] to the [period TP (3)4] is described. It is to be noted that, similarly as in the description of the 5Tr/1C driving circuit, the length of each of the periods of the [period TP (3)1] to [period TP (3)4] may be set suitably in accordance with the design of the organic EL display apparatus.
[Period TP (3)0] (Refer to (B) of FIG. 15)
Operation within this [period TP (3)0] is operation, for example, in a current display frame from a preceding display frame and is substantially same operation as that within the [period TP (5)0] described hereinabove in connection with the 5Tr/1C driving circuit.
[Period TP (3)1] (Refer to (C) of FIG. 15)
Then, the mth horizontal scanning period in a current display frame is started. Upon starting of the [period TP (3)1], the potential of the data line DTL is set to the voltage VOfs-H for initializing the gate electrode of the driving transistor TDrv based on operation of the image signal outputting circuit 102 and then the scanning line SCL is placed into a high level state based on operation of the scanning circuit 101 to place the image signal writing transistor TSig into an on state. As a result, the potential of the first node ND1 becomes VOfs-H. Since the value c1 of the capacitor section C1 is set to a value higher than that of the other driving circuits upon designing as described above, the potential of the source region (potential of the second node ND2) rises. Then, since the potential difference across the light emitting section ELP exceeds the threshold voltage Vth-EL the light emitting section ELP is placed into a conducting state. However, the potential of the source region of the driving transistor TDrv drops immediately to (Vth-EL+VCor). It is to be noted that, while the light emitting section ELP can emit light in the course of the potential drop, such light emission occurs in an instant and does not make a problem in practical use. Meanwhile, the gate electrode of the driving transistor TDrv maintains the voltage Vofs-H.
[Period TP (3)2] (Refer to (D) of FIG. 15)
Thereafter, the potential of the data line DTL is changed over from the voltage VOfs-L for initializing the gate electrode of the driving transistor TDrv to the voltage VOfs-L based on operation of the image signal outputting circuit 102, whereupon the potential of the first node ND1 changes to VOfs-L. Then, as the potential of the first node ND1 drops, also the potential of the second node ND2 drops. In particular, charge based on the variation amount (VOfs-L−VOfs-H) of the potential of the gate electrode of the driving transistor TDrv is distributed to the capacitor section C1, the parasitic capacitance CEL of the light emitting section ELP and the parasitic capacitance between the gate electrode and the source electrode of the driving transistor TDrv. However, as a prerequisite of operation within the [period TP (3)3] hereinafter described, it is necessary for the potential of the second node ND2 to be lower than VOfs-L−Vth at the end timing of the [period TP (3)2]. The value of VOfs-H and so forth are set so as to satisfy this condition. In particular, by the processes described above, the potential difference between the gate electrode and the source region of the driving transistor TDrv becomes higher than Vth, and the driving transistor TDrv is placed into an on state.
[Period TP (3)3] (Refer to (A) of FIG. 16)
Then, a threshold voltage cancellation process is carried out. In particular, while the on state of the image signal writing transistor TSig is maintained, the light emission controlling transistor control line CLEL—C is placed into a high level state based on operation of the light emission controlling transistor control circuit 103 to place the light emission controlling transistor TEL—C into an on state. As a result, although the potential of the first node ND1 does not vary (VOfs-L=0 volts are maintained), the potential of the second node ND2 varies from the potential of the first node ND1 toward a potential of the difference of the threshold voltage Vth of the driving transistor TDrv from the potential of the first node ND1. In other words, the potential of the second node ND2 in the floating state rises. Then, if the potential difference between the gate electrode and the source region of the driving transistor TDrv reaches Vth, then the driving transistor TDrv is placed into an off state. In particular, the potential of the second node ND2 in the floating state varies toward (VOfs-L−Vth=−3 volts) and finally becomes (VOfs-L−Vth). Here, if the expression (2) given hereinabove is assured, or in other words, if the potential is selected and determined so as to satisfy the expression (2), then the light emitting section ELP does not emit light at all.
Within this [period TP (3)3], the potential of the second node ND2 finally becomes, for example, (VOfs-L−Vth) In particular, the potential of the second node ND2 depends only upon the threshold voltage Vth of the driving transistor TDrv and the voltage VOfs-L for initializing the gate electrode of the driving transistor TDrv. Further, the potential of the second node ND2 is independent of the threshold voltage Vth-EL of the light emitting section ELP.
[Period TP (3)4] (Refer to (B) of FIG. 16)
Thereafter, while the on state of the image signal writing transistor TSig is maintained, the light emission controlling transistor control line CLEL—C is placed into a low level state based on operation of the light emission controlling transistor control circuit 103 to place the light emission controlling transistor TEL—C into an off state. As a result, the potential of the first node ND1 does not vary (VOfs-L=0 volts are maintained), and also the potential of the second node ND2 in the floating state does not vary and maintains (VOfs-L−Vth=−3 volts).
Now, periods from the [period TP (3)5] to the [period TP (3)7] are described. Operation in the periods is substantially same operation as that in the [period TP (5)5] to the [period TP (5)7] described hereinabove in connection with the 5Tr/1C driving circuit.
[Period TP (3)5] (Refer to (C) of FIG. 16)
Then, correction (mobility correction process) of the potential of the source region (second node ND2) of the driving transistor TDrv based on the magnitude of the mobility μ of the driving transistor TDrv is carried out. In particular, operation same as that in the [period TP (5)5] described hereinabove in connection with the 5Tr/1C driving circuit may be carried out. It is to be noted that the predetermined time for executing the mobility correction process (total time (tCor) within the [period TP (3)5] may be determined as a design value in advance upon designing of the organic EL display apparatus.
[Period TP (3)6] (Refer to (D) of FIG. 16)
Thereafter, a writing process for the driving transistor TDrv is executed. In particular, the potential of the data line DTL is changed over from the correction voltage VCor to the image signal VSig for controlling the luminance of the light emitting section ELP based on operation of the image signal outputting circuit 102 while the on state of the image signal writing transistor TSig and the light emission controlling transistor TEL—C is maintained. As a result, the potential of the first node ND1 rises to VSig and the potential of the second node ND2 rises almost to (VOfs−Vth+ΔVCor+ΔVSig). Consequently, similarly as in the description given hereinabove in connection with the 5Tr/1C driving circuit, the value described hereinabove in connection with the expression (4) can be obtained as the potential difference between the first node ND1 and the second node ND2, that is, as the potential difference Vgs between the gate electrode and the source region of the driving transistor TDrv.
In particular, also in the 3Tr/1C driving circuit, Vgs obtained in the writing process into the driving transistor TDrv relies only upon the image signal Vng for controlling the luminance of the light emitting section ELP, the threshold voltage Vth of the driving transistor TDrv the voltage VOfs-L for initializing the gate electrode of the driving transistor TDrv and the correction voltage VCor. Moreover, Vgs is independent of the threshold voltage Vth-EL of the light emitting section ELP.
[Period TP (3)7] (Refer to (E) of FIG. 16)
By the foregoing operation, the threshold voltage cancellation process, writing process and mobility correction process are completed. Then, a process same as that in the [period TP (5)7] described hereinabove in connection with the 5Tr/1C driving circuit is carried out, and the potential of the second node ND2 rises and exceeds (Vth-EL+VCat). Therefore, the light emitting section ELP starts emission of light. At this time, since the current flowing through the light emitting section ELP can be obtained using the expression (5) described hereinabove, the drain current Ids flowing through the light emitting section ELP does not rely upon any of the threshold voltage Vth-EL of the light emitting section ELP and the threshold voltage Vth of the driving transistor TDrv. In other words, the light emission amount (luminance) of the light emitting section ELP is not influenced by any of the threshold voltage Vth-EL of the light emitting section ELP and the threshold voltage Vth of the driving transistor TDrv. In addition, occurrence of a dispersion in drain current Ids arising from a dispersion in mobility μ of the driving transistor TDrv can be suppressed.
Then, the light emitting state of the light emitting section ELP continues till the (m+m′−1)th horizontal scanning period. This point of time corresponds to the end of the [period IP (4)−1].
By the operation described above, the light emitting operation of the organic EL element 10 [(n, m)th sub pixel (organic EL element 10)] is completed.
Embodiment 4
The embodiment 4 is a modification to the embodiment 1. In the embodiment 4, the driving circuit is formed from a 2Tr/1C driving circuit. An equivalent circuit diagram of the 2Tr/1C driving circuit is shown in FIG. 17, a conceptual view is shown in FIG. 18, a timing chart of driving is schematically shown in FIG. 19, and on/off states and so forth of the transistors are shown in (A) to (C) of FIG. 20 and (A) to (C) of FIG. 21.
In this 2Tr/1C driving circuit, three transistors of the first node initializing transistor TND1, light emission controlling transistor TEL—C and second node initializing transistor TND2 are omitted from the 5Tr/1C driving circuit described hereinabove. In particular, the present 2Tr/1C driving circuit is composed of two transistors of an image signal writing transistor TSig and a driving transistor TDrv and further includes one capacitor section Ci.
[Driving Transistor TDrv]
The configuration of the driving transistor TDrv is same as that of the driving transistor TDrv described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted. However, the driving transistor TDrv is connected at the drain electrode thereof to the current supplying section 100. It is to be noted that, from the current supplying section 100, a voltage VCC-H for controlling the emission of light of the light emitting section ELP and a voltage VCC-L for controlling the potential of the source region of the driving transistor TDrv are supplied. Here, while

    VCC-H=20 volts
    VCC-L=−10 volts

can be listed as values of the voltages VCC-H and VCC-L, they are not limited to the specific values.



[Image Signal Writing Transistor TSig]
The configuration of the image signal writing transistor TSig is same as that of image signal writing transistor TSig described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
[Light Emitting Section ELP]
The configuration of the light emitting section ELP is same as that of the light emitting section ELP described hereinabove in connection with the 5Tr/1C driving circuit, and therefore, detailed description thereof is omitted.
In the following, operation of the 2Tr/1C driving circuit is described.
[Period TP (2)−1] (Refer to (A) of FIG. 20)
Operation within this [period TP (2)−1] is operation of, for example, in a preceding display frame and is substantially same as that within the [period TP (5)−1] described hereinabove in connection with the 5Tr/1C driving circuit.
The [period TP (2)0] to the [period TP (2)2] shown in FIG. 19 are a period corresponding to the [period TP (5)0] to the [period TP (5)4] shown in FIG. 3 and is an operation period till a point of time immediately before a next writing process is carried out. In addition, similarly as in the 5Tr/1C driving circuit, within the [period TP (2)0] to the [period TP (2)2], the (n, m)th organic EL element 10 is in a no-light emitting state. However, the operation of the 2Tr/1C driving circuit is different from the operation of the 5Tr/1C driving circuit in that not only the [period TP (2)3] but also the [period TP (2)1] to the [period TP (2)2] are included in the mth horizontal scanning period. It is to be noted that, for the convenience of description, it is described that the start timing of the [period TP (2)1] and the end timing the [period TP (2)3] coincide with the start timing and the end timing of the mth horizontal scanning period, respectively.
In the following, each of periods of the [period TP (2)0] to the [period TP (2)2] is described. It is to be noted that, similarly as in the description of the 5Tr/1C driving circuit, the length of each of the periods of the [period TP (2)1] to [period TP (2)3] may be set suitably in accordance with the design of the organic EL display apparatus.
[Period TP (2)0] (Refer to (B) of FIG. 20)
Operation within this [period TP (2)0] is operation of, for example, in a current display frame from a preceding display frame. In particular, the [period TP (2)0] is a period from the (m+m′)th horizontal scanning period in the preceding display frame to the (m−1)th horizontal scanning period in the current display frame. Moreover, within this [period TP (2)0], the (n, m)th organic EL element 10 is in a no-light emitting state. Here, at a point of time of transition from the [period TP (2)−1] to the [period TP (2)0], the potential to be supplied from the current supplying section 100 is changed over from VCC-H to the voltage VCC-L. As a result, the potential of the second node ND2 (source region of the driving transistor TDrv or anode electrode of the light emitting section ELP) drops to VCC-L, and the light emitting section ELP is placed into a no-light emitting state. Further, also the potential of the first node ND1 in the floating state (gate electrode of the driving transistor TDrv) drops in such a manner as to follow up the potential drop of the second node ND2.
[Period TP (2)1] (Refer to (C) of FIG. 20)
Then, the mth horizontal scanning period in the current display frame is started. Upon starting of the [period TP (2)1], the scanning line SCL is set to the high level based on operation of the scanning circuit 101 to place the image signal writing transistor TSig into an on state. As a result, the potential of the first node ND1 becomes VOfs (for example, 0 volts). The potential of the second node ND2 maintains VCC-L (for example, −10 volts).
By the processes described above, the potential difference between the gate electrode and the source region of the driving transistor TDrv becomes greater than Vth, and the driving transistor TDrv is placed into an on state.
[Period TP (2)2] (Refer to (D) of FIG. 20)
Subsequently, a threshold voltage cancellation process is carried out. In particular, while the on state of the image signal writing transistor TSig is maintained, the voltage to be supplied from the current supplying section 100 is changed over from VCC-L to the voltage VCC-H. As a result, although the potential of the first node ND1 does not vary (VOfs=0 volts are maintained), the potential of the second node ND2 varies from the potential of the first node ND1 toward a potential of the difference of the threshold voltage Vth of the driving transistor TDrv from the potential of the first node ND1. In other words, the potential of the second node ND2 in the floating state rises. Then, if the potential difference between the gate electrode and the source region of the driving transistor TDrv reaches Vth, then the driving transistor TDrv is placed into an off state. In particular, the potential of the second node ND2 in the floating state varies toward (VOfs−Vth=−3 volts) and finally becomes (VOfs−Vth). Here, if the expression (2) given hereinabove is assured, or in other words, if the potential is selected and determined so as to satisfy the expression (2), then the light emitting section ELP does not emit light at all.
Within this [period TP (2)2], the potential of the second node ND2 finally becomes, for example, (VOfs−Vth) In particular, the potential of the second node ND2 depends only upon the threshold voltage Vth of the driving transistor TDrv and the voltage VOfs for initializing the gate electrode of the driving transistor TDrv. Further, the potential of the second node ND2 is independent of the threshold voltage Vth-EL of the light emitting section ELP.
[Period TP (2)3] (Refer to (A) of FIG. 21)
Then, correction (mobility correction process) of the potential of the source region (second node ND2) of the driving transistor TDrv based on the magnitude of the mobility μ of the driving transistor TDrv is carried out. In particular, operation same as that in the [period TP (5)5] described hereinabove in connection with the 5Tr/1C driving circuit may be carried out. It is to be noted that the predetermined time for executing the mobility correction process (total time (tCor) within the [period TP (2)3] may be determined as a design value in advance upon designing of the organic EL display apparatus.
Also within this [period TP (2)3], where the value of the mobility μ of the driving transistor TDrv is high, the rise amount ΔVCor of the potential in the source region of the driving transistor TDrv is great, but where the value of the mobility μ of the driving transistor TDrv is low, the rise amount ΔVCor of the potential in the source region of the driving transistor TDrv is small.
[Period TP (2)4] (Refer to (B) of FIG. 21)
Thereafter, a writing process for the driving transistor TDrv is executed. In particular, the potential of the data line DTL is changed over from the correction voltage VCor to the image signal VSig for controlling the luminance of the light emitting section ELP based on operation of the image signal outputting circuit 102 while the on state of the image signal writing transistor TSig is maintained. As a result, the potential of the first node ND1 rises to VSig and the potential of the second node ND2 rises almost to (VOfs−Vth+VCor+ΔVSig). Consequently, similarly as in the description given hereinabove in connection with the 5Tr/1C driving circuit, the value described hereinabove in connection with the expression (4) can be obtained as the potential difference between the first node ND1 and the second node ND2, that is, as the potential difference Vgs between the gate electrode and the source region of the driving transistor TDrv.
In particular, also in the 2Tr/1C driving circuit, Vgs obtained in the writing process into the driving transistor TDrv relies only upon the image signal VSig for controlling the luminance of the light emitting section ELP, the threshold voltage Vth of the driving transistor TDrv, the voltage VOfs-L for initializing the gate electrode of the driving transistor TDrv, and the correction voltage VCor. In addition, Vg, is independent of the threshold voltage Vth-EL of the light emitting section ELP.
[Period TP (2)5] (Refer to (C) of FIG. 21)
By the foregoing operation, the threshold voltage cancellation process, writing process and mobility correction process are completed. Then, a process same as that in the [period TP (5)7] described hereinabove in connection with the 5Tr/1C driving circuit is carried out, and the potential of the second node ND2 rises and exceeds (Vth-EL+VCat). Therefore, the light emitting section ELP starts emission of light. At this time, since the current flowing through the light emitting section ELP can be obtained using the expression (5) given hereinabove, the drain current Ids flowing through the light emitting section ELP does not rely upon any of the threshold voltage Vth-EL of the light emitting section ELP and the threshold voltage Vth of the driving transistor TDrv. In other words, the light emission amount (luminance) of the light emitting section ELP is not influenced by any of the threshold voltage Vth-EL of the light emitting section ELP and the threshold voltage Vth of the driving transistor TDrv. In addition, occurrence of a dispersion in drain current Ids arising from a dispersion in mobility μ of the driving transistor TDrv can be suppressed.
Then, the light emitting state of the light emitting section ELP continues till the (m+m′−1)th horizontal scanning period. This point of time corresponds to the end of the [period TP (2)−1].
By the operation described above, the light emitting operation of the organic EL element 10 [(n, m)th sub pixel (organic EL element 10)] is completed.
While the present invention has been described based on the preferred embodiments thereof, the present invention is not limited to the embodiments. The configuration and structure of the various components of the organic EL display apparatus described in connection with the embodiments are illustrative and can be altered suitably. While, in the embodiments, the correction voltage VCor is varied smoothly in principle by variation of the image signal VSig, according to circumstances, the correction voltage VCor may be varied stepwise. Further, in the 5Tr/1C driving circuit, 4Tr/1C driving circuit and 3Tr/1C driving circuit, the light emission controlling transistor TEL—C may be placed into an on state immediately before the mobility correction process is started to set the potential of the drain region of the driving transistor TDrv to the voltage VCC of the current supplying section 100. Further, the value of the correction voltage VCor may be a fixed value irrespective of the value of the image signal VSig.

## Claims

1. A driving method for an organic electroluminescence light emitting section which uses pixel circuit including a driving transistor and a writing transistor, the driving transistor being connected between a current supplying section and a light emitting section, the writing transistor being connected to a data line, the driving method comprising:
applying a correction voltage to a gate of the driving transistor from the data line through the writing transistor;
applying an image signal to the gate of the driving transistor from the data line through the writing transistor, said applying the correction voltage to the gate and applying the image signal to the gate occurring separately and cumulatively contributing to a potential difference between the gate of the driving transistor and the source of the driving transistor; and
supplying current from the current supplying section to the light emitting section through the driving transistor corresponding to the value of the potential difference between the gate of the driving transistor and the source of the driving transistor,
wherein the value of the correction voltage is a value which depends upon the image signal applied from the data line.

2. A display apparatus comprising:
an organic electroluminescence light emitting section; and
a pixel circuit including
a driving transistor, and
a writing transistor,
the driving transistor being connected between a current supplying section and a light emitting section, the writing transistor being connected to a data line, wherein
a correction voltage is applied to a gate of the driving transistor from the data line through the writing transistor,
an image signal is applied to the gate of the driving transistor from the data line through the writing transistor, said appling the correction voltage to the gate and applying the image signal to the gate occurring separately and cumulatively contributing to a potential difference between the gate of the driving transistor and the source of the driving transistor,
current is supplied from the current supplying section to the light emitting section through the driving transistor corresponding to the value of the potential difference between the gate of the driving transistor and the source of the driving transistor, and
the value of the correction voltage is a value that depends upon the image signal applied from the data line.

3. An electronic device comprising the display apparatus according to claim 2.

4. A display apparatus comprising:
an organic electroluminescence light emitting section; and
a pixel circuit including
a driving transistor,
a writing transistor, and
a storage capacitor,
the driving transistor being connected between a current supplying section and a light emitting section, the writing transistor being connected to a data line,
the storage capacitor being connected between a gate of the driving transistor and a current terminal of the driving transistor,
wherein
a drive transistor characteristic correction is imparted to the storage capacitor,
an image signal is imparted to the storage capacitor from the data line through the writing transistor,
said imparting the drive transistor characteristic correction to the storage capacitor and imparting the image signal to the storage capacitor occurring separately and cumulatively contributing to a potential difference between the gate of the driving transistor and the current terminal of the driving transistor, and
current is supplied from the current supplying section to the light emitting section through the driving transistor corresponding to the value of the potential difference between the gate of the driving transistor and the current terminal of the driving transistor.

5. An electronic device comprising the display apparatus according to claim 4.