# Patent

## Title
Broadband and wavelength-selective bidirectional 3-way optical splitter

## Abstract

Embodiments of a bidirectional 3-way optical splitter are described. This bidirectional 3-way optical splitter includes an optical splitter having: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes.

## Background
GOVERNMENT LICENSE RIGHTS
This invention was made with United States Government support under Contract No. NBCH3039002 awarded by the Defense Advanced Research Projects Administration. The United States Government has certain rights in the invention.


CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to U.S. patent application Ser. No. 11/962,415 entitled “Optical-Signal-Path Routing in a Multi-Chip System,” filed Dec. 21, 2007; U.S. patent application Ser. No. “11/863,815”, entitled “Wavelength-Division Multiplexing for Use in Multi-Chip Systems,” filed Sep. 28, 2007; U.S. patent application Ser. No. “11/853,316”, entitled “Multi-Chip Systems with Optical Bypass,” filed Sep. 11, 2007; U.S. patent application Ser. No. 11/728,845, entitled “Multi-Chip Systems Using On-Chip Photonics,” filed Mar. 26, 2007; U.S. patent application Ser. No. 11/728,844, entitled “Low-Latency Switch Using Optical and Electrical Proximity Communication,” filed Mar. 26, 2007; U.S. patent application Ser. No. 11/728,843, entitled “Transparent Switch Using Optical and Electrical Proximity Communication,” filed Mar. 26, 2007; U.S. patent application Ser. No. 11/515,085, entitled “Resonator System for Optical Proximity Communication,” filed Aug. 31, 2006; U.S. patent application Ser. No. 11/515,207, entitled “Optical Imaging Device for Optical Proximity Communication,” filed Aug. 31, 2006; U.S. patent application Ser. No. 11/165,996, entitled “Proximity Active Connector and Cable,” filed on Jun. 24, 2005; U.S. patent application Ser. No. 11/165,917, entitled “Integrated Proximity-to-Optical Transceiver Chip,” filed on Jun. 24, 2005; and U.S. patent application Ser. No. 11/084,656, entitled “Method and Apparatus for Optimizing Computer Program Performance Using Steered Execution,” filed on Mar. 18, 2005, the contents of each of which are herein incorporated by reference.
BACKGROUND
1. Field of the Invention
The present invention relates to techniques for communicating optical signals. More specifically, the present invention relates to a bidirectional, 3-way optical splitter, which may be used in a multi-chip system that includes semiconductor dies that communicate signals using electrical proximity communication and/or optical communication.
2. Related Art
Advances in semiconductor technology have led to significant increases in microprocessor performance. For example, the clock frequency of a typical microprocessor increased from 16 MHz in 1985 to 3600 MHz by 2005, an improvement of 230 times, which represents an annual growth rate of nearly 30%. These performance gains have allowed computers to perform increasingly complicated operations across a wide variety of applications.
Unfortunately, several issues are beginning to constrain further increases in the clock frequency. In particular, the latency of global on-chip wires is increasing as technological trends reduce their thickness but not their length. In contrast, many local wires do not suffer from this delay penalty because their lengths shrink along with their thickness.
Moreover, as integration densities and clock frequencies continue to increase, the power consumption of high-performance microprocessors also increases. Consequently, many existing microprocessors consume over 100 W of power, which strains the capabilities of air cooling systems. In fact, many microprocessors have become power-limited, which means they could be operated at higher clock frequencies at the cost of significant increases in power consumption, and thus, in required cooling.
These design constraints have led designers to change microprocessor designs. In particular, many microprocessors now include multiple processor cores. These multiple processor cores keep computation and associated communication operations local, which reduces global delays in critical paths. Additionally, individual processor cores can be selectively enabled, thereby allowing unused processor cores to be put into a sleep mode to conserve power and then awakened when they are needed. Moreover, the use of smaller processor cores with shared logical blocks reduces the cost of developing and debugging microprocessors.
Furthermore, many multiple-core microprocessors support chip multi-threading (CMT). This technique helps address the increasing gap between microprocessor performance and the latency associated with fetching instructions and data from main memory, which has grown from a few clock cycles to hundreds of clock cycles over the past two decades. This gap often limits system performance because the microprocessor spends an increasing amount of time waiting for memory accesses instead of executing code. In a microprocessor that uses CMT, a thread can be quickly swapped in and out of execution. This rapid thread switching improves overall system throughput because instead of waiting for a memory request to return when the current thread accesses memory, the microprocessor can put the current thread to sleep and reactivate another thread. Consequently, utilization and throughput in such multi-threaded microprocessors is much higher than in single-threaded microprocessors.
However, microprocessors that include multiple cores and support multiple threads executing on each core have significantly higher communication requirements than single-core, single-threaded microprocessors. In particular, these microprocessors use high-bandwidth communication to maintain coherence; pass messages; and/or perform simultaneous memory accesses. Moreover, as microprocessor throughput continues to increase, corresponding bandwidth requirements are expected to increase to terabits-per-second and beyond. Given the aforementioned latency problems, it may be difficult to meet these requirements using conventional conductive wires.
Optical communication can provide high-bandwidth and low-latency communication, for example, via on-chip optical signal paths (such as waveguides). Unfortunately, in multi-chip systems, data conflicts on optical signal paths can occur at boundaries between chips. One solution to this challenge is to utilize a different optical routing or layout in different chips in the multi-chip system. However, this can significantly increase the number of different types of chips in such a system, with a commensurate impact on the complexity and cost of the multi-chip system.
Hence, what is needed is a method and an apparatus which provide improved communication bandwidth without the problems listed above.
SUMMARY
One embodiment of the present invention provides a bidirectional 3-way optical splitter, which includes an optical splitter having: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes.
In some embodiments, the power ratios of each of the external output optical signals to the external input optical signal are approximately equal.
In some embodiments, the optical splitter includes a 2×2 optical splitter having four internal nodes (where a first internal node of the 2×2 optical splitter is optically coupled to the first external node) and a 2×1 optical coupler having another internal node. This 2×1 optical coupler may be optically coupled to a second internal node and a fourth internal node of the 2×2 optical splitter, and the other internal node may be optically coupled to the second external node. Moreover, the optical splitter may include another 2×2 optical splitter having four internal nodes, where a first internal node of the other 2×2 optical splitter may be optically coupled to the third internal node of the 2×2 optical splitter, and a third internal node of the other 2×2 optical splitter may be optically coupled to the third external node. Additionally, the optical splitter may include another 2×1 optical coupler having an additional internal node, where the other 2×1 optical coupler may be optically coupled to a second internal node and a fourth internal node of the other 2×2 optical splitter, and the additional internal node may be optically coupled to the fourth external node.
Note that in the one mode of operation, the given 2×2 optical splitter may be configured: to receive an internal input optical signal on the first internal node of the given 2×2 optical splitter; to provide an internal output optical signal on the fourth internal node of the given 2×2 optical splitter; and to provide another internal output optical signal on the third internal node of the given 2×2 optical splitter. Moreover, in the other mode of operation the given 2×2 optical splitter may be configured: to receive the internal input optical signal on the third internal node of the given 2×2 optical splitter; to provide the internal output optical signal on the second internal node of the given 2×2 optical splitter; and to provide the other internal output optical signal on the first internal node of the given 2×2 optical splitter.
In some embodiments, the internal input optical signal for the given 2×2 optical splitter is split into the internal output optical signal and the other internal output optical signal with a given power ratio of X/Y between the internal output optical signal and the other internal output optical signal.
In some embodiments, the internal input optical signal for the 2×2 optical splitter is split into the internal output optical signal and the other internal output optical signal with a power ratio of 1/3 between the internal output optical signal and the other internal output optical signal. Moreover, for the other 2×2 optical splitter, the internal input optical signal may be split into the internal output optical signal and the other internal output optical signal with a power ratio of 1/1 between the internal output optical signal and the other internal output optical signal.
In some embodiments, the external output optical signals include the same range of wavelengths as the external input optical signal.
In other embodiments, the optical splitter includes a 2×2 optical switch having four internal nodes, where a first internal node of the 2×2 optical switch is optically coupled to the first external node, and a second internal node of the 2×2 optical switch is optically coupled to the third external node. Moreover, the optical splitter may include a 2×1 unidirectional optical coupler having an internal input node and two internal output nodes, where the internal input node of the 2×1 unidirectional optical coupler may be optically coupled to a third internal node of the 2×2 optical switch, and a first internal output node of the 2×1 unidirectional optical coupler may be optically coupled to a fourth internal node of the 2×2 optical switch. Additionally, the optical splitter may include another 2×1 unidirectional optical coupler having an internal input node and two internal output nodes. Note that: the internal input node of the other 2×1 unidirectional optical coupler may be optically coupled to a second internal output node of the 2×1 unidirectional optical coupler; a first internal output node of the other 2×1 unidirectional optical coupler may be optically coupled to the second external node; and a second internal output node of the other 2×1 unidirectional optical coupler may be optically coupled to the fourth external node.
Furthermore, the optical splitter may include control logic coupled to the 2×2 optical switch, where in the one mode of operation the control logic may configure the 2×2 optical switch to optically couple the first internal node to the third internal node and the second internal node to the fourth internal node. Additionally, in the other mode of operation the control logic may configure the 2×2 optical switch to optically couple the first internal node to the fourth internal node and the second internal node to the third internal node.
In some embodiments, for a given 2×1 unidirectional optical coupler, an internal input optical signal received at the internal input node is split into an internal output optical signal on the second output node and another internal output optical signal on the first output node with a given power ratio of X/Y between the internal output optical signal and the other internal output optical signal.
In some embodiments, for the 2×1 unidirectional optical splitter, an internal input optical signal received at the internal input node is split into an internal output optical signal on the second output node and another internal output optical signal on the first output node with a power ratio of 1/3 between the internal output optical signal and the other internal output optical signal. Moreover, for the other 2×1 unidirectional optical splitter, an internal input optical signal received at the internal input node may be split into an internal output optical signal on the second output node and another internal output optical signal on the first output node with a power ratio of 1/1 between the internal output optical signal and the other internal output optical signal.
In other embodiments, the optical splitter includes: an interferometer having a first internal node, a first arm optically coupled to the first internal node, a second arm optically coupled to the first internal node, and a second internal node optically coupled to the first arm and the second arm. Note that the first internal node may be optically coupled to the first external node and the second internal node may be optically coupled to the third external node. Moreover, an internal input optical signal on a given internal node, which can be the first internal node or the second internal node, may be split between the first arm and the second arm, and optical signals on the first arm and the second arm may be combined and provided on the other internal node than the given internal node. Additionally, the optical splitter may include an add/drop filter optically coupled to the first arm, where an output from the add/drop filter may be optically coupled to the second external node, and the add/drop filter may be configured to selectively couple wavelengths from the first arm to the second external node. Furthermore, the optical splitter may include another add/drop filter optically coupled to the second arm, where an output from the other add/drop filter may be optically coupled to the fourth external node, and the other add/drop filter may be configured to selectively couple wavelengths from the second arm to the fourth external node.
In some embodiments, a given add/drop filter includes a ring resonator. Moreover, the interferometer may include a Mach-Zehnder interferometer.
In some embodiments, the internal input optical signal is split approximately equally between the first arm and the second arm.
In some embodiments, the optical splitter includes an optical waveguide optically coupled to the add/drop filter, where one end of the optical waveguide is optically coupled to a fifth external node and another end of the optical waveguide is optically coupled to the second external node. Note that, in a third mode of operation, the one end of the optical waveguide may be configured to provide another external output optical signal and the other end of the optical waveguide may be configured to receive another external input optical signal.
Moreover, the optical splitter may include another optical waveguide optically coupled to the other add/drop filter, where one end of the other optical waveguide may be optically coupled to the fourth external node and another end of the other optical waveguide may be optically coupled to a sixth external node. Note that, in a fourth mode of operation, the one end of the other optical waveguide may be configured to receive an additional external input optical signal and the other end of the other optical waveguide may be configured to provide an additional external output optical signal.
In some embodiments, at least one of the add/drop filter and the other add/drop filter include two or more ring resonators which are optically coupled in series. Moreover, the optical splitter may include an additional optical waveguide optically coupled to the add/drop filter, wherein one end of the additional optical waveguide may be optically coupled to the fourth external node and another end of the additional optical waveguide may be optically coupled to the sixth external node of the optical splitter. Note that, in a fifth mode of operation, the one end of the additional optical waveguide may be configured to provide another external output optical signal and, in a sixth mode of operation, the one end of the additional optical waveguide may configured to receive another external input optical signal. Additionally, in the fifth mode of operation, the other end of the additional optical waveguide may be configured to receive the other external input optical signal and, in the sixth mode of operation, the other end of the additional optical waveguide may be configured to provide the other external output optical signal.
In some embodiments, the optical splitter includes yet another optical waveguide optically coupled to the other add/drop filter, where one end of this other optical waveguide may be optically coupled to the fifth external node of the optical splitter and another end of this other optical waveguide may be optically coupled to the second external node. Note that, in a seventh mode of operation, the one end of this other optical waveguide may be configured to receive an additional external input optical signal and, in an eighth mode of operation, the one end of this other optical waveguide may be configured to provide an additional external output optical signal. Moreover, in the seventh mode of operation, the other end of this other optical waveguide may be configured to provide the additional external output optical signal and, in the eighth mode of operation, the other end of this other optical waveguide may be configured to receive the additional external input optical signal.
Another embodiment of the present invention provides an array of chip modules that include one or more instance of the 3-way, bidirectional optical splitter.
Another embodiment of the present invention provides a computer system that includes the array.
Another embodiment of the present invention provides a method for 3-way splitting an optical signal, which may be performed by an optical splitter. During operation, the optical splitter receives the optical signal on a given node in a first node and a fourth node of the optical splitter. Next, the optical splitter provides output optical signals on three other nodes of the optical splitter, where the three other nodes include a second node, a third node, and the other of the given node in the first node and the fourth node. Note that the capability to receive the optical signal on either the first node or the fourth node provides bidirectional splitting.



BRIEF DESCRIPTION OF THE FIGURES
FIG. 1A is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 1B is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a device that includes proximity connectors in accordance with an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a system that includes semiconductor dies that communicate using proximity communication in accordance with an embodiment of the present invention.
FIG. 4A is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 4B is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 5 is a block diagram illustrating a conversion element in accordance with an embodiment of the present invention.
FIG. 6A is a block diagram illustrating a device that includes on-chip optical communication in accordance with an embodiment of the present invention.
FIG. 6B is a block diagram illustrating a device that includes on-chip optical communication in accordance with an embodiment of the present invention.
FIG. 7 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 8 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 9 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 10 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 11 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 12 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 13 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 14 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 15 is a block diagram illustrating an arrayed-waveguide grating in accordance with an embodiment of the present invention.
FIG. 16 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 17 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 18 is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 19A is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 19B is a block diagram illustrating a multi-chip module in accordance with an embodiment of the present invention.
FIG. 20A is a block diagram illustrating an existing optical splitter.
FIG. 20B is a block diagram illustrating an existing optical splitter.
FIG. 21A is a block diagram illustrating an optical splitter in accordance with an embodiment of the present invention.
FIG. 21B is a block diagram illustrating an optical splitter in accordance with an embodiment of the present invention.
FIG. 22A is a block diagram illustrating an optical switch in accordance with an embodiment of the present invention.
FIG. 22B is a block diagram illustrating an optical splitter in accordance with an embodiment of the present invention.
FIG. 23 is a block diagram illustrating a wavelength-selective broadcast network in accordance with an embodiment of the present invention.
FIG. 24A is a block diagram illustrating an add/drop filter in accordance with an embodiment of the present invention.
FIG. 24B is a block diagram illustrating an optical splitter in accordance with an embodiment of the present invention.
FIG. 25A is a block diagram illustrating an optical splitter in accordance with an embodiment of the present invention.
FIG. 25B is a block diagram illustrating an optical splitter in accordance with an embodiment of the present invention.
FIG. 26 is a flow chart illustrating a process for 3-way splitting an optical signal in accordance with an embodiment of the present invention.
FIG. 27 is a block diagram illustrating a computer system in accordance with an embodiment of the present invention.



Note that like reference numerals refer to corresponding parts throughout the drawings.
DETAILED DESCRIPTION
The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
Embodiments of a bidirectional 3-way optical splitter and a method for 3-way splitting an optical signal are described. This bidirectional 3-way optical splitter may include: an optical splitter that has: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes.
In some embodiments, the optical splitter includes: a 2×2 optical splitter, a 2×1 optical coupler, another 2×2 optical splitter, and/or another 2×1 optical coupler.
In some embodiments the optical splitter includes: a 2×2 optical switch, a 2×1 unidirectional optical coupler, and/or another 2×1 unidirectional optical coupler. Additionally, the optical splitter may include control logic that is coupled to the 2×2 optical switch, and which configures selective coupling of nodes in the 2×2 optical switch.
In some embodiments the optical splitter includes: an interferometer, an add/drop filter, and/or another add/drop filter. For example, the interferometer may include a Mach-Zehnder interferometer and/or a given add/drop filter may include one or more ring resonators. Additionally, the optical splitter may include one or more waveguides.
Note that the bidirectional 3-way optical splitter may be included in a multi-chip module (MCM) (such as a switch or a processor) and/or in a system that include the MCM. This MCM includes an array of chip modules (CMs) or single-chip modules (SCMs), and a given SCM includes at least one semiconductor die. Note that the MCM is sometimes referred to as a ‘macro-chip.’ Furthermore, the semiconductor die communicates with other semiconductor dies, CMs, SCMs, and/or devices in the MCM using proximity communication of electromagnetically coupled signals (which is referred to as ‘electromagnetic proximity communication’), such as capacitively coupled signals and/or proximity communication of optical signals (which are, respectively, referred to as ‘electrical proximity communication’ and ‘optical proximity communication’). In some embodiments, the electromagnetic proximity communication includes inductively coupled signals and/or conductively coupled signals.
Note that the bidirectional 3-way optical splitter may facilitate arrays in which, in a given CM module, optical signal paths, such as waveguides, are routed in the same way as in the other CMs in the array. In this way, a common optical design in the CMs may be used in the system to prevent data conflicts during the optical communication, thereby reducing the complexity and expense of the system. Consequently, the bidirectional 3-way optical splitter may facilitate the creation of large arrays with very high performance.
Embodiments of the MCM may be used in a variety of applications, including: VLSI circuits, telephony, storage area networks, data centers, networks (such as local area networks), and/or computer systems (such as multiple-core processor computer systems). For example, the MCM may be included in a backplane that is coupled to multiple processor blades, or the MCM may couple different types of components (such as processors, memory, I/O devices, and/or peripheral devices). In some embodiments, the MCM performs the functions of: a switch, a hub, a bridge, and/or a router. Note that the electrical signals and/or optical signals may include analog signals, data packets, and/or data streams. These signals may include binary symbols, un-encoded signals, and/or encoded symbols (for example, using multiple-pulse amplitude modulation and/or WDM, where different sub-channels are used to communicate information). Moreover, communication in the optical signal path may be: unidirectional or bidirectional (including half-duplex and/or full-duplex operation).
We now describe embodiments of a macro-chip or MCM. FIG. 1A presents a block diagram illustrating a top-view of an embodiment of an MCM 100. This MCM includes an array of multiple semiconductor dies 110 and 112. Proximity connectors on the corners (and more generally on side edges) of the semiconductor dies 110 and 112 overlap and couple signals between adjacent semiconductor dies using electromagnetic proximity communication, such as capacitive and/or optical proximity communication. Thus, in some embodiments semiconductor dies 110 are face up and semiconductor dies 112 are face down. However, in other embodiments semiconductor dies 110 are face down and semiconductor dies 112 are face up.
In an exemplary embodiment, MCM 100 includes a computer system, including one or more processors and/or memories. In some embodiments, MCM 100 includes a switch. In these embodiments, one or more of the semiconductor dies 110 and 112 implement some or all of the functionality of a switch. Such semiconductor dies are sometimes referred to as ‘switch chips’ or ‘logic chips.’ Therefore, one or more of the semiconductor dies 110 and 112 may include I/O ports to communicate input signals and output signals, as well as multiple switching elements that selectively couple the input and output ports. Furthermore, in some embodiments at least one of the semiconductor dies 110 and 112 includes a flow-control mechanism or logic that provides flow-control information that configures the switching elements or determines routing of data. This flow-control information may be communicated in the electrical domain and/or in the optical domain, and may be communicated along with the data and/or separately from the data (for example, in a separate flow-control communication channel, i.e., out-of-band control). Moreover, flow-control logic may be internal or external to MCM 100 (or MCM 130 in FIG. 1B), and flow-control logic may be central or distributed.
FIG. 1B presents a block diagram illustrating a top view of an embodiment of MCM 130 (which may include a computer system and/or a switch). This MCM includes an array of multiple semiconductor dies 114 and bridge chips 116. Proximity connectors on the side edges (and in some embodiments on the corners) of the semiconductor dies 114 and the bridge chips 116 overlap and couple signals between adjacent components in the MCM 130 using electromagnetic proximity communication, such as capacitive and/or optical proximity communication. In some embodiments semiconductor dies 114 are face up and the bridge chips 116 are face down. However, in other embodiments semiconductor dies 114 are face down and the bridge chips 116 are face up.
Note that the bridge chips 116 may include one or more waveguides and/or multiple signal lines that couple signals from receive proximity connectors on one end of the bridge chips 116 to transmit proximity connectors on the other end. Such communication across the bridge chips 116 may be synchronous and/or asynchronous. In some embodiments bridge chips 116 include active electronics and/or optical components to transmit and receive signals, to amplify signals, and/or to resynchronize phases of signals on at least two of the signal lines. For example, the bridge chips can include a pipeline circuit that includes flip-flops and/or synchronization circuitry that are latched by clock signals to correct for an accumulated phase error. In these embodiments, the bridge chips 116 may be implemented using semiconductor dies, however, these dies may include different circuits and functionality than the semiconductor dies 114. In other embodiments, the bridge chips 116 are manufactured from a material other than a semiconductor.
As described below with reference to FIGS. 7-10, in some embodiments at least some signals (such as optical signals in an all-optical bypass) are communicated through one or more semiconductor dies 110 (FIG. 1A) and/or 112 (FIG. 1A), or through semiconductor dies 114 and/or bridge chips 116 without detection or conversion by active electronics or optical components. For example, switching or routing in MCMs 100 (FIG. 1A) and/or 130 may include optical switching, i.e., the data and the flow-control information may traverse the array entirely in the optical domain. (However, in general data and/or flow-control information may traverse the array using either capacitively coupled and/or optical communication.) Moreover, the optical signals may be amplified during communication in the optical domain.
In an exemplary embodiment, MCM 130 includes a 6×6 array of semiconductor dies 114 and a 5×5 array of bridge chips 116. In another exemplary embodiment, MCM 130 includes a 4×4 array of semiconductor dies 114 and a 3×3 array of bridge chips 116. Furthermore, electric and optical information in MCMs 100 (FIG. 1A) and 130 may flow in each of the four principal directions (North, South, East, and West) in the MCMs 100 (FIG. 1A) and 130. However, in some embodiments, electric and optical information flow along orthogonal directions in the MCMs 100 (FIG. 1A) and 130 (for example, optical information may flow East-West and electrical information may flow North-South).
In another exemplary embodiment of MCMs 100 (FIG. 1A) and/or 130, data is communicated between semiconductor dies 100 (FIG. 1A) and 112 (FIG. 1A) and/or semiconductor dies 114 that are not nearest neighbors using optical signals (for example, using all-optical bypasses).
Note that because of the use of proximity communication in the MCMs 100 (FIG. 1A) and 130, each of the interior components has a high-bandwidth connection to its immediate neighbors, and the bisection bandwidth of the MCMs 100 (FIG. 1A) and 130 may approach that of a single wafer-scale-integrated chip that has the same total complexity. Thus, the component-to-component bandwidth in the MCMs 100 (FIG. 1A) and 130 may be high enough to effectively hide the component boundaries and create a single ‘virtual’ chip.
In some embodiments, proximity communication transfers information between components in the MCMs 100 (FIG. 1A) and 130 using parallel words, thereby reducing delays. Furthermore, in some embodiments signals communicated in the MCMs 100 (FIG. 1A) and 130 are encoded (either internally or externally) using a channel code (such as time-division-multiple-access, frequency-division-multiple-access, and/or code-division-multiple-access). In an exemplary embodiment, the channel code is a DC-balanced or DC-free code. For example, the channel code may be a (n, k) code, such as an 8/10 code. In some embodiments, header information in data packets or data units is not encoded. Instead, such information may be inverted and repeated to achieve DC-balance. In embodiments where MCMs 100 (FIG. 1A) and 130 include a switch, encoding and decoding of signals may or may not be implemented in the switching elements. For example, encoding and decoding may occur external to the switch or at a centralized component.
Optical routing (in an optical control path and/or an optical signal path) on a given component in MCMs 100 (FIG. 1A) and 130 may be accomplished using: on-chip optical waveguides (such as silicon-on-insulator waveguides), ring resonators, modulators (such as phase modulators), detectors, and/or add or drop waveguides that configure input/output ports on the given component (these waveguides may include: splitters, grating couplers, and/or combiners). To avoid crossing of waveguides on the given component, optical signals may traverse the MCMs 100 (FIG. 1A) and 130 along a first axis (such as East-West) and electrical signals (including power and ground) may traverse the MCMs 100 (FIG. 1A) and 130 along a second axis (such as North-South). This configuration may offer a compact implementation and the fast switching times associated with electric circuits. However, this assignment of directional flow is for the sake of clarity and does not in any way limit the scope of the invention disclosed here. For example, optical and electrical signals may enter and exit any side of the MCMs 100 (FIG. 1A) and 130. Furthermore, optical and electrical input/output ports may be co-positioned next to each another.
Although MCMs 100 (FIG. 1A) and 130 are illustrated as having a number of discrete items, FIGS. 1A-1B and the other embodiments described below are intended to be a functional description of the various features which may be present rather than as a structural schematic of the embodiments described herein. In practice, and as recognized by those of ordinary skill in the art, the functions of the MCMs 100 (FIG. 1A) and 130 (as well as the other embodiments) may be distributed over a large number of components performing particular subsets of functions. Therefore, the MCMs 100 (FIG. 1A) and 130 (as well as the other embodiments) may include fewer components or additional components. Note that in some embodiments, proximity connectors between MCMs 100 (FIG. 1A) and 130 are remateable. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed. For example, in some embodiments bridge chips 116 may be replaced by additional semiconductor dies 114. Furthermore, in some embodiments functions of the MCMs 100 (FIG. 1A) and 130 (as well as the other embodiments) may be implemented in hardware and/or in software.
We now described embodiments of devices (such as SCMs and MCMs) and systems that include proximity communication. FIG. 2 presents a block diagram illustrating an embodiment of a device 200 that includes proximity connectors 212 (which may be capacitive, optical, inductive, and/or conductive-based connectors). Device 200 may include at least one semiconductor die 210, where semiconductor die 210 may include integrated circuit electronics corresponding to layers deposited on a semiconductor substrate. Note that semiconductor die 210 may be packaged in an SCM and/or an MCM, where the MCM may include two or more SCMs. When packaged, for example in the SCM or the MCM, the one semiconductor die 210 is sometimes referred to as a “chip.”
In one embodiment, the proximity connectors 212 may be on or proximate to at least one surface of the semiconductor die 210, the SCM and/or the MCM. In other embodiments, the semiconductor die 210, the SCM and/or the MCM may be coupled to the proximity connectors 212. In an exemplary embodiment, the plurality of proximity connectors 212 are substantially located at or near one or more corners (proximity connectors 212-1 and 212-2) and/or edges (proximity connectors 212-3) of the semiconductor die 210. In other embodiments, proximity connectors 212 may be situated at one or more arbitrary locations on, or proximate to, the surface of the semiconductor die 210.
As illustrated for the proximity connectors 212-1, there is a first pitch 214-1 between adjacent connectors or pads in a first direction (X) 216 of the surface and a second pitch 214-2 between adjacent connectors or pads in a second direction (Y) 218 of the surface. In some embodiments, the first pitch 214-1 and the second pitch 214-2 are approximately equal.
FIG. 3 presents a block diagram illustrating an embodiment of a system 300 that includes semiconductor dies 210 that communicate using capacitive proximity communication (which is used as an illustration). Semiconductor dies 210 may include proximity connectors or pads 212 that are on or proximate to at least respective surfaces 308 of the semiconductor dies 210. For example, the plurality of proximity connectors 212 may be situated beneath protective layers such that they are located below the surfaces 308. Moreover, subsets of the proximity connectors 212 may be coupled to transmit circuits 310 (such as transmit drivers) and receive circuits 312 (such as receivers). One of the transmit circuits 310, at least a subset of the proximity connectors 212 on the adjacent semiconductor dies 210, and one of the receive circuits 312 may constitute a communication channel. For example, the communication channel may include transmit circuit 310-1, some of the proximity connectors 212, and receive circuit 312-1. Note that transmit circuits 310 and receive circuits 312 may utilize voltage-mode signaling (i.e., voltage-mode drivers and receivers). Furthermore, semiconductor dies 210 may also include wiring and electronics (not shown) to relay the data signals to additional electronics on the semiconductor dies 210, such as logic, memory (for example, a packet buffer memory), I/O ports, demultiplexers, multiplexers, and switching elements.
In order to communicate data signals using proximity communication, transmit and receive proximity connectors 212 on adjacent semiconductor dies 210 may have, at worst, only limited misalignment, i.e., substantially accurate alignment. For densely packed proximity connectors, i.e., proximity connectors 212 having a small spacing or pitch 214 (FIG. 2) between adjacent pads, the alignment between two or more proximity connectors 212 on adjacent semiconductor dies 210 may be within a few microns in the first direction (X) 216 (FIG. 2) and/or a few microns in the second direction (Y) 218 (FIG. 2) in a first plane including at least some of the proximity connectors 212, and/or within a few microns in a third direction (Z) approximately perpendicular to the first plane. The system 300 illustrates a misalignment 314 in the third direction (Z).
In some embodiments, the proximity connectors 212 may be aligned in six degrees of freedom, including: the first direction (X) 216 (FIG. 2); the second direction (Y) 218 (FIG. 2); the third direction (Z); an angle in the first plane defined by the first direction (X) 216 (FIG. 2) and the second direction (Y) 218 (FIG. 2); an angle in a second plane defined by the first direction (X) 216 (FIG. 2) and the third direction (Z); and an angle in a third plane defined by the second direction (Y) 218 (FIG. 2) and the third direction (Z). Note that if a surface, such as the surface 308-1, of either of the adjacent semiconductor dies 210 is non-planar (for example, due to quadrapole distortion), additional alignment problems may be introduced.
In some embodiments, allowed misalignment in the first direction (X) 216 (FIG. 2), the second direction (Y) 218 (FIG. 2) and/or the third direction (Z) is less than one half of the pitch 214 (FIG. 2) between adjacent pads 212. For example, misalignment in the first direction (X) 216 (FIG. 2) and/or the second direction (Y) 218 (FIG. 2) may be less than 25 μm, and the misalignment 314 in the third direction (Z) may be less than 5 μm.
Solutions, such as self-alignment and/or self-adjustment of relative positions of the proximity connectors 212 on adjacent semiconductor dies 210 and/or in a component (such as one of the bridge chips 116 in FIG. 1B) coupling two or more semiconductor dies 210, may reduce and/or eliminate the misalignment 314 in the third direction (Z). For example, structures that have flexibility compliance or are spring-like may be used. In other embodiments, a feedback control loop may be used to reduce and/or eliminate the misalignment 314 in the third direction (Z).
Reducing or eliminating the misalignment 314, in turn, may lead to at least partial overlap of one or more proximity connectors 212 on the adjacent semiconductor dies 210 and increase a magnitude of the capacitively coupled data signals. In addition, the solutions may reduce misalignment in the first plane, i.e., the plane including at least some of the proximity connectors 212, when used in conjunction with techniques such as electronic steering (where data signals are routed to respective proximity connectors 212 based on the alignment in the first plane). Consequently, these solutions may facilitate proximity communication between the semiconductor dies 210, SCMs and/or MCMs. The solutions may also reduce and/or eliminate a need for narrow tolerances, precise manufacturing, and/or precise assembly of the semiconductor dies 210, the SCM and/or the MCM. In addition, improved alignment of the proximity connectors 212 may reduce power consumption in MCMs 100 (FIG. 1A) and/or 130 (FIG. 1B).
In the embodiments described above and below, the proximity connectors 212 on the adjacent semiconductor dies 210 utilize capacitive coupling and/or optical coupling for inter-chip communication. In other embodiments, different connectors may be overlapped on adjacent semiconductor dies 210. For example, one embodiment of the present invention uses inductive proximity connectors and/or magnetic proximity connectors, where data signals are communicated inductively and/or magnetically between terminals on closely adjacent semiconductor dies 210. Another embodiment conductively couples connectors in adjacent semiconductor dies 210 using an array of solder balls.
While the device 200 (FIG. 2) and the system 300 are illustrated as having a number of components in a given configuration, in other embodiments the device 200 (FIG. 2) and/or the system 300 may include fewer components or additional components. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
We now describe embodiments of optical components on semiconductor dies that may be included in the MCMs 100 (FIG. 1A) and 130 (FIG. 1B). Existing on-chip metal signal lines often result in large delays, and as technology scales, these delays are increasing. For example, as wire geometries become smaller (thinner, narrower, etc.) they become more resistive. While there are design techniques that can mitigate some of these trends in single-chip systems (for example, using transistors or buffers along long wires to refresh signals), the maximum wire lengths in these systems rarely exceed 2 cm. However, in systems such as MCMs 100 (FIG. 1A) and 130 (FIG. 1B) the maximum wire length is, at least theoretically, unbounded. Consequently, the wire length may be 20 cm, and even though the resulting physical communication channel is routinely broken by proximity communication jumps between components, the latency or delay may be 10 to 20 times larger than that associated with the longest wire in a single chip.
In general, long wire latencies do not restrict the operating frequency in a system. Instead, these latencies may increase the cost of communication within the system. For example, when there are long wire latencies, memories that maintain coherency by snooping on other memories or that operate by casting out scatter or gather requests may be restricted to use a limited set of neighboring memories. In another example, architectures that pipeline communication requests may maintain queues of outstanding requests until these queues are fulfilled. Unfortunately, as communication distances and delays increase, the queues may become larger and larger, increasing the size, the power consumption, and the complexity of the system.
In some embodiments, these problems may be reduced and/or eliminated through the use of on-chip and/or inter-chip optical communication. For example, as discussed previously semiconductor dies 110, 112, and 114 (FIGS. 1A and 1B) and/or bridge chips 116 (FIG. 1B) may include optical waveguides. These waveguides may have widths less than 1 μm and, in some embodiments, may simultaneously carry multiple independent wavelengths, thereby increasing the effective information capacity of each waveguide by the number of independent wavelengths. In an exemplary embodiment, a given waveguide may communicate 32-64 wavelengths.
Note that the speed of light in an optical waveguide is determined by the effective refractive index of the waveguide that is used to confine and communicate the light across the chip or a series of chips. In particular, the speed of light is inversely proportional to this effective refractive index and is essentially c/n, where c is the speed of light in vacuum and n is the effective refractive index of the medium. In general, n has real and imaginary components that depend on wavelength, but for many materials n is a real, non-negative number. For example, for silicon n is approximately 3.5.
In some embodiments, the effective index of a waveguide is reduced by using a so-called ‘slotted’ waveguide, while still strongly confining and guiding the light. Consequently, the speed of optical signal transmission in these waveguides is in the range of 1-1.8×108 cm/s or up to 10 times the speed of corresponding electrical signals. Furthermore, in some embodiments the delay or latency associated with the waveguides is further reduced using photonic-crystal techniques.
FIG. 4A presents a block diagram illustrating an embodiment of an MCM 400. This MCM includes semiconductor dies 410, which include optical waveguides 412 and communicate using optical proximity connectors 418. For example, light may be coupled between the semiconductor dies 410 by: a grating coupler (such as a diffraction grating) embedded in the waveguides 412 (such as the arrayed-waveguide grating discussed below with reference to FIG. 15), a lens, and/or a mirror. Moreover, in some embodiments the optical proximity communication includes evanescent coupling. Note that if the separation between adjacent semiconductor dies is less than a few microns (or a wavelength of the light) additional focusing optics between the semiconductor dies 410 may not be needed. Also note that even single-mode optical waveguides can couple signals across an air gap of these dimensions with minimal loss.
Therefore, in this embodiment proximity communication has been generalized to communication of arbitrary electro-magnetic waves across the gap between the semiconductor dies 410. By increasing the frequency of the electro-magnetic waves, optical frequencies are reached, and the electro-magnetic waves are none other than light. Thus, optical proximity communication may be used to communicate information between the semiconductor dies 410, and optical transmission across the semiconductor dies 410 may occur via the waveguides 412. Note that MCM 400 includes an optical signal path or optical control path that spans multiple semiconductor dies 410 without optical-to-electrical conversions or electrical-to-optical conversions at intermediate points.
As noted previously, it may be difficult to perform logical computations (such as determining local flow-control information) in the optical domain. Therefore, in some embodiments the semiconductor dies 410 include conversion elements 414, which convert optical signals to electrical signals (and vice versa). These electrical signals may be coupled to logic circuits 416, such as a local flow-control mechanism or logic that determines local flow-control information based on information from adjacent semiconductor dies 410 and/or flow-control information communicated within a switch. After determining the local flow-control information, the resulting electrical signals may be converted into optical signals using a conversion element (such as conversion element 414-1) and the optical signals may be communicated to other semiconductor dies 410. Alternatively, optical signals corresponding to flow-control information may be received and converted into electrical signals by the conversion element 414-1 prior to setting switching elements on semiconductor die 410-1. Note that the conversion elements 414 may include wavelength combiners and splitters, or may simply tap a percentage of the light as it passes by in the waveguides 412, thereby facilitating conversion from the optical to the electrical domain.
While MCM 400 uses optical proximity communication between the semiconductor dies 410, in other embodiments electrical proximity communication is used in conjunction with on-chip optical communication. This is shown in FIG. 4B, which presents a block diagram illustrating an embodiment of an MCM 430. During transmitting, at the interface between the on-chip photonics and proximity connectors 442, the optical signals are converted to electrical signals by conversion elements 440. Similarly, during receiving, at the interface between the proximity connectors 442 and the on-chip photonics, the electrical signals are converted to optical signals by the conversion elements 440.
Note that MCM 400 (FIG. 4A) and MCM 430 may include fewer components or additional components. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
FIG. 5 presents a block diagram illustrating an embodiment 500 of a conversion element 510. Modulation control 516 may modulate an optical source 518 based on electrical signals 512 to produce optical signals 514. Furthermore, while not shown, the modulation control 516 may modulate an optical source 518 based on the optical signals 514 to produce the electrical signals 512. Note that the optical source 518 may include: embedded or integrated lasers or light emitting diodes (LEDs), and/or external lasers or LEDs that are coupled to the semiconductor dies 410 (FIG. 4B). For example, the lasers may include vertical cavity surface-emitting lasers or side-emitting lasers. In some embodiments, erbium amplifiers are used to compensate for on-chip optical losses.
There are several techniques in which electrical signals can be used to create modulated optical signals in conversion element 510. For example, electrically modulated signals (such as amplitude modulated signals corresponding to a logical ‘1’ and a logical ‘0’) can be fed directly to an appropriately biased optical source, such as an LED or laser. Via so-called ‘direct” modulation of the optical source, the electrical information can be imposed on the optical output as an optical intensity modulation. Alternatively, electrical modulated signals may be sent to an optical modulator, which has a constant intensity optical beam as an input, and which outputs a modulated intensity optical beam based on the electrically modulated signals. Note that this technique uses two inputs: an electrical modulation signal and an un-modulated optical source.
While these examples illustrate direct and indirect intensity modulation, in other embodiments other types of direct and/or indirect modulation may be used, including: pulse-width modulation, pulse-frequency modulation, pulse-phase modulation, quadrature amplitude modulation, and/or quadrature phase modulation.
Note that the conversion element 510 may include fewer components or additional components. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
FIGS. 6A and 6B present block diagrams illustrating embodiments of devices 600 and 630 that include on-chip optical communication. In these devices, the on-chip photonics include buses (such as waveguides 614) running along the edge and/or across the middle of semiconductor dies 610 and 640. Note that the communication of on-chip and/or inter-chip optical signals may include encoding of information using: time-division-multiple-access, frequency-division-multiple-access, or code-division-multiple-access. For example, communication of the on-chip optical signals may use WDM (such as dense wavelength-division multiplexing and/or coarse wavelength-division multiplexing) to combine different frequencies into a single waveguide (such as the waveguide 614-1). However, in other embodiments there may be a single frequency per waveguide. In either case, the waveguides 614 provide a low-loss, non-radiative communication medium for signaling across the surface of the semiconductor dies 610 and 640. In some embodiments, spatial multiplexing is used when there are multiple parallel channels (such as waveguides 614).
Note that in addition to carrying data and/or flow-control information the semiconductor dies 610 and 640 may also include circuits 612 and 642. For example, these circuits may include a switch or a computer, including a computation core (such as a processor) and/or a storage core (such as memory). Consequently, the photonic networks on each of the semiconductor dies 610 and 640 may also interact with routing points or conversion elements 616 to convert signals from the optical domain to the electrical domain prior to coupling to the circuits 612 and 642 (via signal lines 618), and back again after processing and/or storage.
In some embodiments, the on-chip photonic networks carry one or more synchronization signals in addition to data and/or flow-control information. For example, clock signals may be communicated in an MCM (such as MCM 100 in FIG. 1A and/or MCM 130 in FIG. 1B) with as low a latency as clock signals on a single chip, thereby synchronizing the entire system.
In an exemplary embodiment, data, flow-control information, and/or clock signals are communicated on the waveguides 614 using WDM signaling. Such signaling may be accomplished using optical multiplexers and demultiplexers that are integrated on chip using silicon-on-insulator technology. In addition, the semiconductor dies 610 and 640 may include: arrayed waveguide gratings, ring resonators, and/or Mach-Zander phase modulators.
Note that the semiconductor dies 610 and 640 may include fewer components or additional components. For example, additional components that provide at least some of the previously described functionality may be coupled to semiconductor dies 610 and 640 using flip-chip binding. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
We now described embodiments of devices (such as SCMs and MCMs) and systems with reduced inter-chip communication latency. FIG. 7 presents a block diagram illustrating an embodiment of an MCM 700. In this MCM, semiconductor dies 714 are coupled to bridge chips 710. These bridge chips include waveguides 712 (shown as bold dashed or solid lines) that span multiple components (such as multiple bridge chips 710 and/or semiconductor dies 714). In an exemplary embodiment, waveguides 712 include optical-bypass waveguides that facilitate communication of optical signals between semiconductor dies that are separated by at least one intervening semiconductor die without intermediate processing of electrical signals associated with the optical signals on the intervening semiconductor die. For example, the optical signals may be communicated from a first semiconductor die to a second semiconductor die via optical proximity communication. Next, the optical signals may be communicated through the second semiconductor die via an optical-bypass waveguide (which may bypass any control logic on the second semiconductor die). Then, the optical signals may be communicated from the second semiconductor die to a third semiconductor die via optical proximity communication.
A given semiconductor die in MCM 700, such as semiconductor die 714-1, may include a conversion element (such as a laser or a diode) to convert electrical signals to optical signals, which are transmitted on the optical-bypass waveguides. Similarly, the given semiconductor die may include another conversion element (such as a detector or a diode) to convert the optical signals to the electrical signals (if the given semiconductor die is the destination of the optical signals). More generally, the given semiconductor die may include one or more add-drop elements (such as add or drop waveguides) which are configured: to insert the optical signals onto the optical waveguide(s) 712 (for example, using the conversion element); to remove the optical signals from the optical waveguide(s) 712 (for example, using the other conversion element), and/or to allow the optical signals to pass through the given semiconductor die on the optical waveguide(s) 712.
In some embodiments, the one or more add-drop elements convert a portion of the optical signals in the waveguides 712 to determine if the given semiconductor die is the destination of the optical signals (for example, based on routing information or a header associated with data packets in the optical signals). If yes, the remainder of the optical signals may be converted to electrical signals, and if no, the remainder of the optical signals may pass through the given semiconductor die without processing.
However, in some embodiments the optical signals are encoded (for example, using frequency-division multiplexing and/or WDM) and one or more sub-channels correspond to the given semiconductor die. In these embodiments, the one or more add-drop elements convert the optical signals corresponding to the one or more sub-channels (such as those associated with one or more carrier wavelengths) to electrical signals and the remainder of the optical signals pass through the given semiconductor die without processing.
By using all-optical bypass channels, MCM 700 may facilitate low-latency optical communication between semiconductor dies 714. In particular, signal propagation in optical waveguides may be 5-10× faster than signal propagation on existing on-chip metal wires. Moreover, optical waveguides may not require repeaters (i.e., optical-to-electrical signal conversion and back) on the semiconductor dies 714 and at every coupling between the semiconductor dies 714. Instead, electrically driven optical amplifiers and/or erbium amplifiers may be used to compensate for optical losses without conversion to the electrical signal domain. Moreover, multiple optical signals traversing one or more of the waveguides 712 on separate wavelengths may be simultaneously amplified so long as the wavelengths fall within the amplification band of the amplifier(s). In an exemplary embodiment, such amplifiers occur every few cm along the length of the waveguides 712 (or an associated optical signal path) and/or at every few couplings between semiconductor dies 714.
In some embodiments, optical signals on the all-optical bypass channels are encoded using WDM. Consequently, in some embodiments, a single waveguide provides bandwidth densities that are an order of magnitude greater than in existing electrical interconnects. In an exemplary embodiment, a single waveguide carries up to Terabits per second of bandwidth and the use of all-optical bypass channels between semiconductor dies 714 facilitates inter-chip communication at these bandwidths with: reduced power dissipation, reduced area utilization, and reduced latency.
Note that MCM 700 may include fewer components or additional components. For example, in addition to the full-row waveguides MCM 700 may include full-column waveguides, and these waveguides may support bidirectional communication. In some embodiments, semiconductor dies 714 are interconnected by linear or mesh-like arrays of all-optical bypass channels. Furthermore, in some embodiments, the MCM 700 includes a 1-dimensional chain of semiconductor dies 714 (or CMs) and/or a 2-dimensional array of semiconductor dies 714 (or CMs). Note that two or more components in MCM 700 may be combined into a single component and/or a position of one or more components may be changed.
FIG. 8 presents a block diagram illustrating an embodiment of an MCM 800. This MCM shows a dense cache-coherent multiprocessor system implemented using a mesh of optical waveguides. In particular, groups of processor cores 810 and 812 are coupled to optical signal paths or optical links 816 (which include the optical waveguides) through optical proximity interfaces 814. Each of the optical proximity interfaces 814, such as optical proximity interface 814-1, may support one or more waveguides with each waveguide carrying numerous (e.g., up to 72) wavelengths, and with each wavelength channel supporting multiple Gigabit per second of data transmission (e.g., up to 40 Gbps). Consequently, the data transmission density of the optical proximity interfaces 814 may exceed 100 Tbps/mm2.
Note that MCM 800 may include fewer components or additional components. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
FIG. 9 presents a block diagram illustrating an embodiment of an MCM 900. This MCM extends the cache-coherent multiprocessor architecture using optical waveguides shown in FIG. 8. In particular, each row and column in an array of alternating processors 910 and memory 912 (such as cache memory) may have an associated optical signal path or all-optical bypass channel, such as the full-row waveguides in FIG. 7. Thus, components in the MCM 900 may communicate with each other along two orthogonal directions 914. These optical signal paths may be independent (such as multiple linear buses, which may be coupled end to end) or may be part of a single communication bus (such as a toroid). Moreover, subsets of the MCM 900 may have even higher connectivity.
Note that MCM 900 may include fewer components or additional components. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
FIG. 10 presents a block diagram illustrating an embodiment of an MCM 1000, which includes an optical cross-bar 1012 switch. This switch is coupled to eight processors 1010 by bridge chips 1016, and the processors 1010 are coupled to a perimeter of memory 1014 chips (such as cache memory). Note that signals flow through the optical cross bar 1012 and then bridge chips 1016 distribute these signals to the processors 1010 and memory 1014 using electrical proximity communication and/or optical proximity communication.
Note that MCM 1000 may include fewer components or additional components. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
We now described embodiments of one or more optical signal paths, and in particular, optical signal paths that communicate optical signals which are encoded using WDM. These techniques may facilitate low latency inter-chip communication using a limited number of waveguides, as well as a limited number of sources (such as lasers), and detectors, thereby reducing power consumption.
FIG. 11 presents a block diagram illustrating an embodiment of an MCM 1100. This MCM includes thirty-six chips (such as semiconductor dies 714 in FIG. 7) arranged in a 2-dimensional array, including columns with chips 1110, 1112, 1114, 1116, 1118, and 1120. These chips are coupled by optical waveguides, which communicate optical signals that are, at least in part, encoded based on wavelength (for example, using WDM). In particular, chips 1110-1, 1112-1, 1114-1, 1116-1, 1118-1, and 1120-1 are coupled together by a waveguide 1122, and chips in a given column (such as chips 1110) are coupled together by an additional waveguide. These waveguides may facilitate point-to-point communication between the chips and may provide equal incoming and outgoing data bandwidths.
Coding, such as WDM, may be used to determine where an optical signal has come from and/or where an optical signal is going to, thereby eliminating electrical processing of flow-control information or packet headers at intermediate chips in an optical signal path. For example, a given column (or subset) of the chips may be associated with a given sub-channel (such as a range of wavelengths centered on a carrier wavelength or a group of wavelengths each centered on associated carrier wavelengths) and chips within this column may communicate using this sub-channel. Thus, in MCM 1100 a set of N carrier wavelengths may be used, and a given column (such as chips 1110) may utilize a sub-channel associated with a given carrier wavelength in this set.
In an exemplary embodiment, N is 6, i.e., the set of carrier wavelengths includes λi, λ2, λ3, λ4, λ5 and λ6. An optical signal may be first communicated in a horizontal direction via waveguide 1122 to reach a target column within the MCM 1100. Then, the optical signal may be sent to its destination(s) within the target column. In particular, because a different carrier wavelength is used to send optical signals to different columns, splitters or filters at each chip along the waveguide 1122 can remove optical signals having the appropriate wavelengths while other optical signals are unaffected. Thus, if a transmission targeting chips 1110 uses carrier wavelength λ1, the corresponding optical signals can be tapped out of the waveguide 1122 at chip 1110-1. Similarly, if transmissions targeting chips 1112 use carrier wavelength λ2, the corresponding optical signals can be tapped out at chip 1112-1.
Note that if the linear dimension of the array exceeds the number of carrier wavelengths that can be used in waveguide 1122, multiple waveguides may be used. For example, if a single waveguide can concurrently carry eight carrier wavelengths, a 16×16 array may use at least two horizontal waveguides to couple the columns or subsets of chips.
An extension of this approach allows multiple chips to be specified during transmission while using a common waveguide. This is shown in FIG. 12, which presents a block diagram illustrating an embodiment of an MCM 1200 that includes chips coupled by waveguides 1210. In this MCM, a given chip in a given column and/or a given row is associated with a given carrier wavelength (and thus a given sub-channel) in the set of N carrier wavelengths. By performing a circular permutation on the carrier wavelengths in the set N, each chip in the given column and/or a given row can be assigned a different carrier wavelength. Consequently, a given waveguide in the waveguides 1210 can communicate optical signals coming from and going to different chips without the optical signals interfering with each other.
In an exemplary embodiment, N is 6, i.e., the set of carrier wavelengths includes λ1, λ2, λ3, λ4, λ5 and λ6. Moreover, chips in the MCM 1200 may be associated with carrier wavelengths based on the following array of circular permutations




  
    
      
        
          λ
          1
        
      
      
        
          λ
          2
        
      
      
        
          λ
          3
        
      
      
        
          λ
          4
        
      
      
        
          λ
          5
        
      
      
        
          λ
          6
        
      
    
    
      
        
          λ
          6
        
      
      
        
          λ
          1
        
      
      
        
          λ
          2
        
      
      
        
          λ
          3
        
      
      
        
          λ
          4
        
      
      
        
          λ
          5
        
      
    
    
      
        
          λ
          5
        
      
      
        
          λ
          6
        
      
      
        
          λ
          1
        
      
      
        
          λ
          2
        
      
      
        
          λ
          3
        
      
      
        
          λ
          4
        
      
    
    
      
        
          λ
          4
        
      
      
        
          λ
          5
        
      
      
        
          λ
          6
        
      
      
        
          λ
          1
        
      
      
        
          λ
          2
        
      
      
        
          λ
          3
        
      
    
    
      
        
          λ
          3
        
      
      
        
          λ
          4
        
      
      
        
          λ
          5
        
      
      
        
          λ
          6
        
      
      
        
          λ
          1
        
      
      
        
          λ
          2
        
      
    
    
      
        
          λ
          2
        
      
      
        
          λ
          3
        
      
      
        
          λ
          4
        
      
      
        
          λ
          5
        
      
      
        
          λ
          6
        
      
      
        
          λ
          1
        
      
    
  
  .




Thus, in row 1 or column 1, chip 1110-1 may be uniquely specified using carrier wavelength λ1, and in row 2 or column 3 chip 1114-2 may be uniquely specified using carrier wavelength λ2, etc.

More generally, an array of chips (such as the MCM 1200) may include N subsets, each of which includes M chips. For a given chip in the MCM 1200, a first optical signal path (such as a waveguide) may be coupled to the other chips within a given subset. Communication with a particular one of these chips may utilize a carrier wavelength in a set of M carrier wavelengths. Moreover, the given chip may also be coupled to other subsets via a second optical signal path (such as another waveguide). Communication with a particular one of these subsets may utilize a carrier wavelength in a set of N carrier wavelengths.
Further generalizing this approach, each chip in an array may be specified by a unique carrier wavelength. Thus, each row and each column may have a unique set of carrier wavelengths. This is shown in FIG. 13, which presents a block diagram illustrating an embodiment of an MCM 1300. In general, an MCM includes N subsets of chips, each of which includes M chips. In MCM 1300, N and M both equal 6. Thus, chips in the MCM 1300 communicates with a given chip using a given carrier wavelength in a set of N×N carrier wavelengths.
In a variation on this embodiment, each column in MCM 1300 may be coupled to each row by a separate waveguide. This may reduce the total number of carrier wavelengths at the cost of additional waveguides. For example, a waveguide may couple column 1 with row 4. Similar, but independent waveguides may couple optical signals from column 1 to the other rows. In general, in this embodiment, for an N×N array, a given chip has N outgoing waveguides each communicating optical signals using N carrier wavelengths. The specific choice of waveguide and carrier wavelength, respectively, determines the row and column of the recipient chip. In some embodiments, there are also N incoming waveguides to the given chip.
In a further variation, a given chip in the array is coupled to different subsets of chips using separate waveguides. This is shown in FIG. 14, which presents an illustration of an embodiment of an MCM 1400. In this MCM, chip 1110-1 is coupled to subsets of chips by separate waveguides 1410. For a given waveguide, a particular chip is specified by a given carrier wavelength in a set of N carrier wavelengths. Note that in this embodiment, N is 4.
In an exemplary embodiment, chip 1110-1 communicates optical signals to other chips in row 1 using carrier wavelength λ1 and communicates optical signals to other chips in row 2 using carrier wavelength λ2, etc. Thus, optical signals to chip 1112-1 may be communicated using a first waveguide in the waveguides 1410 via a sub-channel associated with carrier wavelength λ1. Similarly, optical signals to chip 1114-1 may be communicated using a second waveguide in the waveguides 1410 via the sub-channel associated with carrier wavelength λ1.
In the general case, an array includes N subsets of chips, each of which includes M chips. Chips within a given subset are coupled by a separate optical signal path, such as a waveguide. Moreover, a given chip communicates with a particular chip in the given subset using optical signals in a sub-channel on the separate optical signal path, which is associated with a given wavelength in a set of M wavelengths.
Inter-chip communication using optical signal paths to communicate optical signals that are, at least in part, encoded using WDM have several advantages. In particular, these techniques facilitate minimum-distance, point-to-point communication between chips with a manageable number of optical signal paths (such as waveguides) per chip. For example, there may be N outgoing and/or N coming waveguides for each chip in a N×N array, and N carrier wavelengths may be sent and/or received at each chip. By using such dedicated optical signal paths to communicate optical signals between any pair of chips, flow-control and collision-detection control logic may be reduced or eliminated because the sender and/or destination chip is determined by the waveguide and/or carrier wavelength used. This arrangement may ensure that the incoming/outgoing data bandwidth is balanced and that an array of chips is isomorphic (symmetric) at any location, which may reduce the number of components in the array. Note that these techniques and configurations can coexist with other communication techniques and/or networks in the same MCM, for example, a tree network can be embedded in the array of chips to support global operations, such as broadcasts or barriers.
Note that MCM 1100 (FIG. 11), MCM 1200 (FIG. 12), MCM 1300 (FIG. 13), and/or MCM 1400 may include fewer components or additional components. For example, there may be fewer or additional waveguides coupling chips to each another. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
Optical signals that are encoded using WDM may be multiplexed onto and/or de-multiplexed from the optical signal paths (such as the waveguides) using a variety of techniques and optical coupling elements, including: a lens, a diffraction grating, a mirror, and/or an arrayed-waveguide grating. Arrayed-waveguide gratings are capable of precise multiplexing/de-multiplexing of multiple sub-channels traveling in a waveguide with relatively low losses. For example, the multiple sub-channels can be de-multiplexed into separate waveguides, each of which carries a sub-channel associated with a single carrier wavelength.
FIG. 15 presents a block diagram illustrating an embodiment of an arrayed-waveguide grating 1500. This arrayed-waveguide grating includes two optical couplers 1512, such as two slab-waveguide star couplers, which are coupled to a dispersive set of waveguides 1514. During operation as a de-multiplexer, light propagating in an input waveguide 1510 is coupled into the waveguides 1514 via optical coupler 1512-1. These waveguides are designed such that the optical path length difference between adjacent waveguides in the waveguides 1514 equals an integer multiple of the central carrier wavelength of the de-multiplexer. Consequently, the field distribution at the input aperture will be reproduced at the output aperture. Therefore, at this carrier wavelength, the light focuses in the center of the image plane, provided that the input waveguide 1510 is centered in the input plane.
However, if an input wavelength is detuned from this central carrier wavelength, a phase changes will occur in the different waveguides 1514. Because of the constant path length difference between adjacent waveguides in the waveguides 1514, this phase change will increase linearly from the inner waveguide to the outer waveguide in the waveguides 1541. Consequently, the resulting wavefront will be tilted at the output aperture and the focal point in the image plane will be shifted away from the center. By appropriately positioning output waveguides 1516 in the image plane, different carrier wavelengths (or spatial frequencies) can be spatially separated. Note that by reversing the direction of propagation of the light, i.e., by reversing the input and output, the arrayed-waveguide grating 1500 may be used as a multiplexer.
Arrayed-waveguide grating have additional properties that may be of use in the interconnect topologies described above. For example, if additional wavelengths are available for use in an MCM, then the wrap-around property of the arrayed-waveguide grating can be used. In particular, the free spectral range of an arrayed-waveguide grating is defined as the frequency shift for which the phase-shift, ΔΦ, equals 2π. Two frequencies separated by the free spectral range that are input into an arrayed-waveguide-grating de-multiplexer will focus and leave though the same output waveguide, because their phase at the output waveguides 1516 is the same. Thus, if additional sub-channels are available in an MCM, multiple carrier wavelengths separated by the free spectral range can be assigned to the same waveguide destined for a particular chip. Moreover, because these carrier wavelengths are widely spaced, it may be easier to distinguish between these carrier wavelengths on the particular chip with less sensitivity to crosstalk and/or temperature.
Another useful property of arrayed-waveguide gratings is the ability to automatically shuffle the carrier wavelengths, as described above with reference to FIG. 12. In particular, if there are multiple input waveguides and output waveguides, then an arrayed-waveguide grating can be designed so that there is a circular property of carrier-wavelength assignments between input waveguides and output waveguides. This shuffling can occur in a single device or chip, which can significantly reduce the number of separate multiplexers and de-multiplexers, and thus, can reduce the loss associated with a given sub-channel.
Note arrayed-waveguide grating 1500 may include fewer components or additional components. For example, in embodiments that utilize dense wavelength-division multiplexing, there may be a temperature controller that stabilizes the temperature of the arrayed-waveguide grating 1500 to within a few C. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed.
In exemplary embodiments, combinations of encoding techniques and communication channels may be used to achieve a target bandwidth capacity. Each configuration may have unique advantages for a given application. For example, 2.5 Gbps channel data rates can be extended to 40 Gbps using time-domain multiplexing (such as encoding using time-division-multiple-access) of electrical signals and data rates greater than 100 Gbps may be achieved using time-domain multiplexing of optical signals. As noted previously, data rates greater than 1 Tbps may be achieved by wavelength multiplexing several such channels using dense wavelength-division multiplexing and/or coarse wavelength-division multiplexing. Alternatively, a data rate of 1 Tbps may be achieved by multiplexing 1 Gbps time-domain multiplexed channels to a moderate number of SCM channels (e.g. 32) and then either multiplexing these channels onto parallel fibers (or waveguides) or using dense wavelength-division multiplexing.
To match the high bandwidth of an MCM that uses proximity communication, a high bandwidth I/O technology may be used to communicate data (such as data units) to and/or from the MCM. Fiber optic links are one such technology. FIG. 16 presents a block diagram illustrating an embodiment of an MCM 1600 that includes semiconductor dies 1610 coupled to optical transceivers 1614 using electrical proximity communication and/or optical proximity communication and bridge chips 1612. Note that the optical transceivers 1614 are coupled to optical links 1616, such as optical fibers. In some embodiments, these optical links 1616 may use WDM, such as dense wavelength-division multiplexing. In some embodiments, the optical transceivers 1614 and optical links 1616 are external to the MCM 1600. However, in other embodiments the optical transceivers 1614 and/or optical links 1616 are internal to the MCM 1600.
In some embodiments, one or more of the optical transceivers 1614 may convert optical signals received using one or more of the optical links 1616 into electrical signals. These signals may be communicated within the MCM 1600 using electrical proximity communication. In addition, one or more of the optical transceivers 1614 may convert electrical signals from the MCM 1600 into optical signals that are transmitted on one or more of the optical links 1616. Note that the transceivers 1614 may include conversion elements, such as conversion elements 440 (FIG. 4B) and/or conversion element 510 (FIG. 5).
In some embodiments, an MCM includes a semiconductor die and one or more optical transceivers. This shown in FIG. 17, which presents a block diagram illustrating an embodiment of an MCM 1700 that includes a semiconductor die 1610-3 coupled to optical transceivers 1614 using electrical proximity communication and/or optical proximity communication and bridge chips 1612. Note that the optical transceivers 1614 are coupled to optical links (not shown).
Note that MCMs 1600 (FIG. 16) and/or 1700 may include fewer components or additional components. For example, one or more optical transceivers 1614 may be integrated onto the semiconductor dies 1610 (FIG. 16) and/or 1610-3. Moreover, two or more components may be combined into a single component, and the position of one or more components may be changed.
We now describe another embodiment of an MCM. A broadcast network is a technique for coupling an array of chips (such as CMs or SCMs) so that each chip can communicate with any other chip in the array. As illustrated in FIG. 8, in a broadcast network each group of processor cores (and, more generally, each chip) is coupled to all the other groups of processor cores. For example, in an array of N chips, each chip may have a transmitter that sends data to the remaining N−1 chips using a given link (such as one of the optical links 816) in a group of N independent links (or data lines). Additionally, each chip may also have N−1 receivers to receive data from the other N−1 chips within the array. In some embodiments, the N independent links may be optical signal paths, such as on-chip waveguides, that are coupled from chip to chip via optical proximity coupling.
To implement a broadcast architecture for an MCM arranged in a 2-dimensional grid, a simplified ‘tree’ structure can be used. As shown in FIG. 18, which presents a block diagram illustrating an MCM 1800, a transmitter (such as transmitter 1818-1) on a given chip (such as chip 1810-8) in the array transmits data along one of the row-direction optical signal paths (such as optical signal paths 1812-1), which may be a waveguide. These optical signal paths are then split into column-direction optical signal paths (such as optical signal paths 1816-1) using a 3-way optical splitter (such as 3-way splitter 1814-1).
In order for each chip, such as chip 1810-1, to communicate with all the chips 1810 in an N×N MCM, one of the optical signal paths 1812 and N optical signal paths 1816 may be needed. Note that optical signal paths for one row of chips are shown in FIG. 18. When this same ‘tree’ structure is repeated for all of the rows in the array, a fully coupled broadcast network is obtained. In this case, on each of the chips 1810 there are N optical signal paths 1812 and N2 optical signal paths 1816.
One problem associated with such a broadcast architecture is that many different optical layouts may be needed when chips are directly coupled, as shown in FIG. 18. In particular, because transmitters on chips in a given row may communicate data using different optical signal paths in the optical signal paths 1812, a given transmitter, plus the associated optical signal path that couples the given transmitter to one of the optical signal paths 1812, may be at a different location in each of the chips 1810 if the optical signal paths 1812 have a regular arrangement.
Moreover, the locations of the 3-way optical splitters may also vary from chip to chip. As described previously, because each row in MCM 1800 is associated with N optical waveguides 1812, there are N groups of N optical signal paths 1812 on each chip associated with N rows of chips in the array. For chips in different rows, the physical locations of the 3-way optical splitters may be different to avoid data conflicts between the optical signal paths 1816, so that optical signals from different rows do not run into each other.
However, an MCM with many different types of chips (e.g., many different part numbers) may not be desirable. In particular, to reduce expense and improve manufacturability, the chips in an MCM may be identical. Unfortunately, a generic chip layout may result in optical-signal-path conflicts when chips are coupled directly to each other. This is shown in FIG. 19A, which presents a block diagram illustrating an MCM 1900, in which each of chips 1910 communicates data using: a transmitter (such as transmitter 1818-2), a 2-way optical splitter (such as 2-way splitter 1914-1), a 3-way optical splitter (such as 3-way splitter 1814-2), and optical signal paths (such as optical signal path 1912-1). Note that when all the chips 1910 have the same, regular optical routing or layout (e.g., all the transmitters and optical splitters have the same locations on each of the chips 1910), data conflicts occur between both the row-direction and the column-direction optical signal paths.
Consequently, a special optical layout may be used to avoid data conflicts between the optical signal paths and to provide a generic chip design. In this optical layout, permutations of the optical signal paths in both the row direction and the column direction are used to enable a broadcast architecture with a generic chip design for a 2-dimensional array. In particular, each of the optical signal paths (such as a waveguide) on a given chip has two ends that are coupled to different neighboring chips. By permuting the order of the optical signal paths at one of the boundaries (in a given direction) between neighboring chips, data conflicts between the optical signal paths can be avoided.
This is shown in FIG. 19B, which presents a block diagram illustrating an MCM 1950, for a 4×4 array of chips 1960 that are coupled by optical signal paths 1962 in the column direction and optical signal paths 1964 in the row direction. Each chip, such as chip 1960-1, has a transmitter (such as transmitter 1818-3) that communicates data with the remainder of the chips 1960 in the array. For a given chip, a transmitter may output optical signals, which are split into two unidirectional optical signals by a 2-way optical splitter (such as 2-way splitter 1914-2). One of these unidirectional optical signals may propagate to the left on one of the optical signals paths 1964 (which is sometimes referred to as a first primary optical signal path) and the other unidirectional signal may propagate to the right on one of the optical signals paths 1964 (which is sometimes referred to as a second primary optical signal path). Note that the first primary optical signal path is coupled to a neighboring chip on the left-hand side of the given chip and the second primary optical signal path is coupled to a neighboring chip on the right-hand side of the given chip. Also note that for a given row in MCM 1950, there are 4 optical signal paths 1964, such as optical signal paths 1964-1 (three of which, other than the second primary optical signal path, are sometimes referred to as additional primary optical signal paths).
If the row-direction optical signal paths are labeled a, b, c, and d from top to bottom, data conflicts at boundaries between the chips 1960 may be avoided by sequentially changing the order of the optical signal paths 1964 at the right-hand side of the chips 1960 relative to the order at the left-hand side. For example, the order at the right-hand side may be {b, c, d, e} and the order at the left-hand side may be {a, b, c, d}. Using this configuration, a given one of the optical signal paths 1964 in a given row in the array can communicate unidirectional optical signals from a given chip in the array.
This permutation technique can also be applied to the optical signal paths 1962 (which are sometimes referred to as secondary optical signal paths). In order for a given chip to communicate data to the remaining chips 1960 in the array, optical signals on each of the optical signal paths 1964 are split at appropriate column-direction optical signal paths 1962 by 3-way optical splitters (over the entire array, unidirectional optical signals on all of the optical signal paths 1964 are ultimately split at all of the column-direction optical signal paths 1962). Note that a given 3-way optical splitter is configured to receive an input optical signal on an input node and to provide output optical signals on three output nodes.
For an N×N array, optical signal paths 1964 from a given row are associated with N column-direction optical signal paths 1962. Taking all the rows into account, each chip will end up with N groups of N optical signal paths 1962 for a total of N2 optical signal paths 1962. Note that the optical signals propagating on the optical signal paths 1962 are bidirectional optical signals. Consequently, the 3-way optical splitters may be bidirectional optical splitters.
By applying the permutation technique to the optical signal paths 1962, data collisions at boundaries between the chips 1960 can also be avoided in the column direction. MCM 1950 provides an illustration of the routing permutation of 4 groups of 4 optical signal paths 1962 for each column in a 4×4 array. Note that by using this technique, the 3-way optical splitters (such as 3-way splitter 1814-3) on each of the chips 1960 can be at the same locations, thereby facilitating a common or identical chip design.
Thus, with permutations applied on both optical signal paths 1962 and 1964, a broadcast architecture can be implemented for an optically interconnected MCM, such as MCM 1950, using chips 1960 that have an identical optical layout. Additionally, this configuration limits cross-talk between optical signal paths. Note that this technique can be scaled to larger arrays and/or to higher bandwidths per chip (e.g., more than 1 transmitter per chip).
While unidirectional optical signals in the row direction and bidirectional optical signals in the column direction have been used as an illustrative example, in other embodiments either unidirectional and/or bidirectional optical signals may be communicated along either of these directions. Moreover, the optical signals communicated between chips 1960 in MCM 1950 may be communicated from a source chip to a destination chip without intervening processing as electrical signals.
In some embodiments, adjacent chips in the array communicate optical signals at their mutual boundary using optical proximity communication. For example, adjacent chips in the array may be optically coupled via optical coupling elements. Moreover, adjacent chips in the array may be optically coupled via evanescent optical signals. Additionally, in some embodiments adjacent chips in the array communicate additional data signals via electrical proximity communication. Note that the electrical proximity communication may include capacitively coupled proximity communication.
In some embodiments, MCMs 1800 (FIG. 18), 1900 (FIG. 19A), and 1950 may include fewer components or additional components. Note that components, such as optical splitters, may be active or passive devices. For example, a 3-way optical splitter may automatically route a portion of an input optical signal to three output signal paths or may switch data packets to any or all of these output signal paths, for example, based on a destination address. Moreover, two or more components may be combined into a single component, and the position of one or more components may be changed.
Additionally, in some embodiment: different permutations of the optical signal paths 1962 and 1964 may be used; there may be N column-direction optical signal paths 1962 and N2 row-direction optical signal paths 1964; and/or the permutations may be applied at the left-hand side and/or the top of the given chip (as opposed to the right-hand side and/or the bottom of the given chip).
We now described embodiments of a bidirectional 3-way optical splitter, which may facilitate identical optical layout in the chips 1960. In the broadcast architecture shown in MCM 1950, 3-way splitters 1814 are used to split an optical signal on either of the waveguides 1962 and 1964, while further propagating the original input optical signal. Consequently, these components handle bidirectional optical signals (i.e., optical signals that are propagating in either direction on waveguides 1962 and 1964), which is henceforth referred to as a bidirectional 3-way optical splitter.
One existing device, which can be implemented using silicon photonic on-chip waveguide technology, is a unidirectional optical splitter (which is sometimes referred to as an X/Y optical splitter). This is shown in FIG. 20A, which presents a block diagram illustrating an existing unidirectional optical splitter 2010-1. In this optical splitter, an input optical signal is split into two output optical signals (for example, on two waveguides) with power ratio X/Y, where X and Y can be tuned or set to arbitrary values.
As shown in FIG. 20B, which presents a block diagram illustrating an existing optical splitter 2050, a 3-way optical splitter (with one input, and three outputs) can then be built using unidirectional optical splitters 2010. In particular, two unidirectional optical splitters 2010 are optically coupled series. Note that these unidirectional optical splitters may have different power ratios X/Y. For example, the power ratio X/Y of unidirectional optical splitter 2010-2 may be 1/2 and the power ratio X/Y of unidirectional optical splitter 2010-3 may be 1/1. In this way, output optical signals on the three output ports or nodes of the optical splitter 2050 may be the same.
However, the existing optical splitter 2050 typically can only handle optical signals coming from a particular direction. Consequently, if this type of 3-way optical splitter is used in MCM 1950 (FIG. 19B), it may not be possible to use a common optical layout for the chips 1960 (FIG. 19B), which could increase the cost and complexity of such MCMs. To facilitate a common optical layout for the chips 1960 (FIG. 19B), bidirectional 3-way optical splitters may be used.
This 3-way optical splitter may include: a first external node, a second external node, a third external node, and a fourth external node. In one mode of operation, the bidirectional 3-way optical splitter may be configured to receive an external input optical signal on the first external node and to provide external output optical signals on the other external nodes. Moreover, in another mode of operation, the optical splitter may be configured to receive the external input optical signal on the third external node and to provide the external output optical signals on the other external nodes.
Note that the power ratios of each of the external output optical signals to the external input optical signal may be approximately equal. Moreover, note that this bidirectional 3-way optical splitter may be used for broadband and/or wavelength-selective applications.
In one embodiment of the bidirectional 3-way optical splitter, 2×2 optical splitters (which are also referred to as 2×2 X/Y optical splitters) are used. FIG. 21A presents a block diagram illustrating an embodiment 2100 of a 2×2 optical splitter 2110-1. This 2×2 optical splitter can have an input optical signal on port or node 2112-1 and split it to nodes 2112-4 and 2112-3 with a power ratio X/Y. Alternatively, 2×2 optical splitter 2110-1 can have an input optical signal on port or node 2112-3 and split it to nodes 2112-2 and 2112-1 with the power ratio X/Y. Note that the power ratio X/Y can be tuned or set to an arbitrary value.
FIG. 21B presents a block diagram illustrating an embodiment of an optical splitter 2150 that includes 2×2 optical splitters 2110 and 2×1 optical couplers 2160. In particular, two 2×2 optical splitters 2110 are optically coupled in series, and nodes 2 and 4 of a given 2×2 optical splitter are combined by a given 2×1 optical coupler to form an output optical signal on an output node. When an input optical signal is received on node 2162-1, it is split and optical signals are output on nodes 2162-2, 2162-3 and 2162-4. Similarly, when an input optical signal is received on node 2162-3, it is split and optical signals are output on nodes 2162-1, 2162-2 and 2162-4. Because the optical splitter 2150 supports input optical signals on either node 2162-1 or 2162-3, it is a bidirectional 3-way optical splitter.
In some embodiments, the optical signal input to 2×2 optical splitter 2110-2 is split with a power ratio of 1/3, and the optical signal input to 2×2 optical splitter 2110-3 is split with a power ratio of 1/1. In this way, the power of each of the output optical signals from optical splitter 2150 may be the same (or approximately the same).
Note that in some embodiments, the range of wavelengths associated with the output optical signals from the optical splitter 2150 may be the same as the range of wavelengths associated with the input optical signal. Consequently, optical splitter 2150 may be used in broadband applications.
In another embodiment of the bidirectional 3-way optical splitter, an optical switch is used to flip the input/output direction so that the input optical signal is always incident from the same side. FIG. 22A presents a block diagram illustrating an embodiment 2200 of an optical switch 2210-1, which has ports or nodes 2212. This optical switch has two states, ‘through’ and ‘cross,’ which can be selected using electrical control signals. In the through state, node 2212-1 is coupled to node 2212-3, and node 2212-2 is coupled to node 2212-4. Moreover, in the through state, node 2212-1 is coupled to node 2212-4, and node 2212-2 is coupled to node 2212-3.
FIG. 22B presents a block diagram illustrating an embodiment of an optical splitter 2250 that includes optical switch 2210-2 optically coupled in series with a unidirectional 3-way optical splitter, such as optical splitter 2050 (FIG. 20B). In particular, one node of optical switch 2210-2 is coupled to an input node of unidirectional optical splitter 2010-4 and another node of optical switch 2210-2 is coupled to an output node of unidirectional optical splitter 2010-4. Moreover, control logic 2260 may configure the state of the optical switch 2210-2, either before the optical signal is received or dynamically. Thus, the optical switch 2210-2 may be set to the through state in order to appropriately route an optical signal received on node or port 2162-1. Alternatively, the optical switch 2210-2 may be set to the cross state in order to appropriately route an optical signal received on node or port 2162-3. Because the optical splitter 2250 supports input optical signals on either node 2162-1 or 2162-3, it is a bidirectional 3-way optical splitter.
In some embodiments, the optical signal input to unidirectional optical splitter 2010-4 is split with a power ratio of 1/3, and the optical signal input to unidirectional optical splitter 2010-5 is split with a power ratio of 1/1. In this way, the power of each of the output optical signals from optical splitter 2250 may be the same (or approximately the same).
Note that in some embodiments, the range of wavelengths associated with the output optical signals from the optical splitter 2250 may be the same as the range of wavelengths associated with the input optical signal. Consequently, optical splitter 2250 may be used in broadband applications.
The preceding embodiments of the bidirectional 3-way optical splitter are broadband approaches. In particular, the output optical signals convey the same information as the input optical signal. This information may be communicated to all the chips in a 2-dimensional array. However, note that while the row-direction optical signal paths, such as optical signal paths 1964 (FIG. 19B), can convey different information, each group of column-direction optical signal paths, such as optical signal paths 1962 (FIG. 19B), convey the same information as any other group of column-direction optical signal paths. Consequently, the bisection bandwidth of MCM 1950 (FIG. 19B) may be limited, even though each of the optical signal paths is capable of communicating an optical signal that includes multiple carrier wavelengths.
In some embodiments, the optical signal paths in an MCM may be more effectively used, and the bisection bandwidth may be increased, by using a wavelength-selective broadcast network. As shown in FIG. 23, which presents a block diagram illustrating an embodiment of a wavelength-selective broadcast network 2300, a transmitter (T) on each chip uses three carrier wavelengths (λA, λB, and λC) to communicate data. In particular, each transmitter (T) transmits these wavelengths onto a given optical signal path (such as a waveguide) in rows 2312, and receives optical signals on optical signal paths in columns 2310 using receivers (R). However, in contrast with the broadband broadcast network described above (for example, in FIG. 19B), only one wavelength is coupled or dropped into a given one of the optical signal paths in columns 2310.
Note that in order to avoid wavelength conflict, 3-way splitters 1814 optically couple different wavelengths from optical signal paths in different rows 2312 to the given optical signal path in the columns 2310. For example, 3-way splitters 1814 (such as 3-way splitter 1814-2) at the intersection of row 2312-1 and column 2310-1 may couple wavelength λA, 3-way splitters 1814 at the intersection of row 2312-1 and column 2310-2 may couple wavelength λB, and 3-way splitters 1814 at the intersection of row 2312-1 and column 2310-3 may couple wavelength λC. Similarly, 3-way splitters 1814 at the intersection of row 2312-2 and column 2310-1 may couple wavelength λC, 3-way splitters 1814 at the intersection of row 2312-2 and column 2310-2 may couple wavelength λA, and 3-way splitters 1814 at the intersection of row 2312-2 and column 2310-3 may couple wavelength λB. Moreover, 3-way splitters 1814 at the intersection of row 2312-3 and column 2310-1 may couple wavelength λB, 3-way splitters 1814 at the intersection of row 2312-3 and column 2310-2 may couple wavelength λC, and 3-way splitters 1814 at the intersection of row 2312-3 and column 2310-3 may couple wavelength λA.
Note that each chip communicates with chips in different columns 2310 using different carrier wavelengths, and that each chip can communicate with different columns 2310 at the same time. Moreover, not only is the data traffic on different rows 2312 different at any given time, but the data traffic on different columns 2310 is different at any given time. Consequently, the bi-section bandwidth can be N times larger (where N is 3 in this example) compared to a broadband broadcast network in which each of the 3-way splitters 1814 in the chips conveys the same carrier wavelengths.
In order to implement this wavelength-selective broadcast architecture and to have a common optical layout for the chips in an array, a wavelength-selective, bidirectional 3-way optical splitter may be used. This optical splitter optically couples a given carrier wavelength in optical signals on a given row-direction optical signal path in an MCM to column-direction optical signal paths. Additionally, this optical splitter may optically couple the given carrier wavelength and/or other carrier wavelengths (from other row-direction optical signal paths) on the column-direction optical signal paths to the given row-direction optical signal path.
In some embodiments, a wavelength-selective, the bidirectional 3-way optical splitter may include an add/drop filter, which is based on a ring resonator. FIG. 24A presents a block diagram illustrating an embodiment of an add/drop filter 2400. This add/drop filter includes two waveguides 2410 and a ring resonator 2412. Moreover, a distance between the ring resonator 2412 and a given waveguide may satisfy critical coupling (e.g., there may be evanescent coupling between the waveguides 2410 and the ring resonator 2412).
Note that the size of the ring resonator 2412 determines the free spectral range (FSR) of the ring resonator 2412. During operation, an optical signal that includes a group of wavelengths within the FSR of the ring resonator 2412 may be received on an input port or node. A given carrier wavelength (λi) can be selectively coupled or dropped to a drop port or node by tuning the ring resonator 2412 (for example, using thermal tuning). Moreover, the remaining carrier wavelengths will be output at the through port or node with very small loss. Additionally, if an optical signal is injected at the add port or node, a component having the carrier wavelength λi will be coupled or added to the optical signal at the through node, and the remaining carrier wavelengths in the optical signal injected at the add node will pass through to the drop node.
FIG. 24B presents a block diagram illustrating an embodiment of an optical splitter 2450 that includes an interferometer 2460 and add/drop filters 2462. This optical splitter has six ports or nodes 2464. During operation, an optical signal that includes multiple carrier wavelengths is input at node 2464-1. This optical signal is split equally into two optical signals in arms of the interferometer 2460 (such as a static Mach-Zehnder Interferometer or MZI). Note that these arms may be the waveguides in two tunable add/drop filters 2462. These add/drop filters can selectively couple a given carrier wavelength λi to nodes 2464-2 and 2464-5.
Moreover, the remaining carrier wavelengths propagate through the interferometer 2460 and are re-combined at node 2464-6. Note that when the two arms of the MZI have exact the same optical length, these ‘through’ carrier wavelengths experience very little loss.
Similarly, node 2464-6 can receive an optical signal that includes the given carrier wavelength λi. In this case, the given carrier wavelength λi is output on nodes 2464-3 and 2464-4, and the remaining carrier wavelengths in the optical signal are output on node 2464-1.
In some embodiments, the add ports or nodes of optical splitter 2450, such as nodes 2464-3 and 2464-4, can also receive input optical signals. For example, in an MCM, these optical signals may be provided by chips associated with other row-direction optical signal paths. In a wavelength-selective broadcast network, chips associated with other row-direction optical signal paths will transmit data using different carrier wavelengths. Consequently, the optical signals input at these two nodes will have carrier wavelengths that are different from the given carrier wavelength λi, and will propagate straight through the optical splitter 2450 (i.e., to nodes 2464-2 and 2464-5). In some embodiments, wavelength-selective bidirectional 3-way optical splitters, such as optical splitter 2450, can be used in MCMs, such as MCM 1950 (FIG. 19B), without using the permutation technique of the optical signal paths as described previously.
In some embodiments, one or more additional add/drop filters 2462, which are optically coupled in series, are included in an optical splitter. This is shown in FIGS. 25A and 25B, which presents block diagrams illustrating an embodiment of an optical splitter 2500, with an optical signal input at node 2464-1 and 2464-6, respectively. Note that multiple add/drop filters 2462 can improve the filtering performance and/or can make it easier to route the optical signals. For example, output optical signals are on nodes 2464-4 and 2464-5 in FIG. 25A, as opposed to nodes 2464-2 and 2464-5 in FIG. 24B.
Note that optical splitters 2150 (FIG. 21B), 2250 (FIG. 22B), 2450 (FIG. 24B), and 2500 (FIGS. 25A and 25B) may include fewer components or additional components. Moreover, two or more components may be combined into a single component, and the position of one or more components may be changed.
We now describe embodiments of a process for 3-way splitting an optical signal. FIG. 26 presents a flow chart illustrating a process 2600 for 3-way splitting an optical signal, which may be performed by an optical splitter. During operation, the optical splitter receives the optical signal on a given node in the first node and a third node of the optical splitter (2610). Next, the optical splitter provides output optical signals on three other nodes of the optical splitter (2612), where the three other nodes include a second node, a fourth node, and the other of the given node in the first node and the third node. Note that the capability to receive the optical signal on either the first node or the third node provides bidirectional splitting.
In some embodiments of the process 2600 there may be additional or fewer operations. Moreover, the order of the operations may be changed, and two or more operations may be combined into a single operation.
Note that the present invention may include systems that contain one or more MCMs and/or switches, which include components (such as one or more semiconductor dies) that communicate signals using electromagnetically coupled proximity connectors, such as capacitively coupled proximity connectors and/or optical proximity connectors. For example, FIG. 27 presents a block diagram illustrating an embodiment of a computer system 2700, which includes one or more processors 2710 (such as one or more processor cores), a communication interface 2712, a user interface 2714, and one or more signal lines 2722 coupling these components together. Note that the one or more processing units 2710 may support parallel processing and/or multi-threaded operation, the communication interface 2712 may have a persistent communication connection, and the one or more signal lines 2722 may constitute a communication bus. Moreover, the user interface 2714 may include a display 2716, a keyboard 2718, and/or a pointer, such as a mouse 2720.
Computer system 2700 may include memory 2724, which may include high speed random access memory and/or non-volatile memory. More specifically, memory 2724 may include: ROM, RAM, EPROM, EEPROM, FLASH, one or more smart cards, one or more magnetic disc storage devices, and/or one or more optical storage devices. Memory 2724 may store an operating system 2726, such as SOLARIS, LINUX, UNIX, OS X, or WINDOWS, that includes procedures (or a set of instructions) for handling various basic system services for performing hardware dependent tasks. Memory 2724 may also store procedures (or a set of instructions) in a communication module 2728. The communication procedures may be used for communicating with one or more computers and/or servers, including computers and/or servers that are remotely located with respect to the computer system 2700.
Memory 2724 may also include the one or more program modules (or sets of instructions) 2730. Instructions in the program modules 2730 in the memory 2724 may be implemented in a high-level procedural language, an object-oriented programming language, and/or in an assembly or machine language. The programming language may be compiled or interpreted, i.e., configurable or configured to be executed by the one or more processing units 2710.
Computer system 2700 may include one or more macro-chips 2708 (such as one or more MCMs) that include electrical proximity communication and/or optical proximity communication as described in the previous embodiments. While not shown in the computer system 2700, in some embodiments the one or more macro-chips 2708 may be coupled to one or more network interface circuits (such as one or more optical transceivers).
Computer system 2700 may include fewer components or additional components. Moreover, two or more components may be combined into a single component and/or a position of one or more components may be changed. In some embodiments, the functionality of the computer system 2700 may be implemented more in hardware and less in software, or less in hardware and more in software, as is known in the art.
Although the computer system 2700 is illustrated as having a number of discrete items, FIG. 27 is intended to be a functional description of the various features that may be present in the computer system 2700 rather than as a structural schematic of the embodiments described herein. In practice, and as recognized by those of ordinary skill in the art, the functions of the computer system 2700 may be distributed over a large number of servers or computers, with various groups of the servers or computers performing particular subsets of the functions. In some embodiments, some or all of the functionality of the computer system 2700 may be implemented in one or more application specific integrated circuits (ASICs) and/or one or more digital signal processors (DSPs).
The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.

## Claims

1. A bidirectional 3-way optical splitter, comprising an optical splitter having a first external node, a second external node, a third external node, and a fourth external node,
wherein in one mode of operation the optical splitter is configured to receive an external input optical signal on the first external node and to provide external output optical signals on all of the other external nodes; and
wherein in another mode of operation the optical splitter is configured to receive the external input optical signal on the third external node and to provide the external output optical signals on all of the other external nodes,
wherein the 3-way optical splitter comprises a wavelength-selective optical splitter that couples at least one carrier wavelength in the received external input optical signal to the external output optical signals, wherein the received external input optical signal comprises a plurality of carrier wavelengths, and wherein the at least one carrier wavelength is based on a position of the 3-way optical splitter in an array of 3-way optical splitters.

2. The bidirectional 3-way optical splitter of claim 1, wherein the power ratios of each of the external output optical signals to the external input optical signal are approximately equal.

3. The bidirectional 3-way optical splitter of claim 1, wherein the optical splitter includes:
a first 2×2 optical splitter having four internal nodes, wherein a first internal node of the 2×2 optical splitter is optically coupled to the first external node;
a first 2×1 optical coupler having a first internal node, wherein the 2×1 optical coupler is optically coupled to a second internal node and a fourth internal node of the 2×2 optical splitter, and wherein the first internal node of the 2×1 optical coupler is optically coupled to the second external node;
a second 2×2 optical splitter having four internal nodes, wherein a first internal node of the second 2×2 optical splitter is optically coupled to a third internal node of the first 2×2 optical splitter, and wherein a third internal node of the second 2×2 optical splitter is optically coupled to the third external node; and
a second 2×1 optical coupler having an additional internal node, wherein the second 2×1 optical coupler is optically coupled to a second internal node and a fourth internal node of the second 2×2 optical splitter;
wherein the additional internal node is optically coupled to the fourth external node;
wherein in the one mode of operation a given 2×2 optical splitter, wherein the given 2×2 optical splitter can be the first or the second optical splitter, is configured to receive an internal input optical signal on the first internal node of the given 2×2 optical splitter and to provide an internal output optical signal on the fourth internal node of the given 2×2 optical splitter and to provide another internal output optical signal on the third internal node of the given 2×2 optical splitter; and
wherein in the other mode of operation the given 2×2 optical splitter is configured to receive the internal input optical signal on the third internal node of the given 2×2 optical splitter and to provide the internal output optical signal on the second internal node of the given 2×2 optical splitter and to provide the other internal output optical signal on the first internal node of the given 2×2 optical splitter.

4. The bidirectional 3-way optical splitter of claim 3, wherein, for the given 2×2 optical splitter, the internal input optical signal is split into the internal output optical signal and the other internal output optical signal with a given power ratio of X/Y between the internal output optical signal and the other internal output optical signal.

5. The bidirectional 3-way optical splitter of claim 3, wherein, for the first 2×2 optical splitter, the internal input optical signal is split into the internal output optical signal and the other internal output optical signal with a power ratio of 1/3 between the internal output optical signal and the other internal output optical signal; and
wherein, for the second 2×2 optical splitter, the internal input optical signal is split into the internal output optical signal and the other internal output optical signal with a power ratio of 1/1 between the internal output optical signal and the other internal output optical signal.

6. The bidirectional 3-way optical splitter of claim 1, wherein the optical splitter includes:
a 2×2 optical switch having four internal nodes, wherein a first internal node of the 2×2 optical switch is optically coupled to the first external node, and wherein a second internal node of the 2×2 optical switch is optically coupled to the third external node;
a 2×1 unidirectional optical splitter having an internal input node and two internal output nodes, wherein the internal input node of the 2×1 unidirectional optical splitter is optically coupled to a third internal node of the 2×2 optical switch, and wherein a first internal output node of the 2×1 unidirectional optical splitter is optically coupled to a fourth internal node of the 2×2 optical switch;
another 2×1 unidirectional optical splitter having an internal input node and two internal output nodes, wherein the internal input node of the other 2×1 unidirectional optical splitter is optically coupled to a second internal output node of the 2×1 unidirectional optical splitter, wherein a first internal output node of the other 2×1 unidirectional optical splitter is optically coupled to the second external node, and wherein a second internal output node of the other 2×1 unidirectional optical splitter is optically coupled to the fourth external node; and
control logic coupled to the 2×2 optical switch, wherein in the one mode of operation the control logic configures the 2×2 optical switch to optically couple the first internal node to the third internal node and the second internal node to the fourth internal node; and
wherein in the other mode of operation the control logic configures the 2×2 optical switch to optically couple the first internal node to the fourth internal node and the second internal node to the third internal node.

7. The bidirectional 3-way optical splitter of claim 6, wherein, for a given 2×1 unidirectional optical splitter, an internal input optical signal received at the internal input node is split into an internal output optical signal on the second output node and another internal output optical signal on the first output node with a given power ratio of X/Y between the internal output optical signal and the other internal output optical signal.

8. The bidirectional 3-way optical splitter of claim 7, wherein, for the 2×1 unidirectional optical splitter, an internal input optical signal received at the internal input node is split into an internal output optical signal on the second output node and another internal output optical signal on the first output node with a power ratio of 1/3 between the internal output optical signal and the other internal output optical signal; and
wherein, for the other 2×1 unidirectional optical splitter, an internal input optical signal received at the internal input node is split into an internal output optical signal on the second output node and another internal output optical signal on the first output node with a power ratio of 1/1 between the internal output optical signal and the other internal output optical signal.

9. The bidirectional 3-way optical splitter of claim 1, wherein the optical splitter includes:
an interferometer having a first internal node, a first arm optically coupled to the first internal node, a second arm optically coupled to the first internal node, and a second internal node optically coupled to the first arm and the second arm, wherein the first internal node is optically coupled to the first external node, wherein the second internal node is optically coupled to the third external node, wherein an internal input optical signal on a given internal node, which can be the first internal node or the second internal node, is split between the first arm and the second arm, and wherein optical signals on the first arm and the second arm are combined and provided on the other internal node than the given internal node;
an add/drop filter optically coupled to the first arm, wherein an output from the add/drop filter is optically coupled to the second external node, and wherein the add/drop filter is configured to selectively couple wavelengths from the first arm to the second external node; and
another add/drop filter optically coupled to the second arm, wherein an output from the other add/drop filter is optically coupled to the fourth external node, and wherein the other add/drop filter is configured to selectively couple wavelengths from the second arm to the fourth external node.

10. The bidirectional 3-way optical splitter of claim 9, wherein a given add/drop filter includes a ring resonator.

11. The bidirectional 3-way optical splitter of claim 9, wherein the interferometer includes a Mach-Zehnder interferometer.

12. The bidirectional 3-way optical splitter of claim 9, wherein the internal input optical signal is split approximately equally between the first arm and the second arm.

13. The bidirectional 3-way optical splitter of claim 9, further comprising an optical waveguide optically coupled to the add/drop filter, wherein one end of the optical waveguide is optically coupled to a fifth node and another end of the optical waveguide is optically coupled to the second external node; and
wherein, in a third mode of operation, the one end of the optical waveguide is configured to provide another external output optical signal and the other end of the optical waveguide is configured to receive another external input optical signal.

14. The bidirectional 3-way optical splitter of claim 13, further comprising another optical waveguide optically coupled to the other add/drop filter, wherein one end of the other optical waveguide is optically coupled to the fourth external node and another end of the other optical waveguide is optically coupled to a sixth external node; and
wherein, in a fourth mode of operation, the one end of the other optical waveguide is configured to receive an additional external input optical signal and the other end of the other optical waveguide is configured to provide an additional external output optical signal.

15. The bidirectional 3-way optical splitter of claim 9, wherein at least one of the add/drop filter and the other add/drop filter include two or more ring resonators which are optically coupled in series.

16. The bidirectional 3-way optical splitter of claim 15, further comprising an optical waveguide optically coupled to the add/drop filter, wherein one end of the optical waveguide is optically coupled to the fourth external node and another end of the optical waveguide is optically coupled to a sixth external node of the optical splitter;
wherein, in a third mode of operation, the one end of the optical waveguide is configured to provide another external output optical signal and, in a fourth mode of operation, the one end of the optical waveguide is configured to receive another external input optical signal; and
wherein, in the third mode of operation, the other end of the optical waveguide is configured to receive the other external input optical signal and, in the fourth mode of operation, the other end of the optical waveguide is configured to provide the other external output optical signal.

17. The bidirectional 3-way optical splitter of claim 16, further comprising another optical waveguide optically coupled to the other add/drop filter, wherein one end of the other optical waveguide is optically coupled to a fifth external node of the optical splitter and another end of the other optical waveguide is optically coupled to the second external node;
wherein, in a fifth mode of operation, the one end of the other optical waveguide is configured to receive an additional external input optical signal and, in a sixth mode of operation, the one end of the other optical waveguide is configured to provide an additional external output optical signal; and
wherein, in the fifth mode of operation, the other end of the other optical waveguide is configured to provide the additional external output optical signal and, in the sixth mode of operation, the other end of the other optical waveguide is configured to receive the additional external input optical signal.

18. A method for 3-way splitting an optical signal, comprising:
receiving the optical signal on a given node in a first node and a third node of an optical splitter;
providing output optical signals on all of three other nodes of the optical splitter, wherein the three other nodes include a second node, a fourth node, and the other of the given node; and
using the optical splitter to couple a least one carrier wavelength in the received optical signal to the output optical signals, wherein the optical splitter comprises a wavelength-selective optical splitter, wherein the received optical signal comprises a plurality of carrier wavelengths, and wherein the at least one carrier wavelength is based on a position of the 3-way optical splitter in an array of 3-way optical splitters; and
wherein the capability to receive the optical signal on either the first node or the third node provides bidirectional splitting.