# Patent

## Title
Method and apparatus for generating reference voltage to adjust for attenuation

## Abstract

A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current control signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 09/964,911, entitled “Method and Apparatus for Generating Multi-Level Reference Voltage in Systems Using Equalization or Crosstalk Cancellation,” filed Sep. 27, 2001 (the '911 application). The '911 application is a continuation-in-part of U.S. patent application Ser. No. 09/654,643, entitled “Low Latency Equalization in Multi-Level, Multi-Line Communication Systems,” filed Sep. 5, 2000, and of U.S. patent application Ser. No. 09/655,010, now U.S. Pat. No. 6,772,351, entitled “Method and Apparatus for Calibrating a Multi-Level Current Mode Driver,” filed on Sep. 5, 2000 (the '351 patent). The '351 patent claims priority to U.S. Provisional Patent Application Ser. No. 60/158,189, entitled “A Method and Apparatus for Receiving High Speed Signals with Low Latency,” filed on Oct. 19, 1999, the contents of each of which are incorporated herein by reference. The '911 application further claims priority to PCT Application No. PCT/US01/27478, entitled “Method and Apparatus for Calibrating a Multi-Level Current Mode Driver and for Generating a Multi-Level Reference Voltage in Systems Using Equalization or Crosstalk Cancellation,” filed on Sep. 5, 2001, the contents of which are incorporated herein by reference. Additionally, the present application incorporates in its entirety U.S. patent application Ser. No. 09/478,916, entitled “Low Latency Multi-Level Communication Interface,” which claims priority to the above-referenced U.S. Provisional Patent Application Ser. No. 60/158,189.


FIELD
The present invention relates generally to the field of electrical buses. More particularly, the present invention relates to a reference voltage generation for an electrical bus with equalization or crosstalk.
BACKGROUND
Computer systems and other electronic systems typically use buses for interconnecting integrated circuit components so that the components may communicate with one another. The buses frequently connect a master, such as a microprocessor or controller, to slaves, such as memories and bus transceivers. Generally, a master may send data to and receive data from one or more slaves. A slave may send data to and receive data from a master, but not another slave.
Each master and slave coupled to a prior bus typically includes output driver circuitry for driving signals onto the bus. Some prior bus systems have output drivers that use transistor-transistor logic (“TTL”) circuitry. Other prior bus systems have output drivers that include emitter-coupled logic (“ECL”) circuitry. Other output drivers use complementary metal-oxide-semiconductor (“CMOS”) circuitry or N-channel metal-oxide-semiconductor (“NMOS”) circuitry.
While many prior buses were driven by voltage level signals, it has become advantageous to provide buses that are driven by a current mode output driver. A benefit associated with a current mode driver is a reduction of peak switching current. In particular, the current mode driver draws a known current regardless of load and operating conditions. A further benefit is that the current mode driver typically suppresses noise coupled form power and ground supplies.
A known current mode driver is shown in U.S. Pat. No. 5,254,883 (the “'883 patent”), which is assigned to the assignee of the present invention and incorporated herein by reference. The '883 patent discusses an apparatus and method for setting and maintaining the operating current of a current mode driver. The driver in the '883 patent includes an output transistor array, output logic circuitry coupled to the transistor array and a current controller coupled to the output logic circuitry.
For one embodiment, the current controller in the '883 patent is a resistor reference current controller. The current controller receives two input voltages, VTERM and VREF, the latter of which is applied to an input of a comparator. VTERM is coupled by a resistor to a node, which is in turn coupled to a second input of the comparator. The voltage at the node is controlled by a transistor array, which is in turn controlled in accordance with an output of the comparator.
When the transistor array is placed in the “off” state, i.e. there is no current flowing through the transistors of the array to ground, the voltage at the node is equal to VTERM. In addition, by using the output of the comparator to adjustably activate the transistor array, the '883 patent shows that the voltage at the node may be driven to be approximately equal to the reference voltage, VREF.
Knowing the value of VREF and VTERM, the current mode driver of the '883 patent therefore provides a binary signaling scheme utilizing a symmetrical voltage swing about VREF. Specifically, in a first current state (the “off” state), the current mode driver is not sinking current and the signal line (or bus line) is at a voltage, VO=VTERM, representing a logical “0.” In a second current state (the “on” state), the current mode driver is sinking current to drive the voltage on the signal line (or bus line) to be:

VO=VTERM−2(VTERM−VREF)

The second state therefore representing a logical “1.”
While the binary signal levels are commonly used, the use of multi-level signals is a known technique for increasing the data rate of a digital signaling system. Such multi-level signaling is sometimes known as multiple pulse amplitude modulation or multi-PAM, and has been implemented with radio or other long-distance wireless signaling systems. Other long-distance uses for multi-PAM signaling include computer or telecommunication systems that employ Gigabit Ethernet over optical fiber and over copper wires, which use three and five signal levels, respectively.
Additionally, multi-PAM signaling may be used for communication between devices in close proximity or belonging to the same system, such as those connected to the same integrated circuit (“IC”) or printed circuit board (“PCB”). In such systems, the characteristics of transmission lines, such as buses or transmission lines, over which the signals travel are tightly controlled, so that the increase in the data rate may be increased by increasing the transmit frequency. However, at higher frequencies, receiving devices may have a reduced ability to distinguish binary signals. Further, for cases in which attenuation of a signal exists between transmission and reception, different amounts of signal loss may occur depending upon the magnitude of transition between logic states. To compensate for the attenuation of the received signal, different equalization signals may be added to the main signal when driving different transitions in order to add predetermined high-frequency components to the transition signals that raise the slope of the edge of the transition. However, a difficulty with this approach for a typical multi-PAM system is that the voltage can only be pulled down from the VTERM, unless negative current could flow through current sources. To allow overdriving a transition with the equalization signals, the highest logic state may, therefore, be reduced below VTERM. This may cause the respective reference voltages to be no longer centered on the shifted data eyes.
Further, in a system that has numerous closely spaced signal lines, such as a bus for a computer device or a similar device, crosstalk may exist between nearby lines. As is known in the art, crosstalk is a disturbance caused by the electric or magnetic fields of one telecommunication signal and impairs signals on adjacent signal lines. Crosstalk characteristics on a bus may be based upon how many lines are between a crosstalk creator and a signal line being affected by crosstalk. One method for crosstalk cancellation has been described in the co-pending U.S. Patent Application entitled “Low Latency Equalization in Multi-Level, Multi-Line Communication Systems,” identified above. Similarly to the equalization mechanism, the crosstalk cancellation provides high frequency component signal and, thus, the highest logic state of the system is typically reduced below VTERM, causing reference voltage levels to be no longer centered on the shifted data eyes.
Thus, it is still desirable to develop a method and system for reference voltage generation that would track the logic state shifts due to equalization or crosstalk
SUMMARY
A multi-level driver uses multiple pulse amplitude modulation (multi-PAM) output drivers to send multi-PAM signals. A multi-PAM signal has two or more voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol on a signal line. The output symbol preferably represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). A multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
In accordance with one aspect of the invention, a reference voltage generator for a driver, such as a current driver, is provided. The current driver includes at least one reference voltage level, at least one current control signal, and at least one active device coupled to a selected reference voltage level of the at least one reference voltage level and the at least one current control signal. The active device shifts the at least one reference voltage level based on the at least one current control signal such as an equalization signal or a crosstalk cancellation signal. In one embodiment, the current driver is arranged to operate in a 2-PAM mode, a 4-PAM mode, or an N-PAM mode.
In accordance with another aspect of the invention, a method for generating a plurality of reference voltage levels for a driver is provided. The method includes providing at least one reference voltage level, providing at least one current control signal, and adjusting the at least one reference voltage level based on the at least one current control signal. In one embodiment, the at least one reference voltage level is generated on a resistive voltage divider or a reference voltage driver. Further, the at least one current control signal may include, for example, an equalization current control signal or a crosstalk cancellation signal.
These as well as other aspects and advantages of the present invention will become more apparent to those of ordinary skill in the art by reading the following detailed description, with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
Exemplary embodiments of the present invention are described with reference to the following drawings, in which:
FIG. 1 is a block diagram of a memory controller, bus and memories utilizing an output driver in accordance with a preferred embodiment of the present invention.
FIG. 2 illustrates a preferred encoding scheme utilizing a multi-level voltage reference for use with a multi-level output driver.
FIG. 3 is a signaling device that may be used to create the multi-level voltage reference of FIG. 2.
FIG. 4 is an electrical schematic of an on-chip, multi-level reference voltage generator utilizing a resistive voltage divider.
FIG. 5 is an alternative electrical schematic of an on-chip, multi-level reference voltage generator utilizing a resistive voltage divider.
FIG. 6 illustrates attenuation affecting the transitory level obtained by a step.
FIG. 7 illustrates addition of equalization signal to the logic state transitions affected by signal attenuation in FIG. 6.
FIG. 8 is an encoding scheme utilizing a multi-level voltage reference where the logic levels are shifted to allow for overdrive signals.
FIG. 9 illustrates a device that can provide overdrive signals to compensate for signal attenuation.
FIG. 10 illustrates a general equalization system for a signal line, including a self-equalization FIR filter and a number of crosstalk equalization FIRs.
FIG. 11A illustrates a signal transition that may create crosstalk on adjacent signal lines.
FIG. 11B illustrates crosstalk noise from the signal transition of FIG. 11A, imposed on a signal in an adjacent line.
FIG. 11C illustrates an equalization signal that compensates for the crosstalk noise shown in FIG. 11B.
FIG. 11D illustrates a first component of the equalization signal shown in FIG. 11C.
FIG. 11E illustrates a second component of the equalization signal shown in FIG. 11C.
FIG. 12 is a signal driver, self-equalization and crosstalk equalization communication device.
FIG. 13 is an electrical schematic of an on-chip, multi-level reference voltage generator utilizing a resistive voltage divider, where the multi-level reference voltage reflects logic state shifts.
FIG. 14 is an electrical schematic of a multi-level reference voltage generator utilizing op-amp drivers, where the multi-level reference voltage reflects logic state shifts.
FIG. 15 is an electrical schematic of an on-chip multi-level reference voltage generator utilizing on-chip drivers, where the multi-level reference voltage reflects logic state shifts.
FIG. 16 is a flow chart illustrating an exemplary method for generating at least one reference voltage level for a driver using equalization and crosstalk cancellation.
FIG. 17 is an electrical schematic of a gds compensated, multi-level output driver with current control circuitry.
FIG. 18 is an electrical schematic of a circuit for calibrating a gds compensated output driver with current control circuitry.
FIGS. 19A and 19B are a flowchart of a method for calibrating the current control circuitry using the setup of FIG. 18 for the output driver shown in FIG. 17.



DETAILED DESCRIPTION
In FIG. 1, a bus 320 interconnects a memory controller 321 and memories 322-1 to 322-2. The bus 302 is formed of signal lines 320-1, 320-2 that transmit address, data and control signals. Physically, on each integrated circuit 321, 322-1 to 322-2, the address, data and control signals are supplied to an output from external connections, called pins, and the bus 320 interconnects respective pins. The bus 320 may be implemented as traces on a printed circuit board, wires or cables and connectors. Each of these integrated circuits 321, 322-1 to 322-2 has bus output driver circuits 323-1 to 323-2 that connect to the pins to interface with the bus 320 to transmit signals to other ones of the integrated circuits. In particular, the bus output drivers 323-1 to 323-2 in the memory controller 321 and in the memories 322-1 to 322-2 transmit data over the bus 320. Each bus output driver 323-1 to 323-6 drives a signal line of the bus 320. For example, bus output driver 323-1 in the memory controller 321 drives bus line 320-1. The bus 320 supports signaling with characteristics that are a function of many factors such as the system clock speed, the bus length, the amount of current that the output drivers can drive, the supply voltages, the spacing and width of the wires or traces making up the bus 320, the physical layout of the bus itself and the resistance of a terminating resistor ZO attached to each bus.
At least a subset of the signal lines connect to pull-up resistors ZO that connect to a termination voltage VTERM. In some systems, all signal lines connect to pull-up resistors ZO that, in turn, connect to the termination voltage VTERM. The termination voltage VTERM may be different than the supply voltage VDD or not. The termination resistors can be off-chip or on-chip. In one embodiment, the supply voltage VDD is equal to 2.5 volts, the termination voltage VTERM is equal to 1.8 volts, the bus voltage for a signal at low levels VLO is equal to 1.0 volts, and the voltage swing is 0.8 volts. The resistance of the terminating resistors ZO, for this embodiment, is equal to twenty-eight ohms.
The output drivers 323-1 to 323-6 are designed to drive the bus 320 with a predetermined amount of current, and a number of bus receivers 324-1 to 324-6 are designed to receive the signals sent by the bus drivers 323-1 to 323-6 on the bus 320. In a device, each bus receiver 324-1 to 324-6 receives signals from one signal line of the bus 320. The bus receivers 324-1 to 324-6 are integrating receivers according to the preferred embodiments.
In one embodiment, the memories are random access memories (RAMs). In an alternative embodiment, the memories are read-only memories (ROMs). Alternatively, the bus output drivers 323-1 to 323-6 and bus receivers 324-1 to 324-6 of the present invention are implemented in other semiconductor devices that use a bus to interconnect various types of integrated circuits such as microprocessors and disk controllers.
In another alternative embodiment, the output drivers are implemented in a point-to-point system rather than a bus system. Although a bus that uses current mode signaling has been described with respect to FIG. 1, the apparatus and method of the present invention may be used in any signaling system where it is desirable to distinguish between signals having different voltage levels.
Referring back to FIG. 1, in previously known implementations of the bus system, signals transmitted on each signal line of the bus have either of two voltage levels representing a binary zero or one for binary digital communication. For example, an output voltage equal to the voltage level VTERM set by the voltage source at one end of the termination resistor ZO may represent a binary zero. And, an output voltage level equal to VTERM−(I×ZO) may represent a binary one, where the output driver circuit 323-1 to 323-6 sinks an amount of current equal to I. In this way, the bus driver circuits 323-1 to 323-6 can be implemented as switched current sources that sink current when driving binary one's onto the signal lines. When receiving data, the receiver circuits 324-1 to 324-6 detect whether the voltage on the signal line is greater than or less than VTERM−0.5(I×ZO), i.e. the midpoint between a logical zero and a logical one, to determine whether the data is a binary zero or one, respectively. In one embodiment, data is transmitted and received on each edge of the system clock to achieve a data rate equal to twice the frequency of the system clock. In an alternative embodiment, data is transmitted once per clock cycle of the system clock.
The output drivers 323-1 to 323-6 and receivers 324-1 to 324-6 can operate in either 2-PAM or 4-PAM mode. In one embodiment, the control, address and data signals use the same multi-PAM mode, such as 4-PAM. However, because 4-PAM may be more susceptible to errors from noise than 2-PAM, to improve system reliability, in another embodiment, signals on the bus may use the 2-PAM mode. Additionally, data may alternate between the 2-PAM and 4-PAM mode. For example, a pattern generator may be coupled to the memory controller 321 and may be used to periodically determine whether to operate the system at 2-PAM or 4-PAM. In one embodiment, the pattern generator may be arranged to periodically determine an error rate in the system, and if the error rate is above a predetermined threshold, 2-PAM signaling may be used.
Hereinafter, systems and method for generating reference voltages will be described in reference to multi-PAM systems. However, it should be understood that the methods and systems are equally applicable in 2-PAM systems.
As used herein, the term multi-level signaling refers to signaling schemes utilizing two or more signal levels. Multi-level signaling may also be referred to herein as multiple level pulse amplitude modulation, or multi-PAM, signaling, because the preferred coding methods are based upon the amplitude of the voltage signal. Other known multi-level signaling techniques may alternatively be used. Further, although the multi-level signaling of the preferred embodiments will be described with respect to a current source drivers, different or equivalent drivers could also be used.
Output drivers 323-1 to 323-6 generate, and receivers 324-1 to 324-6 detect, multi-PAM signals that allow multiple (k) bits to be transmitted or received as one of 2k possible voltages or data symbols at each clock edge or once per clock cycle. For example, one preferred embodiment is a 4-PAM system in which two bits are represented by 22 or four voltage levels, or data symbols, and the two bits are transferred at every clock edge by transferring an appropriate one of the four voltage levels. Therefore, the data rate of a 4-PAM system is twice that of a binary or 2-PAM system.
In FIG. 2, a graph shows one embodiment utilizing a 4-PAM signaling scheme. Specifically, the multi-PAM voltage levels are associated with two-bit binary values or symbols such as 00, 01, 10, and 11. In the embodiment of FIG. 2, the binary values are assigned to voltage levels using Gray coding, i.e. the symbol sequence from the highest voltage level to the lowest voltage level is 00, 01, 11, 10. Gray coding provides the advantage of reducing the probability of dual-bit errors because only one of the two bits changes at each transition between voltage levels. If a received 4-PAM voltage symbol is misinterpreted as an adjacent symbol, a single-bit error will occur.
The y-axis of the graph in FIG. 2 shows 4-PAM output voltages VOUT for each symbol. To provide the appropriate voltage to transmit a 4-PAM symbol, the output driver sinks a predetermined amount of current for that symbol. In particular, each symbol is associated with a different amount of current, from a minimum of zero to a maximum of I10. To transmit the symbol “00”, the output driver 323-1 to 323-6 sinks no current and the signal line is pulled up to VTERM. To transmit the symbol “01”, the bus output driver 323-1 to 323-6 sinks a predetermined amount of current I01 to cause the output voltage VOUT to equal VTERM−(I01×ZO), where I01 is equal to 1⁄3 I10. To transmit the symbol “11”, the bus output driver 323-1 to 323-6 sinks a predetermined amount of current I11 to cause the output voltage VOUT to equal VTERM−(I11×ZO), where I11 is equal to 2⁄3 I10. To transmit the symbol “10”, the bus output driver 323-1 to 323-6 sinks a predetermined amount of current I10 to cause the output voltage VOUT to equal VTERM −(I10×ZO).
A 4-PAM receiver identifies a received symbol based on a voltage range or range of voltages associated with that symbol. A set of reference voltages such as VREFLO, VREFM, and VREFHI functions as voltage thresholds to define ranges of voltages associated with each 4-PAM symbol. The reference voltages VREFLO, VREFM, and VREFHI are typically set at the midpoint voltage between neighboring symbols. For example, the symbol “00” is associated with voltages greater than VREFHI. The symbol “01” is associated with voltages falling within the range between VREFHI, and VREFM. The symbol “11” is associated with a range of voltages from VREFM to VREFLO. The symbol “10” is associated with a range of voltages less than VREFLO. The reference voltages VREFHI, VREFM, and VREFLO are threshold voltages from which a multi-PAM data symbol is determined to be one of the four possible data symbols.
4-PAM symbols or signals also allow for direct compatibility with 2-PAM or binary signaling. When operating in 4-PAM mode, the received data bits are compared to the three reference voltages, VREFHI, VREFM, and VREFLO to determine the 4-PAM symbol and the associated two bits. Because the most significant bit (MSB) is determined by comparing the received data bit to VREFM, i.e., the MSB is zero for voltages greater than VREFM and the MSB is one for voltages less than VREFM, the multi-PAM system can be used as a 2-PAM system by ignoring the least significant bit (LSB) and using the MSB. Alternatively, to transmit 2-PAM symbols using the gray code of FIG. 2, the LSB is set equal to zero (low), while the MSB determines the output voltage. More information on 2-PAM and multi-PAM systems may be found in the co-pending U.S. Patent Application entitled “Low Latency Multi-Level Communication Interface,” identified above and incorporated herein in its entirety and identified above.
Further, although the circuits described herein use 4-PAM signaling, the embodiments described can be expanded for use in 8-PAM, 16-PAM and, more generally, N-PAM signaling. Accordingly, it is to be understood that the preferred embodiments are not limited to 4-PAM signaling, but rather may be applied to the general, N-PAM signaling, case.
FIG. 3 shows a representation of a communication system that may be used to create voltage levels of FIG. 2. An output driver 420 drives signals to an output pad 418 and over a transmission line 416, which may, for example, be a memory bus or a different interconnection between devices affixed to a circuit board, to be received at a pad 425. The transmission line 416 has a characteristic impedance ZO 427 that is substantially matched to a terminating resistor ZO429 to minimize reflections. The output driver includes a first transistor current source 421, a second transistor current source 422, and a third transistor current source 423, which collectively produce a current I when all active, pulling the voltage at the pad 425 down from VTERM by I×ZO, signaling the logical state 10 under the Gray code system. To produce voltage VOUT=VTERM, signaling the logical state 00, current sources 421, 422, and 423 are all turned off. To produce voltage VOUT equal to VTERM−1⁄3 (I×ZO), signaling the logical state 01, one of the current sources is turned on, and to produce voltage VOUT equal to VTERM−2⁄3 (I×ZO), two of the current sources are turned on.
FIG. 4 illustrates an exemplary 4-PAM reference voltage generator 500 that generates the multi-PAM reference voltages VREFHI, VREFM, and VREFLO from external voltages, VTERM and VREF, supplied on input pins 502 and 504 respectively. Unity gain amplifiers 506, 508 receive and output the input voltages VTERM and VREF respectively. A voltage divider, including series-connected resistors R1, R2, and R3, is coupled between the outputs of the unity gain amplifiers 506 and 508. The lowest voltage VREF is selected to drive VREFLO via a power driver 514. Power drivers 510, 512 are coupled between resistors R1, R2, and R3 to provide reference voltages VREFHI and VREFM respectively. The power drivers 510-514 are connected as unity gain amplifiers.
In one embodiment, the resistor values are selected such that resistors R2 and R3 have twice the resistance of resistor R1, and VREF, which is supplied externally, is equal to the desired VREFLO voltage.
FIG. 5 illustrates an alternative embodiment of a 4-PAM reference voltage generator 600 for generating the multi-PAM reference voltages VREFHI, VREFM, and VREFLO from the external voltage VTERM supplied on an input pin 602. A voltage divider, including series-connected resistors R1, R2, R3, and R4, is coupled between the VTERM and a ground voltage supplied on an input pin 602. In one embodiment, the resistor values are chosen so that the compromise between the static power consumption and noise immunity is achieved. Thus, the resistor values may be selected so that not too much static power is burned, and, further, so that reference voltages are not susceptible to noise injection. However, it should be understood that the reference voltage generation is not limited to the use of the voltage generators illustrated in FIG. 4 or FIG. 5, and different or equivalent reference voltage generators may alternatively be used.
For cases in which attenuation of a signal exists between the signal's reception and transmission, different amounts of signal loss may occur depending upon the magnitude of the transition between logic levels. FIG. 6 illustrates attenuation affecting the transitory level obtained by a step. For instance, transitioning between the 10 state and the 00 state may have a greater signal deficiency than a transition between the 11 state and the 00 state, which in turn may have a greater signal deficiency than a transition between the 01 state and the 00 state, while maintaining the same logic state over plural bit periods may have no attenuation error. Thus, while the correct dc-level will eventually be achieved, each transition between states may have a different error associated with it.
FIG. 7 illustrates the addition of a different equalization signal 3S, 2S, or S to the main signal when driving different transitions to compensate for the attenuation of the received signal. The equalization signals in this embodiment are transitory, so that each signal may, for example, have a duration less than or equal to one bit signal, after which the equalization signal is terminated, allowing the initially overdriven signal to maintain a steady state logic level. In other words, the equalization signals S, 2S or 3S add predetermined high-frequency components to the transition signals that raise the slope of the edge of transition. However, a difficulty with this approach for a system such as shown in FIG. 3 is that the voltage can only be pulled down from the VTERM, unless negative current could flow through the current sources 421, 422, and 423. In other words, with the 00 level set at the VTERM, as illustrated in FIG. 2, it is difficult for the equalization signals S, 2S or 3S to add to the transition above the VTERM.
FIG. 8 depicts a multi-level (4-PAM) signaling system in which the 00 logic is reduced below VTERM by a predetermined amount in order to allow overdriving a transition, for example, from the 10 state to the 00 state by a predetermined equalization signal such as 3S via release of the pulldown current. This 00 logic level may be provided by having none of the main current drivers turned on and three equalization drivers turned on, to produce a voltage level of 0M+3S. The logical state 10 can be pulled lower, if necessary, to overdrive a transition, and it is characterized by having three main drivers turned on, for a total voltage level of 3M+0S. The logical state 01 is pulled down and may have a voltage of 1M+2S, while the state 11 may have a voltage of 2M+1S.
Table 1 illustrates drive signal levels involved in transitioning between the logical stats of FIG. 8.











TABLE 1







First Received
Transition drive
Second


From
To
Signal
Signal
Received Signal







00
10
0M + 3S
3M + 3S
3M + 0S


00
11
0M + 3S
2M + 3S
2M + 1S


00
01
0M + 3S
1M + 3S
1M + 2S


01
00
1M + 2S
0M + 2S
0M + 3S


01
11
1M + 2S
2M + 2S
2M + 1S


01
10
1M + 2S
3M + 2S
3M + 0S


11
00
2M + 1S
0M + 1S
0M + 3S


11
01
2M + 1S
1M + 1S
1M + 2S


11
10
2M + 1S
3M + 1S
3M + 0S


10
00
3M + 0S
0M + 0S
0M + 3S


10
01
3M + 0S
1M + 0S
1M + 2S


10
11
3M + 0S
2M + 0S
2M + 1S









In order to transition from the initial state 00 (0M+3S) to the final state 10 (3M+3S), for example, an overdriven transition drive signal of 3M+3S is provided. Conversely, changing from the initial state 10 (3M+0S) to the final state 00 involves a drive signal of 0M+0S. Table 1 illustrates one set of transition drive signals specific to a 4-PAM signaling system with a single error correction. However, it should be understood that the illustrated set of transition signals may be extrapolated to be used with communication systems having additional signal levels and additional error corrections. Further, it should be understand that similar transition drive signals could also be used in 2-PAM systems with equalization.
FIG. 9 is a schematic block diagram illustrating an exemplary device 700 that may provide the transition drive signals shown in FIG. 8. An encoder 702 receives binary MSB and binary LSB signals and converts pairs of those 2-PAM signals into digital input signals along lines C1, C2, and C3 for a main driver 705 having three current sources 711, 712, and 713, to convert the binary data of the MSB and LSB into 4-PAM data at an output pad 715. As illustrated in FIG. 9, a delay mechanism 718 also receives the input signals from the encoder 702. The delay mechanism 718 inverts and delays the input signals by a one-bit signal period to feed signals E1, E2, and E3 to an auxiliary driver 720 including auxiliary driver current sources 721, 722, and 723 that are similar to the respective main driver current sources 711, 712, and 713. However, each auxiliary driver current source 721, 722, and 723 has a gain that is a fraction of the respective main driver current sources 711, 712, and 713. Thus, when the main driver 705 outputs an output signal, the auxiliary driver 720 outputs a signal that is delayed, inverted and proportional to the output signal of the driver 705. The signals generated by the drivers 705 and 720 combine at the line 728 to form a desired signal. A detailed description of a preferred equalization system can be found in the co-pending U.S. patent application Ser. No. 09/654,643, entitled “Low Latency Equalization in Multi-Level, Multi-Line Communication Systems,” identified above. The preferred embodiments, however, are applicable to systems using other types of equalization, and the invention should not be construed as limited to systems including the described equalization methods.
Referring to Table 1, the main driver 705 can be represented with the letter M and the auxiliary driver 720 can be represented with the letter S, with the numeral proceeding each letter describing how many of the respective current sources are active. A ratio of the gain of the auxiliary driver, S, to that of the main driver, M, is termed k, the equalization coefficient of the auxiliary driver. The ratio k is less than one, and may range from about one percent to about fifty percent. Thus, the driving device on the bus knows the equalization current based on the equalization coefficient set on the auxiliary driver. In one embodiment, the drivers 705 and 720 and the delay element 718 of FIG. 9 may be represented as an FIR filter, where the input signals from the encoder 702 are sent to the filter, which operates on the signals to output a filtered signal.
Equalization techniques similar to those described above for the attenuation can be used to compensate for crosstalk and reflection errors. FIG. 10 and FIG. 11 including FIGS. 11A, 11B, 11C, 11D, and 11E, show a general system 800 using a self equalization FIR filter 806 and crosstalk (XTK) equalization FIR 804 and crosstalk equalization FIR filter 802 for filtering errors on a line V(n) due to crosstalk from adjacent lines A1(n) through AJ(n), respectively, to produce equalized output V(N).
FIG. 11A shows a step function signal 900 on the line A1 that generates, as shown in FIG. 11B, a transient signal 902 in line V due to inductive coupling. FIG. 11C shows an equalization signal 904 that is generated by inputting the signal 900 to the crosstalk equalization FIR filter 804 to compensate for transient signal 902. Capacitive crosstalk generated in line V from lines A1 through AJ can be equalized in a similar fashion. Both inductive and capacitive crosstalk may generate a transient signal having a polarity dependent upon the location of the receiver compared to the location at which the transient signal was generated. FIG. 11D shows a first signal component 906 that may be used to compensate for such an inductive or capacitive crosstalk error, which is a scaled and inverted function of the signal 900 that generated the error. FIG. 11E shows a second signal component 908 that may be added to the signal 906 to create the crosstalk equalization signal 904 of FIG. 11C. The signal 908 can be scaled or a fractional function of signal 900 that is delayed one bit period.
FIG. 12 illustrates an exemplary electrical schematic of a device 901 that may be coupled to a device illustrated in FIG. 9 and can be used to equalize inductive or capacitive errors created by signals in line 728 and sensed in lines that are adjacent to the line 728. A first crosstalk equalization driver 905 receives signals along lines C1, C2, and C3 that have been inverted by inverters 910 controlling current sources 711, 712, and 713. The combined current from the current sources 911, 912, and 913 is output on a crosstalk equalization line 920 that is connected to an adjacent line, not shown, that is subjected to crosstalk errors from the line 728. The output on the line 920 from the driver 905 is thus scaled and inverted compared to the signal produced by the main driver 705, much like the signal 906 of FIG. 11D is scaled and inverted compared to the signal 900 in FIG. 11A.
A second crosstalk equalization driver 925 receives input signals along lines X1, X2, and X3 that have been delayed by the delay 718, where the lines
X1, X2, and X3 control the current sources 921, 922, and 923. Thus, the output of the second crosstalk equalization driver 925 on the line 920 is delayed and scaled compared to the signals produced by the main driver 705, much like the signal 908 of FIG. 11E is scaled and delayed compared to the signal 900 in FIG. 11A. The combined output of the crosstalk equalization driver 905 and 925 on the line 920 is much like the signal 904 of FIG. 11C, which can be used to compensate for the transient signal 902 of FIG. 11B. Thus, the crosstalk equalization drivers 905 and 925 can compensate for the crosstalk inflicted by the line 728 on nearby lines. Similarly to the equalization cancellation, the crosstalk cancellation employs a predetermined crosstalk cancellation current based on the crosstalk coefficients used in the system. More information on alternative embodiments for equalization and crosstalk cancellation may be found in the co-pending U.S. patent application Ser. No. 09/654,643, entitled “Low Latency Equalization in Multi-Level, Multi-Line Communication Systems,” identified above. The preferred embodiments, however, are applicable to systems using other types of equalization and crosstalk cancellation, and the invention should not be construed as being limited to systems that include equalization and crosstalk cancellation.
As mentioned in reference to FIG. 8, in order to compensate for attenuation, crosstalk or reflection errors using, for example, the equalization drivers illustrated in FIG. 12, the highest output logic state is reduced below the VTERM and the lower logic states are shifted respectively based on the equalization and/or crosstalk currents that are used on a device to compensate for signal errors. In such an embodiment, the VREFHI, VREFM, and VREFLO are no longer centered on the shifted data eyes, and thus do not track errors associated with the current control.
Typically, an electronic device on a bus, such as the bus 320 illustrated in FIG. 1, does not set its equalization or crosstalk coefficients until it is assigned to a predetermined signal line, or a signal channel, such as one of the signal lines 320-1 or 320-2 illustrated in FIG. 1. However, when a device is put on a signal line, the device adapts a predetermined set of equalization and/or crosstalk coefficients based on the characteristics of the signal line. Thus, any device on the bus, once put on a signal line, has a direct knowledge of its default and crosstalk currents that shift the logic states down in order to allow equalization and crosstalk signals to overdrive logic state transitions. In accordance with a preferred embodiment, the reference voltage levels are shifted correspondingly to the logic state shifts so that the reference voltage levels provide accurate threshold levels.
Exemplary embodiments for reference voltage generation will be described hereinafter in reference to a 4-PAM system. However, it should be understood that the exemplary embodiments are equally applicable in 2-PAM or N-PAM systems.
FIG. 13 illustrates a 4-PAM voltage generator 1000 that generates the multi-PAM reference voltages VREFHI, VREFM, and VREFLO on respective reference-voltage nodes 1008, 1010, and 1012 from the external voltage VTERM supplied on a voltage pin 1002 using a voltage divider, where the reference voltage levels reflect the shifts in the logic state level shifts in a system employing equalization and/or crosstalk signals. The voltage divider, including series-connected resistors R1, R2, R3, and R4, is coupled between the voltage pin 1002 supplying the VTERM and a voltage pin 1006 supplying a VGROUND.
According to an embodiment illustrated in FIG. 13, one or more active devices on a channel, such as an active device 1004, level-shifts the reference voltage levels based on the logic state shifts. As mentioned in the preceding paragraphs, the logic states are shifted down based on predetermined equalization and crosstalk currents applied by a device on a bus. As illustrated in FIG. 13, the active device 1004 includes an active current source generating an offset current (“IOFFSET”) that is controlled by one or more current control signals (“CCS”) 1016. In one embodiment, the CCS 1016 is controlled by a set of equalization and crosstalk coefficients used by a device on the bus so that the active device 1004 draws a scaled amount of the current used for the highest logic state equalization and crosstalk cancellation. In an embodiment, a scale factor associated with the equalization and crosstalk current corresponds to a ratio of the termination resistor ZO and the first resistor R1 of the voltage divider. In such an embodiment, the IOFFSET is equal to IEQ,XTC×(ZO/R1), where the IEQ,XTC corresponds to a combined equalization and crosstalk current used by a device on a bus. Thus, the active device 1004 pulls down the reference voltage levels VREFHI, VREFM, and VREFLO according to the voltage shifts of the logic states. Table 2 illustrates reference voltage levels for the 4-PAM device that may be implemented using the active device illustrated in FIG. 13.








TABLE 2





Reference



Voltage Level
Output Voltage







VREFHI




  
    V
    REFHI
  
  =
  
    
      
        V
        TERM
      
      ⁡
      
        (
        
          
            
              R
              ⁢
              
                
              
              ⁢
              2
            
            +
            
              R
              ⁢
              
                
              
              ⁢
              3
            
            +
            
              R
              ⁢
              
                
              
              ⁢
              4
            
          
          
            
              R
              ⁢
              
                
              
              ⁢
              1
            
            +
            
              R
              ⁢
              
                
              
              ⁢
              2
            
            +
            
              R
              ⁢
              
                
              
              ⁢
              3
            
            +
            
              R
              ⁢
              
                
              
              ⁢
              4
            
          
        
        )
      
    
    -
    
      R
      ⁢
      
        
      
      ⁢
      
        1
        ·
        
          I
          OFFSET
        
      
    
  






 


VREFM




  
    V
    REFM
  
  =
  
    
      V
      REFHI
    
    ⁡
    
      (
      
        
          
            R
            ⁢
            
              
            
            ⁢
            3
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            4
          
        
        
          
            R
            ⁢
            
              
            
            ⁢
            2
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            3
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            4
          
        
      
      )
    
  






 


VREFLO




  
    V
    REFM
  
  =
  
    
      V
      REFHI
    
    ⁡
    
      (
      
        
          R
          ⁢
          
            
          
          ⁢
          4
        
        
          
            R
            ⁢
            
              
            
            ⁢
            2
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            3
          
          +
          
            R
            ⁢
            
              
            
            ⁢
            4
          
        
      
      )
    
  













According to the output voltage levels illustrated in Table 2, the active device 1004 pulls a predetermined amount of current from the VREFHI level based on the equalization and crosstalk settings used on a device. Further, as illustrated in Table 2, the lower reference voltage levels VREFM and VREFLO are shifted based on the VREFHI level so that the new levels for the VREFM and VREFLO provide accurate threshold levels for the logic states below the highest logic state.
However, it should be understood that more than one active device could also be used, and the present invention is not limited to the use of a single active device. In a bi-directional or multi-drop bus, e.g. a memory bus, having a number of individual drivers, each with different equalization or crosstalk coefficients, each driver on a channel may have an active device to shift the reference voltage levels. In such an embodiment, the amount of current to make the VREF shift may be equal to a ratio of that current to the equalization/crosstalk component so that the current is properly ratioed. Further, it should be understood that the reference voltage generation according to an exemplary embodiment is not limited to using the voltage generator 1000 illustrated in FIG. 13.
FIG. 14 is an electrical schematic 1050 of a multi-level voltage generator that reflects logic state shifts due to equalization or crosstalk cancellation and utilizes the op-amp drive references illustrated in FIG. 4. As illustrated in FIG. 14, one or more active current sources, such a current source 1052, generates an offset current (“IOFFSET”) that is controlled by one or more CCS 1054. The current source 1052 shifts the reference voltage levels based on equalization or crosstalk cancellation parameters. In the illustrated embodiment, the offset current pulls down the op-amp reference voltage levels as discussed in greater detail in reference to FIG. 13.
FIG. 15 illustrates an alternative embodiment of an electronic circuit 1100 that generates level-shifted reference voltages VREFHI, VREFM, and VREFLO via on-chip VREF drivers. An output driver 1104 drives signals to an output pad 1103 and over a transmission line having a characteristic impedance ZO 1118 that is substantially matched to a terminating resistor RTERM to minimize reflection. The output driver 1144 may include three current sources, as illustrated in FIG. 3, which together produce a current I 1130 when all are active, pulling the voltage at the pad 1106 down from VTERM, signaling the logical state 10 under the Gray code system, as illustrated in FIG. 2. To produce the remaining logical states, some of the transistors in the current drivers are deactivated, as described in reference to FIG. 2.
FIG. 15 illustrates three additional drivers for generating the VREFHI, VREFM, and VREFLO. For example, the current driver 1156 drives into a terminating resistor RTERM 1112 half of the current that would normally be driven to generate the logical state 01 under the Gray code system and, further, shifts the VREFHI level according to the equalization and crosstalk currents applied on the chip. Thus, the current driver 1134 drives a current I/6 to generate the VREFHI level that is further shifted by the current driver 1136 to compensate for the equalization and crosstalk.
Similarly, to generate the VREFM voltage level, a current driver 1158 drives into a terminating resistor RTERM 1114 three-fourths of the current that would normally be driven to generate the logical state 11 under the Gray code system, and, further, shifts the VREFM level according to the equalization and crosstalk current applied on the chip. Thus, the current driver 1140 drives a current I2 to generate the VREFM level that is further shifted by the current driver 1142 to compensate for the equalization and crosstalk.
Finally, as illustrated in FIG. 15, to generate the VREFLO voltage level, a current driver 1160 drives into a terminating resistor RTERM 1116 five-sixth of the current that would normally be driven to generate the logical state 10 under the Gray code system and, further, shifts the VREFLO level according to the equalization and crosstalk currents applied on the chip. Thus, the current driver 1144 drives a current 5⁄6×I to generate the VREFLO level that is further shifted by the current driver 1146 to compensate for the equalization and crosstalk. According to one embodiment, the equalization current drivers 1136, 1142, and 1146 drive currents that induce the voltage shift used to compensate for crosstalk and equalization.
Two reference current generation techniques have been described in reference to FIGS. 13, 14, and 15. However, any one of those could be eliminated, and an off-chip voltage divider could be used instead. In such an embodiment, for example, the VREFM could be used from a 2-PAM-compatible-style board.
Referring to FIG. 16, a method 1200 for generating at least one reference voltage level for a driver employing equalization and crosstalk cancellation will be described.
At step 1202, a reference voltage generator generates at least one reference voltage. For example, in a 2-PAM system, the voltage generator generates one reference voltage, and in a 4-PAM system, the voltage generator generates three reference voltage levels. In one embodiment, the voltage generator may include the reference voltage generators described in reference to FIG. 13, 14, or 15; however, different voltage generators could also be used.
At step 1204, at least one current control signal is determined. The at least one current control signal may include an equalization current control signal, a crosstalk current control signal, or the combination of both.
At step 1206, at least one reference voltage level generated by the reference voltage generator is adjusted based on the at least one current control signal determined at step 1204. According to an exemplary embodiment, the at least one reference voltage level is shifted down based on the shift of the highest logic state required by the use of the control signals.
It should be understood that the method 1200 is only an exemplary method, and different or equivalent methods may be used to generate reference voltages based on at least one control signal such as an equalization current control signal or a crosstalk signal.
In FIG. 17, a 4-PAM output driver corrects the gds distortion and provides current control. As described above, the signals A, B, and C preferably determine the output voltage or symbol in accordance with the gray-coded binary signaling shown in Table 2, above. In addition, three sets of current control calibration bits, CC, CCB, and CCC, respectively determine the amount of current supplied by the output driver for various combinations of A, B, and C. The first set of control bits CC provides primary current control, while the second and third sets of current control bits, CCB and CCC, respectively, fine tune the amount of current. The first set of current control bits CC has N bits; the second set of current control bits CCB has n1 bits; and the third set of current control bits CCC has n2 bits. In one embodiment, the relationship between the number of current control bits is as follows:

n1≦n2<N.

There may be different relationships between N, n1 and n2 in alternative embodiments.
Each of the A, B, and C signals is associated with a current drive block 1740-1 to 1740-3 to drive a predetermined amount of current associated with the symbol. Each current drive block 1740-1 to 1740-3 includes one or more sets of stacked transistor pairs that are associated with each set of current control bits for that current driver block 1740-1 to 1740-3. For example, the current drive block 1740-1 that drives the A signal receives current control bits CC. The current drive block 1740-2 that drives the B signal receives current control bits CC and CCB. The amount of current supplied by current drive block 1740-2 is adjusted for gds distortion using the CCB bits. The current drive block 1740-3 that drives the C signal receives current control bits CC and CCC. The amount of current supplied by current drive block 1740-3 is adjusted for gds distortion using the CCC bits.
As shown in FIG. 18, a current control calibration circuit 1850 determines the settings for the current control bits CC, CCB, and CCC by selecting a current control reference voltage, VREF, and comparing the current control reference voltage, VREF, to a voltage at a mid-point between two calibration output voltages, VOUT-1 and VOUT-2. The current calibration circuit 1850 determines settings for each of the sets of current control bits CC, CCB, and CCC for each 4-PAM output voltage such that VOUT-1 and VOUT-2 provide each adjacent pair of voltage levels to the circuit.
A multiplexer 1852 receives the three 4-PAM reference voltages VREFHI, VREFM, and VREFLO. A select reference voltage signal, SelRef, selects one of the referenced voltages as the selected current control reference voltage, VREF. A comparator 1854 compares the selected current control reference voltage VREF to a mid-point voltage VX and generates a comparison signal.
To generate the mid-point VX, output driver 1 1856 sinks a first amount of current to provide the first output voltage VOUT-1 and output diver 2 1858 sinks a second amount of current to provide the second output voltage VOUT-2. Two passgate pairs 1860 and 1862, in response to a current control enable and its complementary signal, act as a resistor divider to provide the midpoint voltage, VX, between the first output voltage, VOUT-1, and the second output voltage, VOUT-2.
A state machine 1864 includes first, second, and third counters 1866-1, 1866-2, and 1866-3 that provide the first, second, and third sets of current control bits, CC, CCB, and CCC, respectively. If the comparison signal indicates that the midpoint signal VX is greater than the reference voltage VREF, the state machine 1864 increments an associated set of current control bits by one to increase the amount of current that is sunk by the output driver, thereby decreasing the midpoint voltage. If the midpoint voltage signal VX is less than the current control reference voltage, VREF, the state machine 1864 decrements the associated current control bits by one, thereby increasing the midpoint voltage.
In one embodiment, the current control bits are calibrated during a power-up sequence. The theory of operation for calibrating the current control bits is as follows. The first set of current control bits CC provide the primary amount of current control for each current control block 1740 (FIG. 17). To compensate for gds distortion, the CCB and CCC current control bits fine tune the amount of current associated with the Gray-coded “11” and “10” signals, respectively. The current control bits are calibrated in the following order: CC, CCB, and then CCC.
The first and main set of current control bits CC are set using the voltage differences between the “00” and “01” symbols. The first set of current control bits CC are set to provide an amount of current to provide the output voltage for the “01” symbol such that VREFHI is placed at the midpoint between the output voltage for the “00” symbol and the output voltage for the “01” symbol.
Because of gds distortion, without compensation, the voltage difference between the “01” symbol and the “11” symbol is less than the voltage difference between the “00” symbol and the “01” symbol. To compensate for the gds distortion, the output voltage for the “11” symbol is decreased by increasing the amount of current sunk by the output driver. The second set of current control bits CCB are set to increase the current sunk by the output driver such that the output voltage becomes equal to the desired voltage level when the midpoint voltage between output voltage for the “01” and “11” is equal to VREFM.
Finally, the third set of current control bits CCC is adjusted such that the midpoint voltage between output voltage for the “11” and “10” is equal to VREFLO.
Referring to FIGS. 18, 19A, and 19B, the operation of the circuit 1850 including the state machine 1864 will be described. The flowchart of FIGS. 19A and 19B uses gray coded output voltages. In step 1970, the current control enable signal (ccen) and its complement (ccenb) are set to activate the passgate pairs 1860 and 1862 and output the midpoint voltage VX, described above.
Three major blocks of steps 1972, 1974, and 1976 set the current control bits, CC, CCB, and CCC, respectively.
In block 1972, step 1978 sets the initial conditions for determining the settings for the first set of current control bits CC. The state machine 1864 outputs the select reference voltage signal (SelRef) which causes the multiplexer 1852 to output the reference voltage VREFHI to the comparator 1854. A “00” symbol is supplied to output driver 1 1856 by outputting multi-PAM bit selection signals A1, B1, and C1 with values of zero. A “01” symbol is supplied to output driver 2 1858 by outputting multi-PAM bit selection signals A2 with a value of one, and B2 and C2 with a value of zero. The initial state of the first, second and third current control bits is as follows:

CC={1 0 0 . . . 0};

CCB={1 0 0 . . . 0}; and

ti CCC={1 0 0 . . . 0}.

The current control bits are initially set such that the stacked transistor pair sinking the most current will be activated.
In step 1980, the output drivers 1 and 2 output the voltages corresponding to the symbols “00” (the VTERM reference) and “01” (the drive level under calibration) and the midpoint voltage VX is generated. In step 1982, the comparator 1854 compares the midpoint voltage VX to the selected reference voltage VREFHI. When the midpoint voltage is within one least significant bit of the reference voltage VREFHI, the first set of current control bits have the proper setting. The state machine 1864 determines that the midpoint voltage VX is within one least significant bit of the reference voltage VREFHI when the current control bits begin to dither between two settings. In other words, the output of the comparator will alternate between a zero and a one.
In step 1984, when the midpoint voltage VX is not within one least significant bit of the reference voltage VREFHI, the state machine 1864 augments the first set of current control bits depending on the result of the comparison. The term “augment” is used to indicate either incrementing or decrementing the current control bits. The process proceeds to step 1980.
If, in step 1982, the state machine 1864 determines that the midpoint voltage VX is within one least significant bit of the reference voltage, the process proceeds to step 1986 to calibrate the second set of current control bits, CCB.
In step 1986, the initial conditions for calibrating the second set of current control bits CCB are set. The state machine 1864 outputs the select reference voltage signal (SelRef) which causes the multiplexer 1852 to output the reference voltage VREFM to the comparator 1854. A “01” symbol is supplied to output driver 1 1856 by outputting multi-PAM bit selection signals Al with a value of one, and B1 and C1 with values of zero. A “11” symbol is supplied to output driver 2 1858 by outputting multi-PAM bit selection signals A2 and B2 with a value of one, and C2 with a value of zero. The state of the first set of current control signals CC remains unchanged. The initial state of the second and third sets of current control bits, CCB and CCC, respectively, is as follows:

CCB={1 0 0 . . . 0};

CCC={1 0 0 . . . 0}.

In step 1988, the output drivers 1 1856 and 2 1858 output the voltages corresponding to the symbols “01” (the level calibrated in step 1072) and “11” (the level now under calibration), and the passgate pairs 1860 and 1862 output the midpoint voltage VX. In step 1990, the comparator 1854 compares the midpoint voltage VX to the selected reference voltage VREFM. When the midpoint voltage is not within one least significant bit of the reference voltage VREFM, as described above with respect to VREFHI, in step 1992, the state machine 1864 augments the second set of current control bits CCB by one and the process repeats at step 1986.
When the midpoint voltage is within one least significant bit of the reference voltage VREFM, as described above with respect to VREFHI, the second set of current control bits CCB have the proper setting and the process proceeds to step 1994 to calibrate the third set of current control bits, CCC.
In step 1994, the initial conditions for calibrating the third set of current control bits CCC are set. The state machine 1864 outputs the select reference voltage signal (SelRef), which causes the multiplexer 1854 to output the reference voltage VREFLO to comparator 1854. A “11” symbol (calibrated in step 1074) is supplied to output driver 1 1856 by outputting multi-PAM bit selection signals A1 and B1 with a value of one, and C1 with a value of zero. A “10” symbol (the level now under calibration) is supplied to output driver 2 1858 by outputting multi-PAM bit selection signals A2, B2, and C2 with a value of one. The state of the first and second sets of current control signals CC and CCB, respectively, remains unchanged. The initial state of the third set of current control bits CCC is as follows:

CCC={1 0 0 . . . 0}.

In step 1996, the output drivers 1 1856 and 2 1858 output the voltages corresponding to the symbols “11” and “10” and the passgate pairs 1860 and 1862 output the midpoint voltage VX. In step 1998, the comparator 1854 compares the midpoint voltage VX to the selected reference voltage VREFLO. When the midpoint voltage is not within one least significant bit of the reference voltage VREFLO, as described above with respect to VREFHI, in step 1999, the state machine 1864 augments the third set of current control bits CCC by one and the process repeats at step 1996.
In step 1998, when the midpoint voltage is within one least significant bit of the reference voltage VREFLO, the appropriate settings for the first, second, and third sets of current control bits, CC, CCB, and CCC respectively are determined and the calibration is complete.
For the foregoing embodiment, a sequential search is described: starting at an initial value and augmenting. It should be emphasized, however, that alternative search techniques known to those skilled in the art may be used. For example, without limiting the foregoing, successive approximation using a binary search may be used. As a further alternative, a direct flash conversion may be used. This alternative is less desirable, however, because it is hardware intensive.
While the invention has been described in connection with a number of preferred embodiments, the foregoing is not intended to limit the scope of the invention to a particular form, circuit arrangement, or semiconductor topology. To the contrary, the invention is intended to be defined by the appended claims and to include such alternatives, modifications and variations as may be apparent to those skilled in the art upon reading the foregoing detailed description.

## Claims

1. In a system in which a sending device sends a signal to a receiving device, and in which the receiving device is provided with a reference voltage, an improvement comprising:
a voltage divider network having a plurality of impedances to generate a divided voltage for use as the reference voltage;
a control to adjust the reference voltage provided by the voltage divider network;
wherein the control is adjusted in association with an attenuation affecting the signal, such that the reference voltage provided to the receiving device is varied with attenuation.

2. The improvement of claim 1, wherein:
the improvement further comprises operatively coupling a transmitter current source to the voltage divider network;
the attenuation includes attenuation based on a current associated with the transmitter current source; and
the voltage divider network is adapted to vary the reference voltage in at least partial response to the current.

3. The improvement of claim 2, wherein operatively coupling the transmitter current source to the voltage divider network includes drawing current from at least one node within the voltage divider network in a manner such that the reference voltage is pulled down with current draw of the transmitter current source.

4. The improvement of claim 3, further comprising using a voltage divider network that provides multiple reference voltages that are different from each other, each reference voltage adapted for use in multi-level signal discrimination, and providing at least one of the multiple reference voltages to the receiving device.

5. The improvement of claim 1, wherein the voltage divider network includes at least two impedances and wherein at least one of the impedances consists of a resistor.

6. The improvement of claim 1, wherein:
the control includes a current signal representing a current associated with a bus driver;
the improvement further comprises coupling the current signal to the voltage divider network, to cause variation of the reference voltage in at least partial response to variation of the current associated with the bus driver; and
the attenuation includes attenuation associated with the current.

7. The improvement of claim 1, wherein:
the attenuation includes attenuation based on transmission path associated with a specific receiving device; and
the improvement further comprises adjusting at least one of the voltage divider network or a voltage provided to the network to pull down the reference voltage in association with the attenuation.

8. The improvement of claim 7, adapted for use in a memory system that includes multiple devices and a multi-drop bus, the improvement further comprising adjusting the reference voltage in response to an active device.

9. The improvement of claim 1, adapted for use in a memory system in which the sending device and the receiving device are each embodied as a chip, the improvement further comprising embodying the voltage divider network as an off-chip voltage divider.

10. The improvement of claim 1, further comprising adjusting the reference voltage in response to a current draw.

11. The improvement of claim 10, further comprising operatively coupling to the voltage divider network a current draw associated with at least one bus driver, to draw current in dependence upon at least some current drawn by the at least one bus driver, to responsively adjust the reference voltage.

12. The improvement of claim 1, wherein the sending device is a memory controller and the receiving device is a memory, and wherein the memory device when accessed has a reference voltage adjusted based on attenuation associated with access.

13. The improvement of claim 1, wherein the sending device is a memory and the receiving device is a memory controller.

14. In a memory system, a method, comprising:
sending data to a recipient;
providing a reference voltage to the recipient for use in discriminating at least one logic level shift represented by the data; and
pulling the reference voltage down in association with attenuation in sending the data to the recipient.

15. The method of claim 14, further comprising using a voltage divider network that is off-chip with respect to each of a memory and a memory controller, to pull down the reference voltage in association with the attenuation.

16. The method of claim 14, further comprising pulling down the reference voltage in response to attenuation associated with a current of at least one bus driver.

17. The method of claim 14, further comprising pulling down the reference voltage in response to transmission attenuation associated with signal path between a sending device and the recipient.

18. The method of claim 14, further comprising pulling down the reference voltage in response to attenuation associated with physical layout of a bus.

19. A system, comprising:
a memory controller;
a memory;
a voltage divider network for providing a reference voltage for use by at least one of the memory controller or the memory;
a voltage divider input for causing the voltage divider network to adjust the reference voltage in association with attenuation of communication between the memory controller and the memory.

20. The system of claim 19, wherein the voltage divider input is adjusted in association with at least one characteristic associated with transmission path between the memory controller and the memory.

21. The system of claim 20, wherein the at least one characteristic includes current draw of a bus driver associated with transmission between the controller and the memory device.