# Patent

## Title
Correction circuit of a switching-current sample for power converters in both CCM and DCM operation

## Abstract

The present invention provides a correction circuit for a power converter. The correction circuit includes a sampling circuit, a demagnetizing-time circuit, a duty circuit, and a compensation circuit. The sampling circuit generates an average-current signal in response to a switching current of the power converter. The demagnetizing-time circuit generates a discharging-time signal in response to a switching signal and an input-voltage signal. The duty circuit generates a duty signal in response to the discharging-time signal, an on-time of the switching signal, and a switching period of the switching signal. The compensation circuit is coupled to receive the average-current signal and the duty signal for generating a corrected signal. The switching signal is utilized to switch a magnetic device for regulating an output voltage of the power converter. The corrected signal is coupled to generate the switching signal.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 61/383,484, filed on Sep. 16, 2010, the contents of which are incorporated herein by reference.


BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to power converters, and, more specifically, the present invention relates to boost power converters.
2. Description of the Related Art
FIG. 1 shows a conventional PFC (power factor correction) power converter, which is embodied in boost topology. The PFC power converter comprises a bridge rectifier 10, a magnetic device 15, a controller 90, a power switch 20, a rectifier 40, a capacitor 50, a line resistor 35, a current-sensing resistor 25, and a voltage divider. The controller 90 comprises a line terminal LN, an output terminal SW, a feedback terminal FB, a sensing terminal VN, and a ground terminal GND. The bridge rectifier 10 rectifies an AC line voltage VAC into an input voltage VIN. The magnetic device 15, which is an inductor for example, is connected between an output of the bridge rectifier 10 and an anode of the rectifier 40. A first terminal of the power switch 20 is connected to the anode of the rectifier 40. A second terminal of the power switch 20 is connected to a ground reference. The line resistor 35 is coupled to detect the input voltage VIN for providing an input-voltage signal IAC to the line terminal LN of the controller 90. The capacitor 50 is connected between a cathode of the rectifier 40 and the ground reference. The controller 90 generates a switching signal SW via its output terminal SW to a control terminal of the power switch 20 for generating an output voltage VO, which is obtained across the capacitor 50. The voltage divider formed by resistors 71 and 72 is connected in parallel with the capacitor 50. A joint of the resistors 71 and 72 provides a feedback signal VFB, which is proportional to the output voltage VO, to the feedback terminal FB of the controller 90. The current-sensing resistor 25 is connected between the second terminal of the power switch 20 and the sensing terminal VN of the controller 90. Referring to FIG. 1, as the power switch 20 is turned on, a switching current IL of the magnetic device 15 will be equal to a charging current IW flowing via the power switch 20 and return to the bridge rectifier 10 via the current-sensing resistor 25 (charging path). As the power switch 20 is turned off, since the polarity of the magnetic device 15 reverses, the switching current IL will be equal to a discharging current IDS flowing via the rectifier 40 and return to the bridge rectifier 10 via the current-sensing resistor 25 (discharging path). The current-sensing resistor 25 is coupled to sense the switching current IL of the magnetic device 15. Since the current-sensing resistor 25 is connected via both the charging path and the discharging path of the magnetic device 15, the switching current IL sensed by the current-sensing resistor 25 can be calculated as a switching current average. As a result, the technique used in the circuit schematic of FIG. 1 is the well known “average-current control technique”. However, the drawback of PFC power converters utilizing this technique is higher power consumption across the current-sensing resistor 25. Furthermore, these PFC power converters also fail to be connected in parallel to achieve higher efficiency, such as the solution shown in an U.S. Pat. No. 7,626,372 titled “Control Circuit for Multi-phase, Multi-channels PFC Converter with Variable Switching Frequency”.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for correcting the switching current sample of a boost power converter operated in a CCM (continuous current mode) and a DCM (discontinuous current mode).
The present invention provides a correction circuit for a power converter. The correction circuit comprises a sampling circuit, a demagnetizing-time circuit, a duty circuit, and a compensation circuit. The sampling circuit generates an average-current signal in response to a switching current of the power converter. The demagnetizing-time circuit generates a discharging-time signal in response to a switching signal and an input-voltage signal. The duty circuit generates a duty signal in response to the discharging-time signal, an on-time of the switching signal, and a switching period of the switching signal. The compensation circuit is coupled to receive the average-current signal and the duty signal for generating a corrected signal. The switching signal is utilized to switch a magnetic device for regulating an output voltage of the power converter. The discharging-time signal is correlated to a demagnetizing time of the magnetic device. The input-voltage signal is correlated to an input voltage of the magnetic device. The corrected signal is coupled to generate the switching signal.
The average-current signal is generated in response to the switching current in a CCM (continuous current mode) operation. The duty signal is coupled to correct the average-current signal for generating the corrected signal when the switching current is operated in a DCM (discontinuous current mode). A maximum value of the corrected signal is equal to the average-current signal. The output voltage of the power converter is coupled to the demagnetizing-time circuit to generate the discharging-time signal. The correction circuit also comprises a period-time circuit generating a period signal in response to the switching period of the switching signal. The period signal is coupled to the duty circuit for generating the duty signal. The duty circuit comprises an available-time circuit generating an available signal in response to the on-time of the switching signal and the discharging-time signal.
The duty circuit further comprises a duty-time circuit. The duty-time circuit comprises a capacitor, a current-source circuit, and a comparator. The current-source circuit generates a charging current in response to the period signal. The charging current charges the capacitor for generating a ramp signal. The comparator is coupled to receive the ramp signal and the available signal for generating the duty signal. The power converter is a boost power converter.
The present invention also provides a method of correcting a switching-current sample for a power converter. The method comprises: generating a discharging-time signal in response to a switching signal and an input-voltage signal; generating a duty signal in response to the discharging-time signal, an on-time of the switching signal, and a switching period of the switching signal; and generating a corrected signal in response to an average-current signal and the duty signal. The switching signal is utilized to switch a magnetic device for regulating an output voltage of the power converter. The discharging-time signal is correlated to a demagnetizing time of the magnetic device. The input-voltage signal is correlated to an input voltage of the magnetic device. The average-current signal is generated in response to a switching current of the power converter. The corrected signal is coupled to generate the switching signal.
The average-current signal is generated in response to the switching current in a CCM (continuous current mode) operation. The duty signal is coupled to correct the average-current signal which is the switching-current sample for generating the corrected signal when the switching current is in a DCM (discontinuous current mode) operation. A maximum value of the corrected signal is equal to the average-current signal. The output voltage of the power converter is coupled to generate the discharging-time signal. The method further comprises generating a period signal in response to the switching period of the switching signal. The period signal is utilized to generate the duty signal. The power converter is a boost power converter.
The present invention also provides an apparatus for correcting a switching-current sample of a power converter. The apparatus comprises a demagnetizing-time circuit, a duty circuit, and a compensation circuit. The demagnetizing-time circuit generates a discharging-time signal in response to a switching signal and an input-voltage signal. The duty circuit generates a duty signal in response to the discharging-time signal and the switching signal. The compensation circuit is coupled to receive an average-current signal and the duty signal for generating a corrected signal. The switching signal is utilized to switch a magnetic device of the power converter. The discharging-time signal is correlated to a demagnetizing time of the magnetic device. The input-voltage signal is obtained via a resistor coupled to an input voltage of the magnetic device. The average-current signal is generated in response to a switching current of the power converter. The corrected signal is coupled to generate the switching signal.
The average-current signal is generated in response to the switching current in a CCM (continuous current mode) operation. The duty signal is coupled to correct the average-current signal for generating the corrected signal when the switching current is in a DCM (discontinuous current mode) operation. A maximum value of the corrected signal is equal to the average-current signal.
The present invention further provides an apparatus for correcting a switching-current sample of a power converter. The circuit comprises a detection circuit, a duty circuit, a compensation circuit. The detection circuit is coupled to an auxiliary winding of a magnetic device of the power converter for generating a discharging-time signal. The duty circuit generates a duty signal in response to the discharging-time signal and a switching signal. The compensation circuit is coupled to receive an average-current signal and the duty signal for generating a corrected signal. The switching signal is utilized to switch the magnetic device. The discharging-time signal is correlated to a demagnetizing time of the magnetic device. The average-current signal is generated in response to a switching current of the power converter. The corrected signal is coupled to generate the switching signal.
The average-current is generated in response to the switching current in a CCM (continuous current mode) operation. The duty signal is coupled to correct the average-current signal for generating the corrected signal when the switching current is in a DCM (discontinuous current mode) operation. A maximum value of the corrected signal is equal to the average-current signal. The power converter is a boost power converter.
It is an object of the present invention to correct the switching-current sample of a power converter in a DCM operation.
It is also an object of the present invention to achieve high efficiency by connecting PFC converters in parallel with precise average-current control.
A detailed description is given in the following embodiments with reference to the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
FIG. 1 shows a conventional PFC power converter.
FIG. 2 shows an embodiment of a PFC power converter according to the present invention.
FIG. 3 shows waveforms of a switching signal, a switching current, a charging current, and a discharging current in a CCM operation.
FIG. 4 shows waveforms of the switching signal, the switching current, a charging current, and the discharging current in a DCM operation.
FIG. 5 shows an embodiment of a controller of the PFC power converter in FIG. 2.
FIG. 6 shows a waveform of a current-sensing signal and relationship between the current-sensing signal and the average-current signal.
FIG. 7 shows an embodiment of a duty-cycle circuit of the controller in FIG. 5.
FIG. 8 shows waveforms of a saw-tooth signal, a pulse signal, a sampling signal, and a clearing signal.
FIG. 9 shows an embodiment of a period-time circuit of the duty-cycle circuit according to the present invention.
FIG. 10 shows an embodiment of a demagnetizing-time circuit of the duty-cycle circuit according to the present invention.
FIG. 11 shows an embodiment of a current generator of the demagnetizing-time circuit according to the present invention.
FIG. 12 shows an embodiment of an available-time circuit of the duty-cycle circuit according to the present invention.
FIG. 13 shows an embodiment of a duty-time circuit of the duty-cycle circuit according to the present invention.
FIG. 14 shows an embodiment of a compensation circuit of the controller according to the present invention.
FIG. 15 shows another embodiment of a PFC power converter according to the present invention.
FIG. 16 shows an embodiment of a controller of the PFC power converter in FIG. 15.
FIG. 17 shows an embodiment of a duty-cycle circuit of the controller in FIG. 16.



DETAILED DESCRIPTION OF THE INVENTION
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sensing. The scope of the invention is best determined by reference to the appended claims.
FIG. 2 shows an embodiment of a PFC (power factor correction) power converter according to the present invention. In the embodiment, the PFC power converter is implemented by a boost power converter. The PFC power converter comprises a bridge rectifier 10, a magnetic device 15, a controller 100, a power switch 20, a rectifier 40, a capacitor 50, a line resistor 35, a current-sensing resistor 30 and a voltage divider. The controller 100 is also referred to a correction circuit and comprises a line terminal LN, an output terminal SW, a feedback terminal FB, a sensing terminal VI, and a ground terminal GND. The bridge rectifier 10 rectifies an AC line voltage VAC into an input voltage VIN. The magnetic device 15, which is an inductor in one embodiment of the present invention, is connected between an output of the bridge rectifier 10 and an anode of the rectifier 40. A first terminal of the power switch 20 is connected to the anode of the rectifier 40. A second terminal of the power switch 20 is connected to a ground reference via the current-sensing resistor 30. The line resistor 35 is coupled to detect the input voltage VIN for providing an input-voltage signal IAC to the line terminal LN of the controller 100. The input-voltage signal IAC is correlated to the input voltage VIN. The capacitor 50 is connected between a cathode of the rectifier 40 and the ground reference. The controller 100 generates a switching signal SW via its output terminal SW to control the power switch 20. The switching signal SW is utilized to switch the magnetic device 15 for regulating an output voltage VO of the PFC power converter. The output voltage VO is obtained across the capacitor 50. The voltage divider formed by resistors 71 and 72 is connected in parallel with the capacitor 50. A joint of the resistors 71 and 72 provides a feedback signal VFB, which is proportional to the output voltage VO, to the feedback terminal FB of the controller 100. The current-sensing resistor 30 is connected between the second terminal of the power switch 20 and the ground reference. Different to the prior art in FIG. 1, the current-sensing resistor 30 is only connected via a charging path for sampling a charging current IW flowing via the power switch 20 for generating a current-sensing signal VI. The charging current IW is used to charge the magnetic device 15; therefore, it is also a charging current thereof. Since the current-sensing resistor 30 is only connected via the charging path of the magnetic device 15, the switching current sampling is accurate in a CCM (continuous current mode) operation but not accurate in a DCM (discontinuous current mode) operation. Therefore, it is required to make an error correction in the DCM operation.
FIG. 3 shows the waveforms of the switching signal SW, the switching current IL, the charging current IW, and a discharging current IDS in a CCM operation. FIG. 4 shows the waveforms of the switching signal SW, the switching current IL, the charging current IW, and the discharging current IDS in a DCM operation. The power switch 20 is turned on during an on-time TON of the switching signal SW. The charging current IW is available only during the on-time TON of the switching signal SW. The switching current IL is the current flowing via the magnetic device 15, including the charging current IW while the power switch 20 is being turned on and the discharging current IDS while the power switch 20 is being turned off The discharging current IDS is available during a demagnetizing time (discharging time TDS) of the magnetic device 15, which is equal to an off-time TOFF of the switching signal SW in the CCM operation. T is the switching period of the switching signal SW. As shown in FIG. 3, the switching signal SW is enabled before the switching current IL is discharged to zero in the CCM operation. The switching current IL is continuous (not discharged to zero) in the switching cycle, and, thus, the average of the switching current IL can be sampled via the current-sensing resistor 30. As shown in FIG. 4, the switching signal SW is enabled after the switching current IL is discharged to zero in the DCM operation. The switching current IL is discontinuous (discharged to zero) in the switching cycle. A duty cycle D.C. of the switching current IL can be expressed as following equation:




  
    
      
        
          D
          .
          C
          .
        
        =
        
          
            (
            
              
                T
                ON
              
              +
              
                T
                DS
              
            
            )
          
          T
        
      
    
    
      
        (
        1
        )
      
    
  




where the duty cycle D.C. of the switching current IL is equal to 1 in the CCM operation and is lower than 1 in the DCM operation.

Referring to FIG. 3, FIG. 4, and equation (1), the discharging times TDS in the DCM and CCM operations are different, and the current-sensing resistor 30 connected at the charging path of the magnetic device 15 fails to sample the discharging current IDS to know the discharging time TDS. Thus, the information of the duty cycle D.C. of the switching current IL will be incomplete to calculate the average of the switching current IL and get a switching-current sample error in the DCM operation, which becomes the main issue to be solved by the present invention.
FIG. 5 shows an embodiment of the controller 100 according to the present invention. The controller 100 comprises a reference-signal generation circuit 110, a duty-cycle circuit 300, a sampling circuit 200, a compensation circuit 700, a PWM circuit 120, an error amplifier 125, and a low-pass filter. The reference-signal generation circuit 110 is coupled to the line terminal LN and feedback terminal FB for respectively receiving the input-voltage signal IAC and the feedback signal VFB. The duty-cycle circuit 300 receives the input-voltage signal IAC, the feedback signal VFB, and the switching signal SW for generating a duty signal DUTY. The duty-cycle circuit 300 further provides a pulse signal PLS and a saw-tooth signal SAW. The pulse signal PLS is coupled to enable the switching signal SW and provide a dead time for the switching signal SW. That is, the switching signal SW is disabled during an enabled period of the pulse signal PLS. In response to the current-sensing signal VI, the sampling circuit 200 generates an average-current signal VCS, which is also a switching-current sample. In response to the duty signal DUTY, the compensation circuit 700 corrects the average-current signal VCS to generate a corrected signal VX when the charging current IW is operated in the DCM operation. The maximum value of the corrected signal VX is equal to the average-current signal VCS. The corrected signal VX can be expressed by following equation:




  
    
      
        
          V
          X
        
        =
        
          
            
              V
              CS
            
            ×
            DUTY
          
          =
          
            
              V
              CS
            
            ×
            
              
                (
                
                  
                    T
                    ON
                  
                  +
                  
                    T
                    DS
                  
                
                )
              
              T
            
          
        
      
    
    
      
        (
        2
        )
      
    
  




A positive terminal of the error amplifier 125 receives a reference signal VM. A negative terminal of the error amplifier 125 receives the corrected signal VX. A resistor 127 and capacitors 128 and 129 form a low-pass filter for loop compensation of the PFC power converter. The resistor 127 is connected in series with the capacitor 128 between an output terminal of the error amplifier 125 and the ground reference. The capacitor 129 is connected between the output terminal of the error amplifier 125 and the ground reference. The output terminal of the error amplifier 125 generates a compensation signal COMI in response to the reference signal VM and the corrected signal VX. The PWM circuit 120 generates the switching signal SW in response to the pulse signal PLS and the compensation signal COMI. The waveform of the reference signal VM follows that of the input-voltage signal IAC, which is a positive sinusoid in one embodiment of the present invention.
FIG. 6 shows the waveform of the current-sensing signal VI and the relationship between the current-sensing signal VI and the average-current signal VCS in the CCM operation. The current-sensing signal VI is generated across the current-sensing resistor 30 in response to the charging current IW of the power switch 20.




  
    
      
        
          V
          CS
        
        =
        
          
            
              V
              IA
            
            +
            
              V
              IB
            
          
          2
        
      
    
    
      
        (
        3
        )
      
    
  




where VIA is an initial value of the current-sensing signal VI at the beginning of each switching cycle in the CCM operation; VIB is a peak value of the current-sensing signal VI; and VCS is the average-current signal.

FIG. 7 shows an embodiment of the duty-cycle circuit 300 of the controller 100 according to the present invention. The duty-cycle circuit 300 comprises an oscillator 310, a period-time circuit 320, a demagnetizing-time circuit 400, and a duty circuit. The oscillator 310 generates the pulse signal PLS, the saw-tooth signal SAW, a sampling signal S1, and a clearing signal S2. The period-time circuit 320 generates a period signal VT in response to the sampling signal S1 and the clearing signal S2. The demagnetizing-time circuit 400 receives the switching signal SW, the input-voltage signal IAC, and a signal VB to generate a discharging-time signal SD. The discharging-time signal SD is correlated to the discharging time TDS of the magnetic device 15. The signal VB can be proportional to the feedback signal VFB or simply a reference signal. The duty circuit generates the duty signal DUTY in response to the discharging-time signal SD, the on-time TON of the switching signal SW, and the switching period T of the switching signal SW. The duty circuit comprises an available-time circuit 500 and the duty-time circuit 600. The available-time circuit 500 generates an available signal VONDS in response to the discharging-time signal SD and the on-time (TON) of the switching signal SW. The amplitude of the available signal VONDS is correlated to a summed duration TONDS of the on-time (TON) of the switching signal SW and the discharging time TDS. The duty-time circuit 600 generates the duty signal DUTY in response to the period signal VT and the available signal VONDS.
FIG. 8 shows waveforms of the saw-tooth signal SAW, the pulse signal PLS, the sampling signal S1, and the clearing signal S2.
FIG. 9 shows an embodiment of the period-time circuit 320 according to the present invention. The period-time circuit 320 comprises switches 322 and 327, capacitors 325 and 329, and a current source 321. The current source 321 can be simply embodied with a voltage-to-current converter having an input supplied with a supply voltage VCC and an output generating a current I321. The capacitor 325 is connected between the current source 321 and the ground reference. The switch 322 is connected in parallel with the capacitor 325. A control terminal of the switch 322 is supplied with the clearing signal S2. The switch 327 and the capacitor 329 are connected in series between the current source 321 and the ground reference. A control terminal of the switch 327 is supplied with the sampling signal S1. The period signal VT is obtained across the capacitor 329. Once the clearing signal S2 is disabled, the current source 321 will start to charge the capacitor 325. When the sampling signal S1 is enabled, a voltage V325 across the capacitor 325 will be conducted to the capacitor 329 for generating the period-time signal VT. The period-time circuit 320 generates the period signal VT in response to the sampling signal S1 and the clearing signal S2. Since a period starting at the leading-edge of the clearing signal S2 and ending at the leading-edge of the sampling signal S1 is approximately equal to the switching period T of the switching signal SW, an amplitude of the period signal VT will be correlated to the switching period T of the switching signal SW.
FIG. 10 shows an embodiment of the demagnetizing-time circuit 400 according to the present invention. The detail operation of the demagnetizing-time circuit 400 can be found in a prior art “Method and apparatus for detecting demagnetizing time of magnetic device”, U.S. Pat. No. 7,471,523. The demagnetizing-time circuit 400 comprises a current generator 450, switches 410 and 415, a capacitor 420, an inverter 430, a comparator 425, and an AND gate 435. The current generator 450 generates a first current I1, a second current I2, and a third current I3 in response to the signal VB and the input-voltage signal IAC. The signal VB is correlated to the feedback signal VFB, which is also correlated to the output voltage VO. The signal VB can also be a reference signal. The input-voltage signal IAC is correlated to the input voltage VIN. A first terminal of the switch 410 receives the first current I1. A second terminal of the switch 410 is connected to a first terminal of the switch 415. A second terminal of the switch 415 is connected to the ground reference. The capacitor 420 is connected to a joint of the switches 410 and 415. A voltage V420 is generated across the capacitor 420. A positive terminal of the comparator 425 receives the voltage V420. A negative terminal of the comparator 425 receives a reference voltage VR2. The switching signal SW is supplied to a control terminal of the switch 410 and an input of the inverter 430. An output of the inverter 430 and an output of the comparator 425 are respectively connected to two inputs of the AND gate 435. An output of the AND gate 435 generates the discharging-time signal SD, which is also supplied to a control terminal of the switch 415. Once the switching signal SW is enabled, the first current I1 start to charge the capacitor 420. While the voltage V420 is greater than the reference voltage VR2 and the switching signal SW is being disabled, the discharging-time signal SD will be enabled. This enabled discharging-time signal SD will turn on the switch 415. The third current I3 is coupled to the second current I2 for discharging the capacitor 420. Once the voltage V420 is lower than the reference voltage VR2, the discharging-time signal SD will be disabled again. Since the signal VB is correlated to the output voltage VO of the PFC power converter, the demagnetizing-time circuit 400 therefore generates the discharging-time signal SD in response to the output voltage VO of the PFC power converter. The discharging-time signal SD is correlated to the discharging time TDS. The discharging time TDS of the magnetic device 15 can be expressed by following equation:




  
    
      
        
          T
          DS
        
        =
        
          
            T
            ON
          
          ×
          k
          ×
          
            
              V
              IN
            
            
              (
              
                
                  V
                  O
                
                -
                
                  V
                  IN
                
              
              )
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




where k is a constant.

FIG. 11 shows an embodiment of the current generator 450 according to the present invention. The current generator 450 basically comprises a voltage-to-current converter and current mirrors to respectively generate the first current I1 and the third current I3 in response to the input-voltage signal IAC and generate the second current I2 in response to the signal VB. The voltage-to-current converter comprises an operational amplifier 451, a transistor 452, and a resistor 453. Transistors 456-459, 471-472, and 475-477 form the current mirrors. The operation of the voltage-to-current converter and the current mirrors are well-known to those skilled in the art and will be omitted herein.
FIG. 12 shows an embodiment of the available-time circuit 500 according to the present invention. The available-time circuit 500 comprises a time-control circuit and a sample-and-hold circuit. The time-control circuit comprises flip-flops 510 and 530, inverters 511, 521, and 522, an AND gate 520, and a NOR gate 525. The sample-and-hold circuit comprises a current source 540, switches 541, 542, and 560, and capacitors 545 and 570. The D-inputs D of the flip-flops 510 and 530 are supplied with the supply voltage VCC. A clock-input ck of the flip-flop 510 is supplied with the discharging-time signal SD. A clock-input ck of the flip-flop 530 is supplied with the switching signal SW. The flip-flop 510 is reset by the clearing signal S2 via the inverter 511. An output Q of the flip-flop 510 is connected to a first input of the AND gate 520. A second input of the AND gate 520 is coupled to receive the switching signal SW via the inverter 521. A third input of the AND gate 520 is coupled to receive the discharging-time signal SD via the inverter 522. An output of the AND gate 520 and the clearing signal S2 are supplied to inputs of the NOR gate 525 for resetting the flip-flop 530. An output Q of the flip-flop 530 generates a time-control signal SONDS. The switch 541 is connected between the current source 540 and the capacitor 545. The switch 542 is coupled to the capacitor 545 in parallel. The switch 560 and the capacitor 570 are connected in series from a joint of the switch 541 and the capacitor 545 to the ground reference. The switch 542 is controlled by the clearing signal S2. The switch 560 is controlled by the sampling signal S1. The available signal VONDS is generated across the capacitor 570. An enabled duration of the time-control signal SONDS is correlated to that of the discharging-time signal SD and the switching signal SW. The amplitude of the available signal VONDS is correlated to the enabled duration of the time-control signal SONDS. As a result, the amplitude of the available signal VONDS is correlated to the summed period TONDS of the on-time (TON) of the switching signal SW and the discharging time TDS.
FIG. 13 shows an embodiment of the duty-time circuit 600 according to the present invention. The duty-time circuit 600 comprises a current-source circuit, a capacitor 620, a switch 625, and a comparator 635. The current-source circuit comprises an operational amplifier 611, transistors 612, 617, and 618, and a resistor 615. The operation of the current-source circuit is basically achieved by a voltage-to-current converter and a current mirror, which is well known to those skilled in the art and will be omitted herein. The current-source circuit generates a charging current I618 in response to the period signal VT, which is input to the aforementioned voltage-to-current converter. The capacitor 620 is coupled to an output of the current-source circuit for receiving the charging current I618. The switch 625 is connected to the capacitor 620 in parallel and controlled by the clearing signal S2. A voltage V620 is generated across the capacitor 620. The voltage V620 is supplied to a negative terminal of the comparator 635. A positive terminal of the comparator 635 is supplied with the available signal VONDS. The comparator 635 generates the duty signal DUTY by comparing the voltage V620 and the available signal VONDS.
FIG. 14 shows an embodiment of the compensation circuit 700. The compensation circuit 700 comprises a voltage-to-current converter, a buffer amplifier 790, a current mirror, switches 731, 732, and 735, and capacitors 750 and 760. The voltage-to-current converter is formed by an operational amplifier 711, a transistor 712, and a resistor 715. The current mirror is formed by transistors 719 and 720. Same as the current-source circuit in FIG. 13, the voltage-to-current converter and the current mirror in FIG. 14 are coupled to generate a charging current I720 in response to the average-current signal VCS, which is input to the voltage-to-current converter in FIG. 14. A negative terminal of the buffer amplifier 790 is connected to an output thereof. A positive terminal of the buffer amplifier 790 is supplied with the average-current signal VCS. The switch 731 and the switch 732 are connected in series between an output of the current mirror and the ground reference. The output of the buffer amplifier 790 is connected to a joint of the switch 731 and the switch 732. The switch 732 is connected in parallel with the capacitor 750. The switch 735 and the capacitor 760 are connected in series between the joint of the switch 731 and the switch 732 and the ground reference. The corrected signal VX is obtained across the capacitor 760. The switch 731 is controlled by the duty signal DUTY. The switch 735 is controlled by the sampling signal S1. The switch 732 is controlled by the clearing signal S2. The buffer amplifier 790 has an open-drain output for limiting the maximum amplitude of the corrected signal VX to be the same as the average-current signal VCS.
According to the embodiments of the compensation circuit 700 of the present invention, in the CCM operation, the corrected signal VX will be equal to the average-current signal VCS. In the DCM operation, the corrected signal VX will be generated according to the enabled period of the duty signal DUTY to correct the error of the switching-current sample.
The theory of the present invention can be found in equations (2)-(13). Referring to FIG. 2,




  
    V
    FB
  
  =
  
    
      V
      O
    
    ×
    
      
        R
        72
      
      
        
          R
          71
        
        +
        
          R
          72
        
      
    
  




where R71 and R72 are respectively the resistance of the resistors 71 and 72.

Referring to FIG. 11,




  
    I
    2
  
  =
  
    
      {
      
        
          [
          
            
              V
              O
            
            ×
            
              
                R
                72
              
              
                
                  R
                  71
                
                +
                
                  R
                  72
                
              
            
          
          ]
        
        ÷
        
          R
          453
        
      
      }
    
    ×
    
      k
      1
    
  




where k1 is the ratio of the current mirror formed by transistors 456 and 457; R453 is the resistance of the resistor 453.

I1=IAC×k2 

where k2 is the ratio of the current mirror formed by transistors 475 and 476.

I3=IAC×k3 

where k3 is the ratio of the current mirror formed by transistors 475 and 477.

Referring to FIG. 2,




  
    I
    AC
  
  =
  
    
      V
      IN
    
    
      R
      35
    
  




where R35 is the resistance of the resistor 35.

Referring to FIG. 10,




  
    
      
        
          V
          
            R
            ⁢
            
              
            
            ⁢
            2
          
        
        =
        
          
            
              
                I
                1
              
              ×
              
                T
                ON
              
            
            
              C
              420
            
          
          =
          
            
              
                (
                
                  
                    I
                    2
                  
                  -
                  
                    I
                    3
                  
                
                )
              
              ×
              
                T
                DS
              
            
            
              C
              420
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




where C420 is the capacitance of the capacitor 420.

Thus, it is obtained as,

I1×TON=(I2−I3)×TDS 

According to the above equations, it can be expressed as,




  
    
      (
      
        
          
            V
            IN
          
          
            R
            35
          
        
        ×
        
          k
          2
        
      
      )
    
    ×
    
      T
      ON
    
  
  =
  
    
      [
      
        
          (
          
            
              
                V
                O
              
              
                R
                453
              
            
            ×
            
              
                R
                72
              
              
                
                  R
                  71
                
                +
                
                  R
                  72
                
              
            
          
          )
        
        ×
        
          k
          1
        
      
      ]
    
    -
    
      
        (
        
          
            
              V
              IN
            
            
              R
              35
            
          
          ×
          
            k
            3
          
        
        )
      
      ×
      
        T
        DS
      
    
  




Setting




  
    
      
        K
        2
      
      
        R
        35
      
    
    =
    
      
        [
        
          (
          
            
              
                K
                1
              
              
                R
                453
              
            
            ×
            
              
                R
                72
              
              
                
                  R
                  71
                
                +
                
                  R
                  72
                
              
            
          
          )
        
        ]
      
      =
      
        
          K
          3
        
        
          R
          35
        
      
    
  
  ,




then, it can be expressed as,

VIN×TON=(VO−VIN)×TDS 

and then





  
    
      
        
          T
          DS
        
        =
        
          
            
              V
              IN
            
            
              (
              
                
                  V
                  O
                
                -
                
                  V
                  IN
                
              
              )
            
          
          ×
          
            T
            ON
          
        
      
    
    
      
        (
        6
        )
      
    
  




Referring to FIG. 12,

TONDS=TON+TDS 

where TONDS is a summed duration of TON and TDS. Then





  
    
      
        
          V
          ONDS
        
        =
        
          
            
              
                I
                540
              
              ×
              
                T
                ONDS
              
            
            
              C
              545
            
          
          =
          
            
              
                
                  V
                  REF
                
                ×
                
                  T
                  ONDS
                
              
              
                
                  R
                  540
                
                ×
                
                  C
                  545
                
              
            
            =
            
              
                
                  V
                  REF
                
                ×
                
                  (
                  
                    
                      T
                      ON
                    
                    +
                    
                      T
                      DS
                    
                  
                  )
                
              
              
                
                  R
                  540
                
                ×
                
                  C
                  545
                
              
            
          
        
      
    
    
      
        (
        7
        )
      
    
  




Referring to FIG. 9,




  
    
      
        
          V
          T
        
        =
        
          
            
              
                I
                321
              
              ×
              T
            
            
              C
              325
            
          
          =
          
            
              
                V
                REF
              
              ×
              T
            
            
              
                R
                321
              
              ×
              
                C
                325
              
            
          
        
      
    
    
      
        (
        8
        )
      
    
  




Referring to FIG. 13,




  
    
      
        
          
            
              
                V
                ONDS
              
              =
              
              ⁢
              
                
                  
                    I
                    618
                  
                  ×
                  
                    T
                    DUTY
                  
                
                
                  C
                  620
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    V
                    T
                  
                  ×
                  
                    k
                    4
                  
                  ×
                  
                    T
                    DUTY
                  
                
                
                  
                    R
                    615
                  
                  ×
                  
                    C
                    620
                  
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    
                      V
                      REF
                    
                    ×
                    T
                  
                  
                    
                      R
                      321
                    
                    ×
                    
                      C
                      325
                    
                  
                
                ×
                
                  
                    
                      k
                      4
                    
                    ×
                    
                      T
                      DUTY
                    
                  
                  
                    
                      R
                      615
                    
                    ×
                    
                      C
                      620
                    
                  
                
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




where TDUTY is a period of the duty signal DUTY; k4 is the ratio of the current mirror formed by transistors 617 and 618; R615 is the resistance of the resistor 615; C620 is the capacitance of the capacitor 620; and the current I321 is represented by VREF/R321.

According to equations (6) and (8),




  
    
      
        
          V
          ONDS
        
        =
        
          
            
              
                V
                REF
              
              ×
              
                (
                
                  
                    T
                    ON
                  
                  +
                  
                    T
                    DS
                  
                
                )
              
            
            
              
                R
                540
              
              ×
              
                C
                545
              
            
          
          =
          
            
              
                
                  V
                  REF
                
                ×
                T
              
              
                
                  R
                  321
                
                ×
                
                  C
                  325
                
              
            
            ×
            
              
                
                  K
                  4
                
                ×
                
                  T
                  DUTY
                
              
              
                
                  R
                  615
                
                ×
                
                  C
                  620
                
              
            
          
        
      
    
    
      
        (
        10
        )
      
    
  




Setting




  
    
      
        R
        321
      
      ×
      
        C
        325
      
    
    
      
        R
        540
      
      ×
      
        C
        545
      
    
  
  =
  1




for the equation (9), which generates the following equation:





  
    
      
        
          T
          DUTY
        
        =
        
          
            
              (
              
                
                  T
                  ON
                
                +
                
                  T
                  DS
                
              
              )
            
            
              
                K
                4
              
              ×
              T
            
          
          ×
          
            (
            
              
                R
                615
              
              ×
              
                C
                620
              
            
            )
          
        
      
    
    
      
        (
        11
        )
      
    
  




Referring to FIG. 14,




  
    
      
        
          V
          ×
        
        =
        
          
            
              
                I
                720
              
              ×
              
                T
                DUTY
              
            
            
              C
              750
            
          
          =
          
            
              
                V
                CS
              
              ×
              
                T
                DUTY
              
            
            
              
                R
                715
              
              ×
              
                C
                750
              
            
          
        
      
    
    
      
        (
        12
        )
      
    
  




Substituting TDUTY of the equation (11) into equation (12), which generates the following equation:




  
    
      
        
          
            
              
                V
                ×
              
              =
              
              ⁢
              
                
                  
                    I
                    720
                  
                  ×
                  
                    T
                    DUTY
                  
                
                
                  C
                  750
                
              
            
          
        
        
          
            
              =
              
              ⁢
              
                
                  
                    V
                    CS
                  
                  
                    
                      R
                      715
                    
                    ×
                    
                      C
                      750
                    
                  
                
                ×
                
                  
                    (
                    
                      
                        T
                        ON
                      
                      +
                      
                        T
                        DS
                      
                    
                    )
                  
                  
                    
                      k
                      4
                    
                    ×
                    T
                  
                
                ×
                
                  (
                  
                    
                      R
                      615
                    
                    ×
                    
                      C
                      620
                    
                  
                  )
                
              
            
          
        
      
    
    
      
        (
        13
        )
      
    
  




Setting




  
    
      
        R
        615
      
      ×
      
        C
        620
      
    
    
      
        k
        4
      
      ×
      
        R
        715
      
      ×
      
        C
        750
      
    
  
  =
  1








  
    
      
        
          
            
              R
              615
            
            ×
            
              C
              650
            
          
          
            
              k
              4
            
            ×
            
              R
              715
            
            ×
            
              C
              750
            
          
        
        =
        1
      
    
    
      
        
      
    
  
  
    
      
        
          V
          X
        
        =
        
          
            V
            CS
          
          ×
          
            
              (
              
                
                  T
                  ON
                
                +
                
                  T
                  DS
                
              
              )
            
            T
          
        
      
    
    
      
        (
        14
        )
      
    
  




As shown in equation (14), with the corrected signal VX, which is correlated to the on-time TON of the switching signal SW, the discharging time TDS, and the switching period T of the switching signal SW, a full duty cycle information is complete. With complete information of the above parameters, the average of the switching current IL can be obtained both in the CCM and DCM operations. The problem of failing to sample the discharging current IDS to know the discharging time TDS by the current-sensing resistor 30 can be therefore solved.
FIG. 15 shows another embodiment of a PFC power converter according to the present invention. Different to the embodiment in FIG. 2, an inductor 16 having an auxiliary winding is utilized to detect the demagnetizing time (the discharging time TDS) thereof. The detail description of detecting the discharging time TDS can be found in the prior art “Switching Control Circuit for Discontinuous Mode PFC Converters”, U.S. Pat. No. 7,116,090. A controller 150 receives an auxiliary voltage VAU via a line resistor 36, which is coupled from the auxiliary winding of the inductor 16 to the controller 150.
FIG. 16 shows an embodiment of the controller 150. Different to the embodiment in FIG. 5, a reference-signal generation circuit 115 (functionally equivalent to the reference-signal generation circuit 110 in FIG. 5) only receives the feedback signal VFB to generate the reference signal VM. Another difference is a duty-cycle circuit 350 (functionally equivalent to the duty-cycle circuit 300 in FIG. 5) receives the feedback signal VFB, the auxiliary voltage VAU, and the switching signal SW for generating the duty signal DUTY.
FIG. 17 shows an embodiment of a duty-cycle circuit 350 of the controller 150. Different to the embodiment in FIG. 7, the demagnetizing-time circuit 400 in FIG. 7 is replaced by a detection circuit. The detection circuit comprises a comparator 363, an inverter 362, and a flip-flop 361. A positive terminal of the comparator 363 receives the auxiliary voltage VAU. A negative terminal of the comparator 363 receives a threshold voltage VTH. A D-input D of the flip-flop 361 is supplied with the supply voltage VCC. A clock-input ck of the flip-flop 361 is driven by the switching signal SW via the inverter 362. An output Q of the flip-flop 361 generates the discharging-time signal SH. The discharging-time signal SD is disabled when the auxiliary voltage VAU is lower than the threshold voltage VTH.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.

## Claims

1. A correction circuit for a power converter, comprising:
a sampling circuit, generating an average-current signal in response to a switching current of said power converter;
a demagnetizing-time circuit, generating a discharging-time signal in response to a switching signal and an input-voltage signal;
a duty circuit, generating a duty signal in response to said discharging-time signal, an on-time of said switching signal, and a switching period of said switching signal; and
a compensation circuit, coupled to receive said average-current signal and said duty signal for generating a corrected signal;
wherein said switching signal is utilized to switch a magnetic device for regulating an output voltage of said power converter, said discharging-time signal is correlated to a demagnetizing time of said magnetic device, said input-voltage signal is correlated to an input voltage of said magnetic device, and said corrected signal is coupled to generate said switching signal.

2. The correction circuit as claimed in claim 1, wherein said average-current signal is generated in response to said switching current in a CCM (continuous current mode) operation.

3. The correction circuit as claimed in claim 1, wherein said duty signal is coupled to correct said average-current signal for generating said corrected signal when said switching current is operated in a DCM (discontinuous current mode), and a maximum value of said corrected signal is equal to said average-current signal.

4. The correction circuit as claimed in claim 1, wherein the output voltage of said power converter is coupled to said demagnetizing-time circuit to generate said discharging-time signal.

5. The correction circuit as claimed in claim 1 further comprising a period-time circuit generating a period signal in response to said switching period of said switching signal, wherein said period signal is coupled to said duty circuit for generating said duty signal.

6. The correction circuit as claimed in claim 1, wherein said duty circuit comprises an available-time circuit generating an available signal in response to said on-time of said switching signal and said discharging-time signal.

7. The correction circuit as claimed in claim 6, wherein said duty circuit further comprises a duty-time circuit comprising:
a capacitor;
a current-source circuit, generating a charging current in response to said period signal, wherein said charging current charges said capacitor for generating a ramp signal; and
a comparator, coupled to receive said ramp signal and said available signal for generating said duty signal.

8. The correction circuit as claimed in claim 1, wherein said power converter is a boost power converter.

9. A method of correcting a switching-current sample for a power converter, comprising:
generating a discharging-time signal in response to a switching signal and an input-voltage signal;
generating a duty signal in response to said discharging-time signal, an on-time of said switching signal, and a switching period of said switching signal; and
generating a corrected signal in response to an average-current signal and said duty signal;
wherein said switching signal is utilized to switch a magnetic device for regulating an output voltage of said power converter, said discharging-time signal is correlated to a demagnetizing time of said magnetic device, said input-voltage signal is correlated to an input voltage of said magnetic device, said average-current signal is generated in response to a switching current of said power converter, and said corrected signal is coupled to generate said switching signal.

10. The method as claimed in claim 9, wherein said average-current signal is generated in response to said switching current in a CCM (continuous current mode) operation; said duty signal is coupled to correct said average-current signal which is said switching-current sample for generating said corrected signal when said switching current is in a DCM (discontinuous current mode) operation, and a maximum value of said corrected signal is equal to said average-current signal.

11. The method as claimed in claim 9, wherein the output voltage of said power converter is coupled to generate said discharging-time signal.

12. The method as claimed in claim 9, further comprising generating a period signal in response to said switching period of said switching signal, wherein said period signal is utilized to generate said duty signal.

13. The method as claimed in claim 9, wherein said power converter is a boost power converter.

14. An apparatus for correcting a switching-current sample of a power converter, comprising:
a demagnetizing-time circuit, generating a discharging-time signal in response to a switching signal and an input-voltage signal;
a duty circuit, generating a duty signal in response to said discharging-time signal and said switching signal; and
a compensation circuit, coupled to receive an average-current signal and said duty signal for generating a corrected signal;
wherein said switching signal is utilized to switch a magnetic device of said power converter, said discharging-time signal is correlated to a demagnetizing time of said magnetic device, said input-voltage signal is obtained via a resistor coupled to an input voltage of said magnetic device, said average-current signal is generated in response to a switching current of said power converter, and said corrected signal is coupled to generate said switching signal.

15. The apparatus as claimed in claim 14, wherein said average-current signal is generated in response to said switching current in a CCM (continuous current mode) operation, said duty signal is coupled to correct said average-current signal for generating said corrected signal when said switching current is in a DCM (discontinuous current mode) operation, and a maximum value of said corrected signal is equal to said average-current signal.

16. An apparatus for correcting a switching-current sample of a power converter, comprising:
a detection circuit, coupled to an auxiliary winding of a magnetic device of said power converter for generating a discharging-time signal;
a duty circuit, generating a duty signal in response to said discharging-time signal and a switching signal; and
a compensation circuit, coupled to receive an average-current signal and said duty signal for generating a corrected signal;
wherein said switching signal is utilized to switch said magnetic device, said discharging-time signal is correlated to a demagnetizing time of said magnetic device, said average-current signal is generated in response to a switching current of said power converter, and said corrected signal is coupled to generate said switching signal.

17. The apparatus as claimed in claim 16, wherein said average-current is generated in response to said switching current in a CCM (continuous current mode) operation, said duty signal is coupled to correct said average-current signal for generating said corrected signal when said switching current is in a DCM (discontinuous current mode) operation, and a maximum value of said corrected signal is equal to said average-current signal.

18. The apparatus as claimed in claim 16, wherein said power converter is a boost power converter.