# Patent

## Title
Logarithmic temperature compensation for detectors

## Abstract

The intercept of a logarithmic amplifier is temperature stabilized by generating a signal having the form H log H where H is a function of temperature such as T/T0. The first H factor is cancelled, thereby generating a correction signal having the form Y log H. The cancellation may be implemented with a transconductance cell having a hyperbolic tangent function. The H log H function may be generated by a pair of junctions biased by one temperature-stable current and one temperature-dependent current. The pair of junctions and the transconductance cell may be coupled together in a translinear loop. A user-accessible terminal may allow adjustment of the correction signal for different operating frequencies.

## Background
This application is a divisional of U.S. patent application Ser. No. 11/621,454 filed Jan. 9, 2007 now U.S. Pat. No. 7,453,309 entitled LOGARITHMIC TEMPERATURE COMPENSATION FOR DETECTORS, which is a divisional of U.S. patent application Ser. No. 11/020,897 filed Dec. 22, 2004 entitled LOGARITHMIC TEMPERATURE COMPENSATION FOR DETECTORS, now issued as U.S. Pat. No. 7,180,359, which are incorporated by reference.


BACKGROUND
A logarithmic amplifier (“log amp”) generates an output signal VOUT that is related to its input signal VIN by the following transfer function:

VOUT=VY log(VIN/VZ)  Eq. 1

where VY is the slope and VZ is the intercept. To provide accurate operation, VY and VZ should be stable over the entire operating temperature range of the log amp. In a monolithic implementation of a progressive compression type log amp, temperature compensation of the slope VY is typically provided in the gain and detector cells since those are the structures that detennine the slope. Temperature stabilization of the intercept VZ, however, is typically provided at the front or back end of the log amp. For example, a passive attenuator with a loss that is proportional to absolute temperature (PTAT) may be interposed between the signal source and the log amp. Such an arrangement is disclosed in U.S. Pat. No. 4,990,803.

Another technique for temperature compensating the intercept of a log amp involves adding a carefully generated compensation signal to the output so as to cancel the inherent temperature dependency of the intercept. The intercept VZ of a typical progressive compression log amp is PTAT and can be expressed as a function of temperature T as follows:




  
    
      
        
          V
          Z
        
        =
        
          
            V
            
              Z
              ⁢
              0
            
          
          ⁡
          
            (
            
              T
              
                T
                0
              
            
            )
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        2
      
    
  




where T0 is a reference temperature (usually 300° K) and VZ0 is the value of VZ at T0. Substituting Eq. 2 into Eq. 1 provides the following expression:





  
    
      
        
          V
          OUT
        
        =
        
          
            V
            Y
          
          ⁢
          
            
          
          ⁢
          
            log
            ⁢
            
              
            
            [
            
              
                (
                
                  
                    V
                    IN
                  
                  
                    V
                    
                      Z
                      ⁢
                      0
                    
                  
                
                )
              
              ⁢
              
                (
                
                  
                    T
                    0
                  
                  T
                
                )
              
            
            ]
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        3
      
    
  




which can be rearranged as follows:





  
    
      
        
          V
          OUT
        
        =
        
          
            
              V
              Y
            
            ⁢
            
              
            
            ⁢
            log
            ⁢
            
              
            
            ⁢
            
              (
              
                
                  V
                  IN
                
                
                  V
                  
                    Z
                    ⁢
                    0
                  
                
              
              )
            
          
          -
          
            
              
                V
                Y
              
              ⁢
              log
              ⁢
              
                
              
              ⁢
              
                (
                
                  T
                  
                    T
                    0
                  
                
                )
              
            
            
              }
              
                Temperature
                ⁢
                
                  -
                
                ⁢
                dependent
              
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        4
      
    
  




It has been shown that accurate intercept stabilization can be achieved by adding a correction signal equal to the second, temperature-dependent term in Eq. 4 to the output of a log amp, thereby canceling the temperature dependency. See, e.g., U.S. Pat. No. 4,990,803; and Barrie Gilbert, Monolithic Logarithmic Amplifiers, Aug. 1994, § 5.2.4. A prior art circuit for introducing such a correction signal is described with reference to FIG. 19 in U.S. Pat. No. 4,990,803.




BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an embodiment of a system for temperature compensating the intercept of a log amp according to the inventive principles of this patent disclosure.
FIG. 2 illustrates an embodiment of a temperature compensation circuit for a log amp according to the inventive principles of this patent disclosure.
FIG. 3 illustrates another embodiment of a temperature compensation circuit for a log amp according to the inventive principles of this patent disclosure.
FIG. 4 illustrates an embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure.
FIG. 5 illustrates another embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure.



DETAILED DESCRIPTION
FIG. 1 illustrates an embodiment of a system for temperature compensating the intercept of a log amp according to the inventive principles of this patent disclosure. The embodiment of FIG. 1 includes a temperature compensation circuit 12 that generates a correction signal SFIX having the form Y log (T/T0) where Y is a generic slope factor. Since the expression T/T0 will be used frequently, it will be abbreviated as H=T/T0 for convenience. The correction signal SFIX is applied to log amp 10 so as to temperature stabilize the intercept.
The temperature compensation circuit 12 generates the correction signal SFIX by multiplying a signal having the form H log H by some other factor having a 1/H component. Thus, the H and 1/H cancel, and the only temperature variation in the correction signal is of the form log H. Any suitable scaling my also be applied to obtain the slope factor Y required for the particular log amp being corrected.
FIG. 2 illustrates an embodiment of a temperature compensation circuit according to the inventive principles of this patent disclosure. The embodiment of FIG. 2, which illustrates one possible technique for implementing the 1/H multiplication shown in FIG. 1, utilizes a transconductance (gm) cell 14. The transfer function of a generic gm cell has a hyperbolic tangent (tanh) form which may be stated a follows:




  
    
      
        
          I
          OUT
        
        =
        
          
            I
            T
          
          ⁢
          
            
          
          ⁢
          tanh
          ⁢
          
            
          
          ⁢
          
            (
            
              
                V
                i
              
              
                V
                T
              
            
            )
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        5
      
    
  




where IT is the bias or “tail” current through the gm cell, Vi is the differential input voltage, and VT is the thermal voltage which may also be expressed as VT=VT0(T/T0)=VT0H. If the input signal to the gm cell is kept relatively small, the tanh function may be approximated as simply the operand itself:





  
    
      
        
          I
          OUT
        
        ≈
        
          
            I
            T
          
          ⁢
          
            
              V
              i
            
            
              V
              T
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        6
      
    
  




Now, to implement the generic gm cell in the compensation circuit of FIG. 2, H log H is used as the input Vi to the gm cell, the output current IOUT is used as the correction signal in the fonn of a current IFIX, and VT0H is substituted for VT:




  
    
      
        
          I
          FIX
        
        ≈
        
          
            I
            T
          
          ⁢
          
            
              H
              ⁢
              
                
              
              ⁢
              log
              ⁢
              
                
              
              ⁢
              H
            
            
              
                V
                
                  T
                  ⁢
                  0
                
              
              ⁢
              H
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        7
      
    
  




Thus, H and 1/H cancel. If a temperature stable signal (sometimes referred to as a ZTAT signal where the Z stands for zero temperature coefficients) is used for IT, then IT/VT0 is a temperature-stable constant that may be set to any suitable value Y to provide the correct slope. The final form of IFIX is then given by:

IFIX≈Y log H  Eq. 8

Therefore, the use of a transconductance cell with its inherent 1/H factor provides a simple and effective solution to generating a correction signal having the requisite log H characteristic.

FIG. 3 illustrates another embodiment of a temperature compensation circuit according to the inventive principles of this patent disclosure. The embodimient of FIG. 3 uses a pair of diode-connected transistors biased by ZTAT and PTAT currents to generate the H log H function, which is then applied to a gm cell in a tightly integrated translinear loop.
Diode-connected transistors Q3 and Q4 are referenced to a positive power supply VPOS, and are biased by currents IP and IZ, respectively. IZ is ZTAT, while IP is a PTAT current. The base-emitter voltages of Q3 and Q4 are:




  
    
      
        
          V
          
            BE
            ⁢
            3
          
        
        =
        
          
            V
            
              
                
              
              ⁢
              T
            
          
          ⁢
          ln
          ⁢
          
            
          
          ⁢
          
            (
            
              
                
                  
                
                ⁢
                
                  I
                  
                    
                      
                    
                    ⁢
                    P
                  
                
              
              
                
                  
                
                ⁢
                
                  I
                  
                    
                      
                    
                    ⁢
                    S
                  
                
              
            
            )
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        9
      
    
  
  
    
      
        
          V
          
            BE
            ⁢
            4
          
        
        =
        
          
            V
            T
          
          ⁢
          ln
          ⁢
          
            
          
          ⁢
          
            (
            
              
                I
                Z
              
              
                I
                S
              
            
            )
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        10
      
    
  




and therefore, the ΔVBE across the bases of Q3 and Q4 is:





  
    
      
        
          
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              BE
            
          
          =
          
            
              
                V
                
                  BE
                  ⁢
                  3
                
              
              -
              
                V
                
                  BE
                  ⁢
                  4
                
              
            
            =
            
              
                
                  V
                  T
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                
                  (
                  
                    
                      I
                      P
                    
                    
                      I
                      S
                    
                  
                  )
                
              
              -
              
                
                  V
                  T
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                
                  (
                  
                    
                      I
                      Z
                    
                    
                      I
                      S
                    
                  
                  )
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              BE
            
          
          =
          
            
              V
              T
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            
              (
              
                
                  I
                  P
                
                
                  I
                  Z
                
              
              )
            
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        11
      
    
  




Since IP can be expressed as IP=IZH, and VT=VT0H:





  
    
      
        
          
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              BE
            
          
          =
          
            
              V
              
                T
                ⁢
                0
              
            
            ⁢
            H
            ⁢
            
              
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            
              (
              
                
                  
                    I
                    Z
                  
                  ⁢
                  H
                
                
                  I
                  Z
                
              
              )
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            Δ
            ⁢
            
              
            
            ⁢
            
              V
              BE
            
          
          =
          
            
              V
              
                T
                ⁢
                0
              
            
            ⁢
            H
            ⁢
            
              
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            H
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        12
      
    
  




Thus, the ΔVBE of Q3 and Q4 provide a signal having the fonn H log H, which is then applied as the input signal Vi to the gm cell.

The gm cell is implemented as a differential pair of emitter-coupled transistors Q1 and Q2 that are biased by a ZTAT tail current IT. The base-emitter junctions of Q1 and Q2 complete the translinear loop with the base-emitter junctions of Q3 and Q4. The output signal IOUT from the differential pair is taken as the difference between the collector currents I1 and I2 of transistors Q1 and Q2, respectively. Substituting ΔVBE of Eq. 12 as Vi in Eq. 6 provides:




  
    
      
        
          
            I
            OUT
          
          ≈
          
            
              I
              T
            
            ⁢
            
              
                
                  V
                  
                    T
                    ⁢
                    0
                  
                
                ⁢
                H
                ⁢
                
                  
                
                ⁢
                ln
                ⁢
                
                  
                
                ⁢
                H
              
              
                
                  V
                  
                    T
                    ⁢
                    0
                  
                
                ⁢
                H
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            I
            OUT
          
          ≈
          
            
              I
              T
            
            ⁢
            ln
            ⁢
            
              
            
            ⁢
            H
          
        
      
    
    
      
        Eq
        .
        
          
        
        ⁢
        13
      
    
  




By exercising some care in the selection of the scale factor for IT, the proper slope factor Y may be obtained. Since the output signal IOUT is in a differential form, it is easy to apply it as the compensation signal IFIX to the output of any log amp having differential current outputs. This is especially true in the case of many progressive compression log amps. IFIX can simply be connected to the same summing nodes that are used to collect the current outputs from the detector cells for the cascaded gain stages.

FIG. 4 illustrates an embodiment of a technique lor providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure. In some implementations, the compensation techniques described above may be frequency dependent. That is, although adding a compensation signal of the form Y log H may stabilize the intercept over the entire operating temperature range at a given frequency, a different amount of compensation may be required at different operating frequencies. The embodiment of FIG. 4 provides a terminal 16 that allows a user to vary the amount of compensation depending on the operating frequency.
The example embodiment of FIG. 4 is fabricated on an integrated circuit (IC) chip, preferably including the target log amp to be temperature compensated. A transconductance cell 14, which generates the Y log H correction signal, is biased by a tail current IT. The tail current is generated by a transistor QT. which in turn is biased by a voltage VBIAS. The magnitude of the tail current is determined by the combination of an internal resistor RINT which is fabricated on the chip, and an external resistor REXT, which may be connected through terminal 16. The appropriate value of REXT may be provided to the user through a lookup table, equation, etc.
FIG. 5 illustrates another embodiment of a technique for providing adjustable intercept compensation to a log amp according to the inventive principles of this patent disclosure. As in the embodiment of FIG. 4, the embodiment of FIG. 5 includes a transconductance cell 14 biased by a tail current IT generated by transistor QT. Rather than setting the tail current directly through an external resistor, however, the current through QT is set by an internal resistor RINT in combination with an operational amplifier (op amp) 18 arranged to drive the base of QT in response to an adjustment signal VADJ which is applied externally by the user through terminal 16. This eliminates any potential problems with mismatches between internal and external resistors. As an added feature, an on-chip reference voltage VREF, which is typically available internally on the IC, can be made available to the user through another terminal 20. This enables the user to set the adjustment signal VADJ using external divider resistors R1 and R2.
This patent disclosure encompasses numerous inventions relating to temperature compensation of log amps. These inventive principles have independent utility and are independently patentable. In some cases, additional benefits are realized when some of the principles are utilized in various combinations with one another, thus giving rise to yet more patentable inventions. These principles can be realized in countless different embodiments. Only the preferred embodiments have been described. Although some specific details are shown for purposes of illustrating the preferred embodiments, other equally effective arrangements can be devised in accordance with the inventive principles of this patent disclosure.
For example, some transistors have been illustrated as bipolar junction transistors (BJTs), but CMOS and other types of devices may be used as well. Likewise, some signals and mathematical values have been illustrated as voltages or currents, but the inventive principles of this patent disclosure are not limited to these particular signal modes. Also, the inventive principles relating to user-adjustable compensation are not limited to a specific form of temperature compensation, or even to temperature compensation in general. An integrated circuit according to the inventive principles of this patent disclosure may have a user-accessible terminal to adjust the magnitude of any type of compensation, e.g., temperature or frequency, to any type of measurement device.
The embodiments described above can be modified in arrangement and detail without departing from the inventive concepts. Thus, such changes and modifications are considered to fall within the scope of the following claims.

## Claims

1. A temperature compensation circuit comprising:
a first junction biased by a first bias current;
a second junction biased by a second bias current; and
a differential pair of transistors to generate a compensation signal and arranged to form a translinear loop with the first and second junctions, where the differential pair of transistors is biased by a third bias current;
where the first bias current comprises a PTAT current.

2. The temperature compensation circuit of claim 1 where the first and second junctions are implemented with diode-connected transistors.

3. The temperature compensation circuit of claim 1 further comprising a terminal to enable a user to adjust the magnitude of the third bias signal.

4. The temperature compensation circuit of claim 3 where the third bias current comprises a ZTAT current.

5. The temperature compensation circuit of claim 1 where the second bias current comprises a ZTAT current.

6. The temperature compensation circuit of claim 1 where the compensation signal varies only as a function of temperature.

7. A system comprising:
a temperature compensation circuit to generate a correction signal by multiplying a signal having a logarithmic temperature dependency and a factor H by a factor having a 1/H component, thereby cancelling the factor H, where H is a function of temperature;
where the signal having the logarithmic temperature dependency and the factor H is generated by biasing a first junction with a first bias current that is PTAT, and biasing a second junction with a second bias current.

8. A temperature compensation circuit comprising:
a first bias current source;
a second bias current source;
a third bias current source;
a first junction having a first terminal connected to the first bias current source;
a second junction having a first terminal connected to the second bias current source and a second terminal connected to a second terminal of the first junction;
a first transistor having a first terminal connected to the third bias current source, a second terminal connected to the first terminal of the first junction, and a third terminal to output a first current; and
a second transistor having a first terminal connected to the third bias current source, a second terminal connected to the first terminal of the second junction, and a third terminal to output a second current;
where the first, second and third bias current sources generate bias currents that are independent of the input signal; and
where the first bias current source comprises a PTAT current source.

9. The temperature compensation circuit of claim 8 where the second bias current source comprises a ZTAT current source.