# Patent

## Title
Optical sensor

## Abstract

The present invention aims at providing a photodetector which can secure both a good S/N ratio and a high speed. With a photodetector 1, (K×M×N) photodiodes PDk,m,n are arranged in M rows and (K×N) columns in a photodetection unit 10, and processes (electric charge accumulation, CDS, filtering, and A/D conversion) regarding each of the (K×N) photodiodes PDk,m,n (k=1 to K, n=1 to N) of each row are carried out successively at each time T. Meanwhile, each of an electric charge accumulation operation in an integrating circuit 20m,n, a CDS operation in a CDS circuit 30m,n, a filtering operation in a filter circuit 40m,n, and an A/D conversion operation in an A/D converter 50m,n is carried out at each time (N×T).

## Background
TECHNICAL FIELD
The present invention relates to a photodetector including a plurality of photodiodes arranged.
BACKGROUND ART
A photodetector is an apparatus comprising a plurality of photodiodes arranged one-dimensionally or two-dimensionally, and an integrating circuit including an amplifier and an integral capacitance part, and may further comprise signal processing circuits subsequent thereto (see for example, Japanese Patent Application Laid-open Gazzete No. H9-270960). With this photodetector, electric charges of amounts that are in accordance with the intensities of light made incident onto the respective photodiodes are output by the photodiodes, these electric charges are accumulated in the integrating capacitance elements, and voltages that are in accordance with the amounts of the accumulated electric charges are output from the integrating circuit. Based on the voltages output from the integrating circuit in accordance with the amounts of electric charges generated at the plurality of photodiodes respectively, the light made incident onto a photodetection surface, on which the plurality of photodiodes are arranged, is detected.
DISCLOSURE OF THE INVENTION
However, in performing photodetection by such a photodetector at high speed, the thermal noise generated at the amplifiers included in the integrating circuit becomes large and this thermal noise causes degradation of the S/N ratio of photodetection. The thermal noise Vn of an amplifier is expressed by the following Equation:




  
    
      
        
          V
          n
        
        =
        
          
            
              C
              d
            
            
              C
              f
            
          
          ⁢
          
            
              
                8
                ⁢
                kTB
              
              
                3
                ⁢
                
                  G
                  m
                
              
            
          
        
      
    
    
      
        (
        1
        )
      
    
  




In the above, Cd is the junction capacitance value of a photodiode and is the sum of the capacitance values of the wiring from the photodiode to an integrating circuit. Cf is the capacitance value of the integrating capacitance element in the integrating circuit. k is the Boltzmann constant. T is the temperature. B is the frequency bandwidth of the amplifier that is included in the integrating circuit. Gm is the input transistor's transconductance of the amplifier included in the integrating circuit.
Of the parameters appearing at the right side of the above Equation (1), those that contribute to the lowering of thermal noise are B and Gm. Though a greater Gm is effective for lowering thermal noise, it increases the consumption power of the amplifier. When the consumption power of the amplifier is high, heat generation becomes problem when a large number of amplifiers are integrated. There is thus a limit to making Gm large. Also, though a smaller B is effective for lowering thermal noise, it lowers the speed of photodetection. It is thus difficult to accomplish high speed of photodetection and improvement of the S/N ratio at the same time.
In order to overcome the problem mentioned above, it is an object of the present invention to provide a photodetector which can secure both a good S/N ratio and a high speed.
This invention's photodetector comprises: (1) (K×M×N) photodiodes PDk,m,n (K being an integer of no less than 2; k being integers of no less than 1 and no more than K; M being an integer of no less than 1; m being integers of no less than 1 and no more than M; N being an integer of no less than 2; and n being integers of no less than 1 and no more than N), each generating electric charges of an amount that is in accordance with an incident light intensity; (2) (M×N) integrating circuits, one of each being provided in correspondence to K photodiodes PDk,m,n (k=1 to K) among the (K×M×N) photodiodes PDk,m,n and each successively inputting and accumulating the electric charges generated at the K photodiodes PDk,m,n (k=1 to K) and outputting a voltage that is in accordance with the amount of the accumulated electric charges; and (3) (M×N) filter circuits, one of each being provided in correspondence to each of the (M×N) integrating circuits and each reducing the thermal noise component contained in the voltage output from the corresponding integrating circuit and outputting the voltage after reduction of the thermal noise component.
With the photodetector of the present invention, for each value of m and each value of n, the electric charges that are respectively generated in accordance with the incidence of light in K photodiodes PDk,m,n (k=1 to K) are successively input and accumulated in a single integrating circuit and a voltage that is in accordance with the amount of the accumulated electric charges is output from the integrating circuit. The thermal noise component that is contained in the voltage output from each integrating circuit is reduced by a filter circuit, and the voltage after reduction of the thermal noise component is output from the filter circuit. Both a good S/N ratio and a high speed can thus be secured with this photodetector.
This invention's photodetector is preferably further equipped with CDS circuits, each being arranged between an integrating circuit and a filter circuit, inputting the voltage output from the integrating circuit, and outputting a voltage expressing the fluctuation of the input voltage over a fixed time. In this case, since the voltage output from each integrating circuit is input into a CDS circuit and the voltage expressing the fluctuation of the input voltage over a fixed time is output from the CDS circuit, the fluctuation of the offset of the amplifier of the integrating circuit can be eliminated by the CDS circuit.
This invention's photodetector is preferably further equipped with A/D converters, each inputting the voltage output from a filter circuit, performing A/D conversion on this voltage, and outputting a digital value that is in accordance with this voltage. In this case, the voltage output from each filter circuit is input into an A/D converter and a digital value that is in accordance with this voltage is output from the A/D converter.
With this invention's photodetector, the (K×M×N) photodiodes PDk,m,n are preferably arranged in M rows and (K×N) columns either two-dimensionally (when M=2) or one-dimensionally (when M=1), with each photodiode PDk,m,n being positioned at the position of the m-th row and (n+k−1)N)-th column. In this case, the processes (electric charge accumulation and filtering, and where necessary, CDS and A/D conversion) concerning the photodiodes can be carried out in the order of alignment in each column for each row.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is an overall diagram of a photodetector 1 in accordance with an embodiment.
FIG. 2 is a partial diagram of the photodetector 1 in accordance with the embodiment.
FIG. 3 is a circuit diagram of photodetector 1 of the embodiment.
FIG. 4 is a timing chart for explaining operations of the photodetector 1 in accordance with the embodiment.
FIG. 5 is a diagram of another circuit example of photodetector 1 of the embodiment.



BEST MODES FOR CARRYING OUT OF THE INVENTION
In the following, embodiments of the present invention will be explained in detail with reference to the accompanying drawings. In the explanation of the drawings, constituents identical to each other will be referred to with numerals identical to each other without repeating their overlapping descriptions.
FIG. 1 is an overall diagram of a photodetector 1 of the embodiment. FIG. 2 is a partial diagram of photodetector 1 of the embodiment. The details of a photodetection unit 10, shown in FIG. 1 are shown in FIG. 2.
A photodetector 1, which is illustrated in these figures, is equipped with photodetection unit 10, (M×N) integrating circuits 201,1 to 20M,N, (M×N) CDS circuits 301,1 to 30M,N, (M×N) filter circuits 401,1 to 40M,N, (M×N) A/D converters 501,1 to 50M,N, and a control circuit 60. Photodetection unit 10 has (K×M×N) photodiodes PD1,1,1 to PDK,M,N and (K×M×N) switches SW1,1,1 to SWK,M,N. Here, K indicates an integer no less than 2, M indicates an integer no less than 1, and N indicates an integer no less than 2. Also, in regard to k, m, n, which shall be used below, k indicates integers no less than 1 and no more than K, m indicates integers no less than 1 and no more than M, and n indicates integers no less than 1 and no more than N. In FIG. 1 and FIG. 2, K is set to 2 and M and N are both set to 4.
Each photodiode PDk,m,n generates electric charges of an amount that is in accordance with an incident light intensity and accumulates these electric charges in a junction capacitance portion. These (K×M×N) photodiodes PDk,m,n are arranged at equal intervals in M rows and (K×N) columns either two-dimensionally (when M=2) or one-dimensionally (when M=1). Each photodiode PDk,m,n is positioned at the position of the m-th row and the (n+k−1)N)-th column. Switches SWk,m,n are provided in a one-to-one correspondence with respect to photodiodes PDk,m,n and are arranged between PDk,m,n and signal lines SLm,n. Each set of K photodiodes PDk,m,n (k=1 to K) is connected via the corresponding switches SWk,m,m to a signal line SLm,n. Each signal line SLm,n is connected to an input end of an integrating circuit 20m,n. The opening/closing of each set of M switches SWk,m,n (m=1 to M) is controlled together by a control signal output to a control line CLk,n from control circuit 60.
Each of integrating circuits 20m,n is provided in correspondence to K photodiodes PDk,m,n (k=1 to K), inputs and accumulates the electric charges that are generated respectively at these K photodiodes PDk,m,n (k=1 to K) and arrive successively via switches SWk,m,n and signal line SLm,n, and outputs a voltage that is in accordance with the amount of the accumulated electric charges. Each CDS (correlated double sampling) circuit 30m,n inputs the voltage output from the corresponding integrating circuit 20m,n and outputs a voltage expressing the fluctuation over a fixed time of this voltage.
Each filter circuit 40m,n inputs the voltage output from the corresponding CDS circuit 30m,n, reduces the thermal noise component contained in this voltage, and outputs the voltage after reduction of the thermal noise component. Each filter circuit 40m,n is preferably a low-pass filter with filter characteristics that can reduce thermal noise components. Each A/D converter 50m,n inputs the voltage output from the corresponding filter circuit 40m,n, performs A/D conversion of this voltage, and outputs a digital value that is in accordance with this voltage (analog value).
Control circuit 60 outputs control signals for controlling the opening/closing of the respective (K×M×N) switches SW1,1,1 to SWK,M,N, to control lines CLk,n. Control circuit 60 also controls the respective operations of integrating circuits 20m,n, CDS circuits 30m,n, and A/D converters 50m,n.
FIG. 3 is a circuit diagram of photodetector 1 of the present embodiment. For the sake of simplification, just one of each of photodiodes PDk,m,n, switches SWk,m,n, integrating circuits 20m,n, CDS circuits 30m,n, filter circuits 40m,n, and A/D converters 50m,n are shown in the figure.
Integrating circuit 20m,n has an amplifier A20, an integrating capacitance element C20, and a switch SW20. The input terminal of amplifier A20 is connected to signal line SLm,n. Integrating capacitance element C20 and switch SW20 are arranged in parallel between the input and output terminals of amplifier A20. The opening/closing of switch SW20 is controlled by control unit 60. When switch SW20 is closed, integrating capacitance element C20 is discharged and the voltage output from integrating circuit 20m,n is initialized. On the other hand, when switch SW20 is open, the electric charges arriving via signal line SLm,n are accumulated in the integrating capacitance element C20 and a voltage that is in accordance with the amount of electric charges accumulated in this integrating capacitance element C20 is output from integrating circuit 20m,n.
CDS circuit 30m,n has an amplifier A30, an integrating capacitance element C31, a junction capacitance element C32, and a switch SW30. The input terminal of amplifier A30 is connected via junction capacitance element C32 to the output terminal of amplifier A20 of integrating circuit 20m,n. Integrating capacitance element C31 and switch SW30 are arranged in parallel between the input and output terminals of amplifier A30. The opening/closing of switch SW30 is controlled by control unit 60. When switch SW30 is closed, integrating capacitance element C31 is discharged and the voltage output from CDS circuit 30m,n is initialized. On the other hand, onwards from a time t at which switch SW30 is open, electric charges corresponding to the fluctuation of the voltage output from integrating circuit 20m,n, are accumulated in integrating capacitance element C31 and a voltage that is in accordance with the amount of electric charges accumulated in this integrating capacitance element C31 is output from CDS circuit 30m,n.
Filter circuit 40m,n has a resistance element R40 and a capacitance element C40. Resistance element R40 is arranged between the input end and the output end of filter circuit 40m,n and the output end thereof is connected via capacitance element C40 to the ground potential. This filter circuit 40m,n acts as a low-pass filter and in term of filter characteristics, the cutoff frequency thereof is in accordance with the resistance value of resistance element R40 and the capacitance value of capacitance element C40.
The characteristic values of the respective elements in the circuit diagram shown in FIG. 3 are, for example, as follows. That is, the sum of the junction capacitance value Cd of photodiode PDk,m,n and the parasitic capacitance value of signal line SLm,n is 220 pF and the resistance value of signal line SLm,n is 1 kΩ. The capacitance value Cf of integrating capacitance element C20 of integrating circuit 20m,n is 1.25 pF, the frequency bandwidth B of amplifier A20 of integrating circuit 20m,n is 1 MHz, and the input transistor's transconductance Gm of amplifier A20 is 10 mS. The temperature T is 27° C. In this case, the thermal noise Vn generated at amplifier A20 of integrating circuit 20m,n is 1210 μVrms. If the capacitance value of capacitance element C40 of filter circuit 40m,n is 100 pF and the resistance value of resistance element R40 of filter circuit 40m,n n is 20 kΩ, the cutoff frequency of the filter characteristics of filter circuit 40m,n will be 0.08 MHz and the thermal noise component contained in the voltage output from filter circuit 40m,n will be reduced to 724 μVrms.
The operations of the photodetector 1 of the present embodiment shall now be described. The photodetector 1 of the present embodiment operates as described below under the control of control unit 60. FIG. 4 is a timing chart illustrating the operations of photodetector 1 of the present embodiment. With this photodetector 1, the first row to the M-th row operate in parallel.
In this figure, the opening/closing of switch SW1,m,1, the opening/closing of switch SW1,m,2, the opening/closing of switch SW1,m,3, the opening/closing of switch SW1,m,4, the opening/closing of switch SW2,m,1, the opening/closing of switch SW2,m,2, the opening/closing of switch SW2,m,3, and the opening/closing of switch SW2,m,4 are shown in that order from the top. Thereafter, the output voltage of integrating circuit 20m,1, the output voltage of integrating circuit 20m,2, the output voltage of integrating circuit 20m,3, the output voltage of integrating circuit 20m,4, the output voltage of filter circuit 40m,1, the output voltage of filter circuit 40m,2, the output voltage of filter circuit 40m,3, the output voltage of filter circuit 40m,4, the output digital value of A/D converter 50m,1, the output digital value of A/D converter 50m,2, the output digital value of A/D converter 50m,3, and the output digital value of A/D converter 50m,4 are shown.
Also as shown in this figure, the operations of photodetector 1 are divided into the eight periods of T1,1, T1,2, T1,3, T1,4, T2,1, T2,2, T2,3, and T2,4 that cycle. The duration T of each of these periods Tk,n is fixed. Switch SW1,m,1 is closed during period T1,1, switch SW1,m,2 is closed during period T1,2, switch SW1,m,3 is closed during period T1,3, switch SW1,m,4 is closed during period T1,4, switch SW2,m,1 is closed during period T2,1, switch SW2,m,2 is closed during period T2,2, switch SW2,m,3 is closed during period T2,3, and switch SW2,m,4 is closed during period T2,4. Subsequently, such opening and closing of the switches are repeated.
Switch SW1,m,1 is closed during period T1,1. Also, prior to this period T1,1, switch SW20 of integrating circuit 20m,1 closes once and then opens and the output voltage of integrating circuit 20m,1 is thereby initialized. When switch SW1,m,1 closes, the electric charges generated in photodiode PD1,m,1 and accumulated in the junction capacitance portion until then are input via switch SW1,m,1 and signal line SLm,1 into integrating circuit 20m,1 and become accumulated in integrating capacitance element C20 of integrating circuit 20m,1 and a voltage that is in accordance with the amount of the accumulated electric charges is output from integrating circuit 20m,1. After period T1,1, the output voltage of integrating circuit 20m,1 is held until period T1,3, and when switch SW20 of integrating circuit 20m,1 closes at period T1,4, the output voltage of integrating circuit 20m,1 is initialized.
The output voltage of integrating circuit 20m,1 is input into CDS circuit 30m,1. From this CDS circuit 30m,1 is output a voltage that is in accordance with the amount of fluctuation of the output voltage of integrating circuit 20m,1 in the fixed duration from period T1,1 to T1,2. The output voltage of CDS circuit 30m,1 is input into filter circuit 40m,1 and the thermal noise component is reduced. However, due to the filter characteristics of filter circuit 40m,1, the output voltage waveform of filter circuit 40m,1 is dulled in comparison to the output voltage waveform of CDS circuit 30m,1.
At the point at which the output voltage of filter circuit 40m,1 is stable, this voltage is A/D converted by A/D converter 50m,1 and a digital value is output from A/D converter 50m,1 in period T1,3. The digital value that is output from A/D converter 50m,1 in period T1,3 is in accordance with the amount of electric charges that have moved from the junction capacitance portion of photodiode PD1,m,1 to integrating capacitance element C20 of integrating circuit 20m,1 and thus in accordance with the intensity of light incident on photodiode PD1,m,1 in period T1,1.
Switch SW2,m,1 is closed during period T2,1. Prior to this period T2,1, switch SW20 of integrating circuit 20m,1 closes once and then opens and the output voltage of integrating circuit 20m,1 is thereby initialized. When switch SW2,m,1 closes, the electric charges generated in photodiode PD2,m,1 and accumulated in the junction capacitance portion until then are input via switch SW2,m,1 and signal line SLm,1 into integrating circuit 20m,1 and are accumulated in integrating capacitance element C20 of integrating circuit 20m,1 and a voltage that is in accordance with the amount of the accumulated electric charges is output from integrating circuit 20m,1. After period T2,1, the output voltage of integrating circuit 20m,1 is held until period T2,3, and when switch SW20 of integrating circuit 20m,1 closes at period T2,4, the output voltage of integrating circuit 20m,1 is initialized.
The output voltage of integrating circuit 20m,1 is input into CDS circuit 30m,1. From this CDS circuit 30m,1 is output a voltage that is in accordance with the amount of fluctuation of the output voltage of integrating circuit 20m,1 in the fixed duration from period T2,1 to T2,2. The output voltage of CDS circuit 30m,1 is input into filter circuit 40m,1 and the thermal noise component is reduced. However, due to the filter characteristics of filter circuit 40m,1, the output voltage waveform of filter circuit 40m,1 is dulled in comparison to the output voltage waveform of CDS circuit 30m,1.
At the point at which the output voltage of filter circuit 40m,1 is stable, this voltage is A/D converted by A/D converter 50m,1 and a digital value is output from A/D converter 50m,1 in period T2,3. The digital value that is output from A/D converter 50m,1 in period T2,3 is in accordance with the amount of electric charges that have moved from the junction capacitance portion of photodiode PD2,m,1 to integrating capacitance element C20 of integrating circuit 20m,1 and thus in accordance with the intensity of light incident on photodiode PD2,m,1 in period T2,1.
In the above, the operations of switch SW1,m,1, switch SW2,m,1, integrating circuit 20m,1, CDS circuit 30m,1, filter circuit 40m,1, and A/D converter 50m,1, that is, the operations in the case where n is 1 was described. For n=2 to 4, the same operations are carried out with the timing of the operations being shifted.
A digital value that is in accordance with the intensity of light incident on photodiode PD1,m,1 is thus output in period T1,3, a digital value that is in accordance with the intensity of light incident on photodiode PD1,m,2 is output in period T1,4, a digital value that is in accordance with the intensity of light incident on photodiode PD1,m,3 is output in period T2,1, a digital value that is in accordance with the intensity of light incident on photodiode PD1,m,4 is output in period T2,2, a digital value that is in accordance with the intensity of light incident on photodiode PD2,m,1 is output in period T2,3, a digital value that is in accordance with the intensity of light incident on photodiode PD2,m,2 is output in period T2,4, a digital value that is in accordance with the intensity of light incident on photodiode PD2,m,3 is output in the subsequent period T1,1, and a digital value that is in accordance with the intensity of light incident on photodiode PD2,m,4 is output in period T1,2.
As described above, with photodetector 1 of the present embodiment, (K×M×N) photodiodes PDk,m,n are arranged in M rows and (K×N) columns in photodetection unit 10, and processes (electric charge accumulation, CDS, filtering, and A/D conversion) regarding the (K×N) photodiodes PDk,m,n (K=1 to K, n=1 to N) of each row are carried out successively at each time T. Meanwhile, each of the electric charge accumulation operation in integrating circuit 20m,n, the CDS operation in CDS circuit 30m,n, the filtering operation in filter circuit 40m,n, and the A/D conversion operation in A/D converter 50m,n is carried out at each time (N×T).
With photodetector 1 of the present embodiment, the thermal noise component contained in the voltage output from integrating circuit 20m,n is reduced by filter circuit 40m,n. Also, though the voltage waveform output from filter circuit 40m,n is dulled, the operations from the electric charge accumulation in integrating circuit 20m,n to the A/D conversion in A/D converter 50m,n are carried out at each time (N×T), and the voltage that is output from filter circuit 40m,n is A/D converted by A/D converter 50m,n at the point at which it has stabilized. Thus with this photodetector 1, the S/N ratio of photodetection can be improved while maintaining high speed of photodetection. Also, since the S/N ratio of photodetection can be improved without making large the input transistor's transconductance Gm of amplifier A20 included in integrating circuit 20m,n, increase of the consumption power of amplifier A20 is restrained and the problem of heat generation is reduced.
Also, since by the provision of CDS circuit 30m,n, the offset fluctuation of amplifier A20 of integrating circuit 20m,n is eliminated by CDS circuit 30m,n, the S/N ratio of photodetection is improved from this point as well. Though CDS circuit 30m,n also contains amplifier A30, the thermal noise generated at this amplifier A30 is minute in comparison to the thermal noise generated at amplifier A20 included in integrating circuit 20m,n.
Also, since by the provision of A/D converter 50m,n, the photodetection data obtained by photodetector 1 are output as digital values, storage and image processing of the photodetection data can be carried out readily Also, since the requirement of high-speed processing is relaxed in terms of A/D converter 50m,n, the increase of consumption power at A/D converter 50m,n is also restrained.
Furthermore, since (K×M×N) photodiodes PDk,m,n are arranged in M rows and (K×N) columns, each photodiode PDk,m,n is positioned at the position of the m-th row and the (n+(k−1)N)-th column, and the processes (electric charge accumulation, CDS, filtering, and A/D conversion) regarding photodiodes PDk,m,n are carried out in the order of alignment in each column for each row, the storage and image processing of the photodetection data obtained by the photodetector 1 are facilitated from this point as well.
Though in the above-described embodiment, filter circuit 40m,n was arranged at a stage subsequent CDS circuit 30m,n, the filter circuit may instead be arranged between integrating circuit 20m,n and CDS circuit 30m,n. Though the filter circuit that is arranged between integrating circuit 20m,n and CDS circuit 30m,n may have the same arrangement as filter circuit 40m,n described above, it may instead be arranged from just a resistance element R as shown in FIG. 5. This resistance element R can also act as a low-pass filter.
INDUSTRIAL APPLICABILITY
As has been described in detail above, with the photodetector of the present invention, for each value of m and each value of n, the electric charges that are respectively generated in accordance with the incidence of light in K photodiodes PDk,m,n (k=1 to K) are successively input and accumulated in a single integrating circuit and a voltage that is in accordance with the amount of the accumulated electric charges is output from the integrating circuit. The thermal component that is contained in the voltage output from each integrating circuit is reduced by a filter circuit, and the voltage after reduction of the thermal noise component is output from the filter circuit. Both a good S/N ratio and a high speed can thus be secured with this photodetector.

## Claims

1. A photodetector comprising:
(K×M×N) photodiodes PDk,m,n (K being an integer of no less than 2; k being integers of no less than 1 and no more than K; M being an integer of no less than 1; m being integers of no less than 1 and no more than M; N being an integer of no less than 2; and n being integers of no less than 1 and no more than N), each generating an electric charge by an amount corresponding to an intensity of light incident thereon;
(M×N) integrating circuits, one of each being provided in correspondence to K photodiodes PDk,m,n (k=1 to K) among the (K×M×N) photodiodes PDk,m,n and each successively inputting and accumulating the electric charges generated at the K photodiodes PDk,m,n (k=1 to K) and outputting a voltage that is in accordance with the amount of the accumulated electric charges; and
(M×N) filter circuits, one of each being provided in correspondence to each of the (M×N) integrating circuits and each reducing the thermal noise component contained in the voltage output from the corresponding integrating circuit and outputting the voltage after reduction of the thermal noise component,
wherein the (K×M×N) photodiodes PDk,m,n are arranged in M rows and (K×N) columns either two-dimensionally (when M=2) or one-dimensionally (when M=1), with each photodiode PDk,m,n being positioned at the position of the m-th row and (n+(k−1)N)-th column,
switches SWk,m,n are provided in a one-to-one correspondence with respect to photodiodes PDk,m,n and are arranged between the photodiodes PDk,m,n and signal lines SLm,n,
each set of K photodiodes PDk,m,n (k=1 to K) is connected via the corresponding switches SWk,m,n to a signal line SLm,n,
each signal line SLm,n is connected to an input end of an integrating circuit, and
switches SWk,m,n on the same row are connected to the same control line CLk,n and the opening/closing of each row of switches SWk,m,n is controlled together by a control signal that is transmitted via the control line CLk,n.

2. The photodetector according to claim 1, further comprising CDS circuits, each being arranged between said integrating circuit and said filter circuit, inputting the voltage output from the integrating circuit, and outputting a voltage expressing the fluctuation of the input voltage over a fixed time.

3. The photodetector according to claim 1, further comprising A/D converters, each inputting the voltage output from said filter circuit, performing A/D conversion on this voltage, and outputting a digital value that is in accordance with this voltage.