# Patent

## Title
Low drop-out regulator with fast current limit

## Abstract

An LDO with fast current limit includes P-type transistor, an error amplifier, an adjustable reference voltage circuit for generating an adjustable reference voltage, and an N-type transistor. The P-type transistor includes a first end coupled to the input voltage source, a second end for outputting an output voltage source, and a control end for receiving a current control signal in order to control the current of the output voltage source. The error amplifier generates the current control signal according to the reference voltage and a voltage divided from the output voltage source. N-type transistor includes a first end coupled to the output end of the error amplifier, a second end coupled to the input voltage source, and a control end for receiving the adjustable reference voltage. When the N-type transistor is turned on, the voltage of the current control signal is clamped by the adjustable reference voltage.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a Low Drop-Out (LDO) regulator, and more particularly, to an LDO regulator with fast current limit.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional LDO regulator 100. As shown in FIG. 1, the LDO regulator 100 comprises a sensing resistor RSEN, a reference resistor RREF, two feedback resistors RFB1 and RFB2, a reference current source IREF, a comparator CMP, an error amplifier EA, and a transistor Q1. The transistor Q1 is a P channel Metal Oxide Semiconductor (PMOS) transistor.
The LDO regulator 100 is used to convert an input voltage source VIN to an output voltage source VOUT for providing the voltage VOUT and the load current ILOAD to the load X. The detail of operation principles is explained as follows.
The feedback resistors RFB1 and RFB2 are coupled between the output voltage source VOUT and a ground end for providing a feedback voltage VFB divided from the output voltage VOUT to the error amplifier EA. The error amplifier EA comprises a positive input end for receiving the feedback voltage VFB, a negative input end for receiving a reference voltage VREF2, and an output end for outputting a current control signal VA according to the signals received on the positive and negative input ends of the error amplifier EA. The control end (gate) of the transistor Q1 is coupled to the output end of the error amplifier EA for receiving the current control signal VA. In this way, the transistor Q1 controls the magnitudes of the output voltage VOUT and the load current ILOAD according to the current control signal VA. More particularly, if the voltage of the current control signal VA is lower, the load current ILOAD is higher; if the voltage of the current control signal VA is lower, the load current ILOAD is higher. Consequently, when the feedback voltage VFB is lower than the reference voltage VREF2 (for example, when the load current ILOAD drained by the load X increases), the current control signal VA generated from the error amplifier EA turns on the transistor Q1 more for raising the output voltage VOUT. That is, the voltage of the current control signal VA is decreased.
The reference resistor RREF is coupled between the input voltage source VIN, the reference current source IREF and the positive input end of the comparator CMP for providing a reference voltage VREF1 to the comparator CMP. The sensing resistor RSEN is coupled between the input voltage source VIN and the negative input end of the comparator CMP for providing the sensing voltage VSEN to the comparator CMP. The comparator CMP generates the current limit signal SC according to the comparing result of the magnitudes of the reference voltage VREF1 between the sensing voltage VSEN. More particularly, if the sensing voltage VSEN is higher than the reference voltage VREF1, the current limit signal SC is logic “0” (low voltage level); otherwise, if the sensing voltage VSEN is lower than the reference voltage VREF1, the current limit signal SC is logic “1” (high voltage level). Since the sensing resistor RSEN is serial-connected between the input voltage source VIN and the transistor Q1, the magnitude of the load current ILOAD can be detected according to the values of the sensing voltage VSEN and the sensing resistor RSEN. In this way, the load current ILOAD can be limited by the comparator CMP. More particularly, if the sensing voltage VSEN is lower than the reference voltage VREF1, which means the load current ILOAD is higher than current limit ILIMIT, the comparator CMP outputs the current limit signal with logic “1” to the error amplifier EA to disable the error amplifier EA. In other words, when the current limit signal SC is logic “1”, the error amplifier EA is disabled to keep lowering the voltage of the current control signal VA. In this way, the level of the transistor Q1 being turning on is limited, which limits the magnitude of the load current ILOAD.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating variation of the load current of the conventional LDO regulator 100. As shown in FIG. 2, the drawback of the conventional LDO regulator 100 is that, in the conventional LDO regulator 100, detecting the load current has to execute through the conversion from the sensing resistor RSEN and the comparator CMP for providing the current limit control signal SC. Therefore, by such mechanism for detecting the load current ILOAD, some reaction time has to be required in order to effectively limit the load current ILOAD. If the load current LLOAD increases excessively and suddenly (for example, the load X is short-circuited), the conventional LDO regulator 100 is not able to effectively and quickly limit the load current ILOAD so that the load current ILOAD is possibly higher than current limit ILIMIT, which damages the related components.
Additionally, since the sensing resistor RSEN and the transistor Q1 are serial-connected, consequently, the equivalent impedance between the input and the output voltage sources VIN and VOUT is increased because of the addition of the sensing resistor RSEN, causing power waste and increasing the minimal voltage difference between the input and the output voltages of the LDO regulator 100, and thus the efficiency of the LCO regulator 100 is decreased.
SUMMARY OF THE INVENTION
The present invention provides a Low Drop-Out (LDO) regulator with fast current limit. The LDO regulator comprises a first transistor, an error amplifier, an adjustable reference voltage circuit, and a second transistor. The first transistor comprises a first end coupled to an input voltage source, a second end for outputting an output voltage source, and a control end for receiving a current control signal to control current of the output voltage source outputted from the second end of the first transistor. The error amplifier comprises a negative input end for receiving a reference voltage, a positive input end for receiving a voltage divided from the output voltage source, and an output end. The error amplifier generates the current control signal through the output end of the error amplifier according to the reference voltage and the voltage divided from the output voltage source. The adjustable reference voltage circuit is for generating an adjustable reference voltage. The second transistor comprises a first end coupled to the output end of the error amplifier, a second end, coupled to the input voltage source, and a control end coupled to the adjustable reference voltage circuit for receiving the adjustable reference voltage. When the second transistor is turned on, voltage of the current control signal is clamped by the adjustable reference voltage.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram illustrating a conventional LDO regulator.
FIG. 2 is a diagram illustrating variation of the load current of the conventional LDO regulator.
FIG. 3 is a diagram illustrating the LDO regulator with fast current limit of the present invention.
FIG. 4 is a diagram illustrating the variation of the load current of the LDO regulator with fast current limit of the present invention.
FIG. 5 is a diagram illustrating the adjustable reference voltage circuit according to a first embodiment of the present invention.
FIG. 6 is a diagram illustrating the adjustable reference voltage circuit according to a second embodiment of the present invention.



DETAILED DESCRIPTION
Please refer to FIG. 3. FIG. 3 is a diagram illustrating the LDO regulator 300 with fast current limit of the present invention. As shown in FIG. 3, the LDO regulator 300 comprises an error amplifier EA, two feedback resistors RFB1 and RFB2, two transistors Q1 and Q2, and an adjustable reference voltage circuit 310. The transistor Q1 is a PMOS transistor, and the transistor Q2 is an N channel Metal Oxide Semiconductor (NOMS) transistor.
The LDO regulator 300 is used to convert an input voltage source VIN to an output voltage source VOUT for providing the voltage VOUT and the load current ILOAD to the load X. The detail of operation principles is explained as follows.
The feedback resistor RFB1 and RFB2 are coupled between the output voltage source VOUT and a ground end for providing the feedback voltage VFB divided from the output voltage VOUT to the error amplifier EA. The error amplifier EA comprises a positive input end for receiving the feedback voltage VFB, a negative input end for receiving a reference voltage VREF2, and an output end for outputting current control signal VA according to the signals received on the positive and negative input ends of the error amplifier EA. The control end (gate) of the transistor Q1 is coupled to the output end of the error amplifier EA for receiving the current control signal VA. In this way, the transistor Q1 controls the magnitudes of the output voltage VOUT and the load current ILOAD according to the current control signal VA. More particularly, if the current control signal VA is lower, the load current ILOAD is higher; otherwise, if the current control signal VA is higher, the load current ILOAD is lower. Consequently, if the feedback voltage VFB is lower than the reference voltage VREF2 (for example, when the load current ILOAD drained by the load X increases), the current control signal VA generated from the error amplifier EA turns on the transistor Q1 more for raising the output voltage VOUT. That is, the voltage of the current control signal VA is decreased.
The adjustable reference voltage circuit 310 provides an adjustable reference voltage VB. The value of the adjustable reference voltage VB is adjusted according to the magnitude of the input voltage VIN. The control end (gate) of transistor Q2 is coupled to the adjustable reference voltage circuit 310 for receiving the adjustable reference voltage VB; the first end (source) of the transistor Q2 is coupled to the output end of the error amplifier EA; the second end (drain) of transistor Q2 is coupled to the input voltage source VIN.
In the normal operation, the transistor Q2 is turned off, which means that the current control signal VA of the error amplifier EA is able to adjust the load current ILOAD conducted by the transistor Q1 without limit. In the abnormal condition, such as the load current ILOAD exceeding a predetermined value (for example, when the load X is short-circuited), the transistor Q2 is turned on, and thus the current control signal VA of the error amplifier EA is limited at a voltage lower than the voltage VB by a threshold voltage VTH2, wherein the threshold voltage VTH2 represents the threshold voltage of the transistor Q2. In this way, the current control signal VA is unable to decrease further, and the magnitude of the load current ILOAD is effectively controlled not to be higher than current limit ILIMIT. Besides, the adjustable reference voltage VB has to be adjusted according to the magnitude of the input voltage VIN for keeping the load current ILOAD having the same current limit as the current limit ILIMIT under different magnitudes of the input voltage VIN. The detail of operation principles of the LDO regulator 300 of the present invention limiting the load current is explained as follows.
Under the condition that the load current is lower, the current control signal VA of the error amplifier EA is high enough to turn off the transistor Q2. More particularly, the current control signal VA has to be not lower than the adjustable reference voltage VB by the threshold voltage VTH2 (VA>VTH2) so that the current control signal VA is not affected by the transistor Q2. However, when the load current ILOAD increases, which means the current control signal VA decreases, once the voltage of the current control signal VA is lower than the adjustable reference voltage VB by the threshold voltage VTH2, the transistor Q2 is turn on, and the voltage of current control signal VA is clamped at a voltage lower than the adjustable reference voltage VB by the threshold voltage VTH2. In other word, by the clamping mechanism of the transistor Q2 of the present invention, the voltage of the current control signal VA is never lower than the adjustable reference voltage VB by the threshold voltage VTH2. In this way, the load current ILOAD outputted from the transistor Q1 does not exceed the current limit ILIMIT even for a very short moment. Therefore, the problem of the related components damaged by the sudden large current can be solved.
Additionally, the magnitude of the adjustable reference voltage VB is used to set the magnitude of the current limit ILIMIT.
Please refer to FIG. 4. FIG. 4 is a diagram illustrating the variation of the load current of the LDO regulator 300 with fast current limit of the present invention. As shown in FIG. 4, because of the adjustable reference voltage circuit 310 and the transistor Q2, the load current ILOAD is not higher than the current limit ILIMIT even if the load X is short-circuited, which avoids the damage of the related components.
Furthermore, since the LDO regulator 300 of the present invention does not dispose a sensing resistor between the input voltage source VIN and the transistor Q1, consequently, the equivalent resistance of the LDO regulator between the input voltage source VIN and the transistor Q1 is lower than that of the conventional LDO regulator. Therefore, the power waste between the input voltage source VIN and the transistor Q1 is reduced, and the minimal voltage drop between the input voltage source VIN and the transistor Q1 is reduced as well, and thus the efficiency of the LCO regulator 300 of the present invention is increased.
Please refer to FIG. 5. FIG. 5 is a diagram illustrating the adjustable reference voltage circuit 310 according to a first embodiment of the present invention. As shown in FIG. 5, the adjustable reference voltage circuit 310 comprises two dividing resistors RX1 and RX2. The dividing resistors RX1 and RX2 are serial-coupled between the input voltage source VIN and the ground end. The adjustable reference voltage VB is a voltage divided from the input voltage source VIN according to the resistances of the resistors RX1 and RX2. More particularly, the adjustable reference voltage VB is the voltage on the dividing resistor RX2. As shown in FIG. 5, if the input voltage source VIN is higher, the adjustable reference voltage VB is higher; otherwise, if the input voltage source VIN is lower, the adjustable reference voltage VB is lower. In this way, the adjustable reference voltage VB is able to dynamically change in accordance with the input voltage source VIN, which allows the range of the limit of the current control signal VA to change as well for controlling the current limit ILIMIT at a fixed value.
Please refer to FIG. 6. FIG. 6 is a diagram illustrating the adjustable reference voltage circuit 310 according to a second embodiment of the present invention. As shown in FIG. 6, the adjustable reference voltage circuit 310 comprises an impedance circuit 311, a first current mirror 312, a second mirror 313, and a resistor RX2. The voltage on the resistor RX2 is served as the adjustable reference voltage VB. The impedance circuit 311 comprises a resistor RX1, and N transistors QD1 ̃QDN. The drain and the gate of each of the N transistors QD1 ̃QDN are coupled together to form a diode, and therefore, the N transistors QD1 ̃QDN can be seen as a plurality of diodes connected in series. The impedance circuit 311 is coupled between the input voltage source VIN and the first current mirror 312, where the reference current IB passes. The first current mirror 312 comprises the transistors Q5 and Q6 for replicating the reference current IB to the second mirror 313. The second mirror 313 comprises the transistors Q3 and Q4 for replicating the reference current IB again and providing to the resistor RX2. In this way, the adjustable reference voltage VB is generated on the resistor RX2 (VB=RX2×IB). As shown in FIG. 6, if the input voltage VIN increases, the current IB increases, and the adjustable reference voltage VB increases; otherwise, if the input voltage source VIN decreases, the current IB decreases, and the adjustable reference voltage VB decreases. In this way, the adjustable reference voltage VB is able to dynamically change in accordance with the input voltage VIN, which allows the range of the limit of the current control signal VA to change as well for controlling the current limit ILIMIT at a fixed value.
To sum up, the LDO regulator provided by the present invention limits the load current to be not higher than current limit fast and effectively, and reduces the power waste between the input and output voltage sources of the LDO regulator, which decreases the rising temperature caused by the power waste of the LDO regulator, providing great convenience.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

## Claims

1. A Low Drop-Out (LDO) regulator with fast current limit, comprising:
a first transistor, comprising:
a first end, coupled to an input voltage source;
a second end for outputting an output voltage source; and
a control end for receiving a current control signal to control current of the output voltage source outputted from the second end of the first transistor;

an error amplifier, comprising:
a negative input end for receiving a reference voltage;
a positive input end for receiving a voltage divided from the output voltage source; and
an output end, the error amplifier generating the current control signal through the output end of the error amplifier according to the reference voltage and the voltage divided from the output voltage source;

an adjustable reference voltage circuit for generating an adjustable reference voltage; and
a second transistor, comprising:
a first end, coupled to the output end of the error amplifier;
a second end, coupled to the input voltage source; and
a control end, coupled to the adjustable reference voltage circuit for receiving the adjustable reference voltage;
wherein when the second transistor is turned on, voltage of the current control signal is clamped by the adjustable reference voltage.

2. The LDO regulator of claim 1, further comprising:
a first resistor, coupled to the output voltage source; and
a second resistor, coupled between the first resistor and a ground end, and coupled to the positive input end of the error amplifier for providing a voltage divided from the output voltage source.

3. The LDO regulator of claim 1, wherein when the voltage of the current control signal is lower, current of the output voltage source outputted from the first transistor is higher; when the voltage of the current control signal is higher, the current of the output voltage source outputted from the first transistor is lower.

4. The LDO regulator of claim 1, wherein the second transistor is turned on when the voltage of the current control signal is lower than a predetermined value.

5. The LDO regulator of claim 4, wherein the second transistor is turned on according to a following equation:


VA≦(VB−VTH);

wherein VA represents the voltage of the current control signal, VB represents the adjustable reference voltage, and VTH represents threshold voltage of the second transistor.

6. The LDO regulator of claim 5, wherein when the second transistor is turned on, the voltage of the current control signal is cramped at VB−VTH.

7. The LDO regulator of claim 1, wherein the first transistor is a P channel Metal Oxide Semiconductor (PMOS) transistor and the second transistor is an N channel Metal Oxide Semiconductor (NMOS) transistor.

8. The LDO regulator of claim 1, wherein the adjustable reference voltage outputted from the adjustable reference voltage circuit is adjusted according to a voltage of the input voltage source.

9. The LDO regulator of claim 8, wherein the adjustable reference voltage comprises:
a first resistor, coupled to the input voltage source; and
a second resistor, coupled between the first resistor and a ground end, and coupled to the control end of the second transistor;
wherein a voltage on the second resistor is served as the adjustable reference voltage.

10. The LDO regulator of claim 8, wherein the adjustable reference voltage circuit comprises:
an impedance circuit, coupled to the input voltage source for generating a reference current accordingly;
a first current mirror, coupled to the impedance circuit for replicating the reference current and outputting the replicated reference current;
a second current mirror, coupled to the first current mirror for replicating the reference current again and outputting the replicated reference current; and
a third resistor, coupled to the second current mirror, for receiving the replicated reference current, and generating the adjustable reference voltage accordingly.

11. The LDO regulator of claim 10, wherein the impedance circuit comprises:
a fourth resistor, coupled to the input voltage source; and
a plurality of transistors connected in series, coupled between the fourth resistor and the first current mirror;
wherein a first end of each of the plurality of the transistors is coupled to a control end of a corresponding transistor of the plurality of the transistors in order to be utilized as a diode.

12. The LDO regulator of claim 11, wherein the first current mirror comprises:
a third transistor, comprises:
a first end, coupled to the plurality of the transistors connected in series;
a second end, coupled to a ground end; and
a control end, coupled to the first end of the third transistor; and

a fourth transistor, comprises:
a first end for outputting the replicated reference current;
a second end, coupled to the ground end; and
a control end, coupled to the first end of the third transistor.

13. The LDO regulator of claim 12, wherein the second current mirror comprises:
a fifth transistor, comprises:
a first end, coupled to the input voltage source;
a second end, coupled to the first end of the fourth transistor; and
a control end, coupled to the first end of the fourth transistor; and

a sixth transistor, comprises:
a first end, coupled to the third resistor, for outputting the replicated reference current in order to generate the adjustable reference voltage;
a second end, coupled to the input voltage source; and
a control end, coupled to the first end of the fourth transistor.