# Patent

## Title
Power supply circuit containing multiple DC-DC converters having programmable output current capabilities

## Abstract

A apparatus and method of operating a power converter circuit is provided. The method selectively couples control signals to at least one output driver stage of a plurality of output driver stages of the power converter circuit to obtain a desired output at a select output port of the plurality of output ports. Wherein each output driver stage has a defined current drive capacity that is output to the select output port in response to the control signals.

## Background
RELATED CASES
The present application claims priority to and is a continuation application of U.S. application Ser. No. 11/006,006 entitled “Power Supply Circuit Containing Multiple DC-DC Converters Having Programmable Output Current Capabilities,” filed on Dec. 7, 2004, now U.S. Pat. No. 7,345,378, which is herein incorporated by reference in its entirety.


BACKGROUND OF THE INVENTION
The continuing growth and expansion of the electronics industry has been accompanied by a demand for DC power supplies having a wide variety of performance specifications. Depending upon the application, it is not uncommon for a given product design to employ a plurality of DC power supplies, which not only differ in terms of their output voltages, but which have differing current capabilities among the power supply outputs. Although power supply manufacturers have been able to provide power supplies that meet these and other user needs, each power supply's implementation is often custom-configured to a given specification (e.g., output voltage and output current drive capability). This means that the user must maintain an inventory of different power supply circuits, to accommodate variations in application requirements. To reduce cost and inventory complexity, the user would prefer that performance characteristics of the various circuits within its power supply inventory be programmable or user-configurable.
SUMMARY OF THE INVENTION
The above-mentioned problems of current systems are addressed by embodiments of the present invention and will be understood by reading and studying the following specification. The following summary is made by way of example and not by way of limitation. It is merely provided to aid the reader in understanding some of the aspects of the invention.
In one embodiment, a method of operating a power converter circuit is provided. The method comprises selectively coupling control signals to at least one output driver stage of a plurality of output driver stages of the power converter circuit to obtain a desired output at a select output port of the plurality of output ports. Wherein each output driver stage has a defined current drive capacity that is output to the select output port in response to the control signals.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic-block diagram of the general architecture of a user-configurable synchronous buck power supply circuit architecture in accordance with the invention;
FIG. 2 shows an augmentation of the user-configurable synchronous buck power supply circuit architecture of FIG. 1, which enables the user to determine whether the power supply circuit has been configured as intended; and
FIG. 3 shows a further augmentation of the user-configurable synchronous buck power supply circuit architecture of FIG. 1, which includes logic circuitry that is operative to automatically internally configure connections provided by respective switches from the buck controllers to the output driver stages.



DETAILED DESCRIPTION
Before detailing the user-configurable power supply circuit architecture of the invention, it should be observed that the present invention resides primarily in a novel combination of conventional controlled power supply and switching circuits and components therefor. In a practical implementation, these circuits and components may be readily implemented using field programmable gate array (FPGA)-configured, application specific integrated circuit (ASIC) chip sets and associated power MOSFETs. Consequently, the configuration of such circuits and components have, for the most part, been depicted in the drawings by readily understandable schematic-block diagrams, which show only those specific features that are pertinent to the present invention, so as not to obscure the disclosure with details which will be readily apparent to those skilled in the art having the benefit of the description herein. Thus, the diagrammatic illustrations are primarily intended to show the major functional components of the invention in convenient groupings that will enable the present invention to be more readily understood.
The synchronous buck converter has been selected for representation in FIGS. 1 to 3 and detailed description, but the invention is equally applicable to standard buck, standard boost, synchronous boost, and linear converters as will be understood by those skilled in the art. Although only one type of converter has been selected for detailed description, the synchronous buck, it is to be understood that the invention is not limited to synchronous buck converters.
Attention is now directed to FIG. 1, which is a schematic-block diagram of the general architecture of a user-configurable synchronous buck power supply circuit architecture in accordance with the invention. Implementation of the invention may be accomplished by alternative configurations. In one embodiment all of the power supply components may be contained in a common semi-conductor chip. In an alternative embodiment a modular architecture containing multiple circuit chips may be employed. As pointed out briefly above, and as will be detailed hereinafter, the power supply architecture of the present invention contains a plurality of DC-DC converter control loops that are operative to provide respectively different control signals, PWM signals for switching regulators and bias voltages for linear regulators, associated with different output voltages capable of being supplied by the circuit. In the illustrated embodiment, only two such control loops, designated buck controller 10 and buck controller 20, are shown. It is to be understood, however, that the invention is not limited to this or any other number. The number of control loops in the architecture of FIG. 1 has been limited to two, in order to reduce the complexity of the drawings, while still providing a readily understandable illustration of both the architecture and functionality of the invention.
In a similar manner, although only four (power MOSFET-based) output driver stages (designated output driver stages 31, 32, 33, 34) and only two output voltage terminals (designated output terminals Vout1 and Vout2) have been shown, it is to be understood that the invention is not limited to these or any other numbers of output driver stages or output voltage terminals. As in the case of illustrating only two control loops 10 and 20, the illustrated numbers of output driver stages and output voltage terminals are for the purpose of facilitating a ready understanding of the functionality and architecture of the invention, without unduly burdening the drawings.
In order to provide an appreciation for the considerable flexibility that is offered by the architecture of the present invention, each of the output driver stages 31-34 has a respectively different current drive capability. It is to be observed, however, that the current drive capabilities of the output driver stages need not be respectively different from one another; they may be the same, or differ in any manner desired. For purposes of the present description, output driver stage 31 may have a one amp (1 A) current drive capability, output driver stage 32 may have a two amp (2A) current drive capability, output driver stage 33 may have a three amp (3 A) current drive capability, and output driver stage 34 may have a four amp (4 A) current drive capability.
Each output driver stage includes an upper electronic driver device, such as an upper power field effect transistor, or UFET, having its source-drain current flow path coupled between an upper power supply rail UR and a common or phase node, which corresponds to one of the phase nodes A, B, C and D. Each of the phase nodes of the output driver stages constitutes an available output port that is intended to be selectively externally connected to one end of an output inductor L, a second end of which is coupled to an output filter capacitor C and one of a pair of output voltage ports Vout1 and Vout2 of the overall power supply. Each output driver stage further includes a lower electronic driver device, such as a lower power FET, or LFET, having its source-drain current flow path coupled between a lower power supply rail LR and one of the phase nodes A, B, C and D.
In an integrated circuit realization of the invention the inductors and output capacitors would be external to the integrated circuit, and the phase nodes of the output stages would be individually available to connect as required. In a multi-component module realization, inductors and capacitors would be included in the module with access to pins allowing arbitrary connection to output stages and output voltage ports.
The gate control input to the UFET of a respective output driver stage is selectively coupled through an upper input switch SWU to the upper PWM output of a selected buck controller which, in the illustrated embodiment corresponds to either buck controller 10 or buck controller 20. Similarly, the gate control input to the LFET of a respective output driver stage is selectively coupled through a lower input switch SWL to the lower PWM output of one of the buck controllers 10 and 20. Buck controller 10 provides PWM gate drive signals UG1 and LG1 associated with a first output voltage V1, and being respectively available for controlling the turn ON/OFF times of the UFET and LFET of an output driver stage controlled thereby, while buck controller 20 provides PWM gate drive signals UG2 and LG2 associated with a second output voltage V2, and being respectively available for controlling the turn ON/OFF times of the UFET and LFET of an output driver stage controlled thereby.
As a non-limiting example, in the illustrated embodiment of a dual buck DC-DC converter architecture having a two-fold output voltage supply capability (V1 and V2), the input switches SWU and SWL that are used to interface the outputs of the buck controllers with the control inputs of the output driver stages may be readily implemented as digital components, such as 2:1 logic gates, control inputs for which comprise single pin connections. These pins are tied to one of a pair of preselected voltages for establishing the path through the switch, as will be readily understood by one skilled in the art.
Considering the (four amp) output driver stage 34, as a non-limiting example, configuring the switches SWU and SWL, so as to connect the gate drive inputs of its UFET and LFET to the PWM gate drive signals UG1 and LG1 supplied by buck controller 10, will result in the output driver stage 34 producing an output waveform consistent with an output voltage of V1 volts in accordance with the PWM signal supplied by buck controller 10, and at a current drive capability of four amps. In order to supply this voltage V1 at external output port Vout1, it is necessary for the user to externally connect the phase node A of output driver stage 34 to the output inductor L that feeds the voltage output port Vout1. This set of connections will result in voltage output port Vout1 supplying an output voltage of V1 volts at a current drive capability of four amps.
If it is desired to increase the current drive capability from its value of four amps for the output voltage V1 being supplied at the voltage output Vout1, it is necessary to configure the input switches SWU and SWL for the UFET and LFET pairs of one or more of the other output driver stages 33, 32 and 31, in the same manner described above for the four amp output driver stage 34, and to also provide a connection between one or more of the phase nodes B, C and D of these output driver stages to the input side of the inductor L that feeds the voltage output port Vout1.
Take, for example, the case where it is desired to provide voltage output port Vout1 with an output voltage V1 having a five amp current drive capability, and to provide voltage output port Vout2 with an output voltage V2 having a five amp current drive capability. One solution would be to have the (four amp) output driver stage 34 connected in the manner described above, and to also connect the (one amp) output driver stage 31 in the same manner. Namely, the switches SWU and SWL coupled to the control gates of the UFET and LFET of (one amp) output driver stage 31 would be connected to receive the gate drive signals UG1 and LG1 supplied by the buck controller 10. This will result in the one amp output driver stage 31 producing at phase node D waveform in accordance with the PWM signal supplied by buck controller 10, and a current capability of one amp.
In order to supply this additional one amp current drive capability to the output port Vout1, it is necessary for the user to connect the phase node D of output driver stage 31 to the output inductor L that feeds the voltage output port Vout1. What results is a summation of the currents from the four amp node A of the output driver stage 34 and the one amp node D of the output driver stage 31 to the output inductor L that is connected to the voltage output port Vout1. This combining of the outputs of the output driver stages 34 and 31 therefore produces, at voltage output port Vout1, a voltage of V1 volts at a total current drive capability of five amps.
To provide an output voltage V2 at a five amp current drive capability at the voltage output port Vout2, use may be readily made of the two amp and three amp current drive capabilities of the remaining two output driver stages 32 and 33, respectively. Since each of these driver stages is to supply the voltage V2, it is necessary to apply to their associated input switches SWU and SWL, that are respectively coupled to the gates of the UFET and LFET of output driver stages 32 and 33, the PWM gate drive signals UG2 and LG2 that are generated by the V2 voltage buck controller 20. This will cause the output driver stage 32 to produce an output voltage waveform averaging V2 volts and a drive current capability of two amps at the phase node C, in accordance with the PWM signal supplied by buck controller 20.
It will also cause the three-amp output driver stage 33 to produce an output voltage waveform averaging V2 volts and a current drive capability of three amps, in accordance with the PWM signal supplied by buck controller 20. In order to supply, to the output port Vout2, the voltage V2 that is represented as the average at the phase nodes B and C of respective output drive stages 32 and 33, it is necessary for the user to externally connect the phase node B of output driver stage 33 and the phase node C of output driver stage 32 to the output inductor L that feeds the voltage output port Vout2. This results in a summation of the currents from the two-amp node C of output driver stage 32 and the three-amp node B of output driver stage 33 to the output inductor L that is connected to the voltage output port Vout2. This summation of the outputs of output driver stages 32 and 33 therefore produces a voltage V2 having a current capability of five amps at voltage output port Vout2.
It is to be understood that the foregoing description is not limitative of the capabilities of the two buck controller, four output driver stage power supply architecture example shown in FIG. 1. Many other output parameters other than the V1/five amp and V2/five amp examples described are possible. Indeed, the dual buck DC-DC converter example of FIG. 1 provides for a substantial number of different permutations of either or both voltage outputs V1 and V2, and current drive capabilities at these voltages. As pointed out above, the number of control loops, output driver stages and output ports may be varied as desired without a loss in generality.
For example, the dual buck architecture of FIG. 1 can be used to produce a single voltage V1 with a (maximum available) ten amp drive capability at output port Vout1. For this purpose, the switches SWU and SWL feeding each output driver stage are configured to couple the gate inputs to each driver stage's UFET and LFET pair to the PWM UG1 and LG1 outputs of the buck controller 10. In addition, the phase nodes A, B, C and D of respective output drivers 34, 33, 32 and 31 are externally connected to the inductor feeding the output voltage port Vout1. Alternatively, to achieve the same ten amp capability at voltage V2, one would configure the four sets of switches SWU and SWL so that the gate inputs to each driver stage's UFET and LFET pair are coupled to the PWM UG2 and LG2 outputs of the buck controller 20. In addition, each of phase nodes A, B, C and D is externally connected to the inductor feeding the output voltage port Vout2.
FIG. 2 shows an augmentation of the user-configurable power supply circuit architecture in accordance with the present invention, which enables the user to determine whether the overall power supply circuit has been configured as intended. In accordance with this embodiment, for each output voltage that is supplied by the power supply circuit (in the above example, a voltage V1 at five amps is to be supplied from output terminal Vout1 and a voltage V2 at five amps is to be supplied from output terminal Vout2), a pulse generator 100 is coupled to the front end of that output voltage terminal's associated inductor L. In addition, a combinational logic circuit 200 is coupled to the phase nodes of the output drivers that should have been externally connected by the user to the front end of an inductor. In the above example, phase nodes A and D should be tied together at the front end of an output inductor L feeding voltage output port Vout1, while phase nodes B and C should be tied together at the front end of an output inductor L feeding voltage output port Vout2.
As an alternative to the use of pulse generator 100, its function may be implemented by selectively supplying a control command to buck controllers 10 and 20, so as to cause selected ones of the output drivers 31, 32, 33 and 34 to generate output pulses at any of nodes A, B, C and D, which are coupled via inductors L to the output ports Vout1 and Vout2.
In response to pulse generator 100 supplying a test pulse to the front end of the inductor L feeding voltage output port Vout1, monitoring logic circuit 200 should detect a response pulse at each of phase nodes A and D. Similarly, in response to pulse generator 100 supplying a test pulse to the front end of the inductor L feeding voltage output port Vout12 monitoring logic circuit 200 should detect a response pulse at each of phase nodes B and C. If each of these response pulses is not detected a fault is indicated for the corresponding phase node. Thus, for example, for the case of voltage output port Vout1, if a response pulse is detected at phase node A, but not at phase node D, it may be inferred that there has been a miswiring of the phase node D of driver stage 31, and a fault indication for phase node D is produced. Likewise, for the case of voltage output port Vout2, if a response pulse is detected at phase node B, but not at phase node C, it may be inferred that there has been a miswiring of the phase node C of driver stage 32, and a fault indication for phase node C is produced.
In addition to connecting fault detection logic circuitry in the manner described above, combinational logic circuitry may also be used to used to automatically internally configure connections provided through the respective switches SWU and SWL from the buck controllers to the output driver stages, based upon the external connections made by the user from the phase nodes of the output drivers to the inductors feeding the voltage output ports. To this end, as diagrammatically illustrated in FIG. 3, the user will have made intended external connections from the output drivers' phase nodes to the inductors feeding the voltage output ports that have been defined a priori to be associated with respectively different ones of the voltages produced by the plurality of buck converters, so as to establish the intended amperage for the voltage port of interest. In addition, input switches SWU and SWL will have a third position that connects the common terminal to the pulse generator and MUX 300 putting all FETs under direct control of the pulse generator with all FETs being normally non-conducting.
The pulse generator and MUX 300 is used to individually pulse the inputs to one of the switches SWU of each respective output driver stage. As a non-limiting example, the pulse may be applied to upper switch SWU, so that the phase node of a respective driver stage will be briefly pulled high (to the voltage of the upper power supply rail UR) in response to the pulse. A combinational logic circuit 400 then looks at the front ends of the inductors (which have been externally connected by the user to respective phase nodes of the output driver stages) for the presence of a response pulse. For each inductor at which a response pulse is produced, logic circuit 400 knows that an external connection has been provided by the user from the phase node of the output driver stage to the gate of which a pulse has been applied by pulse generator and MUX 300. Knowing which phase nodes produce output pulses, logic circuit 400 may then proceed to selectively enable either upper or lower feedthrough paths of the switches SWU and SWL, and thereby configure the output drivers' input switches to the appropriate buck controller.
As will be appreciated from the foregoing description, the desire to make voltage and current drive output parameters of a power supply user-configurable is readily achieved in accordance with the power supply architecture of the present invention, having a plurality of synchronous buck DC-DC converter control loops that provide respectively different output voltages, together with a plurality of output driver stages having given current drive capabilities, and inputs to which are connectable via a set of selectively (user- or automatically) configurable switches to PWM outputs of any of the buck converter control loops. The output of each output driver stage is selectively connectable by the user to any of plural output voltage ports, so that each output voltage port is capable of supplying any of the respectively different output voltages provided by the synchronous buck DC-DC converter control loops, and has an output current capability that depends upon which output driver stages are coupled to it.
While I have shown and described several embodiments in accordance with the present invention, it is to be appreciated that the same is not limited thereto but, as described above, is susceptible to numerous changes and modifications as will be readily understood by a person skilled in the art. Consequently, I do not wish to be limited to the details shown and described herein, but intend to cover all such changes and modifications as are obvious to one of ordinary skill in the art.

## Claims

1. A method of operating a power circuit, the method comprising:
selectively activating one or more output driver stages of the power circuit to obtain a desired output current at one or more output voltage ports of the power circuit;
determining external connections made by a user from phase nodes of the output driver stages to output inductors; and
based on the determination, selectively activating the one or more output driver stages of the power circuit to obtain the desired output current at the one or more output voltage ports of the power circuit.

2. The method of claim 1, wherein selectively activating one or more output driver stages further comprises:
closing select switches to selectively couple control signals from one or more controllers to select driver devices in select output driver stages.

3. The method of claim 2, wherein at least one of the select driver devices is a semiconductor switch and wherein the method further comprises,
activating the semiconductor switch with the control signals.

4. The method of claim 1, further comprising:
confirming the activation of the select output driver stages.

5. The method of claim 1, further comprising:
controlling one or more controllers that activate the one or more output driver stages at least in part with select feedback signals from select output voltage ports.

6. A method of operating a power converter circuit, the method comprising:
selectively coupling control signals to at least one output driver stage of a plurality of output driver stages of the power converter circuit to obtain a desired output at a select output port of a plurality of output ports, wherein each output driver stage has a defined current drive capacity that is output to the select output port in response to the control signals;
determining external connections made by a user from phase nodes of the output driver stages to output inductors; and
based on the determination, selectively activating the at least one output driver stage to obtain the desired output at the select output port of the power converter circuit.

7. The method of claim 6, wherein selectively coupling control signals to the at least one output driver stage further comprises:
activating at least one switch to couple the control signals from at least one controller to the at least one output driver stage.

8. A power converter circuit comprising:
a plurality of output driver stages, each output driver stage having a select current drive capacity;
a plurality of controllers, each controller operative to cause at least one of the output driver stages to output a current;
a plurality of switches to selectively couple select controllers to select output driver stages;
a plurality of output inductors, each output inductor coupled to a plurality of select output driver stages;
an output voltage port coupled to each inductor, each output port configured to provide an output of the power supply circuit; and
combinational circuitry configured to determine the proper switching arrangement of the switches based upon external connections by a user, wherein the combinational circuitry comprises:
a pulse generator multiplexer configured to supply pulse inputs to select switches to create a response pulse from transistors in the output driver stages; and
a combinational logic circuit coupled between the output driver stages and the output inductors, the combinational logic configured to detect response pulses based on the external connections made by the user from phase nodes of the output driver stages to the output inductors.

9. The power converter circuit of claim 8, wherein each output driver stage further comprises:
at least one transistor having its gate coupled to a respective controller, the at least one transistor further having a source-drain path coupled between a power supply rail and a respective one of the output inductors.

10. The power converter circuit of claim 9, wherein the at least one transistor is a field effect transistor.

11. The power converter circuit of claim 8, wherein each output driver stage further comprises:
an upper field effect transistor (UFET), the UFET having a gate coupled to a respective controller, the UFET also having source-drain current flow path coupled between an upper power supply rail and a respective output inductor; and
a lower field effect transistor (LFET), the LFET having a gate coupled to a respective controller, the LFET also having source-drain current flow path coupled between a lower power supply rail and a respective output inductor.

12. The power converter circuit of claim 8, wherein at least one of the controllers is a buck controller.

13. The power converter circuit of claim 8, wherein each controller is coupled to a respective output voltage port and is operable to control select output driver stages based in part on signals at the respective output voltage port.

14. The power converter circuit of claim 8, further comprising:
an output filter capacitor coupled to each output voltage port.

15. The power converter circuit of claim 8, wherein at least one output driver stage has a different select current drive capacity than the other output driver stages.

16. The power converter circuit of claim 8, further comprising:
a test circuit configured to determine if the power converter is properly configured.

17. The power converter circuit of claim 16, wherein the test circuit further comprises:
a pulse generator coupled between the output driver stages and the output inductors, the pulse generator configured to supply test pulses; and
fault detect logic coupled to the pulse generator and coupled to phase nodes of each output driver stage, the fault detect logic configured to detect a response pulse at the phase nodes.