# Patent

## Title
Temperature sensor providing a temperature signal in digital form

## Abstract

An embodiment of a temperature sensor providing a digital signal representative of temperature comprises a measurement unit providing a first measurement current equal to the sum of at least a first current proportional to temperature and of a second current; a comparator capable of providing a comparison signal which depends on the comparison between the first current and the difference between a third current and the second current; a coding unit receiving the comparison signal and providing said digital signal; a digital-to-analog converter capable of providing the second current and the third current, said difference corresponding to the conversion of said digital signal; and a unit for providing a reference voltage.

## Background
PRIORITY CLAIM
This application claims priority from French patent application No. 06/53397, filed Aug. 18, 2006, which is incorporated herein by reference.
TECHNICAL FIELD
An embodiment of the present invention relates to a temperature sensor providing a signal representative of the temperature in digital form.
BACKGROUND
There currently is a tendency to manufacture integrated circuits performing more and more complex functions, in ever-increasing numbers. This results in an increase in the heat dissipated in the integrated circuit. For reasons of performance and reliability, it is often necessary to provide a device for controlling the integrated circuit temperature to maintain the circuit within an acceptable temperature range. The control device generally comprises a temperature sensor made in integrated fashion.
The temperature sensor typically must comply with several constraints:

    
    
        it typically must provide a signal representative of the integrated circuit temperature in a readily-usable digital form;
        it typically must provide a signal representative of temperature with a sufficient accuracy;
        it typically must operate properly in a noisy digital environment;
        the sensor setting, or calibration, typically must be simple; and
        the sensor manufacturing method typically must be compatible with CMOS manufacturing processes.
    
    


To comply with such constraints, different temperature sensor circuits have been provided.
FIG. 1 schematically shows a conventional embodiment of a temperature sensor 10 providing a signal representative of temperature in digital form.
Sensor 10 comprises a temperature-measurement unit 12 (TEMP. SENSOR) providing an analog signal ST representative of temperature. An amplifier 14 (A) receives signal ST and provides an amplified signal AST. An analog-to-digital converter 16 (A.D.C) converts signal AST into a digital signal Code, coded over N bits, representative of temperature. The operation of converter 16 generally requires a constant reference signal SREF provided by a reference signal generation unit 18 (REF.GEN).
Typically, signal ST corresponds to a voltage varying between 45 and 75 mV, respectively for −40° C. and +125° C., which represents a 30-mV variation. Most analog-to-digital converters require for the analog voltages which are provided thereto to be within a range from 0 to 1 V. It thus may be necessary for amplifier 14 to have a high and accurate amplification factor. Indeed, an inaccuracy at the level of amplifier 14 would translate as a significant inaccuracy of the provided digital signal Code. Further, amplified though it may be, signal AST keeps a limited slope, typically on the order of 5 mV/K. The forming of analog-to-digital converter 16 can then be critical. Indeed, if it is desired for the least significant bit of signal Code to represent 1 K, a 5-mV variation of signal AST must be translated by it. The forming of an amplifier 14 and of an analog-to-digital converter 16 of high accuracy typically translates as the obtaining of a temperature sensor 10 taking up a large surface area of the integrated circuit and having a high power consumption.
SUMMARY OF THE INVENTION
An embodiment of the present invention is a temperature sensor providing a signal representative of temperature in digital form which can be made in integrated fashion, taking up a decreased surface area and having a limited power consumption.
According to another embodiment of the present invention, the resolution of the temperature sensor can easily be modified.
According to another embodiment of the present invention, the parameterizing of the temperature sensor can be made in simple fashion.
An embodiment of the present invention provides a temperature sensor providing a digital signal representative of temperature, comprising a measurement unit providing a first measurement current equal to the sum of at least a first current proportional to temperature and of a second current; a comparator capable of providing a comparison signal which depends on the comparison between the first current and the difference between a third current and the second current; a coding unit receiving the comparison signal and providing said digital signal; a current-switching digital-to-analog converter capable of providing the second current to a first output terminal and the third current to a second output terminal, said difference corresponding to the conversion of said digital signal, the measurement unit being connected to the first output terminal; and a unit for providing a reference voltage to the first and second output terminals having a value distinct from the sensor ground voltage.
According to an embodiment of the present invention, the sensor comprises a unit for providing said reference voltage to the first output terminal and a unit capable of applying the reference voltage to the second output terminal.
According to an embodiment of the present invention, the sensor comprises a first operational amplifier having a first input connected to the first output terminal and a second input connected to the second output terminal, and a resistor connecting the second input and the output of the first operational amplifier, the comparator comprising a second operational amplifier having third and fourth inputs, the voltages across the resistor being applied between the third and fourth inputs of the second operational amplifier.
According to an embodiment of the present invention, the digital signal comprises an integral number N of bits of ranks 0 to N−1, the bit of rank N−1 being the most significant, and the digital-to-analog converter is a ladder network comprising N successive cells, each comprising an input node, an intermediary node, and an output node; a first resistor at a first resistance value between the input node and the intermediary node; a second resistor at a second resistance value between the intermediary node and the output node, the output node of a cell of rank i, where i is an integer ranging between 0 and N−2, being connected to the intermediary node of the cell of rank i+1; and a switch capable of connecting the input node to the first output terminal or to the second output terminal according to the value of the bit of rank i of said digital signal; the output node of the cell of rank N−1 is connected to the sensor ground, a third resistor at the first resistance value connecting the intermediary node of the cell of rank 0 to the second output terminal.
According to an embodiment of the present invention, the sensor further comprises a fourth resistor connecting the output node of the cell of rank N−1 to the second output terminal.
According to an embodiment of the present invention, the unit for providing the reference voltage comprises first and second bipolar transistors having their bases and collectors connected to the sensor ground; an operational amplifier having a first input connected to the first output terminal via a first resistor and to the emitter of the first transistor and a second input connected to the first output terminal via a second resistor and to the emitter of the second transistor via a third resistor, said operational amplifier providing a control voltage; and a current source controlled by the control voltage and connected to the first output terminal.
According to an embodiment of the present invention, the measurement unit comprises an additional current source controlled by the control voltage and connected to the second output terminal.



BRIEF DESCRIPTION OF THE DRAWINGS
Features and advantages of one or more embodiments of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
FIG. 1, previously described, shows a conventional embodiment of a temperature sensor.
FIG. 2 shows another embodiment of a temperature sensor.
FIG. 3 shows a temperature sensor according to an embodiment of the present invention.
FIG. 4 shows a more detailed embodiment of the temperature sensor of FIG. 3.
FIG. 5 shows a more detailed embodiment of the temperature sensor of FIG. 4.



DETAILED DESCRIPTION
For clarity, same elements have been designated with same reference numerals in the different drawings.
An embodiment of the present invention has been developed from the analysis of an analog-to-digital converter 16 having a specific structure.
FIG. 2 shows a temperature sensor comprising a feedback-loop analog-to-digital converter 16 which comprises a comparator 20 receiving, on its positive input (+), amplified signal AST, and providing a binary signal SCOMP to a coding unit 22, for example, a finite state machine (F.S.M.). Coding unit 22 provides binary signal Code corresponding to the digital conversion of signal AST. A digital-to-analog converter 24 (D.A.C.) receives digital signal Code and converts it into an analog signal DA provided to the negative input (−) of comparator 20. Reference signal VREF is provided to converter 24.
Analog-to-digital converter 16 may operate according to a method by piecewise approximation or by digital ramp. As an example, with the operating method by successive approximation, unit 22 initially provides a signal Code for which the most significant bit is at “1”, the other bits being at “0”, which thus corresponds to the median value likely to be coded by signal Code. According to the result of the comparison of signal DA, corresponding to the conversion of signal Code, and of signal AST, the most significant bit of signal Code is maintained at “1” or set to “0”. The method is successively repeated for decreasingly significant bits down to the least significant bit. Signal Code finally obtained corresponds to the digital conversion of signal AST.
Calling bi, i being an integer varying between 0 and N−1, the successive bits of signal Code, bN−1 being the most significant bit, signal DA may be written as follows:




  
    
      
        DA
        =
        
          
            
              
                DA
                FS
              
              
                
                  2
                  N
                
                -
                1
              
            
            ⁢
            
              (
              
                
                  
                    b
                    
                      N
                      -
                      1
                    
                  
                  ·
                  
                    2
                    
                      N
                      -
                      1
                    
                  
                
                +
                
                  
                    b
                    
                      N
                      -
                      2
                    
                  
                  ·
                  
                    2
                    
                      N
                      -
                      2
                    
                  
                
                +
                ...
                +
                
                  
                    b
                    1
                  
                  ·
                  
                    2
                    1
                  
                
                +
                
                  
                    b
                    0
                  
                  ·
                  
                    2
                    0
                  
                
              
              )
            
          
          +
          
            DA
            0
          
        
      
    
    
      
        (
        1
        )
      
    
  




where DAFS is the full scale swing of signal DA and DA0 is the value of signal DA when all the bits of signal Code are at “0”.

When the conversion method is over, signal DA complies with the following equation:

A·ST−DA=0  (2)

neglecting the remaining error, which is lower than the analog value corresponding to the least significant bit of signal Code.

Based on equations (1) and (2), the following equation is obtained:




  
    
      
        
          
            
              b
              
                N
                -
                1
              
            
            ·
            
              2
              
                N
                -
                1
              
            
          
          +
          
            
              b
              
                N
                -
                2
              
            
            ·
            
              2
              
                N
                -
                2
              
            
          
          +
          ...
          +
          
            
              b
              1
            
            ·
            
              2
              1
            
          
          +
          
            
              b
              0
            
            ·
            
              2
              0
            
          
        
        =
        
          
            (
            
              
                2
                N
              
              -
              1
            
            )
          
          ⁢
          
            
              
                A
                ·
                
                  S
                  T
                
              
              -
              
                DA
                0
              
            
            
              DA
              FS
            
          
        
      
    
    
      
        (
        3
        )
      
    
  




If signal ST is proportional to the absolute temperature, and if values DA0 and DAFS are obtained from a reference signal independent from temperature, signal Code effectively is a linear digital representation of temperature.
Parameters DAFS and DA0 may be set to enable the coding of a temperature T belonging to any temperature range [T0,T1], where T0 is the minimum operating temperature of the sensor and corresponds to the value of signal Code for which all bits are at “0”, and where T1 is the maximum operating temperature of the sensor and corresponds to the value of signal Code for which all bits are at “1”. Indeed, signal ST being proportional to absolute temperature T, it may be expressed as follows:

A·ST=B·T  (4)

where B is a constant term.

For the value of signal Code (0, . . . ,0), one has:




  
    
      
        0
        =
        
          
            (
            
              
                2
                N
              
              -
              1
            
            )
          
          ⁢
          
            
              
                B
                ·
                
                  T
                  0
                
              
              -
              
                DA
                0
              
            
            
              DA
              FS
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




For the value of signal Code (1, . . . ,1), one has:




  
    
      
        
          
            2
            N
          
          -
          1
        
        =
        
          
            (
            
              
                2
                N
              
              -
              1
            
            )
          
          ⁢
          
            
              
                B
                ·
                
                  T
                  1
                
              
              -
              
                DA
                0
              
            
            
              DA
              FS
            
          
        
      
    
    
      
        (
        6
        )
      
    
  




Based on equations (5) and (6), the expressions of parameters DAFS and DA0 are obtained as follows:

DA0=B·T0  (7)

DAFS=B·(T1−T0)  (8)

It is thus possible to arbitrarily select the operating temperature range of the sensor by setting the minimum value and the full-scale swing of digital-to-analog converter 24 based on equations (7) and (8).
Between temperatures T0 and T1, signal Code is obtained from the following equation:




  
    
      
        
          
            
              b
              
                N
                -
                1
              
            
            ·
            
              2
              
                N
                -
                1
              
            
          
          +
          ...
          +
          
            
              b
              1
            
            ·
            
              2
              1
            
          
          +
          
            
              b
              0
            
            ·
            
              2
              0
            
          
        
        =
        
          
            (
            
              
                2
                N
              
              -
              1
            
            )
          
          ⁢
          
            
              T
              -
              
                T
                0
              
            
            
              
                T
                1
              
              -
              
                T
                0
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




A potential disadvantage of such a converter 16 is that it may be difficult to simultaneously obtain an amplifier 14 and a digital-to-analog converter 24 which are simple to form. Indeed, assume that for T0 equal to 233 K, ST is equal to 45 mV, and that for T1 equal to 398 K, ST is equal to 75 mV. For an amplification factor A equal to 33, DA0 is equal to 1.5 V and DAFS is equal to 2.5 V. Such an amplification factor A is in practice very difficult to obtain with the necessary accuracy: for example, a 1% error on this factor causes an error greater than 3 degrees Celsius. For an amplification factor A more easy to obtain, for example, equal to 10, DA0 is equal to 0.45 V and DAFS is equal to 0.75 V. In this case, the values of parameters DA0 and DAFS are difficult to obtain with accuracy.
FIG. 3 shows a temperature sensor comprising an analog-to-digital converter 16′ modified with respect to analog-to-digital converter 16 of FIG. 2. In particular, converter 16′ comprises an error amplification unit 25 receiving signal ST and signal DA and providing a signal A′(ST−DA) across comparator 20. As compared with the sensor of FIG. 2, amplifier 14 is not present. Signal A′(ST−DA) corresponds to the difference between signals ST and DA, this difference being amplified by gain A′. With such a structure of converter 16′, the difference between signals ST and DA is calculated before amplification. Gain A′ is thus not necessarily accurate since only the sign of the difference between signals ST and DA matters. Thereby, typically only the offset introduced by amplification unit 25 can have an incidence on the decision of comparator 20.
However, a potential disadvantage of such a sensor is that the full scale swing of signal DA between the values corresponding to codes Code (0, . . . ,0) and Code (1, . . . ,1) must now correspond to the full scale swing of signal ST, for example on the order of 30 mV. In practice, it may be difficult to form a digital-to-analog converter 24 providing a signal DA with such a full-scale swing.
An embodiment of the present invention is a specific implementation of the temperature sensor of FIG. 3 which enables getting rid of the previously-mentioned disadvantage.
FIG. 4 shows an embodiment of the temperature sensor according to the present invention in which digital-to-analog converter 24 is a current-switching converter, for example, a ladder network (R-2R converter). Converter 24 comprises an output terminal 26 receiving a current IDP and an output terminal 28 receiving a current IDN.
Reference current generator 18 is connected to output terminal 26 to which it applies voltage VREF. Temperature sensor 30 provides a current I1 to a node 32 connected to output terminal 28 of converter 24 and to an input of a voltage equalizer 34 (VOLT.EQ.). Reference voltage VREF is also provided to voltage equalizer 34. Call IE the current flowing between node 32 and unit 34. Current IE is provided by unit 34 to a current-to-voltage converter 36 (C.V.C) which applies a voltage VE across comparator 20. A connection 38 is provided between temperature sensor 30 and reference voltage provision unit 18.
The operation of the present embodiment of the temperature sensor according to the present invention will now be described.
To ensure a proper operation of converter 24, the voltages at output terminals 26, 28 are maintained substantially constant and equal. Conventionally, the output terminals of a current-switching scale-network digital-to-analog converter are grounded. The present embodiment of the present invention provides an original biasing of converter 24 since output terminals 26, 28 of converter 24 are set to a constant voltage different from the ground voltage of the sensor. For this purpose, reference voltage generator 18 applies voltage VREF to terminal 26 and equalization unit 34 imposes voltage VREF on node 28.
Signal DA, provided by converter 24, is obtained by the following relation:

DA=IDN−IDP  (10)

Temperature sensor 30 provides a current I1 which is equal to the sum of a current IT proportional to the absolute temperature and of current IDP. Node 32 plays the role of a subtractor. Current IE provided to voltage equalizer 34 is thus obtained by the following relation:

IE=I1−IDN=IT+IDP−IDN=IT−DA   (11)

Voltage VE is proportional to current IE and is thus effectively proportional to the difference between signal IT, proportional to the absolute temperature, and the analog conversion of digital signal Code coding current IT. Current-to-voltage converter 36 simply has the function of ensuring that voltage VE and current IE are of same sign, the gain of converter 36 mattering little.
FIG. 5 shows a more detailed embodiment of the temperature sensor of FIG. 4. According to the present detailed embodiment, the functions performed by temperature sensor 30 and reference voltage provision unit 18 are performed by a same circuit 40. Circuit 40 comprises a first bipolar transistor Q1 having its collector and its base connected to a source of a low reference voltage GND, for example, the ground. The emitter of transistor Q1 is connected to a positive terminal (+) of an operational amplifier 42 (A.O.1). Circuit 40 comprises a second bipolar transistor Q2 having its collector and its base connected to ground GND. A resistor R0 connects the emitter of transistor Q2 to the negative input (−) of amplifier 42. Call VT the voltage between the emitter of transistor Q1 and the emitter of transistor Q2, and Vp the voltage at the output of amplifier 42.
Circuit 40 comprises a voltage-controlled current source 44 which provide a current I0. A terminal of current source 44 is connected to a high reference voltage source, for example, VDD, the other terminal of current source 44 being connected to a first output terminal 46 of circuit 40. Circuit 40 comprises a voltage-controlled current source 48, identical to current source 44 and providing a current I1. A terminal of current source 48 is connected to power supply VDD, the other terminal of current source 48 being connected to a second output terminal 50 of circuit 40. Current sources 44, 48 are controlled by voltage Vp provided by amplifier 42. A resistor R1 connects the negative input (−) of amplifier 42 and output terminal 50. A resistor R2 connects the positive input (+) of amplifier 42 and output terminal 46. Call IR1 and IR2 the currents respectively crossing resistors R1 and R2. Voltage VREF corresponds to the voltage on terminal 46. Call Vt the voltage at terminal 50. Output terminal 50 is connected to output terminal 28 of converter 24 and output terminal 46 is connected to output terminal 26 of converter 24.
According to the present embodiment, the functions performed by voltage equalizer 34 and current-to-voltage conversion unit 36 are performed by a same circuit 60. Circuit 60 comprises an operational amplifier 62 (A.O.2) having its negative input (−) connected to output terminal 28 of converter 24 and having its positive input (+) connected to output terminal 26 of converter 24. The positive input of amplifier 62 is connected to a terminal of a resistor R3 having its other terminal connected to the output of amplifier 62. Voltage VE across resistor R3 is applied across comparator 20.
Converter 24 is of current-switching ladder network type. In the present embodiment, number N of bits of signal Code is equal to 4. Circuit 24 comprises a resistor RT0 connected between ground GND and output terminal 28. Circuit 24 comprises a stacking of N cells. Each cell Celli, i being an integer ranging between 0 and N−1, comprises an input terminal ITi, an intermediary terminal MTi, and an output terminal OTi, a resistor 2R connecting input terminal ITi to intermediary terminal MTi and a resistor R connecting intermediary terminal MTi to output terminal OTi. Output terminal OTi of a cell Celli is connected to intermediary terminal MTi+1 of the adjacent cell Celli+1. Output terminal OTN−1 of last cell CellN−1 is connected to ground GND. A resistor 2R connects input terminal MT0 of first cell Cell0 to output terminal 28 of converter 24. Each cell Celli comprises a switch SWi controlled by bit bi of signal Code and capable of connecting input terminal ITi to terminal 26 or to output terminal 28 of converter 24 according to the value of bit bi. As an example, when bit bi is at “1”, switch SWi connects input terminal ITi of cell Celli to output terminal 28 and when bit bi is at “0”, switch SWi connects input terminal ITi of cell Celli to output terminal 26. Transistor switches SWi may be formed by MOS transistors.
The operation of the present embodiment of the temperature sensor will now be described.
Calling h the ratio of the currents crossing the emitters of transistors Q1 and Q2 and m the ratio of the surface areas of the emitters of transistors Q1 and Q2, voltage VT is given by the following relation:




  
    
      
        
          V
          T
        
        =
        
          
            
              λ
              T
            
            ·
            T
          
          =
          
            
              
                k
                ·
                T
              
              q
            
            ⁢
            
              ln
              ⁡
              
                (
                
                  h
                  ·
                  m
                
                )
              
            
          
        
      
    
    
      
        (
        12
        )
      
    
  




where k is Boltzmann's constant and where q is the charge of an electron. Voltage VT is thus proportional to the absolute temperature. Amplifier 42 controls current sources 44, 48 so that the voltage between its positive and negative inputs remains zero. The voltage across resistor R0 is thus, in steady state, equal to VT.

Further, voltage VREF at output terminal 46 is obtained by the following relation:




  
    
      
        
          V
          REF
        
        =
        
          
            
              (
              
                1
                +
                
                  
                    R
                    1
                  
                  
                    R
                    0
                  
                
              
              )
            
            ·
            
              V
              T
            
          
          -
          
            V
            BE
          
        
      
    
    
      
        (
        13
        )
      
    
  




where VBE is the voltage between the base and the emitter of transistor Q2. Voltage VBE is obtained by the following relation:

VBE=VBE0−λBE·T−c(T)  (14)

where VBE0 and λBE are constant terms and c(T) is a second order term which depends on temperature.

One then has:




  
    
      
        
          V
          REF
        
        =
        
          
            
              -
              
                V
                
                  BE
                  ⁢
                  
                    
                  
                  ⁢
                  0
                
              
            
            +
            
              
                [
                
                  
                    
                      λ
                      T
                    
                    ⁡
                    
                      (
                      
                        1
                        +
                        
                          
                            R
                            1
                          
                          
                            R
                            0
                          
                        
                      
                      )
                    
                  
                  +
                  
                    λ
                    BE
                  
                
                ]
              
              ·
              T
            
            +
            
              c
              ⁡
              
                (
                T
                )
              
            
          
          =
          
            α
            +
            
              β
              ·
              T
            
            +
            
              c
              ⁡
              
                (
                T
                )
              
            
          
        
      
    
    
      
        (
        15
        )
      
    
  




By adaptedly selecting resistances R1 and R0, coefficient β can be annulled and a voltage VREF, which depends on temperature at the second order, that is, which is substantially independent from temperature, can be obtained.
Due to the regulation performed by amplifier 62, the voltage between the positive and negative inputs of amplifier 62 remains substantially zero. This enables ensuring that voltage Vt at terminals 50 and 28 is permanently and substantially equal to VREF. The maintaining of constant equal voltages at terminals 26 and 28 of converter 24 causes the good operation thereof.
Call IT the sum of currents IR1 and IR2. One has the following relation:




  
    
      
        
          I
          T
        
        =
        
          
            (
            
              1
              +
              
                
                  R
                  1
                
                
                  R
                  2
                
              
            
            )
          
          ·
          
            
              V
              T
            
            
              R
              0
            
          
        
      
    
    
      
        (
        16
        )
      
    
  




Voltage VT being proportional to the absolute temperature, current IT is itself proportional to the absolute temperature.
Currents sources 44 and 48 being identical and both controlled by voltage VP, currents I1 and I0 are identical and provided by the following relation:

I1=I0=IT+IDP  (17)

Currents IDP and IDN are provided by the following relations:




  
    
      
        
          I
          DP
        
        =
        
          
            
              V
              REF
            
            
              2
              ⁢
              
                
              
              ⁢
              R
            
          
          ⁢
          
            
              ∑
              
                i
                =
                0
              
              
                N
                -
                1
              
            
            ⁢
            
              
                
                  b
                  i
                
                _
              
              ⁢
              
                2
                
                  i
                  -
                  N
                
              
            
          
        
      
    
    
      
        (
        18
        )
      
    
  




and





  
    
      
        
          
            I
            DP
          
          +
          
            I
            DN
          
        
        =
        
          
            (
            
              
                1
                
                  2
                  ⁢
                  
                    
                  
                  ⁢
                  R
                
              
              +
              
                1
                
                  R
                  
                    T
                    ⁢
                    
                      
                    
                    ⁢
                    0
                  
                
              
            
            )
          
          ·
          
            V
            REF
          
        
      
    
    
      
        (
        19
        )
      
    
  




One thus obtains:




  
    
      
        
          DA
          FS
        
        =
        
          
            
              (
              
                1
                -
                
                  2
                  
                    -
                    N
                  
                
              
              )
            
            ·
            
              V
              REF
            
          
          R
        
      
    
    
      
        (
        20
        )
      
    
  
  
    
      
        
          DA
          0
        
        =
        
          
            (
            
              
                1
                
                  R
                  
                    T
                    ⁢
                    
                      
                    
                    ⁢
                    0
                  
                
              
              -
              
                
                  1
                  -
                  
                    2
                    
                      
                        -
                        N
                      
                      +
                      1
                    
                  
                
                
                  2
                  ⁢
                  
                    
                  
                  ⁢
                  R
                
              
            
            )
          
          ·
          
            V
            REF
          
        
      
    
    
      
        (
        21
        )
      
    
  




The fact of using difference IDN−IDP as signal DAC rather than directly signal IDP enables doubling the full-scale swing of converter 24. Parameter DAFS can easily be modified by varying R and parameter DA0 can easily be modified by varying RT0. The resolution of the present embodiment of the sensor can easily be increased by providing additional cells at the level of digital-to-analog converter 24.
An embodiment of the present invention enables obtaining a temperature sensor comprising an analog-to-digital converter that can easily be made in integrated fashion. Further, the sensor comprises a decreased number of components and can thus be made in integrated fashion while taking up a decreased surface area and having a limited consumption. The present embodiment of the sensor limits sources of errors which might alter digital signal Code. Indeed, the reference voltage is directly applied across converter 24, which avoids any offset due to copying or intermediary storages of the reference voltage. Further, comparator 20 receives the voltage across resistor R3, which enables getting rid, in the comparison, of the offset introduced by amplifier 62. Further, digital-to-analog converter 24 only comprises resistors and transistors that can easily be made with accuracy. Further, the accuracy of the signal provided by digital-to-analog converter 24 only depends at the first order on the resistors, since the transistors that it contains are used as switches and only intervene at the second order.
Of course, the present invention is likely to have various alterations, modifications, and improvements which will readily occur to those skilled in the art. In particular, coding unit 22 may be adapted to the selected analog-to-digital conversion method. As an example, for an analog-to-digital conversion with a digital ramp, coding unit 22 may comprise an AND gate receiving signal VCOMP and a clock signal, the gate output driving a counter which provides signal Code.
The temperature sensor circuit of FIGS. 4 and 5 may be disposed on an integrated circuit (IC), which may be coupled to another circuit, such as a controller, to form a system. The IC and the other circuit may be disposed on the same die to form a system on a ship; or the IC and other circuit may be disposed on separate dies.
Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting.

## Claims

1. A temperature sensor providing a digital signal representative of temperature, comprising:
a measurement unit providing a first measurement current equal to the sum of at least a first current proportional to temperature and of a second current;
a comparator capable of providing a comparison signal which depends on the comparison between the first current and the difference between a third current and the second current;
a coding unit receiving the comparison signal and providing said digital signal;
a current-switching digital-to-analog converter capable of providing the second current to a first output terminal and the third current to a second output terminal, said difference corresponding to the conversion of said digital signal, the measurement unit being connected to the first output terminal; and
a unit for providing a reference voltage to the first and second output terminals having a value distinct from the sensor ground voltage.

2. The sensor of claim 1, comprising a unit for providing said reference voltage to the first output terminal and a unit capable of applying the reference voltage to the second output terminal.

3. The sensor of claim 2, comprising a first operational amplifier having a first input connected to the first output terminal and a second input connected to the second output terminal, and a resistor connecting the second input and the output of the first operational amplifier, the comparator comprising a second operation amplifier having third and fourth inputs, the voltage across the resistor being applied between the third and fourth inputs of the second operational amplifier.

4. The sensor of claim 1, wherein the digital signal comprises an integral number N of bits of ranks 0 to N−1, the bit of rank N−1 being the most significant, and wherein the digital-to-analog converter is a ladder network comprising N successive cells, each comprising:
an input node, an intermediary node, and an output node;
a first resistor at a first resistance value between the input node and the intermediary node;
a second resistor at a second resistance value between the intermediary node and the output node, the output node of a cell of rank i, where i is an integer ranging between 0 and N−2, being connected to the intermediary node of the cell of rank i+1; and
a switch capable of connecting the input node to the first output terminal or to the second output terminal according to the value of the bit of rank i of said digital signal,
and wherein the output node of the cell of rank N−1 is connected to the sensor ground, a third resistor at the first resistance value connecting the intermediary node of the cell of rank 0 to the second output terminal.

5. The sensor of claim 4, further comprising a fourth resistor connecting the output node of the cell of rank N−1 to the second output terminal.

6. The sensor of claim 1, wherein the unit for providing the reference voltage comprises:
first and second bipolar transistors having their bases and collectors connected to the sensor ground;
an operational amplifier having a first input connected to the first output terminal via a first resistor and to the emitter of the first transistor and a second input connected to the first output terminal via a second resistor and to the emitter of the second transistor via a third resistor, said operational amplifier providing a control voltage; and
a current source controlled by the control voltage and connected to the first output terminal.

7. The sensor of claim 6, wherein the measurement unit comprises an additional current source controlled by the control voltage and connected to the second output terminal.

8. A circuit, comprising:
first and second nodes;
a digital-analog-converter operable to provide, in response to a first signal, respective second and third signals to the first and second nodes;
a temperature sensor coupled to the first and second nodes and operable to generate a fourth signal that is proportional to temperature, and provide a fifth signal to the second node, the fifth signal substantially equal to a sum of the second and fourth signals; and
a generator operable to generate the first signal in response to a difference between the third and fifth signals.

9. The circuit of claim 8, further comprising:
a comparator circuit coupled to the first and second nodes and operable to generate a comparison signal having a value related to a polarity of the difference between the third and fifth signals; and
wherein the generator generates the first signal in response to the comparison signal.

10. The circuit of claim 8 wherein the generator is operable to:
change the first signal from a first value to a second value; and
maintain the first signal at the second value if the third signal has a predetermined relationship to the fifth signal.

11. The circuit of claim 8 wherein the generator is operable to:
change the first signal from a first value to a second value; and
change the first signal from the second value to a third value if the third current has a predetermined relationship to the fifth current.

12. The circuit of claim 8 wherein:
the first signal comprise a digital signal; and
wherein the generator is operable to change a digit of the first signal from a first value to a second value;
maintain the digit at the second value if the third signal has a predetermined relationship to the fifth signal; and
change the digit back to the first value if the third signal does not have the predetermined relationship to the fifth signal.

13. The circuit of claim 8 wherein:
the first signal comprises a digital signal;
the digital signal has a number of digits;
the generator is operable to sequentially set each of the digits in response to the difference between the third and fifth signals; and
after the generator sets the digits, the digital signal has a value that represents a temperature measured by the temperature sensor.

14. The circuit of claim 8, further comprising an amplifier operable to maintain a voltage on the second node substantially equal to a voltage on the first node.

15. The circuit of claim 8 wherein:
the first signal comprises a digital signal; and
the second, third, fourth, and fifth signals respectively comprises second, third, fourth, and fifth currents.

16. An integrated circuit, comprising:
first and second nodes;
a digital-analog-converter operable to provide, in response to a first signal, respective second and third currents to the first and second nodes;
a temperature sensor coupled to the first and second nodes and operable to generate a fourth signal that is proportional to temperature, and provide a fifth signal to the second node, the fifth signal substantially equal to a sum of the second and fourth signals; and
a generator operable to generate the first signal in response to a difference between the third and fifth signals.

17. A system, comprising:
a first integrated circuit, comprising
first and second nodes,
a digital-analog-converter operable to provide, in response to a first signal, respective second and third signals to the first and second nodes,
a temperature sensor coupled to the first and second nodes and operable to generate a fourth signal that is proportional to temperature, and provide a fifth signal to the second node, the fifth signal substantially equal to a sum of the second and fourth signals, and
a generator operable to generate the first signal in response to a difference between the third and fifth signals; and

a second integrated circuit coupled to the first integrated circuit.

18. The system of claim 17 wherein the first and second integrated circuits are disposed on a same die.

19. The system of claim 17 wherein the first and second integrated circuits are respectively disposed on first and second dies.

20. The system of claim 17 wherein the second integrated circuit comprises a controller.

21. A method, comprising:
generating first and second signals in response to a code;
generating a third signal that is proportional to temperature; and
generating the code in response to a difference between the second signal and a fourth signal having a magnitude that is substantially equal to a combination of the magnitudes of the first and third signals.

22. The method of claim 21 wherein a sum of the first and second signals is substantially constant.

23. The method of claim 21 wherein the magnitude of the fourth signal is substantially equal to a sum of the magnitudes of the first and third signals.

24. The method of claim 21, further comprising:
wherein the first, second, third, and fourth signals comprise respective first, second, third, and fourth currents;
sinking the first and second currents from respective first and second nodes; and
sourcing the fourth current to the second node.

25. The method of claim 21, further comprising:
wherein the first, second, third, and fourth signals comprise respective first, second, third, and fourth currents;
sinking the first and second currents from respective first and second nodes;
sourcing the fourth current to the second node; and
maintaining a voltage difference between the first and second nodes at substantially zero.

26. The method of claim 21 wherein generating the value comprises:
changing a digit of the code from a first value to a second value;
changing the digit from the second value to the first value if the difference between the second and fourth signals has a first polarity;
maintaining the digit at the second value if the difference between the second and fourth signals has a second polarity opposite to the first polarity; and
repeating changing, changing, and maintaining for each digit of the code.

27. The method of claim 21 wherein the code represents the temperature.

28. The method of clam 21 wherein generating the first and second signals comprises generating the first and second signals with a digital-to-analog converter.