# Patent

## Title
Analog to digital converter and recording medium

## Abstract

An analog-to-digital conversion apparatus includes an interleaving section that aligns the digital data respectively output from a plurality of analog-to-digital conversion sections and generates a data sequence, and a correction arithmetic section that corrects a data value error caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, in which the correction arithmetic section includes: a data partitioning section that generates a plurality of partition data by partitioning the data sequence, a data inserting section that inserts data with data value zero at the head or end of each of the partition data by a predetermined insertion data number to sequentially output these data, an arithmetic section that sequentially outputs data after correction made by sequentially performing correction arithmetic on the partition data, and a data connecting section that adds sequentially connects the data after correction and the data after correction following the data after correction.

## Background
CROSS REFERENCE TO RELATED APPLICATION
This is a continuation application of PCT/JP2006/310543 filed on May 26, 2006 which claims priority from a Non-Provisional patent application Ser. No. 11/138,651 filed on May 26, 2005, now U.S. Pat. No. 7,292,166, the contents of which are incorporated herein by reference.


BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an analog-to-digital conversion apparatus that corrects digital data output from a plurality of analog-to-digital conversion sections and a recording medium.
2. Related Art
Conventionally, in case of converting an analog signal into an digital signal, there is known an N-phase (N-way) interleaved analog-to-digital conversion method using N analog-to-digital converters (hereinafter, referred to as ADCs) in order to raise a sampling rate apparently.
However, in the interleaved analog-to-digital conversion method as described above, when some errors are observed in phases of sampling clocks being supplied to each of ADCs and a frequency characteristic of each of ADCs, a frequency spectrum of a digital signal cannot be computed with high precision.
For example, phases of sampling clocks being supplied to each of ADCs have to be different from one another by a predetermined phase. However, it is difficult to move a phase of each of sampling clocks by a predetermined phase precisely. Moreover, although sampling clocks are supplied to each of ADCs with a precise phase, when a frequency characteristic of ADC is not ideal, a variation is observed in sampling timing and a gain in each of ADCs and thus it is difficult to compute a frequency spectrum of a digital signal with high precision.
For this reason, it is necessary to correct the sampled digital signal according to a frequency characteristic of each ADC. For example, a method for correcting a spectrum transformed from the digital signal by way of discrete Fourier transform according to a frequency characteristic of each ADC is considered.
In this case, an arithmetic section that conducts discrete Fourier transform and correction arithmetic sequentially acquires digital signal data by a predetermined data number and performs arithmetic processing. However, since the digital signal data are separately processed, there has been a problem that it is not possible to hold a continuity of a waveform of a digital signal.
SUMMARY
Therefore, it is an object of the present invention to provide an analog-to-digital conversion apparatus and a recording medium that can solve the foregoing problems. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
That is, according to the first aspect related to the innovations herein, one exemplary analog-to-digital conversion apparatus to which an analog signal is split and supplied and which corrects digital data output from a plurality of analog-to-digital conversion sections that sequentially convert the analog signal in different timing by a predetermined phase, may include: an interleaving section that aligns the digital data respectively output from the plurality of analog-to-digital conversion sections according to the timing in which the digital data are respectively converted and generates a data sequence; and a correction arithmetic section that corrects a data value error of the data sequence caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, based on a frequency characteristic of each of the analog-to-digital conversion sections, in which the correction arithmetic section includes: a data partitioning section that generates a plurality of partition data by partitioning the data sequence by a predetermined partition data number; a data inserting section that inserts data with data value zero at the head or end of each of the partition data by a predetermined insertion data number to sequentially output these data; an arithmetic section that sequentially acquires the partition data sequentially output from the data inserting section and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each analog-to-digital conversion section with respect to the acquired partition data; and a data connecting section that adds the data of the insertion data number at the end of each data after correction sequentially output from the arithmetic section according to each partition data and the data of the insertion data number at the head of the data after correction following that data after correction in order to sequentially connect that data after correction and the data after correction following that data after correction.
Moreover, according to the second aspect related to the innovations herein, one exemplary analog-to-digital conversion apparatus to which an analog signal is split and supplied and which corrects digital data output from a plurality of analog-to-digital conversion sections that sequentially converts the analog signal in different timing by a predetermined phase, may include: an interleaving section that aligns the digital data respectively output from the plurality of analog-to-digital conversion sections according to the timing in which the digital data are respectively converted and generates a data sequence; and a correction arithmetic section that corrects a data value error of the data sequence caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, based on a frequency characteristic of each of the analog-to-digital conversion sections, in which the correction arithmetic section includes: a data partitioning section that partitions the data sequence into a plurality of partition data having a predetermined partition data number and respectively generates the partition data so that duplicated data of a predetermined number at the head of each of the partition data is overlapped with duplicated data of the predetermined number at the end of the partition data in front of that partition data; an arithmetic section that sequentially acquires the partition data respectively generated from the data partitioning section and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each analog-to-digital conversion section with respect to the acquired partition data; and a data connecting section that removes either of the duplicated data at the end of each data after correction sequentially output from the arithmetic section according to each partition data or the duplicated data at the head of that data after correction and sequentially connects the end of that data after correction and the head of the data after correction following that data after correction.
Moreover, according to the third aspect related to the innovations herein, one exemplary recording medium for storing a program causing an analog-to-digital conversion apparatus, to which an analog signal is split and supplied and which corrects digital data output from a plurality of analog-to-digital conversion sections that sequentially converts the analog signal in different timing by a predetermined phase, to function. The program causes the analog-to-digital conversion apparatus to function as: an interleaving section that aligns the digital data respectively output from the plurality of analog-to-digital conversion sections according to the timing in which the digital data are respectively converted and generates a data sequence; and a correction arithmetic section that corrects a data value error of the data sequence caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, based on a frequency characteristic of each of the analog-to-digital conversion sections, in which the program causes said correction arithmetic section to function as: a data partitioning section that generates a plurality of partition data by partitioning the data sequence by a predetermined partition data number; a data inserting section that inserts data with data value zero at the head or end of each of the partition data by a predetermined insertion data number to sequentially output these data; an arithmetic section that sequentially acquires the partition data sequentially output from the data inserting section and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each analog-to-digital conversion section with respect to the acquired partition data; and a data connecting section that adds the data of the insertion data number at the end of each data after correction sequentially output from the arithmetic section according to each partition data and the data of the insertion data number at the head of the data after correction following that data after correction in order to sequentially connect that data after correction and the data after correction following that data after correction.
Moreover, according to the fourth aspect related to the innovations herein, one exemplary recording medium for storing a program causing an analog-to-digital conversion apparatus, to which an analog signal is split and supplied and which corrects digital data output from a plurality of analog-to-digital conversion sections that sequentially converts the analog signal in different timing by a predetermined phase, to function. The program causes the analog-to-digital conversion apparatus to function as: an interleaving section that aligns the digital data respectively output from the plurality of analog-to-digital conversion sections according to the timing in which the digital data are respectively converted and generates a data sequence; and a correction arithmetic section that corrects a data value error of the data sequence caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, based on a frequency characteristic of each of the analog-to-digital conversion sections, in which the program causes said correction arithmetic section to function as: a data partitioning section that partitions the data sequence into a plurality of partition data having a predetermined partition data number and respectively generates the partition data so that duplicated data of a predetermined number at the head of each of the partition data is overlapped with duplicated data of the predetermined number at the end of the partition data in front of that partition data; an arithmetic section that sequentially acquires the partition data respectively generated from the data partitioning section and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each analog-to-digital conversion section with respect to the acquired partition data; and a data connecting section that removes either of the duplicated data at the end of each data after correction sequentially output from the arithmetic section according to each partition data or the duplicated data at the head of that data after correction and sequentially connects the end of that data after correction and the head of the data after correction following that data after correction.
The summary of the invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a view exemplary showing a configuration of an analog-to-digital conversion apparatus 100.
FIG. 2 is a view explaining a sampling clock being supplied to each of ADCs 10.
FIG. 3 is a view exemplary showing a frequency characteristic of a signal output from each of Fourier transform sections 12.
FIG. 4 is a view exemplary showing a part of a frequency characteristic of a signal output from a Fourier transform section 12-1.
FIG. 5 is a view exemplary in which each of frequency characteristics is displayed on a complex space.
FIG. 6 is a view showing another example of a part of a frequency characteristic of a signal output from a Fourier transform section 12-1.
FIG. 7 is a flowchart exemplary showing an operation of an analog-to-digital conversion apparatus 100.
FIG. 8 is a view showing another example of a configuration of an analog-to-digital conversion apparatus 100.
FIG. 9 is a view exemplary showing a configuration of a correction arithmetic section 42.
FIG. 10 is a view exemplary explaining an operation of a correction arithmetic section 42.
FIG. 11 is a view showing another example of a configuration of a correction arithmetic section 42.
FIG. 12 is a view exemplary explaining an operation of a correction arithmetic section 42 shown in FIG. 11.
FIG. 13 is a view showing another example of a configuration of a correction arithmetic section 42.
FIG. 14 is a view showing another example of a configuration of a correction arithmetic section 42.
FIG. 15 is a view exemplary showing a configuration of an arithmetic section 48.
FIG. 16 is a view explaining an operation of an arithmetic section 48 shown in FIG. 15.
FIG. 17 is a view exemplary showing a configuration of a computer 400 that stores a program causing a analog-to-digital conversion apparatus 100 to function.



DESCRIPTION OF EXEMPLARY EMBODIMENTS
The invention will now be described based on the preferred embodiments, which do not intend to limit the scope of the present invention, but exemplify the invention. All of the features and the combinations thereof described in the embodiment are not necessarily essential to the invention.
FIG. 1 is a view exemplary showing a configuration of an analog-to-digital conversion apparatus 100. The analog-to-digital conversion apparatus 100 is a device that converts an analog signal provided as an input signal into a digital signal, and includes a plurality of ADCs 10-0 to 10-3 (hereinafter, generally referred to as ADC 10), a plurality of Fourier transform sections 12-0 to 12-3 (hereinafter, generally referred to as Fourier transform section 12), a plurality of correction sections 16-0 to 16-3 (hereinafter, generally referred to as correction section 16), a measuring section 14, and an interleaving section 18. Moreover, in this example, although the analog-to-digital conversion apparatus 100 converts analog signals into digital form by means of four ADCs 10, the number of ADCs 10 is not limited to four. For example, the analog-to-digital conversion apparatus 100 may convert analog signals into digital signals by means of 2n pieces (here, n is one or more integer number) of ADC 10. Even in this case, since the analog-to-digital conversion apparatus 100 realizes an operation similar to the analog-to-digital conversion apparatus 100 in this example, it is possible to compute a frequency spectrum of digital signals with high precision.
Sampling clocks having phases different from one another by a predetermined phase are respectively supplied to the ADCs 10. The supplied sampling clocks will be described below referring to FIG. 2. Then, analog signals are supplied to the ADCs 10 as input signals, and are sampled according to the sampling clocks.
The Fourier transform sections 12 are respectively provided corresponding to the ADCs 10, respectively perform Fourier transform on data output from the plurality of ADCs 10 by sampling the analog signals, and generate a plurality of frequency domain signals corresponding to the plurality of ADCs 10. The Fourier transform section 12 performs Fourier transform, e.g., by discrete Fourier transform.
The measuring section 14 previously measures a frequency characteristic of each of the ADCs 10. For example, the measuring section 14 makes each of the ADCs 10 input a known analog signal and measures a frequency characteristic of each of the ADCs 10 based on data output from the ADCs 10. At this time, the measuring section 14 may measure a frequency characteristic of each of the ADCs 10 using sampling clocks obtained when the analog signals are converted into the digital signals. In this way, it is possible to measure a frequency characteristic of sampling performed in each of the ADCs 10, which include a phase error of the supplied sampling clock.
The correction section 16 multiplies each of the frequency domain signals by correction coefficients based on the frequency characteristics of all ADCs 10 to convert the frequency domain signals into ideal frequency domain signals obtained when frequency characteristics of the corresponding ADCs 10 are ideal. At this time, the frequency characteristic of any one of the ADCs 10 may be taken as ideal frequency characteristics, or a predetermined frequency characteristic may be given as ideal frequency characteristics. In this way, it is possible to generate ideal frequency domain signals in which a spurious component caused by an error of the frequency characteristic of each of the ADCs 10 is removed.
Moreover, the interleaving section 18 synthesizes the ideal frequency domain signals, and generates a frequency spectrum of the digital signal. By such a configuration, it is possible to obtain a frequency spectrum in which a spurious component caused by the frequency characteristics of sampling performed in the ADCs 10 is removed.
FIG. 2 is a view explaining a sampling clock being supplied to each of the ADCs 10. For example, when converting analog signals of [−1/(2Ts), 1/(2Ts)] band into digital signals, sampling clocks having a frequency of 1/(4Ts) are supplied to each of the ADCs 10 in different timing by phase Ts. Since an analog signal is sampled using such a sampling clock, it is possible to sample the analog signal at a rate of four times of a sampling frequency of each of the ADCs 10.
FIG. 3 is a view exemplary showing a frequency characteristic of a signal output from each of Fourier transform sections 12. Spurious components (k=−1, 1, 2, 3, 4, and 5) occur on the frequency domain signal that is made by sampling analog signals in [−1/(2Ts), 1/(2Ts)] band with 1/(4Ts) frequency in addition to a signal component (k=0) as shown by a solid line in FIG. 3. All frequency characteristics have the signal component and the spurious components as shown in FIG. 3. However, since the sampling clocks of the ADCs 10 deviate from one another by Ts, the components of frequency characteristics have directions different from one another in a complex space.
FIG. 4 is a view exemplary showing a part of a frequency characteristic of a signal output from the Fourier transform section 12-1. Assuming that all components (k=−1 to 5) of the frequency characteristic of a signal output from the Fourier transform section 12-0 have the same direction in a complex space as shown in FIG. 3, a signal component (k=0) of the frequency characteristic output from the Fourier transform section 12-1 has the same direction as that of a signal component (see FIG. 3) of the frequency component output from the Fourier transform section 12-0. However, since a phase of a sampling clock of the ADC 10-1 advances by Ts compared with a phase of a sampling clock of the ADC 10-0, a spurious component (k=1) of the frequency characteristic of the signal output from the Fourier transform section 12-1 rotates by 90 degrees relative to a signal component (k=0). Similarly, the other spurious components (k=2, 3, 4, 5, not shown) sequentially rotate by 90 degrees.
FIG. 5 is a view exemplary in which each of frequency characteristics is displayed on a complex space. Although a signal component and a spurious component are discretely shown in FIG. 5, a signal component and a spurious component may be overlapped like the frequency characteristic shown in FIG. 3.
As described above, a component of the frequency characteristic of the signal output from the Fourier transform section 12-1 sequentially rotates by 90 degrees. Moreover, since a phase of a sampling clock of the ADC 10-2 advances by 2Ts compared with the phase of the sampling clock of the ADC 10-0, a component of the frequency characteristic of the signal output from the Fourier transform section 12-2 rotates by 180 degrees as shown in FIG. 5. Similarly, since a phase of a sampling clock of the ADC 10-3 advances by 3Ts compared with the phase of the sampling clock of the ADC 10-0, a component of the frequency characteristic of the signal output from the Fourier transform section 12-3 rotates by 270 degrees as shown in FIG. 5.
The spurious components (k=−1, 1, 2, 3, 5) of each frequency characteristic are removed by synthesizing these frequency characteristics, only signal component (k=0) and aliasing component (k=4) remain. However, when a variation occurs in sampling timing of the ADC 10 due to a phase error of each sampling clock and a frequency characteristic error of the ADC 10, it is not possible to remove a spurious component by causing a variation in an angle of the spurious component.
FIG. 6 is a view showing another example of a part of a frequency characteristic of a signal output from the Fourier transform section 12-1. As described above, when there is a phase error in the sampling clock supplied from the ADC 10-1 or the frequency characteristic of the ADC 10-1 is not ideal, as shown in FIG. 6, since a variation occurs in an angle of the spurious component (e.g., k=1) and thus the spurious component is not offset by a spurious component (k=1) of the other frequency characteristic, a spurious component remains when synthesizing all frequency characteristics.
The analog-to-digital conversion apparatus 100 explained in FIG. 1 corrects a variation of an angle of such a spurious component, which is caused by the frequency characteristic of the ADC 10 and the phase error of the sampling clock, to perform interleaving and thus removes a spurious component. An operation of the analog-to-digital conversion apparatus 100 will be described below.
FIG. 7 is a flowchart exemplary showing an operation of an analog-to-digital conversion apparatus 100. At first, in measurement step S200, a measuring section 10 previously measures a frequency characteristic of each ADC 10. Here, the frequency characteristic of each ADC 10 is given by the following expression.




  
    
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Here, 1 shows the corresponding ADC 10, and 1=0, 1, 2, and 3.
Next, in sampling step S202, an analog signal supplied as an input signal is sampled by means of the plurality of ADCs 10. At this time, sampling clocks p0(t), p1(t), p2(t), and p3(t) supplied to each of the ADCs 10 is given by the following expression.




  
    
      
        
          
            
              
                
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Next, in Fourier transform step S204, the Fourier transform section 12 respectively transforms the data sampled by the plurality of ADCs 10 by means of Fourier transform method, and generates a plurality of frequency domain signals corresponding to the plurality of ADCs 10. At this time, the Fourier transform of the sampling clock shown in Expression 1 is given by the following expression.




  
    
      
        
          
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The frequency domain signal X1(f) output from each Fourier transform section 12 is given by the following expression by means of Expression 2.




  
    
      
        
          
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each frequency domain signal can be expressed as follows. Here, in this example, the frequency characteristic of the ADC 10-0 is explained as an ideal frequency characteristic. In other words, it is explained as a0(k)=1.

X0(f)= x(−1)+ x(0)+ x(1)+ x(2)+ x(3)+ x(4)+ x(5)

X1(f)=a1(−1) x(−1)+a1(0) x(0)+a1(1) x(1)+a1(2) x(2)+a1(3) x(3)+a1(4) x(4)+a1(5) x(5)

X2(f)=a2(−1) x(−1)+a1(0) x(0)+a2(1) x(1)+a1(2) x(2)+a2(3) x(3)+a1(4) x(4)+a1(5) x(5)

X3(f)=a1(−1) x(−1)+a3(0) x(0)+a3(1) x(1)+a3(2) x(2)+a1(3) x(3)+a1(4) x(4)+a3(5) x(5)  Expression 4

Here, fs is sampling frequency of each analog-digital converter, items from k=−1 to 5 show components included in a band [0053] assuming that a band of X(f) is [−2fs, 2fs], and aj(k) shows a component corresponding to x(k) among frequency characteristics of the j-th analog-digital converter.
Next, in correction step S206, the frequency domain signals are multiplied by correction coefficients based on the frequency characteristics of all ADCs 10 using the correction section 16 in order to be converted into frequency domain signals obtained when the frequency characteristics of the corresponding ADCs 10 is ideal. In this example, in the correction section 16, the spurious components of k=−1, 1, 2, 3, 5 are removed and a correction coefficient in which only the signal component of k=0 and the aliasing component of that signal component remain is multiplied by each of the frequency characteristics when computing linear sum of frequency components X0(f) to X3(f) shown in Expression 4. In other words, the correction coefficients L1, L2, L3 such as Expression 5 are computed, and the correction coefficients are multiplication by each frequency characteristic. Here, α, β are arbitrary real number.

X0(f)+L1X1(f)+L2X2(f)+L3X3(f)=α x(0)+β x(4)  Expression 5

At this time, the correction section 16 divides the frequency band [−2fs, 2fs] of the digital signal to be computed according to the number of ADCs 10. In this example, the correction section 16 divides the frequency band of the digital signal to be computed into a first region of band [0, fs], a second region of band [fs, 2fs], a third region of band [2fs, 3fs], and a fourth region of band [3fs, 4fs].
As we know from Expression 4, although the spurious components included in the frequency band [−2fs, 2fs] of the digital signal are four, e.g., k=−1, 1, 2, 3, as clear from Expression 5, there are not correction coefficients L1, L2, L3 to erase four spurious components in the same time. However, each divided region when dividing a frequency band of digital signal like this example has three spurious components as shown in FIG. 3. For this reason, the correction section 16 can compute each correction coefficient for each frequency band as shown in the following expression.
The first region




  
    
      
        
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The second region and the third region




  
    
      
        
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                        (
                        1
                        )
                      
                    
                  
                  
                    
                      
                        a
                        3
                      
                      ⁡
                      
                        (
                        1
                        )
                      
                    
                  
                
                
                  
                    
                      
                        a
                        
                          1
                          ⁢
                          
                            
                          
                        
                      
                      ⁡
                      
                        (
                        2
                        )
                      
                    
                  
                  
                    
                      
                        a
                        2
                      
                      ⁡
                      
                        (
                        2
                        )
                      
                    
                  
                  
                    
                      
                        a
                        3
                      
                      ⁡
                      
                        (
                        2
                        )
                      
                    
                  
                
                
                  
                    
                      
                        a
                        1
                      
                      ⁡
                      
                        (
                        3
                        )
                      
                    
                  
                  
                    
                      
                        a
                        2
                      
                      ⁡
                      
                        (
                        3
                        )
                      
                    
                  
                  
                    
                      
                        a
                        3
                      
                      ⁡
                      
                        (
                        3
                        )
                      
                    
                  
                
              
              )
            
            
              -
              1
            
          
          ⁢
          
            (
            
              
                
                  
                    -
                    1
                  
                
              
              
                
                  
                    -
                    1
                  
                
              
              
                
                  
                    -
                    1
                  
                
              
            
            )
          
        
      
    
    
      
        Expression
        ⁢
        
          
        
        ⁢
        7
      
    
  




The fourth region




  
    
      
        
          (
          
            
              
                
                  L
                  1
                
              
            
            
              
                
                  L
                  2
                
              
            
            
              
                
                  L
                  3
                
              
            
          
          )
        
        =
        
          
            
              (
              
                
                  
                    
                      
                        a
                        1
                      
                      ⁡
                      
                        (
                        2
                        )
                      
                    
                  
                  
                    
                      
                        a
                        2
                      
                      ⁡
                      
                        (
                        2
                        )
                      
                    
                  
                  
                    
                      
                        a
                        3
                      
                      ⁡
                      
                        (
                        2
                        )
                      
                    
                  
                
                
                  
                    
                      
                        a
                        
                          1
                          ⁢
                          
                            
                          
                        
                      
                      ⁡
                      
                        (
                        3
                        )
                      
                    
                  
                  
                    
                      
                        a
                        2
                      
                      ⁡
                      
                        (
                        3
                        )
                      
                    
                  
                  
                    
                      
                        a
                        3
                      
                      ⁡
                      
                        (
                        3
                        )
                      
                    
                  
                
                
                  
                    
                      
                        a
                        1
                      
                      ⁡
                      
                        (
                        5
                        )
                      
                    
                  
                  
                    
                      
                        a
                        2
                      
                      ⁡
                      
                        (
                        5
                        )
                      
                    
                  
                  
                    
                      
                        a
                        3
                      
                      ⁡
                      
                        (
                        5
                        )
                      
                    
                  
                
              
              )
            
            
              -
              1
            
          
          ⁢
          
            (
            
              
                
                  
                    -
                    1
                  
                
              
              
                
                  
                    -
                    1
                  
                
              
              
                
                  
                    -
                    1
                  
                
              
            
            )
          
        
      
    
    
      
        Expression
        ⁢
        
          
        
        ⁢
        8
      
    
  




Then, in synthesizing step S208, the interleaving section 18 synthesizes each of the frequency domain signals obtained in correction step S206 to generate a frequency spectrum of the digital signal. At this time, since the computed correction coefficients L1, L2, L3 are multiplied by each frequency domain signal in correction step S206, the phases of signal component (k=0) and aliasing component (k=4) are changed. For this reason, in correction step S206, a correction coefficient correcting the change is further computed.
The correction step S206 in this example has a first computation step computing the first correction coefficient and a second computation step computing the second correction coefficient. In the first computation step, each of the first correction coefficients L1, L2, L3 multiplied by each of the frequency domain signals is computed based on the frequency characteristics of all ADCs 10 so that a spurious component of each of the frequency domain signals caused by the frequency characteristic of each of the ADCs 10 is offset. Moreover, in the first computation step, the first correction coefficients L1, L2, L3 offsetting a spurious component existing in each region, which is made by dividing the previously described frequency band, among the spurious components of each frequency signal are computed for each divided region.
Moreover, in the second computation step, the second correction coefficients for correcting a phase error of a signal component and an aliasing component of frequency domain signal caused by multiplying the first correction coefficients are computed for each divided region based on each of the first correction coefficients and each of the frequency characteristics. Since only signal component (k=0) remains in the first region and the second region, in the first region and the second region 1/(1+a1(0)L1+a2(0)L2+a3(0)L3) is computed as the second correction coefficient. Moreover, since only aliasing component (k=4) remains in the third region and the fourth region, 1/(1+a1(4)L1+a2(4)L2+a3(4)L3) is computed as the second correction coefficient.
Then, in synthesizing step S208, the result that is made by synthesizing each of the frequency domain signals obtained in correction step S206 is multiplied by the previously described second correction coefficient. Moreover, in this example, although the second correction coefficient is multiplied in synthesizing step S208, in another example, the second correction coefficient may be multiplied in correction step S206. In other words, in correction step S206, the corresponding first correction coefficient and the corresponding second correction coefficient are multiplied by each frequency domain signal.
As described above, in synthesizing step S208, a frequency spectrum of digital signal is computed for each region based on the following expression. The first region and the second region




  
    
      
        
          
            X
            ′
          
          ⁡
          
            (
            f
            )
          
        
        =
        
          
            1
            
              
                
                  
                    1
                    +
                    
                      
                        
                          a
                          1
                        
                        ⁡
                        
                          (
                          0
                          )
                        
                      
                      ⁢
                      
                        L
                        1
                      
                    
                    +
                  
                
              
              
                
                  
                    
                      
                        
                          a
                          2
                        
                        ⁡
                        
                          (
                          0
                          )
                        
                      
                      ⁢
                      
                        L
                        2
                      
                    
                    +
                    
                      
                        
                          a
                          3
                        
                        ⁡
                        
                          (
                          0
                          )
                        
                      
                      ⁢
                      
                        L
                        3
                      
                    
                  
                
              
            
          
          ⁢
          
            {
            
              
                
                  
                    
                      
                        X
                        0
                      
                      ⁡
                      
                        (
                        f
                        )
                      
                    
                    +
                    
                      
                        L
                        1
                      
                      ⁢
                      
                        X
                        1
                      
                      ⁢
                      
                        (
                        f
                        )
                      
                    
                    +
                  
                
              
              
                
                  
                    
                      
                        L
                        2
                      
                      ⁢
                      
                        
                          X
                          2
                        
                        ⁡
                        
                          (
                          f
                          )
                        
                      
                    
                    +
                    
                      
                        L
                        3
                      
                      ⁢
                      
                        
                          X
                          3
                        
                        ⁡
                        
                          (
                          f
                          )
                        
                      
                    
                  
                
              
            
            }
          
        
      
    
    
      
        Expression
        ⁢
        
          
        
        ⁢
        9
      
    
  




The third region and the fourth region




  
    
      
        
          
            X
            ′
          
          ⁡
          
            (
            f
            )
          
        
        =
        
          
            1
            
              
                
                  
                    1
                    +
                    
                      
                        
                          a
                          1
                        
                        ⁡
                        
                          (
                          4
                          )
                        
                      
                      ⁢
                      
                        L
                        1
                      
                    
                    +
                  
                
              
              
                
                  
                    
                      
                        
                          a
                          2
                        
                        ⁡
                        
                          (
                          4
                          )
                        
                      
                      ⁢
                      
                        L
                        2
                      
                    
                    +
                    
                      
                        
                          a
                          3
                        
                        ⁡
                        
                          (
                          4
                          )
                        
                      
                      ⁢
                      
                        L
                        3
                      
                    
                  
                
              
            
          
          ⁢
          
            {
            
              
                
                  
                    
                      
                        X
                        0
                      
                      ⁡
                      
                        (
                        f
                        )
                      
                    
                    +
                    
                      
                        L
                        1
                      
                      ⁢
                      
                        X
                        1
                      
                      ⁢
                      
                        (
                        f
                        )
                      
                    
                    +
                  
                
              
              
                
                  
                    
                      
                        L
                        2
                      
                      ⁢
                      
                        
                          X
                          2
                        
                        ⁡
                        
                          (
                          f
                          )
                        
                      
                    
                    +
                    
                      
                        L
                        3
                      
                      ⁢
                      
                        
                          X
                          3
                        
                        ⁡
                        
                          (
                          f
                          )
                        
                      
                    
                  
                
              
            
            }
          
        
      
    
    
      
        Expression
        ⁢
        
          
        
        ⁢
        10
      
    
  




In other words, in synthesizing step S208, a frequency spectrum in the first region is computed by using the correction coefficients L1, L2, L3 computed by Expression 6 in Expression 9. Moreover, a frequency spectrum in the second region is computed by using the correction coefficients L1, L2, L3 computed by Expression 7 in Expression 9, a frequency spectrum in the third region is computed by using the correction coefficients L1, L2, L3 computed by Expression 7 in Expression 10, and a frequency spectrum in the fourth region is computed by using the correction coefficients L1, L2, L3 computed by Expression 8 in Expression 10. By such an operation, it is possible to obtain a frequency spectrum in which a spurious component is removed.

Moreover, in this example, the frequency characteristic of ADC 10-0 is explained as ideal frequency characteristic. However, although the frequency characteristic of ADC 10-0 is not ideal but has a certain frequency characteristic, it is possible to remove a spurious component by correcting the signals based on this frequency characteristic.
In this case, assuming that the result obtained by dividing the frequency characteristic of other ADC 10 by the frequency characteristic of ADC 10-0 is the frequency characteristic a1(k) of the other ADC 10, it is possible to correct the signal. In other words, assuming that the previously measured frequency characteristics of ADC 10-1 (1=0, 1, 2, 3) are respectively Fad(l), each frequency characteristic a1(k) used to correct the signal is expressed by the following expressions.

a0(k)=Fad(0)

a1(k)=Fad(1)/Fad(0)

a2(k)=Fad(2)/Fad(0)

a3(k)=Fad(3)/Fad(0)  Expression 11

Moreover, using the frequency characteristics shown in Expression 11, Expression 9 and Expression 10 are expressed by the following expressions.




  
    
      
        
          
            X
            ′
          
          ⁡
          
            (
            f
            )
          
        
        =
        
          
            
              1
              
                
                  a
                  0
                
                ⁡
                
                  (
                  0
                  )
                
              
            
            ·
            
              1
              
                
                  
                    
                      1
                      +
                      
                        
                          
                            a
                            1
                          
                          ⁡
                          
                            (
                            0
                            )
                          
                        
                        ⁢
                        
                          L
                          1
                        
                      
                      +
                    
                  
                
                
                  
                    
                      
                        
                          
                            a
                            2
                          
                          ⁡
                          
                            (
                            0
                            )
                          
                        
                        ⁢
                        
                          L
                          2
                        
                      
                      +
                      
                        
                          
                            a
                            3
                          
                          ⁡
                          
                            (
                            0
                            )
                          
                        
                        ⁢
                        
                          L
                          3
                        
                      
                    
                  
                
              
            
          
          ⁢
          
            {
            
              
                
                  
                    
                      
                        X
                        0
                      
                      ⁡
                      
                        (
                        f
                        )
                      
                    
                    +
                    
                      
                        L
                        1
                      
                      ⁢
                      
                        X
                        1
                      
                      ⁢
                      
                        (
                        f
                        )
                      
                    
                    +
                  
                
              
              
                
                  
                    
                      
                        L
                        2
                      
                      ⁢
                      
                        
                          X
                          2
                        
                        ⁡
                        
                          (
                          f
                          )
                        
                      
                    
                    +
                    
                      
                        L
                        3
                      
                      ⁢
                      
                        
                          X
                          3
                        
                        ⁡
                        
                          (
                          f
                          )
                        
                      
                    
                  
                
              
            
            }
          
        
      
    
    
      
        Expression
        ⁢
        
          
        
        ⁢
        9
      
    
  








  
    
      
        
          
            X
            ′
          
          ⁡
          
            (
            f
            )
          
        
        =
        
          
            
              1
              
                
                  a
                  0
                
                ⁡
                
                  (
                  4
                  )
                
              
            
            ·
            
              1
              
                
                  
                    
                      1
                      +
                      
                        
                          
                            a
                            1
                          
                          ⁡
                          
                            (
                            4
                            )
                          
                        
                        ⁢
                        
                          L
                          1
                        
                      
                      +
                    
                  
                
                
                  
                    
                      
                        
                          
                            a
                            2
                          
                          ⁡
                          
                            (
                            4
                            )
                          
                        
                        ⁢
                        
                          L
                          2
                        
                      
                      +
                      
                        
                          
                            a
                            3
                          
                          ⁡
                          
                            (
                            4
                            )
                          
                        
                        ⁢
                        
                          L
                          3
                        
                      
                    
                  
                
              
            
          
          ⁢
          
            {
            
              
                
                  
                    
                      
                        X
                        0
                      
                      ⁡
                      
                        (
                        f
                        )
                      
                    
                    +
                    
                      
                        L
                        1
                      
                      ⁢
                      
                        X
                        1
                      
                      ⁢
                      
                        (
                        f
                        )
                      
                    
                    +
                  
                
              
              
                
                  
                    
                      
                        L
                        2
                      
                      ⁢
                      
                        
                          X
                          2
                        
                        ⁡
                        
                          (
                          f
                          )
                        
                      
                    
                    +
                    
                      
                        L
                        3
                      
                      ⁢
                      
                        
                          X
                          3
                        
                        ⁡
                        
                          (
                          f
                          )
                        
                      
                    
                  
                
              
            
            }
          
        
      
    
    
      
        Expression
        ⁢
        
          
        
        ⁢
        10
      
    
  




Hereinbefore, a given analog signal has been explained as a complex signal. However, when a given analog signal is a real signal, only an operation corresponding to the first region and the second region is applied among the correction methods. For example, in synthesizing step S208, the frequency spectrums in the first region and the second region are computed by using the correction coefficient computed by Expression 6 or Expression 7 in Expression 9, and the complex conjugate of the frequency spectrums in the first region and the second region is computed as the frequency spectrums in the third region and the fourth region.
Moreover, although a band of the computed frequency spectrum has been explained as [0070] in this example, it is possible to realize a similar operation even in case of using the band as [−2fs, 2fs]. For example, it is possible to remove a spurious component in a similar operation by regarding the band of the third region as [−fs, 0] and the band of the fourth region as [−2fs, −fs].
Moreover, each frequency characteristic may be computed as follows on the basis of the frequency characteristic a(0) of k=0.

a(−1):shift a(0) by −fs/4

a(1):shift a(0) by fs/4

a(2):shift a(0) by 2fs/4

a(3):shift a(0) by 3fs/4

a(5):shift a(0) by 5fs/4

Moreover, when the Fourier transform section 12 performs Fourier transform by means of discrete Fourier transform, the discrete Fourier transform of each output signal of ADCs 10 is given by the following expression.




  
    
      
        
          
            D
            ⁢
            
              
            
            ⁢
            F
            ⁢
            
              
            
            ⁢
            
              
                T
                0
              
              ⁡
              
                (
                k
                )
              
            
          
          =
          
            
              ∑
              
                n
                =
                0
              
              
                
                  (
                  
                    N
                    /
                    4
                  
                  )
                
                -
                1
              
            
            ⁢
            
              
                x
                ⁡
                
                  (
                  
                    4
                    ⁢
                    nTs
                  
                  )
                
              
              ⁢
              
                e
                
                  
                    -
                    j2π
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    kn
                    /
                    
                      N
                      4
                    
                  
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            D
            ⁢
            
              
            
            ⁢
            F
            ⁢
            
              
            
            ⁢
            
              
                T
                1
              
              ⁡
              
                (
                k
                )
              
            
          
          =
          
            
              ∑
              
                n
                =
                0
              
              
                
                  (
                  
                    N
                    /
                    4
                  
                  )
                
                -
                1
              
            
            ⁢
            
              
                x
                ⁡
                
                  (
                  
                    
                      (
                      
                        
                          4
                          ⁢
                          n
                        
                        +
                        1
                      
                      )
                    
                    ⁢
                    Ts
                  
                  )
                
              
              ⁢
              
                e
                
                  
                    -
                    j2π
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    kn
                    /
                    
                      N
                      4
                    
                  
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            D
            ⁢
            
              
            
            ⁢
            F
            ⁢
            
              
            
            ⁢
            
              
                T
                2
              
              ⁡
              
                (
                k
                )
              
            
          
          =
          
            
              ∑
              
                n
                =
                0
              
              
                
                  (
                  
                    N
                    /
                    4
                  
                  )
                
                -
                1
              
            
            ⁢
            
              
                x
                ⁡
                
                  (
                  
                    
                      (
                      
                        
                          4
                          ⁢
                          n
                        
                        +
                        2
                      
                      )
                    
                    ⁢
                    Ts
                  
                  )
                
              
              ⁢
              
                e
                
                  
                    -
                    j2π
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    kn
                    /
                    
                      N
                      4
                    
                  
                
              
            
          
        
        ⁢
        
          

        
        ⁢
        
          
            D
            ⁢
            
              
            
            ⁢
            F
            ⁢
            
              
            
            ⁢
            
              
                T
                3
              
              ⁡
              
                (
                k
                )
              
            
          
          =
          
            
              ∑
              
                n
                =
                0
              
              
                
                  (
                  
                    N
                    /
                    4
                  
                  )
                
                -
                1
              
            
            ⁢
            
              
                x
                ⁡
                
                  (
                  
                    
                      (
                      
                        
                          4
                          ⁢
                          n
                        
                        +
                        3
                      
                      )
                    
                    ⁢
                    Ts
                  
                  )
                
              
              ⁢
              
                e
                
                  
                    -
                    j2π
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    kn
                    /
                    
                      N
                      4
                    
                  
                
              
            
          
        
      
    
    
      
        Expression
        ⁢
        
          
        
        ⁢
        12
      
    
  




Then, the frequency domain signal transformed by the discrete Fourier transform method is given by the following expression.




  
    
      
        
          
            X
            l
          
          ⁡
          
            (
            
              k
              NTs
            
            )
          
        
        =
        
          
            ∑
            
              n
              =
              0
            
            
              
                (
                
                  N
                  /
                  4
                
                )
              
              -
              1
            
          
          ⁢
          
            
              x
              ⁡
              
                (
                
                  
                    (
                    
                      
                        4
                        ⁢
                        n
                      
                      +
                      l
                    
                    )
                  
                  ⁢
                  Ts
                
                )
              
            
            ⁢
            
              e
              
                
                  -
                  j2π
                
                ⁢
                
                  
                
                ⁢
                
                  f
                  ⁡
                  
                    (
                    
                      
                        (
                        
                          4
                          ⁢
                          ntl
                        
                        )
                      
                      ⁢
                      Ts
                    
                    )
                  
                
              
            
          
        
      
    
  
  
    
      
        =
        
          
            e
            
              
                -
                j2π
              
              ⁢
              
                
              
              ⁢
              
                kl
                /
                N
              
            
          
          ⁢
          
            
              ∑
              
                n
                =
                0
              
              
                
                  (
                  
                    N
                    /
                    4
                  
                  )
                
                -
                1
              
            
            ⁢
            
              
                x
                ⁡
                
                  (
                  
                    
                      (
                      
                        
                          4
                          ⁢
                          n
                        
                        +
                        l
                      
                      )
                    
                    ⁢
                    Ts
                  
                  )
                
              
              ⁢
              
                e
                
                  
                    -
                    j2π
                  
                  ⁢
                  
                    
                  
                  ⁢
                  
                    kn
                    /
                    
                      N
                      4
                    
                  
                
              
            
          
        
      
    
  
  
    
      
        =
        
          
            e
            
              
                -
                j2π
              
              ⁢
              
                
              
              ⁢
              
                kl
                /
                N
              
            
          
          ⁢
          D
          ⁢
          
            
          
          ⁢
          F
          ⁢
          
            
          
          ⁢
          
            
              T
              l
            
            ⁡
            
              (
              k
              )
            
          
        
      
    
  




For this reason, Expression 9 and Expression 10 are expressed as follows.




  
    
      
        
          
            X
            ′
          
          ⁡
          
            (
            
              k
              NTs
            
            )
          
        
        =
        
          
            1
            
              
                
                  
                    1
                    +
                    
                      
                        
                          a
                          1
                        
                        ⁡
                        
                          (
                          0
                          )
                        
                      
                      ⁢
                      
                        L
                        1
                      
                    
                    +
                  
                
              
              
                
                  
                    
                      
                        
                          a
                          2
                        
                        ⁡
                        
                          (
                          0
                          )
                        
                      
                      ⁢
                      
                        L
                        2
                      
                    
                    +
                    
                      
                        
                          a
                          3
                        
                        ⁡
                        
                          (
                          0
                          )
                        
                      
                      ⁢
                      
                        L
                        3
                      
                    
                  
                
              
            
          
          ⁢
          
            (
            
              
                
                  
                    
                      D
                      ⁢
                      
                        
                      
                      ⁢
                      F
                      ⁢
                      
                        
                      
                      ⁢
                      
                        
                          T
                          0
                        
                        ⁡
                        
                          (
                          k
                          )
                        
                      
                    
                    +
                    
                      
                        L
                        1
                      
                      ·
                      
                        e
                        
                          
                            -
                            j2π
                          
                          ⁢
                          
                            
                          
                          ⁢
                          
                            k
                            ·
                            
                              1
                              /
                              N
                            
                          
                        
                      
                      ·
                    
                  
                
              
              
                
                  
                    
                      D
                      ⁢
                      
                        
                      
                      ⁢
                      F
                      ⁢
                      
                        
                      
                      ⁢
                      
                        
                          T
                          1
                        
                        ⁡
                        
                          (
                          k
                          )
                        
                      
                    
                    +
                    
                      
                        L
                        2
                      
                      ·
                      
                        e
                        
                          
                            -
                            j2π
                          
                          ⁢
                          
                            
                          
                          ⁢
                          
                            k
                            ·
                            
                              2
                              /
                              N
                            
                          
                        
                      
                      ·
                    
                  
                
              
              
                
                  
                    
                      D
                      ⁢
                      
                        
                      
                      ⁢
                      F
                      ⁢
                      
                        
                      
                      ⁢
                      
                        
                          T
                          2
                        
                        ⁡
                        
                          (
                          k
                          )
                        
                      
                    
                    +
                    
                      
                        
                          L
                          3
                        
                        ·
                        
                          e
                          
                            
                              -
                              j2π
                            
                            ⁢
                            
                              
                            
                            ⁢
                            
                              k
                              ·
                              
                                3
                                /
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Moreover, it has been explained that the number of ADCs 10 is four. However, although the number of ADCs 10 is N (N is two or more integer number), it is possible to compute the frequency spectrum in which a spurious component is removed. For example, Expression 4, Expression 5, Expression 9, and Expression 10 are expressed by the following expressions.




  
    
      
        
          
        
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(Here, in the above expression, assuming that the band of X(f) is [−Nfs/2, Nfs/2] (fs is sampling frequency of each analog-digital converter), terms from −1 to m are components included in the band [0076], and aj(k) shows a component corresponding to x(k) among the frequency characteristics of the j-th analog-digital converter).

X0(f)+L1X1(f)+L2X2(f)+ . . . +LN−1XN−1(f)=α x(0)+β x(u)  Expression 5′

(Here, in the above expression, α and β are arbitrary real number, and x(u) is an aliasing component of x(0).)




  
    
      
        
          
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          10
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FIG. 8 is a view showing another example of a configuration of the analog-to-digital conversion apparatus 100. The analog-to-digital conversion apparatus 100 according to this example holds a continuity of a waveform of the digital data output from the plurality of ADCs 10 to perform discrete Fourier transform and correction arithmetic. The analog-to-digital conversion apparatus 100 includes a plurality of ADCs 10, an interleaving section 40, and a correction arithmetic section 42.
In this example, it will be described about the analog-to-digital conversion apparatus 100 having four ADCs 10. However, although the analog-to-digital conversion apparatus 100 includes N ADCs 10, it is possible to perform similar correction.
Moreover, the analog-to-digital conversion apparatus 100 may not include the ADCs 10, but receive the digital data output from outside ADCs 10. In this case, the analog-to-digital conversion apparatus 100 may use, e.g., a FPGA (Field Programmable Gate Array).
The plurality of ADCs 10 has the same function as that of the ADCs 10 explained using FIGS. 1 to 7. The plurality of ADCs 10 splits and receives an input signal (an analog signal) respectively and converts the analog signal into digital data in different timing by a predetermined phase.
The interleaving section 40 aligns the digital data respectively output from the plurality of ADCs 10 according to the timing in which each digital data is converted to generate a data sequence. For example, the interleaving section 40 may be a FIFO memory that sequentially stores and outputs data received from the plurality of ADCs 10.
The correction arithmetic section 42 corrects a data value error of the data sequence caused by a phase error of the timing in which the plurality of ADCs 10 samples the analog signal based on a frequency characteristic of each of the ADCs 10. The correction arithmetic section 42 performs the similar arithmetic process to that of the Fourier transform section 12 and the correction section 16 explained using FIGS. 1 to 7 while holding a continuity of a waveform of the data sequence.
FIG. 9 is a view exemplary showing a configuration of the correction arithmetic section 42. The correction arithmetic section 42 has a data partitioning section 44, a data inserting section 46, an arithmetic section 48, and a data connecting section 50. An operation of each section will be explained by means of FIG. 10.
FIG. 10 is a view exemplary explaining an operation of the correction arithmetic section 42. The data partitioning section 44 receives a data sequence, and generates a plurality of partition data by dividing the received data sequence by a predetermined partition data number N-L (N and L are natural number). Here, N shows the number of processing data that the arithmetic section 48 can sequentially acquire. For example, when the arithmetic section 48 performs fast Fourier transform, N is a power-of-two number. Moreover, L is a predetermined value.
The data inserting section 46 sequentially outputs zero-inserted data that are made by inserting data with data value zero at the head or end of each partition data by the predetermined insertion data number L. That is, the number of data of the zero-inserted data is equal with the process data number N that the arithmetic section 48 can acquire. In FIG. 10, the data with data value zero is inserted at the end of the partition data.
The arithmetic section 48 sequentially acquires the zero-inserted data sequentially output from the data inserting section 46, and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each ADC 10 with respect to the acquired zero-inserted data. The arithmetic section 48 has the plurality of Fourier transform sections 12, the plurality of correction sections 16, and the interleaving section 18 described related to FIG. 1, and outputs the data after correction made by performing correction described using FIGS. 1 to 7 with respect to the data corresponding to each of the ADCs 10. The arithmetic section 48 may have a means for dividing the zero-inserted data into the data corresponding to each of the ADCs 10 in order to perform correction arithmetic with respect to the data corresponding to each of the ADCs 10. The partitioned data are input to the corresponding Fourier transform section 12.
The data connecting section 50 adds the data of the insertion data number L at the end of each data after correction sequentially output from the arithmetic section 48 and the data of the insertion data number L at the head of the data after correction output from the arithmetic section 48 following that data after correction in order to sequentially connect each data after correction and the next data after correction. For example, when connecting data after correction 1 and data after correction 2, data from the head data R0 to the data RN-L−1 of the data after correction 1 are held. Then, the data of the insertion data number L at the end of data after correction 1 and the data of the insertion data number L at the head of data after correction 2 are added to be connected to the data RN-L−1. Then, the data after the L+1th from the head of data after correction 2 are further connected. By such a configuration, it is possible to improve a continuity of a waveform in correction arithmetic.
FIG. 11 is a view showing another example of a configuration of the correction arithmetic section 42. The correction arithmetic section 42 has a data partitioning section 44, an arithmetic section 48, and a data connecting section 50. An operation of each section will be explained by means of FIG. 12.
FIG. 12 is a view exemplary explaining an operation of the correction arithmetic section 42 shown in FIG. 11. The data partitioning section 44 receives a data sequence, and divides the received data sequence into a plurality of partition data respectively having data of a predetermined data number N. Here, the data number N of the partition data is equal with the number of process data that the arithmetic section 48 can sequentially acquire.
At this time, the data partitioning section 44 generates each partition data so that data of a predetermined duplicated data number L at the head of each partition data are overlapped with data of the duplicated data number L at the end of partition data in front of that partition data. Moreover, about the head partition data, since the partition data in front of that partition data does not exist, data with data value zero may be inserted at the head of that partition data by L. For example, the data partitioning section 44 extracts a data stream having N-L data from the head of the data sequence, and generates data made by inserting L zero data at the head of that data stream as partition data 1. Moreover, the data partitioning section 44 extracts a data stream having N data from the data sequence to generate the stream as partition data 2 so that the L data at the head of partition data 2 are overlapped with the L data at the end of partition data 1.
The arithmetic section 48 sequentially acquires the partition data sequentially output from the data partitioning section 44, and sequentially outputs data after correction made by sequentially performing correction arithmetic according to a frequency characteristic of each ADC 10 with respect to the acquired partition data. The arithmetic section 48 has the same configuration and function as those of the arithmetic section 48 explained using FIGS. 9 and 10.
The data connecting section 50 removes either of the duplicated data at the end of each data after correction sequentially output from the arithmetic section 48 according to each partition data or the duplicated data at the head of that data after correction, and sequentially connects the end of that data after correction and the head of the data after correction following that data after correction. For example, when connecting the data after correction 1 and the data after correction 2, the L data at the head of each of the data after correction 1 and the data after correction 2 may be removed. Then, the end of the data after correction 1 from which the data have been removed and the head of the data after correction 2 from which the data have been removed are connected. By such a configuration, it is possible to improve a continuity of a waveform in correction arithmetic.
FIG. 13 is a view showing another example of a configuration of the correction arithmetic section 42. The correction arithmetic section 42 according to this example further has a characteristic storing section 62, a Fourier inverse transform section 64, a data number adjusting section 66, a Fourier transform section 68, and an error computing section 70 in addition to a configuration of the correction arithmetic section 42 shown in FIG. 9. The correction arithmetic section 42 in this example holds a continuity of a waveform in regard to an operation of the arithmetic section 48 by adjusting the insertion data number with respect to the correction arithmetic section 42 explained related to FIG. 9.
The characteristic storing section 62 previously stores a frequency characteristic of ADC 10. Here, the frequency characteristic of ADC 10 may be measured by means of the measuring section 14 explained using FIG. 1. Moreover, the characteristic storing section 62 may store a frequency characteristic of either of the plurality of ADCs 10.
The Fourier inverse transform section 64 converts the frequency characteristic of ADC 10 stored on the characteristic storing section 62 into a discrete signal on a time axis. The Fourier inverse transform section 64 inputs the discrete signal to the data partitioning section 44. At this time, the interleaving section 40 does not input the sequence data to the data partitioning section 44.
The data partitioning section 44, the data inserting section 46, the arithmetic section 48, and the data connecting section 50 performs the same process as that described using FIG. 10 with respect to the discrete signal. Moreover, the arithmetic section 48 may not perform correction arithmetic with respect to the discrete signal.
The Fourier transform section 68 converts the signals output from the data connecting section 50 according to the discrete signal into signals in a frequency domain. The error computing section 70 compares the signals in the frequency domain converted by the Fourier transform section 68 and the frequency characteristic stored on the characteristic storing section 62 in order to compute an error. The error computing section 70 may compute a squared error of these signals.
The data number adjusting section 66 adjusts the insertion data number in the data partitioning section 44 and the data inserting section 46 so that the error computed by the error computing section 70 is within a predetermined range. For example, the data number adjusting section 66 sequentially changes the insertion data number to cause the error computing section 70 to compute an error with respect to each insertion data number. Then, the data number adjusting section 66 detects the smallest insertion data number among the insertion data number in which the error is within the predetermined range. The data number adjusting section 66 causes the data partitioning section 44 and the data inserting section 46 to process the data sequence provided from the interleaving section 40 using the detected insertion data number.
By such a configuration, it is possible to set the insertion data number such that a continuity of a waveform of the data sequence can be held in arithmetic process of the arithmetic section 48. Moreover, the arithmetic section 48 may perform correction arithmetic corresponding to the set insertion data number using the frequency characteristic output from the Fourier transform section 68. In this case, the characteristic storing section 62 stores a frequency characteristic of each ADC 10. Moreover, the error computing section 70 computes an error for each frequency characteristic of each ADC 10, and the data number adjusting section 66 detects the insertion data number in which all errors of frequency characteristic of all the ADCs 10 are within the predetermined range.
FIG. 14 is a view showing another example of a configuration of the correction arithmetic section 42. The correction arithmetic section 42 according to this example further has a characteristic storing section 62, a Fourier inverse transform section 64, a data number adjusting section 66, a Fourier transform section 68, and an error computing section 70 in addition to a configuration of the correction arithmetic section 42 shown in FIG. 11. The correction arithmetic section 42 in this example holds a continuity of a waveform in regard to an operation of the arithmetic section 48 by adjusting the duplicated data number with respect to the correction arithmetic section 42 explained related to FIG. 11.
In this example, the operations of the characteristic storing section 62, the Fourier inverse transform section 64, the data number adjusting section 66, the Fourier transform section 68, and the error computing section 70 are similar to those described in FIG. 13. However, the data number adjusting section 66 adjusts the duplicated data number in the data partitioning section 44. By such a configuration, it is possible to set the insertion data number such that a continuity of a waveform of the data sequence can be held in arithmetic process of the arithmetic section 48.
FIG. 15 is a view exemplary showing a configuration of the arithmetic section 48. The arithmetic section 48 in the present example performs correction arithmetic according to a frequency characteristic of each of the ADCs 10 described in FIG. 10 by means of butterfly arithmetic. The arithmetic section 48 has a data distributing section 80, a plurality of Fourier transform sections (82-1 to 82-4, referred to as 82), and a plurality of butterfly arithmetic sections (84-1 to 84-3, referred to as 84).
In the present example, the arithmetic section 48 has the Fourier transform sections 82 of which the number is same as that of the plurality of ADCs 10. The Fourier transform sections 82 are provided one-to-one corresponding to the ADCs 10. Moreover, the arithmetic section 48 has the butterfly arithmetic sections 84 according to the number of the Fourier transform sections 82. For example, when there are provided 2^k pieces of the Fourier transform sections 82, the butterfly arithmetic sections 84 of 2^0+2^1+ . . . +2^(k−1) pieces are provided (however, m is 0 to k−1).
FIG. 16 is a view explaining an operation of the arithmetic section 48 shown in FIG. 15. The data distributing section 80 receives zero-inserted data which are sequentially output from the data inserting section 46, and distributes each data of each zero-inserted data every data corresponding to the ADC 10. In this example, the data distributing section 80 distributes each zero-inserted data into four distributed data because the four ADCs 10 are provided.
For example, the data distributing section 80 extracts (k+1+4n)th data of the zero-inserted data as the distributed data corresponding to the ADC10-k (however, n=0, 1, 2, . . . ). For example, the data distributing section 80 extracts data of (D0, D4, D8, . . . ) as the distributed data 1 corresponding to the ADC 10-0.
The data distributing section 80 inputs each distributed data into the corresponding Fourier transform section 82. The Fourier transform section 82 Fourier-transforms the input distributed data into a signal in a frequency domain.
The butterfly arithmetic section 84 performs butterfly arithmetic on the signals output from the plurality of Fourier transform sections 82. In this example, the butterfly arithmetic section 84-1 performs butterfly arithmetic on the signal output from the Fourier transform section 82 corresponding to the ADC 10-0 and the signal output from the Fourier transform section 82 corresponding to the ADC 10-2. Moreover, the butterfly arithmetic section 84-2 performs butterfly arithmetic on the signal output from the Fourier transform section 82 corresponding to the ADC 10-1 and the signal output from the Fourier transform section 82 corresponding to the ADC 10-3. Moreover, the butterfly arithmetic section 84-3 performs butterfly arithmetic on the signal output from the butterfly arithmetic section 84-1 and the signal output from the butterfly arithmetic section 84-2.
Here, the plurality of butterfly arithmetic sections 84 performs a correction arithmetic described with reference to FIGS. 1 to 7. Input/output relation of one butterfly arithmetic section 84 is given by the following expression assuming that an input to the butterfly arithmetic section 84 is DFTeven(n) and DFTodd(n) and an output from the butterfly arithmetic section 84 is DFT(n).

DFT(n)=DFTeven(n)+P×WN(n)×DFTodd(n)  Expression (13)

However, WN(n) is a rotational operator that corrects phase error τ of a sampling timing of the analog-to-digital converter 52 to an ideal sampling timing, N is the number of data after arithmetic, Ts is a sampling interval of data after arithmetic, and r is a signal component described in FIG. 3.

Moreover, WN(n)=e^(−j2π(1+τ/Ts)n/N)

P=e^(jπrτ/Ts)

Assuming that the output of the Fourier transform section 82-1 is DFT0(n), the output of the Fourier transform section 82-3 is DFT1(n), the output of the Fourier transform section 82-2 is DFT2(n), and the output of the Fourier transform section 82-4 is DFT3(n), if applying Expression (13) to Expression (9′),

DFTeven(n)=DFT0(n)+P2×WN(n)×DFT2(n)  Expression (14)

DFTodd(n)=DFT1(n)+P3×WN(n)×DFT3(n)  Expression (15)

DFT(n)=DFTeven(n)+P1×WN(n)×DFTodd(n)  Expression (16)

Here, Expression (14) shows input/output relation for the butterfly arithmetic section 84-1, Expression (15) shows input/output relation for the butterfly arithmetic section 84-2, and Expression (16) shows input/output relation for the butterfly arithmetic section 84-3. Moreover, P1=L1, P2=L2, P3=L3/L1. Moreover, the butterfly arithmetic section 84-3 multiplies 1/(a0)+a1(0)L1+a2(0)L2+a3(0)L3) by the output DFT(n) shown in Expression (16), and output the result. Moreover, the butterfly arithmetic section 84-3 may convert this output into a data row in a time domain and output the result.
As described in FIGS. 1 to 7, each of the butterfly arithmetic sections 84 divides a frequency band into a plurality of bands, and performs phase correction butterfly arithmetic on each band by means of phase correction coefficients L1, L2, and L3 different from one another. By such a process, the signal which is output from the butterfly arithmetic section 84-3 for each zero-inserted data becomes a data equal to each data after correction described in FIG. 10.
Moreover, although the process in the arithmetic section 48 shown in FIGS. 9 and 10 has been above described, the same process can be also performed in the arithmetic section 48 shown in FIGS. 11 and 12. In this case, the data distributing section 80 distributes partition data shown in FIG. 12 as distributed data corresponding to each ADC 10. Moreover, the same process is also performed in the arithmetic section 48 described in FIG. 13 or 14.
FIG. 17 is a view exemplary showing a configuration of a computer 400 that stores a program causing the analog-to-digital conversion apparatus 100 to function. In this example, the computer 400 stores a program making the analog-to-digital conversion apparatus 100 function as described in FIGS. 1 to 16. The computer 400 may be a workstation controlling the analog-to-digital conversion apparatus 100, or may function as the correction arithmetic section 42.
The computer 400 includes a CPU 700, a ROM 702, a RAM 704, a communication interface 706, a hard disk drive 710, a FD drive 712, and a CD-ROM drive 714. The CPU 700 operates based on a program stored on the ROM 702, the RAM 704, the hard disk 710, the FD disk 720, and/or the CD-ROM 722.
The communication interface 706 communicates with, e.g., the analog-to-digital conversion apparatus 100 to send and receive data. The hard disk drive 710 as an example of a storing section stores setting information and a program to cause the central processing section 700 to operate. The ROM 702, the RAM 704, and the hard disk drive 710 store a program causing the analog-to-digital conversion apparatus 100 to function as the analog-to-digital conversion apparatus 100 described related to FIGS. 1 to 16. Moreover, the program may be stored on the flexible disk 720, the CD-ROM 722, the hard disk drive 710, etc.
The FD drive 712 reads the program from the flexible disk 720 and provides it to the CPU 700. The CD-ROM drive 714 reads the program from the CD-ROM 722 and provides it to the CPU 700.
Moreover, the program may be read from a recording medium and stored on a RAM to be executed, or may be read from a recording medium to be once installed in a hard disk drive and stored on a RAM to be executed. Furthermore, the program may be stored on single recording medium, or may be stored on a plurality of recording media. Moreover, a program stored on the recording medium may provide each of the functions in association with an operating system. For example, a program may request an execution of all or some of the functions to an operating system, and provide the function based on an answer from the operating system.
It is possible to use an optical recording medium such as a DVD and a PD, a magneto-optical recording medium such as an MD, a tape medium, a magnetic recording medium, an IC card, and a semiconductor memory such as a miniature card besides a flexible disk and a CD-ROM as a recording medium storing a program. Moreover, a storing section such as a hard disk or a RAM that is provided in a server system connected to a private telecommunication network, an Internet, etc. may be used as a recording medium.
Although the present invention has been described by way of an exemplary embodiment, it should be understood that those skilled in the art might make many changes and substitutions without departing from the spirit and the scope of the present invention. It is obvious from the definition of the appended claims that embodiments with such modifications also belong to the scope of the present invention. As apparent from the above descriptions, according to the present invention, it is possible to divide digital data sampled using a plurality of ADCs provided in parallel and hold a continuity of a waveform of the digital data when performing correction arithmetic in a frequency domain in order to perform the correction arithmetic.

## Claims

1. An analog-to-digital conversion apparatus to which an analog signal is split and supplied and which corrects digital data output from a plurality of analog-to-digital conversion sections that sequentially convert the analog signal in different timing by a predetermined phase, the analog-to-digital conversion apparatus comprising:
an interleaving section that aligns the digital data respectively output from the plurality of analog-to-digital conversion sections according to the timing in which the digital data are respectively converted and generates a data sequence; and
a correction arithmetic section that corrects a data value error of the data sequence caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, based on a frequency characteristic of each of the analog-to-digital conversion sections, wherein
said correction arithmetic section comprises:
a data partitioning section that generates a plurality of partition data by partitioning the data sequence by a predetermined partition data number;
a data inserting section that inserts data with data value zero at the head or end of each of the partition data by a predetermined insertion data number to sequentially output these data;
an arithmetic section that sequentially acquires the partition data sequentially output from the data inserting section and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each analog-to-digital conversion section with respect to the acquired partition data; and
a data connecting section that adds the data of the insertion data number at the end of each data after correction sequentially output from the arithmetic section according to each partition data and the data of the insertion data number at the head of the data after correction following that data after correction in order to sequentially connect that data after correction and the data after correction following that data after correction.

2. The analog-to-digital conversion apparatus as claimed in claim 1, wherein the data partitioning section generates the plurality of partition data using a value, which is obtained by subtracting the insertion data number from the number of process data sequentially acquired by the arithmetic section, as the partition data number.

3. The analog-to-digital conversion apparatus as claimed in claim 1, wherein the arithmetic section comprises:
a data distributing section that generates distributed data obtained by distributing data of the partition data to each of the corresponding analog-to-digital conversion sections; and
a butterfly arithmetic section that divides, for the distributed data, a frequency band into a plurality of bands and performs correction butterfly arithmetic on each band by means of a correction coefficient according to the frequency characteristics of the analog-to-digital conversion section, in order to perform the correction arithmetic.

4. An analog-to-digital conversion apparatus to which an analog signal is split and supplied and which corrects digital data output from a plurality of analog-to-digital conversion sections that sequentially converts the analog signal in different timing by a predetermined phase, the analog-to-digital conversion apparatus comprising:
an interleaving section that aligns the digital data respectively output from the plurality of analog-to-digital conversion sections according to the timing in which the digital data are respectively converted and generates a data sequence; and
a correction arithmetic section that corrects a data value error of the data sequence caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, based on a frequency characteristic of each of the analog-to-digital conversion sections, wherein
said correction arithmetic section comprises:
a data partitioning section that partitions the data sequence into a plurality of partition data having a predetermined partition data number and respectively generates the partition data so that duplicated data of a predetermined number at the head of each of the partition data is overlapped with duplicated data of the predetermined number at the end of the partition data in front of that partition data;
an arithmetic section that sequentially acquires the partition data respectively generated from the data partitioning section and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each analog-to-digital conversion section with respect to the acquired partition data; and
a data connecting section that removes either of the duplicated data at the end of each data after correction sequentially output from the arithmetic section according to each partition data or the duplicated data at the head of that data after correction and sequentially connects the end of that data after correction and the head of the data after correction following that data after correction.

5. The analog-to-digital conversion apparatus as claimed in claim 4, wherein the data partitioning section generates the plurality of partition data using the number of process data sequentially acquired by the arithmetic section as the partition data number.

6. The analog-to-digital conversion apparatus as claimed in claim 4, wherein the arithmetic section comprises:
a data distributing section that generates distributed data obtained by distributing data of the partition data to each of the corresponding analog-to-digital conversion sections; and
a butterfly arithmetic section that divides, for the distributed data, a frequency band into a plurality of bands and performs correction butterfly arithmetic on each band by means of a correction coefficient according to the frequency characteristics of the analog-to-digital conversion section, in order to perform the correction arithmetic.

7. The analog-to-digital conversion apparatus as claimed in claim 2, wherein said correction arithmetic section further comprises:
a characteristic storing section that previously stores a frequency characteristic of the analog-to-digital conversion section;
a Fourier inverse transform section that converts the frequency characteristic of the analog-to-digital conversion section into a discrete signal on a time axis and inputs the signal to the data partitioning section;
a Fourier transform section that converts the signal output from the data connecting section into a signal on a frequency axis when the Fourier inverse transform section inputs the discrete signal to the data partitioning section;
an error computing section that compares the signal output from the Fourier transform section and the frequency characteristic stored on the characteristic storing section and computes an error; and
a data number adjusting section that controls the number of insertion data so that the error computed by the error computing section is within a predetermined range.

8. The analog-to-digital conversion apparatus as claimed in claim 7, wherein the data number adjusting section sequentially changes the number of insertion data to cause the error computing section to compute the error every the number of insertion data.

9. The analog-to-digital conversion apparatus as claimed in claim 8, wherein the arithmetic section performs the correction arithmetic using the signal output from the Fourier transform section as the frequency characteristic of the analog-to-digital conversion section when the error is within the predetermined range.

10. The analog-to-digital conversion apparatus as claimed in claim 5, wherein said correction arithmetic section further comprises:
a characteristic storing section that previously stores a frequency characteristic of the analog-to-digital conversion section;
a Fourier inverse transform section that converts the frequency characteristic of the analog-to-digital conversion section into a discrete signal on a time axis and inputs the signal to the data partitioning section;
a Fourier transform section that converts the signal output from the data connecting section into a signal on a frequency axis when the Fourier inverse transform section inputs the discrete signal to the data partitioning section;
an error computing section that compares the signal output from the Fourier transform section and the frequency characteristic stored on the characteristic storing section and computes an error; and
a data number adjusting section that controls the number of insertion data so that the error computed by the error computing section is within a predetermined range.

11. A recording medium for storing a program causing an analog-to-digital conversion apparatus, to which an analog signal is split and supplied and which corrects digital data output from a plurality of analog-to-digital conversion sections that sequentially converts the analog signal in different timing by a predetermined phase, to function, the program causing the analog-to-digital conversion apparatus to function as:
an interleaving section that aligns the digital data respectively output from the plurality of analog-to-digital conversion sections according to the timing in which the digital data are respectively converted and generates a data sequence; and
a correction arithmetic section that corrects a data value error of the data sequence caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, based on a frequency characteristic of each of the analog-to-digital conversion sections, wherein
the program causes said correction arithmetic section to function as:
a data partitioning section that generates a plurality of partition data by partitioning the data sequence by a predetermined partition data number;
a data inserting section that inserts data with data value zero at the head or end of each of the partition data by a predetermined insertion data number to sequentially output these data;
an arithmetic section that sequentially acquires the partition data sequentially output from the data inserting section and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each analog-to-digital conversion section with respect to the acquired partition data; and
a data connecting section that adds the data of the insertion data number at the end of each data after correction sequentially output from the arithmetic section according to each partition data and the data of the insertion data number at the head of the data after correction following that data after correction in order to sequentially connect that data after correction and the data after correction following that data after correction.

12. A recording medium for storing a program causing an analog-to-digital conversion apparatus, to which an analog signal is split and supplied and which corrects digital data output from a plurality of analog-to-digital conversion sections that sequentially converts the analog signal in different timing by a predetermined phase, to function, the program causing the analog-to-digital conversion apparatus to function as:
an interleaving section that aligns the digital data respectively output from the plurality of analog-to-digital conversion sections according to the timing in which the digital data are respectively converted and generates a data sequence; and
a correction arithmetic section that corrects a data value error of the data sequence caused by errors of frequency characteristics of the plurality of analog-to-digital conversion sections, based on a frequency characteristic of each of the analog-to-digital conversion sections, wherein
the program causes said correction arithmetic section to function as:
a data partitioning section that partitions the data sequence into a plurality of partition data having a predetermined partition data number and respectively generates the partition data so that duplicated data of a predetermined number at the head of each of the partition data is overlapped with duplicated data of the predetermined number at the end of the partition data in front of that partition data;
an arithmetic section that sequentially acquires the partition data respectively generated from the data partitioning section and sequentially outputs data after correction made by sequentially performing correction arithmetic according to the frequency characteristic of each analog-to-digital conversion section with respect to the acquired partition data; and
a data connecting section that removes either of the duplicated data at the end of each data after correction sequentially output from the arithmetic section according to each partition data or the duplicated data at the head of that data after correction and sequentially connects the end of that data after correction and the head of the data after correction following that data after correction.