# Patent

## Title
Electronic devices and components for high efficiency power circuits

## Abstract

An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package.

## Background
CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation of U.S. patent application Ser. No. 12/684,838, filed Jan. 8, 2010, the disclosure of which is hereby incorporated by reference in its entirety.


TECHNICAL FIELD
Power switching circuits and components which can be used in power switching circuit applications to realize power circuits with very high efficiencies are described.
BACKGROUND
As the amount of worldwide electrical power consumption has been constantly increasing, power supplies and power converters have become increasingly important in our society. A circuit schematic of the primary elements of a boost-mode DC-to-DC power converter (herein a “boost converter”) is shown in FIG. 1. The boost converter circuit includes inductors 10 and 14, a switching device, i.e., a transistor 11, a rectifying device, i.e., a diode 12, and charge storage devices, i.e., capacitors 13 and 15. During the time that the transistor 11 is ON, the inductor 10 sustains the entire input voltage, and the input current flows through the inductor 10 and the transistor 11, while the electric energy is stored as magnetic energy in the inductor 10. At the same time, the diode 12 prevents the capacitor 13 from discharging through the transistor 11. When the transistor 11 is OFF, the potential across the inductor 10 is reversed and the input current flowing through the inductor 10 also flows through the diode 12, thereby charging the capacitor 13 and supplying energy to the output load at a higher voltage potential than that at the input line.
To date, the diodes and transistors used in power circuits such as the boost converter circuit of FIG. 1 have typically been fabricated with silicon (Si) semiconductor materials. Common diode and transistor devices for power applications include Silicon (Si) Schottky diodes, Si Power MOSFETs such as CoolMOS, and Si Insulated Gate Bipolar Transistors (IGBTs). While Si power devices are inexpensive, they suffer from a number of disadvantages, including relatively low switching speeds and high levels of electrical noise, commonly referred to as electro-magnetic interference or EMI. There has been a consistent trend to increase switching frequencies for more compact power supplies, which requires that the devices used in the power supply have higher switching speeds and that circuit architecture be improved to adequately suppress increased electrical noise resulting from higher frequency of operation. Recently, silicon carbide (SiC) power devices have been researched due to their superior electrical and thermal properties as compared to Si devices. III-Nitride (III-N) based semiconductor devices are now also emerging as attractive candidates for power circuit applications.
While the use of III-N devices has shown to be beneficial in power applications, further improvements may be necessary to adequately suppress EMI while simultaneously maintaining a high efficiency as circuit switching frequencies and switching speeds are further increased.
SUMMARY
In one aspect, an electronic component having a III-N transistor and a III-N rectifying device is described. A single package encloses both the III-N transistor and the III-N rectifying device. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package.
In another aspect, a voltage converter having an efficiency greater than 97.8% and a peak output voltage noise less than 1 Volt when operated at a frequency of at least 100 kHz and a conversion ratio of 1:2 is described.
In yet another aspect, a method for operating a switching transistor in a power switching circuit is described. The method includes switching a voltage on a gate of the switching transistor, relative to a source of the switching transistor, from a value above a transistor threshold voltage to a value below the transistor threshold voltage, or from a value below a transistor threshold voltage to a value above the transistor threshold voltage. The voltage is switched at a rate of about 150 volts/nanosecond or higher.
In implementations, the following features are included or enabled. The III-N transistor can be a field-effect transistor. The III-N transistor can be a high voltage switching transistor. The III-N transistor can be an enhancement-mode device. The III-N rectifying device can be a III-N diode, the first electrode can be an anode electrode, and the second electrode can be a cathode electrode. The III-N transistor or the III-N diode can be a lateral device comprising an insulating or semi-insulating portion, and the insulating or semi-insulating portion can be mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N transistor and the conductive structural portion of the single package or between the III-N diode and the conductive structural portion of the single package. The insulating or semi-insulating portion can be an insulating or semi-insulating substrate. The III-N transistor or the III-N diode can be a lateral device comprising a conducting or semi-conducting substrate, and an insulating or semi-insulating III-N layer can be between the conducting or semi-conducting substrate and a channel of the III-N transistor or the III-N diode, where the conducting or semi-conducting substrate can be mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N transistor and the conductive structural portion of the single package or between the III-N diode and the conductive structural portion of the single package. The conducting or semi-conducting substrate can be a silicon substrate. The III-N transistor and the III-N diode can be on a common substrate. The III-N transistor can be a first III-N transistor and the III-N rectifying device can be a second III-N transistor. The first III-N transistor or the second III-N transistor can be a lateral device comprising an insulating or semi-insulating portion, and the insulating or semi-insulating portion can be mounted directly to the conductive structural portion of the single package without an insulating spacer between the first III-N transistor and the conductive structural portion of the single package or between the second III-N transistor and the conductive structural portion of the single package. The insulating or semi-insulating portion can be an insulating or semi-insulating substrate. The first III-N transistor or the second III-N transistor can be a lateral device comprising a conducting or semi-conducting substrate, and an insulating or semi-insulating III-N layer between the conducting or semi-conducting substrate and a channel of the first III-N transistor or the second III-N transistor, wherein the conducting or semi-conducting substrate can be mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N transistor and the conductive structural portion of the single package or between the III-N diode and the conductive structural portion of the single package. The first III-N transistor and the second III-N transistor can be formed on a common substrate. A source electrode of the III-N transistor can be electrically connected to a conductive structural portion of the single package or to a source lead of the single package. The III-N transistor can be a III-N depletion-mode transistor, and the electronic component can further comprise an enhancement-mode transistor encased in the single package, the enhancement-mode transistor comprising an e-mode transistor source electrode, an e-mode transistor gate electrode, and an e-mode transistor drain electrode, wherein the e-mode transistor source electrode can be electrically connected to the conductive structural portion of the single package or to a source lead of the single package, the e-mode transistor drain electrode can be electrically connected to a source electrode of the III-N depletion-mode transistor, and the e-mode transistor gate electrode can be electrically connected to the first lead of the single package. The III-N depletion-mode transistor can be a high-voltage switching transistor, and the enhancement-mode transistor can be a low-voltage transistor. The enhancement-mode transistor can be a Si MOS device. A voltage converter can comprise one of the electronic components described herein. A voltage converter can have an efficiency is greater than 97.8% and the peak output voltage noise is less than 1 Volt when the voltage converter is operated at a frequency of at least 1 MHz. The voltage converter can include device which is capable of operating as a normally-off switch. The device of the voltage converter can be an enhancement-mode III-N transistor. The device of the voltage converter can be an assembly comprising a low-voltage enhancement-mode transistor and a high-voltage depletion-mode transistor. The low-voltage enhancement-mode transistor can be a Si MOS transistor and the high-voltage depletion-mode transistor can be a III-N transistor. A peak output voltage noise of the power switching circuit can be less than 1V.



DESCRIPTION OF DRAWINGS
FIG. 1 is a circuit schematic of a voltage converter circuit of the prior art.
FIG. 2 is a representative plot of transistor source-drain current versus time and source-drain voltage versus time for a transistor in the circuit of FIG. 1.
FIG. 3 is a plot of transient voltage noise versus time at the output node of the voltage converter circuit of FIG. 1.
FIGS. 4 and 5 are perspective and exposed plan views, respectively, of an electronic component.
FIG. 6 is a perspective view of an electronic component.
FIG. 7 is a schematic cross-sectional view of a III-N HEMT device.
FIG. 8 is a schematic cross-sectional view of a III-N diode.
FIGS. 9 and 10 are exposed plan views of electronic components.
FIGS. 11 and 12 are circuit schematics of voltage converter circuits.
FIG. 13 is a plot of transient voltage noise versus time at the output node of the voltage converter circuit of FIG. 12.
FIGS. 14 and 15 are plots of efficiency and power loss versus output power for the boost converter circuit of FIG. 12.



Like reference symbols in the various drawings indicate like elements.
DETAILED DESCRIPTION
In high power switching circuits, for example the boost converter of FIG. 1, switching losses are incurred each time transistor 11 is switched from OFF to ON or from ON to OFF. Switching losses include both RC charging losses and cross-over losses. As seen in the representative plots of transistor source-drain current versus time and source-drain voltage versus time shown in FIG. 2, during the time tswitch that the transistor is switched from ON to OFF, the voltage 17 across the transistor increases while the current 16 through the transistor decreases (conversely, the voltage across the transistor decreases while the current through the transistor increases during the time that the transistor is switched from OFF to ON). The instantaneous cross-over power loss during switching is given by the product of the current through the transistor and the voltage across the transistor, and the total energy lost during switching is given by the time integral of the power loss over the entire switching time. Reducing the transistor switching time tswitch (i.e., increasing the switching speed) reduces the total cross-over energy loss during switching and can thereby reduce power loss and increase the efficiency of the circuit. Hence, it can be beneficial to switch the transistor at higher switching speeds during circuit operation, since this can increase the efficiency of the circuit.
The maximum speed a switching transistor can be switched during circuit operation is largely limited by physical properties of the transistor, such as the channel charge density, channel charge mobility, and channel charge saturation velocity, as well as any intrinsic or parasitic capacitances or resistances in the transistor. Operation of the transistor at a switching speed that exceeds the maximum that the transistor is designed or rated for can result in reliability problems and/or electro-magnetic interference (EMI). Switching transistors currently used in conventional power switching circuits such as boost converter circuits, for example Si-based CoolMOS transistors, are typically rated to be operated at a maximum switching speed of 50 Volts/nanosecond. III-Nitride (i.e., III-N) transistors, such as III-N HEMTs or HFETs, typically have superior intrinsic electronic properties and lower capacitances as compared to Si-based transistors designed to operate at similar voltages and currents, and may therefore be capable of operating at higher switching speeds, such as about 150 Volts/nanosecond or higher, about 200 Volts/nanosecond or higher, or about 250 Volts/nanosecond or higher. As used herein, the terms III-Nitride or III-N materials, layers, devices, etc., refer to a material or device comprised of a compound semiconductor material according to the stoichiometric formula AlxInyGazN, where x+y+z is about 1.
FIG. 3 shows a plot of output voltage noise versus time as measured by the applicant at the output node 5 of the boost converter circuit of FIG. 1 during circuit operation, where a III-N HEMT was used for transistor 11 and a III-N diode was used for diode 12, and the transistor 11 was switched at a switching speed of 200 Volts/nanosecond. As shown, a substantial amount of voltage fluctuation, i.e., “ringing” 6, which is an indication of EMI, was observed at node 5 immediately after each time the III-N HEMT transistor was switched. As seen in FIG. 3, the peak output voltage noise was greater than 10 V. Hence, further improvements were necessary to suppress EMI for operation at higher switching speeds.
While the III-N HEMT and III-N diode that applicant inserted into the boost converter circuit of FIG. 1 are themselves inherently capable of operating at higher circuit switching speeds without generating substantial EMI, other circuit parasitics can still generate EMI or contribute to EMI generation within the circuit. Therefore, layout configurations which reduce or eliminate these parasitics may be necessary in order for the circuit to operate at higher switching speeds without generating substantial EMI.
FIGS. 4 and 5 show a perspective view and an exposed plan view, respectively, of a single electronic component 20 that can be used in place of both the transistor 11 and the diode 12 in the boost converter circuit of FIG. 1. Using electronic component 20 in place of the transistor 11 and the diode 12 in a boost converter circuit, where transistor 11 and diode 12 are each individually packaged, can result in reduced or negligible EMI produced by the circuit even when the transistor switching speed is increased during operation. The perspective view of FIG. 4 shows only the package of the electronic component, while the plan view of FIG. 5 illustrates portions of the package along with the electronic devices which are encased or encapsulated within the package. The electronic component 20 includes a III-N transistor 21 and a III-N rectifying device 22 both encased, enclosed, or encapsulated in a single package.
The single package includes encapsulating structural portions, such as a case 24 and a package base 23, as well as non-structural portions, such as leads 91-95. As used herein, “structural portions” of a package are portions which form the basic shape or molding of the package and provide the structural rigidity of the package necessary to protect the enclosed devices. In many cases, when an electronic component which includes a package is used in a discrete circuit, a structural portion of the package is directly mounted to the circuit or circuit board. In the single package of FIG. 4, the package base 23 is formed of an electrically conducting material, i.e., the package base 23 is an electrically conductive structural portion of the package, and the case 24 is formed of an insulating material. The single package includes at least three leads, a gate lead 91, a drain lead 94, and a cathode lead 95, and can optionally include at least two additional leads, such as open lead 92 and source lead 93. The leads 91-95 are each formed of an electrically conducting material. The source lead 93, when included, can be either electrically connected to or electrically isolated from the package base 23, and all other leads are electrically isolated from the package base. As used herein, two or more contacts or other items are said to be “electrically connected” if they are connected by a material which is sufficiently conducting to ensure that the electric potential at each of the contacts or other items is intended to be the same, i.e., is about the same, at all times under any bias conditions.
As used herein, a “single package” is a package containing, enclosing, encapsulating, or encasing one or more electronic devices or components (i.e., the III-N transistor 21 and the III-N rectifying device 22), which are not each individually encased or encapsulated in a package separate from one another. That is, a single package can have a perimeter within which the one or more electronic devices are located and there is no packaging separating or in the space between one of the electronic devices and another of the electronic devices within the single package. A single package includes structural portions, such as the package base 23 and case 24 in FIG. 4, which can form a single cavity in which the electronic devices or components are enclosed. Or, the electronic devices or components contained in the package can be supported by the package base, and a single case 24 can be molded around the enclosed electronic devices or components, such that the single package does not contain any cavity or cavities (i.e., the single package is free of any cavity or cavities), and the case material contacts the enclosed electronic devices or components. The footprint of the case 24, i.e., the area of the case as measured parallel to a main surface of the package base 23 may be less than 900 square millimeters, less than 400 square millimeters, or less than 100 square millimeters. The enclosed electronic devices or components are supported by the package base 23. There may be no package base material or case material between any of the electronic devices, i.e., if there is a cavity formed by the case 24 the cavity may be a continuous cavity. The connections between the various electronic devices or components enclosed in the single package can be wire bonds or can be formed by wire bonding. Connections between various enclosed electronic devices or components to one another, or to portions of the package, are not formed by circuit traces on a circuit board. That is, the interior of the cavity in the single package can be free of circuit traces, i.e., conductive trace lines that are deposited on a circuit board. A single package has mechanical integrity without inclusion of any additional casing.
As shown in FIG. 6, in some implementations, the package base 23 and case 24 are replaced by a conducting case 123, i.e., an electrically conductive structural portion, which completely surrounds the enclosed transistor, in which case the source lead 93, when included, is either electrically connected to or electrically isolated from the conducting case, and all other leads are electrically isolated from the conducting case.
The III-N transistor 21 can be a field-effect transistor (FET), such as a high-electron mobility transistor (HEMT), a heterojunction field-effect transistor (HFET), a POLFET, a JFET, a MESFET, a CAVET, or any other III-N transistor structure suitable for power switching applications. Examples of III-N transistors that may be suitable for power switching applications can be found in U.S. Pat. No. 7,915,643, U.S. Pat. No. 7,795,642, U.S. Pat. No. 7,851,825, U.S. Pat. No. 8,519,438, U.S. Pat. No. 7,898,004, U.S. Pat. No. 7,884,394, and U.S. Patent Publication No. 2009/0072269, published Mar. 19, 2009—all of which are hereby incorporated by reference.
In some implementations, the III-N transistor 21 is an enhancement-mode (E-mode) device, i.e., a normally off device, such that the threshold voltage is greater than 0V, such as about 1.5V-2V or greater than 2V. In other implementations, the III-N transistor is a depletion-mode (D-mode) device, i.e., a normally on device, such that the threshold voltage is less than 0V. Enhancement-mode devices can be preferable in power switching applications in order to prevent accidental turn on of the devices in case of device or circuit failure. In some implementations, the III-N transistor 21 is a high voltage switching transistor. As used herein, a high voltage switching transistor is a transistor optimized for high voltage switching applications. That is, when the transistor is off, it is capable of blocking high voltages, such as about 300V or higher, about 600V or higher, or about 1200V or higher, and when the transistor is on, it has a sufficiently low on-resistance (RON) for the application in which it is used, i.e., it experiences sufficiently low conduction loss when a substantial current passes through the device.
The III-N transistor 21 can be a lateral device with an insulating or semi-insulating portion on an opposite side of the semiconductor body from all of the electrodes, such as the III-N HEMT illustrated in FIG. 7. In some implementations, a semi-insulating layer is formed by doping a semiconductor layer to render the layer electrically insulating, although not as insulating as some insulating materials. The III-N HEMT of FIG. 7 includes an insulating or semi-insulating portion 61, a semiconductor body 62 which includes a III-N buffer layer 63, such as a layer of GaN, and a III-N barrier layer 64, such as a layer of AlGaN, a two-dimensional electron gas (2 DEG) channel 65, a source electrode 25, a gate electrode 26, and a drain electrode 27. The III-N HEMT can optionally include a conducting or semi-conducting portion 66, such as a silicon substrate.
In some implementations, conducting or semi-conducting portion 66 is not included, and the insulating or semi-insulating portion 61 is an insulating or semi-insulating substrate or carrier wafer. In other implementations, conducting or semi-conducting portion 66 is included and is a silicon substrate or an electrically conducting carrier wafer, and the insulating or semi-insulating portion 61 is an insulating or semi-insulating III-N layer. As used herein, a “substrate” is a material layer on top of which semiconductor material layers of a semiconductor device are epitaxially grown such that the crystalline structure of the portion of semiconductor material contacting or adjacent to the substrate at least partially conforms to or is at least partially determined by the crystalline structure of the substrate. In some implementations, the substrate does not contribute to any conduction of current through the semiconductor device. Having the III-N transistor 21 be a lateral device with an insulating or semi-insulating portion on an opposite side of the semiconductor body 62 from all of the electrodes can be advantageous, since when mounting the III-N transistor 21 inside the package, the surface of the device on a side opposite the electrodes, i.e., surface 68, can be mounted directly to the package base 23 without requiring an insulating spacer, such as a “shim”, between the III-N transistor 21 and the package base 23. For example, when conducting or semi-conducting portion 66 is not included, the insulating or semi-insulating portion 61 can be mounted directly to the package base 23 without requiring an insulating spacer between the III-N transistor 21 and the package base 23, and when conducting or semi-conducting portion 66 is included, the conducting or semi-conducting portion 66 can be mounted directly to the package base 23 without requiring an insulating spacer between the III-N transistor 21 and the package base 23. Transistors which are currently used in conventional power switching circuits, for example Si CoolMOS transistors, are typically vertical devices with electrodes on both sides of the semiconductor body, and therefore require an insulating spacer between the transistor and the package base, which can result in poorer dissipation of heat generated during operation of the transistor and in some cases can result in more EMI produced during circuit operation.
The III-N transistor 21 may also include additional features for power switching applications. These can include, but are not limited to, insulating layers between the gate and the semiconductor body, surface passivation layers, field plates, recesses in the semiconductor body beneath the gate, and additional semiconductor layers, such as an AN layer between the III-N buffer layer 63 and the III-N barrier layer 64, or a III-N back-barrier layer between the 2 DEG 65 and the insulating or semi-insulating portion 61 or between the 2 DEG 65 and the conducting or semi-conducting portion 66.
The III-N rectifying device 22 can be a III-N diode. Examples of III-N diodes that may be used can be found in U.S. Pat. No. 7,898,004 and in U.S. Patent Publication No. 2009/0072269, published Mar. 19, 2009, both of which are hereby incorporated by reference throughout. The III-N rectifying device 22 can be a lateral III-N diode with an insulating or semi-insulating portion on an opposite side of the semiconductor body from all of the electrodes, such as the III-N diode illustrated in FIG. 8. The III-N diode of FIG. 8 includes an insulating or semi-insulating portion 61, a semiconductor body 62 which includes a III-N buffer layer 63, such as GaN, and a III-N barrier layer 64, such as AlGaN, a two-dimensional electron gas (2 DEG) channel 65, an anode contact 28 contacting the semiconductor body 62 on a side opposite the insulating or semi-insulating portion 61 and forming a Schottky contact with the semiconductor materials of the semiconductor body 62, and a cathode contact 29 which forms an ohmic contact with the 2 DEG channel 65. The III-N diode can optionally include a conducting or semi-conducting portion 66, such as a silicon substrate.
In some implementations, the conducting or semi-conducting portion 66 is not included, and the insulating or semi-insulating portion 61 is an insulating or semi-insulating substrate or carrier wafer. In other implementations, conducting or semi-conducting portion 66 is included and is a silicon substrate or an electrically conducting carrier wafer, and the insulating or semi-insulating portion is an insulating or semi-insulating III-N layer. Having the III-N rectifying device 22 be a lateral diode with an insulating or semi-insulating portion on an opposite side of the semiconductor body 62 from all of the electrodes can be advantageous. When mounting the III-N diode inside the package, the surface of the device on a side opposite the electrodes, i.e., surface 69, can be mounted directly to the package base 23 without requiring an insulating spacer, such as a “shim”, between the III-N diode 22 and the package base 23. For example, when conducting or semi-conducting portion 66 is not included, the insulating or semi-insulating portion 61 can be mounted directly to the package base 23 without requiring an insulating spacer between the III-N diode 22 and the package base 23, and when conducting or semi-conducting portion 66 is included, the conducting or semi-conducting portion 66 can be mounted directly to the package base 23 without requiring an insulating spacer between the III-N diode 22 and the package base 23. Diodes which are currently used in conventional power switching circuits, for example SiC diodes, are typically vertical devices with electrodes on both sides of the semiconductor body, and therefore require an insulating spacer between the diode and the package base, which can result in poorer dissipation of heat generated during operation of the diode and in some cases can result in more EMI produced during circuit operation.
III-N diodes used as a III-N rectifying device 22 may also include additional features for power switching applications. These can include, but are not limited to, surface passivation layers, field plates, recesses in the semiconductor body beneath the anode, and additional semiconductor layers, such as an AlN layer between the III-N buffer layer 63 and the III-N barrier layer 64, or a III-N back-barrier layer between the 2 DEG 65 and the insulating or semi-insulating portion 61.
In some implementations, the III-N transistor 21 is formed of or includes the same III-N material layer structure as the III-N rectifying device 22 (see FIGS. 7 and 8). In some implementations, the III-N transistor 21 and the III-N rectifying device 22 share or are formed on a common substrate. Forming the devices on a common substrate can be advantageous, since both devices can be integrated onto a single die, and electrical contacts between electrodes can be lithographically defined rather than being formed of wire bonds, thereby simplifying the circuit and reducing production costs. Examples of III-N transistors and diodes that can be formed of or include the same III-N material layer structure, and/or can share a common substrate, can be found in U.S. Pat. No. 7,898,004.
In some implementations, the III-N rectifying device is a second III-N transistor, as shown in FIG. 9. The III-N rectifying device is hereby referred to as III-N rectifying device 22′ or second III-N transistor 22′ when it is formed of a second III-N transistor. For example, the III-N rectifying device 22′ can be formed of a III-N transistor which is similar to or the same in structure as the III-N transistor 21. The III-N transistor 22′ can be a high voltage switching transistor. A description of methods in which a III-N transistor can be used as a rectifying device in circuits such as boost converters can be found in U.S. Pat. No. 8,289,065, which is hereby incorporated by reference throughout.
When a III-N diode is used for III-N rectifying device 22, the III-N transistor 21 and the III-N diode are mounted inside the single package and connected as follows. Referring back to FIG. 5, electrical connectors 35-39, which can be single or multiple wire bonds, are used to electrically connect portions of the package, III-N transistor, and III-N diode to one another. The III-N transistor 21 and the III-N diode 22 are both mounted inside the package with their respective insulating or semi-insulating substrates in contact with the package base 23. The source electrode 25 of the III-N transistor 21 is electrically connected to a conductive structural portion of the package, such as the package base 23, or can alternatively be electrically connected to source lead 93 of the package, such as by conductive connector 35. The gate electrode 26 of the III-N transistor 21 is electrically connected to the gate lead 91 of the package, such as by conductive connector 36. The drain electrode 27 of the III-N transistor 21 is electrically connected to the anode contact 28 of the III-N diode, such as by conductive connector 38. The drain electrode 27 and anode contact 28 are both electrically connected to drain lead 94 of the package, such as by wire bonding one or both of these contacts/electrodes to the drain lead 94, as shown by conductive connector 37. The cathode contact 29 of the III-N diode is electrically connected to cathode lead 95 of the package, such as by conductive connector 39.
When a second III-N transistor is used for III-N rectifying device 22′, the first III-N transistor 21 and the second III-N transistor 22′ are mounted inside the single package and connected as follows. Referring to FIG. 9, the III-N transistor 21 and the second III-N transistor 22′ are both mounted inside the package with their respective insulating or semi-insulating substrates in contact with the package base 23. The source electrode 25 of the III-N transistor 21 is electrically connected to a conductive structural portion of the package, such as the package base 23, or can alternatively be electrically connected to source lead 93 of the package, such as by conductive connector 35. The gate electrode 26 of the III-N transistor 21 is electrically connected to the gate lead 91 of the package, such as by conductive connector 91. The drain electrode 27 of the III-N transistor 21 is electrically connected to the source electrode 28′ of the second III-N transistor 22′, such as by conductive connector 38. Both of drain electrode 27 of the first transistor and the source electrode 28′ of the second transistor are electrically connected to drain lead 94 of the package, such as by wire bonding one or both of these electrodes to the drain lead, e.g., by conductive connector 37. The drain electrode 29′ of the second III-N transistor 22′ is electrically connected to cathode lead 95 of the package, such as by conductive connector 39. The gate electrode 58′ of the second III-N transistor 22′ can be electrically connected to lead 92 of the package, such as by conductive connector 59.
When the electronic component of FIG. 6 is used in a boost converter circuit or in many other circuits, the source electrode 25 of the III-N transistor 21 is electrically connected to a DC ground, an AC ground, or a circuit ground. As used herein, a node, device, layer, or component is said to be “AC grounded” if it is held at a fixed DC potential at all times during operation. AC and DC grounds are collectively referred to as “circuit grounds”. When the source electrode 25 is electrically connected to the package base 23, the source electrode 25 can be DC or AC grounded by mounting the package base 23 to a ground plane of the circuit. In this case, package leads 92 and 93 can be omitted, resulting in a package with only 3 leads, with one lead, e.g., gate lead 91, connected to the transistor gate electrode 26, one lead, e.g., drain lead 94, connected to the transistor drain electrode 27, and one lead, e.g., cathode lead 95, connected to the diode cathode contact 29. Forming a device with only three leads can be advantageous in that there are many standard commercially available packages that are only available with 3 leads. When the package includes source lead 93, and the source electrode 25 is electrically connected to source lead 93, the source electrode 25 can be DC or AC grounded either by connecting source lead 93 to a circuit ground, or else having source lead 93 electrically connected to the package base 23 and connecting the package base to a circuit ground. Regardless of the number of leads on the package, the leads may be ordered from one side of the package to the other in any order desired, the order not limited to that of the example shown in FIG. 6. Ideally, the leads are ordered such that the total length of all electrical connectors and/or the total footprint of the transistor, diode, and package lead network is minimized, thereby reducing parasitics and potentially reducing EMI produced during circuit operation.
Although it is desirable to have III-N transistor 21 in FIGS. 6 and 9 be an enhancement-mode device, in practice it can be difficult to fabricate III-N transistors with threshold voltages sufficiently greater than 0V that also have desirable characteristics for use in high power switching applications. This problem can be resolved by replacing the III-N transistor 21 in FIG. 6 with a high-voltage III-N depletion-mode (D-mode) transistor 21′, herein III-N D-mode transistor 21′, and a low-voltage enhancement-mode transistor 41, herein E-mode transistor 41, connected as shown in FIG. 10.
FIG. 10 shows a plan view of another single electronic component 40 that can be used in place of both the transistor 11 and the diode 12 in the boost converter circuit of FIG. 1. Using electronic component 40 in place of the transistor 11 and the diode 12 in a boost converter circuit, wherein transistor 11 and diode 12 are each individually packaged, can result in reduced or negligible EMI produced by the circuit even when the transistor is operated at higher switching speeds during circuit operation. The exposed plan view of FIG. 10 illustrates portions of the package along with the electronic devices which are encased in the package (not all of which is shown). The electronic component 40 includes a high-voltage III-N depletion-mode transistor 21′, a low-voltage enhancement-mode transistor 41, and a III-N rectifying device 22 all encased in a single package. The package used for single electronic component 40 in FIG. 10 can be the same as that used for single electronic components 20 and 20′ in FIGS. 5 and 9, respectively, i.e., the package for single electronic component 40 can be that of FIG. 4. The III-N rectifying device 22 can be a III-N diode, as in FIG. 5, or alternatively a second III-N transistor, as in FIG. 9, and has the same requirements and structure as the III-N rectifying device 22 in the single electronic component of FIG. 5 or 9.
The III-N D-mode transistor 21′ is a high-voltage device, and is thereby at least capable of blocking the maximum voltage that would drop across transistor 11 in the conventional boost converter circuit of FIG. 1, which for high-voltage applications can be 300V, 600V, 1200V, or other suitable blocking voltage required by the application. In other words, III-N D-mode transistor 21′ can block any voltage between 0V and at least Vmax, where Vmax is the maximum voltage that would drop across the transistor 11. In some implementations, III-N D-mode transistor 21′ can block any voltage between 0V and at least 2*Vmax. Typical III-N D-mode transistor threshold voltages Vth for high-voltage devices are about −5 to −10V (D-mode=negative Vth). The E-mode transistor 41 can block any voltage between 0V and at least |Vth|, where |Vth| is the magnitude (absolute value) of the threshold voltage of the III-N D-mode transistor 21′. In some implementations, the E-mode transistor 41 can block any voltage between 0V and at least about 2*Vth. Hence, E-mode transistor 41 is a low-voltage device, as the voltages that it must be capable of blocking are substantially less than the circuit high voltage. In some implementations, the III-N D-mode transistor 21′ can block any voltage between 0V and at least about 1200V and has a threshold voltage of about −5V, and the E-mode transistor 41 can block any voltage between 0V and at least about 5V, such as at least about 10V. In some implementations, III-N D-mode transistor 21′ is a high-voltage III-N HEMT device, and E-mode transistor 41 is a Si MOS device or a III-N HEMT device. In other implementations, E-mode transistor 41 is a nitrogen-face III-N device, and III-N D-mode transistor 21′ is a III-face III-N device.
When a III-N diode is used for III-N rectifying device 22 and a Si MOS device is used for E-mode transistor 41, the III-N D-mode transistor 21′, E-mode transistor 41, and the III-N diode 22 are mounted inside the single package and connected as follows. Referring to FIG. 10, electrical connectors 37′, 38′, 39, and 52-55, which can be single or multiple wire bonds, are used to electrically connect portions of the package, III-N D-mode transistor 21′, E-mode transistor 41, and III-N diode 22 to one another. The III-N D-mode transistor 21′ and the III-N diode 22 are both mounted inside the package with their respective insulating or semi-insulating substrates or their respective conducting or semi-conducting substrates in contact with the package base 23, while the E-mode transistor 41 is mounted on an insulating spacer, and the side of the spacer opposite the E-mode transistor 41 contacts the package base 23. The insertion of an insulating spacer between the Si MOS device and the package base 23 may be required for a conventional Si MOS device, since a conventional Si MOS device tends to be a vertical device with its drain contact on an opposite side of the semiconductor body from its source electrode 42. The gate electrode 26′ of the III-N D-mode transistor 21′ and the e-mode transistor source electrode 42 (the source electrode of the Si MOS device) are both electrically connected to a conductive structural portion of the package, such as the package base 23, or can alternatively be electrically connected to source lead 93 of the package. Conductive connector 55 can be used to electrically connect e-mode transistor source electrode 42 to the package base 53 or to the source lead 93. The e-mode transistor gate electrode 43 (the gate electrode of the Si-MOS device) is electrically connected to the gate lead 91 of the package, such as by conductive connector 54. The e-mode transistor drain electrode 44 (the drain electrode of the Si MOS device) is electrically connected to the source contact 25′ of the III-N D-mode transistor 21′, such as by conductive connector 52. The drain electrode 27′ of the III-N D-mode transistor 21′ is electrically connected to the anode contact 28 of the III-N diode, such as by conductive connector 53. The drain electrode 27′ and anode contact 28 are both electrically connected to drain lead 94 of the package, such as by wire bonding one or both of these contacts/electrodes to the drain lead 94. The cathode contact 29 of the III-N diode is electrically connected to cathode lead 95 of the package, such as by conductive connector 39.
When a low-voltage III-N enhancement-mode device is used for E-mode transistor 41, the electrical connections are the same as those shown in FIG. 10. However, a low-voltage III-N enhancement-mode device can include an insulating or semi-insulating portion, such as an insulating or semi-insulating substrate, in which case the III-N enhancement-mode device can be mounted directly to the package base 23 with its insulating or semi-insulating portion in contact with the package base or between the package base 23 and the device channel.
Assembly 60 in FIG. 10, which includes the high-voltage III-N D-mode transistor 21′ and the low-voltage E-mode transistor 41 connected as shown, can operate similarly to or as a single high-voltage III-N E-mode transistor, i.e., a normally-off switch, with about the same threshold voltage as that of E-mode transistor 41 and a similar breakdown voltage to that of III-N D-mode transistor 21′. That is, an input voltage signal applied to the gate lead 91 relative to the package base 23 or source lead 93 can produce an output signal at the drain lead 94 that is the same as that produced when a single high-voltage III-N E-mode transistor replaces assembly 60 and is connected as shown in FIGS. 6 and 9. High-voltage III-N D-mode transistors and low-voltage E-mode transistors may both be fabricated more readily and manufactured more reproducibly than high-voltage III-N E-mode devices, so the electronic component 40 of FIG. 10 may be easier to manufacture than the electronic components 20 and 20′ of FIGS. 6 and 9, respectively.
A circuit schematic of a boost converter circuit utilizing the electronic component 20 of FIG. 5 is shown in FIG. 11, while FIG. 12 shows a circuit schematic of a boost converter circuit utilizing the electronic component 40 of FIG. 10. In FIGS. 11 and 12, node 191 is electrically connected to package lead 91 of electronic component 20 or 40, node 194 is electrically connected to package lead 94 of electronic component 20 or 40, node 195 is electrically connected to package lead 95 of electronic component 20 or 40, and node 193 is electrically connected to either package lead 93 or to the package base 23 of electronic component 20 or 40.
FIG. 13 shows a plot of the output voltage noise versus time as measured by the applicant at the output node 5 of the boost converter circuit of FIG. 12 during circuit operation. For this measurement, a high-voltage III-N D-mode heterojunction field effect transistor (HFET) was used for III-N D-mode transistor 21′, a low-voltage Si MOS E-mode device was used for E-mode transistor 41, a III-N diode was used for diode 22, and the circuit operating conditions were the same as those for FIG. 3. The transistor was switched at a switching speed of 200 Volts/nanosecond. As can be seen, the ringing 9 measured at the output node 5 was substantially smaller than the ringing at the output node measured in FIG. 3. The peak output voltage noise was less than 1 V, which is over 10 times less than the peak output voltage noise measured in FIG. 3. EMI could be reduced even further, and/or even higher switching speeds could be used without generating higher levels of EMI if electronic component 20 or 20′ from FIGS. 5 and 9, respectively, were used in place of electronic component 40, as in the circuit of FIG. 11.
The reduction in EMI observed for the circuit of FIG. 12, as compared to that illustrated in FIG. 3 for a boost-converter circuit which included a smaller number of discrete devices but in which the transistor and diode were individually packaged, may be attributed to reductions in parasitic resistances, capacitances, and/or inductances, these reductions being enabled by the use of a single package encasing all of the diodes and transistors. In the circuit of FIG. 1, in which the transistor 11 and diode 12 are individually packaged, the area of the circuit footprint as well as the length of the electrical connections is limited by the individual packages and may be too large, thus resulting in intolerably high parasitics and substantial EMI generation, even when III-N devices are used for transistor 11 and diode 12. The use of a single package encasing or encapsulating the rectifying device and transistors in the circuit of FIG. 12 can allow for a smaller circuit footprint as well as shorter electrical connectors, i.e., wire bonds, between electrodes and components, thereby reducing parasitic resistances, capacitances, and/or inductances. Hence, the electronic components 20, 20′, and 40 of FIGS. 6, 9, and 10, respectively, should be configured such that parasitic resistances, capacitances, and inductances are minimized, i.e., they should be configured such that the area of the footprint as well as the lengths of the electrical connectors are minimized. For electronic component 40 of FIG. 10, when a Si MOS device is used for E-mode transistor 41, it is also preferable for the Si MOS device to have as small a drain area (as measured parallel to a main surface of the package base 23) as possible, since the large drain-to-ground capacitance, resulting from the drain being separated from the package base 23 only by an insulating spacer, can further contribute to EMI in the circuit. Furthermore, since the electronic components 20 and 20′ of FIGS. 6 and 9, respectively, include a smaller number of discrete devices than electronic component 40 in FIG. 10, and all of the diodes and transistors in electronic components 20 and 20′ can be mounted to the package base 23 without requiring an insulating shim, EMI produced by a circuit using electronic component 20 or 20′ could be even smaller than that produced by the same circuit in which electronic component 20 or 20′ is replaced by electronic component 40, and/or higher switching speeds could be used without generating higher levels of EMI.
FIGS. 14 and 15 show plots of the efficiency 121 and power loss 122 versus output power for the boost converter of FIG. 12, which includes electronic component 40 of FIG. 10. Electronic component 40 included a high-voltage III-N depletion-mode HEMT, a low-voltage enhancement-mode Si MOS transistor, and a III-N diode. For the measurements of both FIGS. 14 and 15, voltage was converted from 200V to 400V, i.e., the conversion ratio was 1:2. For the measurement of FIG. 14, the circuit was operated at a frequency of 100 kHz, while for the measurement of FIG. 15, the circuit was operated at a frequency of 1 MHz. As seen in FIG. 14, at 100 kHz the boost converter exhibits an efficiency greater than 97.8% at all output powers between about 50 W and 700 W, with a peak efficiency greater than about 99%. As seen in FIG. 15, at 1 MHz the boost converter exhibits an efficiency greater than 91.8% at all output powers between about 50 W and 700 W, with a peak efficiency greater than about 97.8%.
A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the techniques and devices described herein. Accordingly, other implementations are within the scope of the following claims.

## Claims

1. A method of forming an electronic component, comprising:
providing a pair of transistors, wherein a first transistor of the pair of transistors is a III-N transistor;
providing a rectifying device;
enclosing the pair of transistors and the rectifying device in a single package;
electrically connecting a gate electrode of the III-N transistor to a first lead of the single package or to a conductive structural portion of the single package,
electrically connecting a drain electrode of the III-N transistor to a second lead of the single package and to a first electrode of the rectifying device, and
electrically connecting a second electrode of the rectifying device to a third lead of the single package.

2. The method of claim 1, wherein the III-N transistor is a field-effect transistor.

3. The method of claim 1, wherein the III-N transistor is a high voltage switching transistor.

4. The method of claim 1, wherein a second transistor of the pair of transistors is an enhancement-mode device.

5. The method of claim 1, wherein the rectifying device is provided as a III-N rectifying device.

6. The method of claim 5, wherein the III-N rectifying device is a III-N diode, the first electrode is an anode electrode, and the second electrode is a cathode electrode.

7. The method of claim 6, wherein the III-N transistor is a lateral device comprising an insulating or semi-insulating portion, and the insulating or semi-insulating portion is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N transistor and the conductive structural portion of the single package.

8. The method of claim 7, wherein the insulating or semi-insulating portion is an insulating or semi-insulating substrate.

9. The method of claim 6, wherein the III-N transistor is a lateral device comprising a conducting or semi-conducting substrate, and an insulating or semi-insulating III-N layer is between the conducting or semi-conducting substrate and a channel of the III-N transistor, wherein the conducting or semi-conducting substrate is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N transistor and the conductive structural portion of the single package.

10. The method of claim 9, wherein the conducting or semi-conducting substrate is a semi-conducting silicon substrate.

11. The method of claim 6, wherein the III-N transistor and the III-N diode are on a common substrate.

12. The method of claim 6, wherein the III-N diode is a lateral device comprising a conducting or semi-conducting substrate, and an insulating or semi-insulating III-N layer is between the conducting or semi-conducting substrate and a channel of the III-N diode, wherein the conducting or semi-conducting substrate is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N diode and the conductive structural portion of the single package.

13. The method of claim 12, wherein the conducting or semi-conducting substrate is a semi-conducting silicon substrate.

14. The method of claim 6, wherein the III-N diode is a lateral device comprising an insulating or semi-insulating portion, and the insulating or semi-insulating portion is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N diode and the conductive structural portion of the single package.

15. The method of claim 14, wherein the insulating or semi-insulating portion is an insulating or semi-insulating substrate.

16. The method of claim 1, wherein the III-N transistor is a first III-N transistor and the rectifying device is provided as a second III-N transistor.

17. The method of claim 16, wherein the first III-N transistor or the second III-N transistor is a lateral device comprising an insulating or semi-insulating portion, and the insulating or semi-insulating portion is mounted directly to the conductive structural portion of the single package without an insulating spacer between the first III-N transistor and the conductive structural portion of the single package or between the second III-N transistor and the conductive structural portion of the single package.

18. The method of claim 17, wherein the insulating or semi-insulating portion is an insulating or semi-insulating substrate.

19. The method of claim 16, wherein the first III-N transistor or the second III-N transistor is a lateral device comprising a conducting or semi-conducting substrate, and an insulating or semi-insulating III-N layer between the conducting or semi-conducting substrate and a channel of the first III-N transistor or the second III-N transistor, wherein the conducting or semi-conducting substrate is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the first III-N transistor and the conductive structural portion of the single package or between the second III-N transistor and the conductive structural portion of the single package.

20. The method of claim 19, wherein the conducting or semi-conducting substrate is a semi-conducting silicon substrate.

21. The method of claim 16, wherein the first III-N transistor and the second III-N transistor are formed on a common substrate.

22. The method of claim 1, further comprising connecting a source electrode of a second transistor of the pair of transistors to the conductive structural portion of the single package or to a source lead of the single package.

23. The method of claim 1, wherein the III-N transistor is a III-N depletion-mode transistor, and a second transistor of the pair of transistors is an enhancement-mode transistor, the enhancement-mode transistor comprising an e-mode transistor source electrode, an e-mode transistor gate electrode, and an e-mode transistor drain electrode, wherein the e-mode transistor source electrode is electrically connected to the conductive structural portion of the single package or to a source lead of the single package, the e-mode transistor drain electrode is electrically connected to a source electrode of the III-N depletion-mode transistor, and the e-mode transistor gate electrode is electrically connected to the first lead of the single package.

24. The method of claim 23, wherein the III-N depletion-mode transistor is a high-voltage switching transistor, and the enhancement-mode transistor is a low-voltage transistor.

25. The method of claim 24, wherein the enhancement-mode transistor is a Si MOS device.

26. The method of claim 1, wherein the electronic component is a part of a voltage converter.

27. A method of forming an electronic component, comprising:
providing a III-N depletion-mode transistor;
providing an enhancement-mode transistor;
providing a rectifying device;
enclosing each of the III-N depletion-mode transistor, the enhancement-mode transistor, and the rectifying device in a single package, and
electrically connecting a gate electrode of the III-N depletion-mode transistor to a source electrode of the enhancement-mode transistor, electrically connecting a source electrode of the III-N depletion-mode transistor to a drain electrode of the enhancement-mode transistor, electrically connecting a drain electrode of the III-N depletion-mode transistor to a second lead of the single package and to a first electrode of the rectifying device, and electrically connecting a second electrode of the rectifying device to a first lead of the single package.

28. The method of claim 27, wherein the enhancement-mode transistor is a Si MOS device.

29. The method of claim 28, wherein the rectifying device comprises a III-N transistor.

30. The method of claim 27, wherein the rectifying device is a III-N diode, the first electrode is an anode electrode, and the second electrode is a cathode electrode.

31. The method of claim 27, wherein the electronic component is a part of a voltage converter.

32. The method of claim 27, wherein the III-N depletion-mode transistor and the rectifying device are on a common substrate.

33. A method of forming an electronic component, comprising:
providing a III-N depletion-mode transistor;
providing an enhancement-mode transistor;
providing a rectifying device; and
enclosing each of the III-N depletion-mode transistor, the enhancement-mode transistor, and the rectifying device in a single package, the single package comprising a first lead and a second lead; wherein
a gate electrode of the III-N depletion-mode transistor is electrically connected to the first lead of the single package or to a conductive structural portion of the single package, a source electrode of the III-N depletion-mode transistor is electrically connected to a drain electrode of the enhancement-mode transistor, a drain electrode of the III-N depletion-mode transistor is electrically connected to a first electrode of the rectifying device, and a second electrode of the rectifying device is electrically connected to the second lead of the single package.

34. The method of claim 33, wherein the drain electrode of the III-N depletion-mode transistor is also electrically connected to a third lead of the single package.

35. The method of claim 33, wherein the rectifying device comprises a diode, and the first electrode of the rectifying device comprises an anode.

36. The method of claim 33, wherein the electronic component is a part of a voltage converter.

37. The method of claim 33, wherein the III-N depletion-mode transistor and the rectifying device are on a common substrate.

38. The method of claim 33, wherein the drain electrode of the III-N depletion-mode transistor is electrically connected to the second lead of the single package.