# Patent

## Title
Semiconductor device having first and second portions with opposite conductivity type which contact an electrode

## Abstract

A semiconductor device having first and second portions with opposite conductivity types. There are first through fourth layers in the semiconductor device. A peak value of the impurity concentration of the fourth layer is higher than the peak value of the impurity concentration of the second layer and lower than the peak value of the impurity concentration of a first portion of the third layer. The fourth layer includes a third portion located on the first portion and a fourth portion which is located on the second portion. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.

## Background
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a power semiconductor device.
2. Description of the Background Art
A power semiconductor device includes a high breakdown voltage power module which can withstand a voltage of, for example, 600 V or higher. Such a power module may have a diode formed thereon.
For example, Japanese Patent Laying-Open No. 02-066977 discloses a diode having a pn junction formed by an n− layer adjacent to a p layer, in which an n+ region and a p+ region are located on the surface of then layer opposite to the p+ layer. In addition, an n buffer layer is located between the n− and the region including the n+ region and the p+ region. This document discloses that the p+ region has an effect of reducing a reverse recovery current of the diode and also shortening the reverse recovery time. It also discloses that the n buffer layer can prevent the depletion layer from extending to the n− layer during application of the reverse voltage, which allows a reduction in thickness of the n− layer, with the result that the reverse recovery characteristics of the high breakdown voltage diode can be improved.
Furthermore, for example, Japanese Patent Laying-Open No. 08-172205 discloses a diode including an n− semiconductor layer formed on one main surface of an n-type semiconductor substrate; an n+ cathode region formed on the surface layer of the n− semiconductor layer; a trench extending from the surface of the n+ cathode region through the n− semiconductor layer to the n-type semiconductor substrate; a gate electrode filling the trench with a gate oxide film interposed therebetween; an insulation film formed on the gate electrode; a cathode electrode in contact with the surface of the n+ cathode region interposed between the trenches; a p+ anode region formed on a part of the surface layer of the n-type semiconductor substrate, and an anode electrode in contact with the p+ anode region. According to this document, as the gate electrode is applied with a voltage which is negative with respect to the cathode electrode, a breakdown of the diode and burning of the switching transformer can be prevented when an overcurrent flows through the diode.
With regard to the power diode, it is difficult to solve the problems involved in both of the tasks of decreasing a forward voltage drop (VF) and suppressing the oscillation at the time of recovery (reverse recovery). For example, Japanese Patent Laying-Open No. 02-066977 as described above merely discloses that the recovery characteristics can be improved by providing a p+ region, but fails to disclose how to configure the p+ region for allowing the above-described problems to be solved in a balanced manner.
Furthermore, it may be desirable to especially decrease VF depending on the use of the power diode. However, according to the technique disclosed in Japanese Patent Laying-Open No. 08-172205 described above, the gate electrode is applied with a voltage that is negative with respect to the cathode electrode, which causes a problem of an increase in VF.
SUMMARY OF THE INVENTION
The present invention has been made in light of the above-described problems, and an object of the present invention is to provide a semiconductor device capable of decreasing VF and suppressing the oscillation at the time of recovery. Furthermore, another object of the present invention is to provide a semiconductor device capable of particularly decreasing VF.
A semiconductor device according to one aspect of the present invention includes first and second electrodes, and first to fourth layers. The first layer is located on the first electrode and has a first conductivity type. The second layer is located on the first layer and has a second conductivity type different from the first conductivity type. The third layer is located on the second layer. The second electrode is located on the third layer. The fourth layer is located between the second layer and the third layer, and has the second conductivity type. The third layer includes first and second portions. The first portion has the second conductivity type and has a peak value of an impurity concentration higher than the peak value of the impurity concentration in the second layer. The second portion has the first conductivity type. An area of the second portion accounts for not less than 20% and not more than 95% of a total area of the first and the second portions.
A semiconductor device according to another aspect of the present invention includes first and second electrodes, first to third layers, and a trench structure. The first layer is located on the first electrode and has a first conductivity type. The second layer is located on the first layer and has a second conductivity type different from the first conductivity type. The third layer is located on the second layer and has a first portion. The first portion has the second conductivity type and has a peak value of an impurity concentration higher than the peak value of the impurity concentration in the second layer. The second electrode is located on the third layer. The trench structure is located in the first portion and applied with an electric potential which is positive with respect to an electric potential of the second electrode.
The semiconductor device according to an aspect of the present invention allows a decrease in VF of a diode and also allows suppression of the oscillation at the time of recovery.
The semiconductor device according to another aspect of the present invention allows a decrease in VF of the diode.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view schematically showing the configuration of a diode as a semiconductor device according to the first embodiment of the present invention.
FIG. 2 is a graph schematically showing impurity profiles CA and CB along arrows DA and DB, respectively, in FIG. 1.
FIG. 3 is a diagram showing a circuit used for each simulation for the diode in FIG. 1 and a comparative example thereof.
FIG. 4 is a graph showing an example of the simulations for the recovery characteristic waveform with regard to each diode in FIG. 1 and in the comparative example.
FIG. 5 is a graph showing an example of a relationship JA1 between a voltage VAK and a current density JA in the forward direction of the diode in FIG. 1, and an example of a relationship JA0 between a voltage VAK and a current density JA in the forward direction of the diode in the comparative example.
FIG. 6 is a diagram showing an example of the cross point at which relationships between voltage VAK and current density JA cross each other in accordance with the temperature change.
FIG. 7 is a graph schematically showing an example of a relationship JR1 between a voltage VRA and a current density JR in the reverse direction of the diode in FIG. 1, and an example of a relationship JR0 between voltage VRA and current density JR in the reverse direction of the diode in the comparative example.
FIG. 8 is a graph schematically showing an electric field intensity E and a carrier concentration CC at a point PB in FIG. 4.
FIG. 9 is a graph showing an example of the relationship between each of a surge voltage Vsurge and VF at the rated current density in the diode in FIG. 1 and the ratio of a width WP of a p layer to a width WC of a cathode portion.
FIG. 10 is a graph showing an example of the recovery characteristics of the diode in the case where width WP of the p layer accounts for 0% of width WC of the cathode portion in FIG. 1.
FIG. 11 is a graph showing an example of the recovery characteristics of the diode in the case where width WP of the p layer accounts for 10% of width WC of the cathode portion in FIG. 1.
FIG. 12 is a graph showing an example of the recovery characteristics of the diode in the case where width WP of the p layer accounts for 20% of width WC of the cathode portion in FIG. 1.
FIG. 13 is a graph showing an example of the recovery characteristics of the diode in the case where width WP of the p layer accounts for 50% of width WC of the cathode portion in FIG. 1.
FIG. 14 is a graph showing an example of the relationship between each of a maximum reverse voltage VRRM, VF at the rated current density and surge voltage Vsurge in the diode in FIG. 1, and a ratio C1/C3 of peak values C1 and C3 of the impurity concentration in FIG. 2.
FIG. 15 is a graph showing an example of a characteristic curve EREC1 illustrating trade-off characteristics between a recovery loss EREC and VF at the rated current density of the diode in FIG. 1 in the case where a peak value C2 is higher than C1 in FIG. 2; an example of a characteristic curve EREC2 illustrating the relationship between recovery loss EREC and VF at the rated current density of the diode in FIG. 1 in the case where peak value C1 is equal to peak value C2 in FIG. 2; and an example of a characteristic curve EREC0 illustrating the relationship between recovery loss EREC and VF at the rated current density of the diode in the comparative example.
FIG. 16 is a graph showing an example of the relationship between VF at the rated current density in the diode in FIG. 1 and a ratio C2/C1 of peak values C1 and C2 of the impurity concentration in FIG. 2.
FIG. 17 is a graph showing an example of a hole concentration CCh1 and an electron concentration CCe1 along an arrow DA (FIG. 1) in the ON state in the case where peak value C2 is higher than C1 in FIG. 2; and an example of a hole concentration CCh2 and an electron concentration CCe2 along arrow DA (FIG. 1) in the ON state in the case where peak value C1 is equal to C2 in FIG. 2.
FIG. 18 is a cross-sectional view schematically showing the configuration of the diode as a semiconductor device in the second embodiment of the present invention.
FIG. 19 is a cross-sectional view schematically showing the configuration of a modification of the diode in FIG. 18.
FIG. 20 is a cross-sectional view schematically showing the configuration of the diode as a semiconductor device in the third embodiment of the present invention.
FIG. 21 is a cross-sectional view schematically showing the configuration of the first modification of the diode in FIG. 20.
FIG. 22 is a cross-sectional view schematically showing the configuration of the second modification of the diode in FIG. 20.
FIG. 23 is a graph showing an example of carrier concentrations CC3 and CC0 in the ON state in each diode in FIG. 20 and in the comparative example.
FIG. 24 is a graph showing an example of a relationship JA3 between voltage VAK and current density JA in the forward direction of the diode in FIG. 20; and an example of a relationship JA0 between voltage VAK and current density JA in the forward direction of the diode in the comparative example.
FIG. 25 is a graph showing an example of the relationship between a trench depth y in FIG. 20 and VF at the rated current density.
FIG. 26 is a cross-sectional view showing the configuration of the diode in the comparative example.



DESCRIPTION OF THE PREFERRED EMBODIMENTS
An embodiment of the present invention will be hereinafter described with reference to the drawings.
(First Embodiment)
Referring to FIG. 1, a diode as a semiconductor device according to the present embodiment includes an anode electrode 5 (the first electrode), a p layer 3 (the first layer), an n− drift layer 1 (the second layer), an n layer 15 (the fourth layer), a cathode layer CLa (the third layer), and a cathode electrode 4 (the second electrode). For example, p layer 3, n− drift layer 1, n layer 15, and cathode layer CLa are, for example, made of Si to which conductive impurities are added.
P layer 3 is located on (in the figure, immediately below) anode electrode 5 and has a p-type (the first conductivity type).
N− drift layer 1 is located on (in the figure, immediately below) p layer 3 to have a thickness of a dimension t3. Furthermore, n− drift layer 1 has a conductivity type different from a p-type, that is, an n-type (the second conductivity type).
Cathode layer CLa is located on (in the figure, below) n− drift layer 1 with n layer 15 interposed therebetween. Cathode layer CLa is in a rectangular shape having a width Wc in plan view taken at right angles to the width direction. Cathode layer CLa also includes an n+ region 2 (the first portion) having an n-type and a p region 16 (the second portion) having a p-type.
Furthermore, in the present embodiment, n+ region 2 and p region 16 are each in a rectangular shape having a width Wn and a width Wp, respectively, in plan view. Cathode layer CLa, n+ region 2 and p region 16 are identical in length (at right angles to the width) in plan view. Width Wc, width Wn and width Wp establish the relationship of Wc=Wn+Wp. Consequently, the ratio of the area of n+ region 2 to the area of p region 16 in plan view is Wn:Wp. Furthermore, cathode layer CLa is formed such that the following expression is satisfied.

0.2≦Wp/Wc≦0.95

Accordingly, the area of p region 16 accounts for not less than 20% and not more than 95% of the total area of n+ region 2 and p region 16 on n layer 15.
It is to be noted that a dimension t1 in the figure is equivalent to each thickness of n+ region 2 and p region 16 which is, for example, 0.2 to 5 μm. Furthermore, a dimension tsub is equivalent to the entire thickness of the semiconductor layer.
N layer 15 is located between n− drift layer 1 and cathode layer CLa, and has an n-type (the second conductivity type). Furthermore, n layer 15 has a thickness of a dimension obtained by subtracting dimension t1 from a dimension t2 in the figure, which is 1 to 50 μm, for example. N layer 15 has an n region 15n (the third portion) located on n+ region 2 and an n region 15p (the fourth portion) located on p region 16. In addition, n layer 15 substantially contains only the n-type conductive impurities but does not substantially contain the p-type conductive impurities.
Cathode electrode 4 is located on cathode layer CLa.
Referring to FIG. 2, impurity profiles CA and CB each show a distribution of the impurity concentration in depths DA and DB, respectively (FIG. 1). N+ region 2 has a peak value C4 of an impurity concentration higher than a peak value C0 of the impurity concentration in n− drift layer 1, and also higher than a peak value C3 of the impurity concentration in p region 16. The ratio of a peak value C1 of the impurity concentration in n region 15p to peak value C3 of the impurity concentration in p region 16 is not less than 0.001 and not more than 0.1. N layer 15 has peak values C1 and C2 of the impurity concentration higher than peak value C0 of the impurity concentration in n− drift layer 1 and lower than peak value C4 of the impurity concentration in n+ region 2 of cathode layer CLa.
For example, the surface concentration of n+ region 2 is 1×1017 to 1×1021 cm−3, and the surface concentration of p region 16 is 1×1016 to 1×1021 cm−3. Furthermore, peak values C1 and C2 of the impurity concentration in n layer 15 each are 1×1016 to 1×1020 cm−3.
In the present embodiment, n layer 15 substantially contains only the n-type conductive impurities, but does not substantially contain the p-type conductive impurities. Thus, impurity profile CB within a section between dimensions t1 and t2 in FIG. 2 shows the concentration of the n-type conductive impurities. In the case where n region 15p also substantially contains the p-type conductive impurities in addition to the n-type conductive impurities, the impurity concentration means an effective impurity concentration, that is, a concentration difference between the p-type and n-type conductive impurities.
The diode according to a comparative example will then be described.
Referring to FIG. 26, the diode in the comparative example has a cathode layer CLb including n+ region 2, in place of cathode layer CLa according to the present embodiment. N layer 15 is located immediately on cathode layer CLb. The following two problems may be caused in this comparative example.
As to the first problem, during the recovery operation, it is more likely that the hole concentration remaining on the side close to n+ region 2 and n layer 15 decreases and a depletion layer extends. The oscillation phenomenon occurs at the instant when this depletion layer reaches n layer 15. Consequently, the safe operating area (SOA) tolerance and the recovery tolerance are reduced.
As to the second problem, in order to address the oscillation phenomenon during recovery, it is necessary to delay extension of the depletion layer from the junction of p layer 3/n− drift layer 1 serving as a main junction toward the cathode side. This requires an increase in dimension t3 corresponding to the thickness of the n− drift layer in the present comparative example. As a result, it becomes difficult to improve the trade-off characteristics between a decrease in VF and a recovery loss (EREC).
In the comparative example, dimension t3 is set to be relatively short which causes the above-described first problem, and dimension t3 is set to be relatively long which causes the above-described second problem. Thus, in the present comparative example, it is difficult to achieve an improvement of the trade-off characteristics between a decrease in VF and recovery loss, and also achieve an improvement of the SOA tolerance by suppression of the oscillation phenomenon and the like.
In contrast, the present embodiment allows a decrease in VF and also allows an improvement of the SOA tolerance while ensuring a high breakdown voltage. In other words, it becomes possible to decrease VF, improve the maximum reverse voltage, and suppress the oscillation at the time of recovery.
Referring to FIG. 3, in order to verify the above-described operations and effects, simulations were performed for the circuit including a diode rated at 3300V class as an example of the semiconductor device according to the present embodiment. This circuit includes a diode DD, a transistor TR corresponding to an IGBT (Insulated Gate Bipolar Transistor), coils LM, LAK and LCE, resistances RL, RAK, RCE, and RG, power supplies VC and VG, and a current source ION. Coil LM is provided for a parasitic inductance, resistance RG is provided for the gate resistance of the IGBT, and power supply VG is provided for the gate voltage of the IGBT. Furthermore, coils LAK and LCE are provided for a wiring impedance for providing matching between the measured results and the simulation results. Resistances RL, RAK and RCE are provided for a wiring-related resistance for providing matching between the measured results and the simulation results. The simulation results will be hereinafter described.
Referring to FIG. 4, with regard to the present example and the comparative example, simulations were performed for the recovery characteristic waveform, that is, changes over time of a voltage VAK and a current density JA during the recovery. The figure shows a voltage VAK1 and a current density JA1 in the case of the diode in the present example (FIG. 1), and shows a voltage VAK0 and a current density JA0 in the case of the diode in the comparative example (FIG. 26). In the present example, the oscillation occurring during the recovery can be suppressed as compared to the case in the comparative example. Accordingly, a surge voltage Vsurge corresponding to a peak voltage of voltage VAK which is not less than 5000V in the comparative example can be suppressed approximately to 3000V in the present example.
It is to be noted that the simulation conditions are set such that coil LM is 12 μm, power supply VC is 1700V, a rated current density JAR is 90 A/cm2, and a current JF in the forward direction is JAR/10, and a temperature is 298K.
Referring to FIG. 5, simulations were performed for the characteristics of current density JA-voltage VAK. The figure shows a relationship JA1 in the case of the diode in the example (FIG. 1) according to the present embodiment, and a relationship JA0 in the case of the diode in the comparative example (FIG. 26). Furthermore, VF shows voltage VAK at the time when current density JA corresponds to rated current density JAR=90 A/cm2. According to the present example, VF can be decreased as compared to the case in the comparative example.
In addition, the characteristics of current density JA-voltage VAK generally vary with temperature. The characteristics of current density JA-voltage VAK at temperatures of 25 C.° and 12 C.° are as shown in FIG. 6, for example. It is to be noted that the point at which the characteristic curves cross each other is assumed to be a cross point CP.
Referring to FIG. 7, simulations were performed for the characteristics in the reverse direction (current density JR-voltage VRA). The figure shows a relationship JR1 in the case of the diode in the present example (FIG. 1) and a relationship JR0 in the case of the diode in the comparative example (FIG. 26). Furthermore, a maximum reverse voltage VRRM is assumed to be a voltage VRA at the time when current density JR=1×10−2 A/cm2. According to the present example, maximum reverse voltage VRRM can be increased as compared to the case in the comparative example.
In the case where n layer 15 substantially contains p-type conductive impurities, maximum reverse voltage VRRM is decreased. Conversely, in the case where n layer 15 substantially contains only the n-type conductive impurities, maximum reverse voltage VRRM is increased.
Mainly referring to FIG. 8, the distributions of an electric field intensity E and a carrier concentration CC in the depth direction of the device at a point PB (FIG. 4) were analyzed by simulation. In the figure, the horizontal axis corresponds to a depth along an arrow DA (FIG. 1). Furthermore, the figure shows a hole concentration CCh1, an electron concentration CCe1 and an electric field intensity E1 in the case of the diode in the present example (FIG. 1), and also shows a hole concentration CCh0, an electron concentration CCe0 and an electric field intensity E0 in the case of the diode in the comparative example (FIG. 26). According to the configuration in the present example (FIG. 1), when holes are injected from p region 16 located close to the cathode side during the recovery phenomenon, hole concentration CCh1 on the cathode side is improved as compared to the case of hole concentration CCh0 in the comparative example. Consequently, as indicated by an arrow RE in the figure, the electric-field relaxation phenomenon occurs in which electric field intensity E on the cathode side is reduced.
Mainly referring to FIGS. 9-13, in order to examine the correlation (FIG. 9) of each of VF (FIG. 5) and surge voltage Vsurge (FIG. 4) with a width ratio Wp/Wc (FIG. 1), simulations (for example, FIGS. 10-13) were performed for the recovery characteristic waveform (changes over time of a current IA and voltage VAK during recovery) under various ratios Wp/Wc.
As a result, in the case where width Wp accounts for 20% or more of width Wc, that is, in the case where the area of p region 16 accounts for 20% or more of the total area of n+ region 2 and p region 16 (FIG. 1), the oscillation is suppressed during the recovery, which allows surge voltage Vsurge to be remarkably suppressed to 3300V or lower that is a rated voltage.
Furthermore, when width Wp exceeds 95% of width Wc, VF increases rapidly which may affect the operation of the diode. Conversely, as width Wp is set to account for 95% or less of width Wc, that is, as the area of p region 16 is set to account for 95% or less of the total area of n+ region 2 and p region 16, VF is remarkably suppressed.
Mainly referring to FIG. 14, the correlation of each of maximum reverse voltage VRRM, VF and surge voltage Vsurge with the ratio C1/C3 of peak values C1 and C3 (FIG. 2) of the impurity concentration was examined by simulation. In light of the results shown in FIG. 9, width Wp was set to account for 20% of width Wc such that the oscillation during recovery might be suppressed.
The results of the simulations show that ratio C1/C3 is set to be 1×10−1 or lower, to thereby allow surge voltage Vsurge to be remarkably suppressed to 3300V or lower which corresponds to a rated voltage.
The results also show that ratio C1/C3 is set to be 1×10−3 or more, to thereby allow maximum reverse voltage VRRM (FIG. 7) to be maintained at 3300V or more which corresponds to a rated voltage. It is considered that this is because ratio C1/C3 is set to be 1×10−3 or more, which allows suppression of extension of the depletion layer from the junction of p layer 3/n− drift layer 1 serving as a main junction toward the cathode side.
Referring to FIG. 15, simulations were performed to examine the trade-off characteristics between recovery loss EREC (mJ/A·pulse) and VF (V). The figure shows a characteristic curve EREC1 in the case where peak values C1 and C2 of the impurity concentration (FIG. 2) satisfy the relation of C2<C1, and a characteristic curve EREC2 in the case where peak values C1 and C2 satisfy the relation of C2=C1. The figure also shows a characteristic curve EREC0 in the case of the diode in the comparative example (FIG. 26).
The results show that, as compared to the configuration (characteristic curve EREC0) in the comparative example (FIG. 26), the configuration (characteristic curves EREC1 and EREC2) in the present example (FIG. 1) serves to achieve an improvement in the trade-off relationship between recovery loss EREC and VF, and also achieve a further improvement particularly in the case where peak values C1 and C2 of the impurity concentration satisfy the relation of C2>C1. In other words, it is found that the above-described trade-off relationship can be improved while maintaining dimension t3 (FIGS. 1 and 26) in terms of the SOA, that is, without the need to decrease dimension t3.
It is to be noted that VF decreases with an increase in ratio C2/C1 of the peak values of the impurity concentration, as shown in FIG. 16.
FIG. 17 shows the simulation results of carrier concentration CC in the ON state, that is, in the case where current density JA is equal to rated current density JAR (FIG. 5). In the figure, the horizontal axis corresponds to a depth along arrow DA (FIG. 1). Furthermore, the figure shows hole concentration CCh1 and electron concentration CCe1 in the case where peak values C1 and C2 of the impurity concentration satisfy the relation of C2>C1, and also shows a hole concentration CCh2 and an electron concentration CCe2 in the case where peak values C1 and C2 of the impurity concentration satisfy the relation of C2=C1.
The results described above show that, when peak values C1 and C2 satisfy the relation of C2>C1, the carrier concentration near the cathode is increased in the ON state. It is considered that this increase in carrier concentration causes a decrease in VF (FIG. 16), with the result that the trade-off relationship between recovery loss EREC and VF (FIG. 15) is improved.
According to the present embodiment, VF is decreased, the oscillation at the time of recovery is suppressed, and maximum reverse voltage VRRM is improved, which will be hereinafter described in detail.
According to the diode structure (FIG. 1) in the present embodiment, when holes are injected from p region 16 during the recovery phenomenon, hole concentration CCh1 (FIG. 8) on the cathode side is increased above hole concentration CCh0 in the case of the diode structure (FIG. 26) according to the comparative example. Consequently, in the present embodiment, the electric field on the cathode side is relaxed as indicated by arrow RE (FIG. 8) during the recovery, as compared to the case in the comparative example, which allows suppression of extension of the depletion layer from the junction of p layer 3/n− drift layer 1 serving as a main junction toward the cathode side. Accordingly, the oscillation phenomenon during the recovery is suppressed as shown in FIG. 4, resulting in improvement of the SOA tolerance of the diode. Thus, according to the diode of the present embodiment (FIG. 1), the oscillation can be suppressed by injecting holes from p region 16 during the recovery phenomenon to thereby cause electric-field relaxation (to suppress extension of the depletion layer). Consequently, thickness t3 of n− drift layer 1 can be reduced, and thus, the trade-off characteristics between recovery loss EREC and VF can be improved as shown in FIG. 15.
The proportion of the area of p region 16 occupying the area of cathode layer CLa in FIG. 1 (ratio Wp/Wc between widths Wp and Wc in FIG. 1) serves as an important parameter for facilitating hole injection from the cathode side during the recovery operation. In other words, as shown in FIG. 4, VF and surge voltage Vsurge greatly vary significantly depending on this parameter. According to the present embodiment, as the following expression (1) is satisfied, an excellent operation of the diode can be ensured while suppressing the oscillation at the time of recovery.

20%≦ratio Wp/Wc≦95%  (1)

In the above expression (1), the upper limit value, 95%, represents a condition for sufficiently decreasing VF (FIG. 9) for practical application. Furthermore, the lower limit value, 20%, represents a condition for remarkably suppressing a waveform surge in the VAK waveform (FIGS. 10 to 13), that is, Vsurge (FIG. 9), to not more than the value of the breakdown voltage class (3300V in the above-described simulations). As expression (1) is satisfied in this way, VF is decreased and the oscillation during recovery is suppressed.
As described above, ratio C1/C3 (FIG. 14) of peak values C1 and C3 (FIG. 2) of the impurity concentration satisfies the following expression (2) while decreasing VF and suppressing the oscillation at the time of recovery, which allows maximum reverse voltage VRRM to be improved.

0.001≦ratio C1/C3≦0.1  (2)

In the above expression (2), the upper limit value, 0.1, represents a condition for suppressing Vsurge to not more than the value of the breakdown voltage class (3300V in the above-described simulations) by injecting sufficient holes from p region 16 of cathode layer CLa. Furthermore, the lower limit value, 0.001, represents a condition for preventing a decrease in maximum reverse voltage VRRM resulting from the fact that the depletion layer extending toward the cathode side from the junction of p layer 3/n− drift layer 1 serving as a main junction during application of a reverse bias reaches p region 16.
Furthermore, peak values C1 and C2 of the impurity concentration (FIG. 2) satisfy the following expression (3), which causes an increase in carrier concentration CC on the cathode side (FIG. 17) at the time when the diode is in the ON state.

C2>C1  (3)

As described above, the increased carrier concentration CC results in a decrease in VF (FIG. 16), and accordingly, the trade-off characteristics between recovery loss EREC and VF (FIG. 15) is improved.
In the case where the above-described relations (1) to (3) are satisfied, a diode having particularly excellent characteristics can be achieved as compared to the diode in the comparative example (FIG. 26).
(Second Embodiment)
Referring to FIG. 18, a diode as a semiconductor device according to the present embodiment includes an n-type diffusion layer 17 (the fifth layer), a trench structure 26a, a p+ diffusion layer 18, an interlayer dielectric film 19, insulation films 20 and 23, a silicide layer 21a, and a barrier metal layer 22.
N-type diffusion layer 17 is located between a p layer 3 and an n− drift layer 1, and has an n-type. Trench structure 26a has a trench extending through p layer 3 and n-type diffusion layer 17 and also has a gate electrode 14 filling the trench with a gate insulation film 12 interposed therebetween. Gate electrode 14 is electrically insulated from an anode electrode 5 by interlayer dielectric film 19. Silicide layer 21a serves to implement a low contact resistance with an Si diffusion layer and is, for example, made of TiSi2, CoSi or WSi. Barrier metal layer 22 is, for example, made of TiN. Interlayer dielectric film 19 is made of a silicate glass film to which boron, phosphorus and the like are added.
It is to be noted that since the configurations other than those described above are almost the same as the configuration according to the above-described first embodiment, the same or corresponding components are designated by the same reference characters, and description thereof will not be repeated.
The method for manufacturing the diode according to the present embodiment will then be described.
First, a substrate which is a thick n− drift layer 1 is prepared. The impurity concentration of n− drift layer 1 is determined depending on the breakdown voltage class and is set to be 1×1012 to 1×1015 cm−3 in 600 to 6500V class, for example.
Then, p layer 3 is formed on the surface of this substrate with n-type diffusion layer 17 interposed therebetween. For example, p layer 3 has a peak concentration of 1×1016 to 1×1018 cm−3 and a diffusion depth of 1 to 4 μm. The peak concentration of the impurities in n-type diffusion layer 17 is equal to or higher than the concentration of the impurities in n− drift layer 1 and is equal to or lower than the peak value of the impurity concentration in p layer 3. Then, p+ diffusion layer 18 is formed on the surface of the substrate on which p layer 3 and n-type diffusion layer 17 are formed. P+ diffusion layer 18 has, for example, a surface concentration of 1×1018 to 1×1020 cm−3 and a diffusion depth of approximately 0.5 μm. Trench structure 26a and a cathode layer CLa are then formed.
It is to be noted that p+ diffusion layer 18 may be formed after trench structure 26a is formed.
The diode according to the present embodiment is used such that the electric potential lower than that of a cathode electrode 4 is applied to gate electrode 14 when the reverse voltage is applied to the diode. For the purpose of this, gate electrode 14 is electrically connected to anode electrode 5, for example. In addition, in the case where the electric potential of cathode electrode 4 is rendered positive when a reverse voltage is applied to the diode, gate electrode 14 may be grounded.
In this case, the simulation results show that a current density JA at a cross point CP (FIG. 6) can be decreased. Accordingly, the current density at cross point CP can be decreased below the current density at which the diode is overloaded. In this case, since the overloaded diode exhibits a positive temperature coefficient at VF, the current concentration on the overloaded diode can be prevented.
Furthermore, the amount of hole injection from p layer 3 at the time when the device is turned on can be controlled by n-type diffusion layer 17.
Furthermore, trench structure 26a serves as a quasi-field plate structure, to facilitate extension of the depletion layer from the junction between p layer 3 and n-type diffusion layer 17, with the result that a maximum reverse voltage VRRM can be maintained. Also, as trench structure 26a is formed deeper than the interface between p layer 3 and n-type diffusion layer 17, maximum reverse voltage VRRM can be more reliably maintained.
Furthermore, according to the diode in the comparative example (FIG. 26), the trade-off characteristics between a recovery loss EREC and VF are controlled generally by adjusting the lifetime of carriers in n− drift layer 1. In contrast, according to the present embodiment, the concentration in p layer 3 is adjusted to control the trade-off characteristics and expand the controllable range of the trade-off characteristics, and thus, eliminating the lifetime adjusting process, to thereby allow simplification of the wafer process.
Referring to FIG. 19, a modification of the present embodiment will be described. The diode according to the present modification includes an n-type diffusion layer 17, a trench structure 27, a p+ diffusion layer 18, silicide layers 21a and 21b, and a barrier metal layer 22b. Trench structure 27 includes a trench extending through a p layer 3 and n-type diffusion layer 17 and also includes a gate electrode 14 filling the trench with a gate insulation film 12 interposed therebetween. In addition, gate electrode 14 is electrically connected to an anode electrode 5 and has the same electric potential as that of anode electrode 5.
According to the present modification, gate electrode 14 is applied with the same electric potential as that of anode electrode 5. Accordingly, when the voltage in the reverse direction is applied to the diode, the electric potential lower than that of cathode electrode 4 can be applied to gate electrode 14 without the need to control the electric potential of gate electrode 14 from outside the diode. Consequently, the effects similar to those in the present embodiment can be achieved.
(Third Embodiment)
Referring to FIG. 20, the diode as a semiconductor device according to the present embodiment includes an anode electrode 5 (the first electrode), a p layer 3 (the first layer), an n− drift layer 1 (the second layer), an n layer 15 (the fourth layer), a cathode layer CLb (the third layer), a cathode electrode 24 (the second electrode), a trench structure 26b, an interlayer dielectric film 19, insulation films 20 and 23, and a barrier metal layer 22.
P layer 3 is located on anode electrode 5 and has a p-type (the first conductivity type). N− drift layer 1 is located on p layer 3 and has a conductivity type different from the p-type, that is, an n-type (the second conductivity type).
Cathode layer CLb is located on n− drift layer 1 with n layer 15 interposed therebetween. Cathode layer CLb includes an n+ region 2 (the first portion) having an n-type and having a peak value of the impurity concentration higher than the peak value of the impurity concentration in n− drift layer 1.
N layer 15 is located between n− drift layer 1 and cathode layer CLb. N layer 15 having an n-type has a peak value of the impurity concentration higher than the peak value of the impurity concentration in n− drift layer 1, and also has a peak value of the impurity concentration lower than the peak value of the impurity concentration in n+ region 2.
Cathode electrode 24 is located on cathode layer CLb.
Trench structure 26b includes a trench extending through n+ region 2 and n layer 15 and also includes a gate electrode 14 filling the trench with gate insulation film 12 interposed therebetween. In other words, trench structure 26b is located in n+ region 2 and n layer 15.
Gate electrode 14 and cathode electrode 24 are connected to the positive terminal side and the negative electrode side, respectively, of a voltage source 30. Thus, trench structure 26b is configured such that the electric potential that is positive with respect to the electric potential of cathode electrode 24 may be applied.
It is to be noted that since the configurations other than those described above are almost the same as the configuration according to the above-described first embodiment, the same or corresponding components are designated by the same reference characters, and description thereof will not be repeated.
Furthermore, it may be possible to apply the structure having cathode layer CLa in place of the above-described cathode layer CLb (FIG. 21) or the structure without having n layer 15.
The simulations similar to those in the first embodiment were performed in order to examine the characteristics of the diode according to the present embodiment. The simulation results will be hereinafter described.
Referring to FIG. 23, simulations were performed for a carrier concentration CC in the ON state. The results show that a carrier concentration CC3 of the diode (FIG. 20) in the example of the present embodiment is higher than carrier concentration CC0 of the diode in the comparative example (FIG. 26). In other words, it is found that the carrier concentration near the cathode is increased in the ON state. It is considered that this increase in carrier concentration causes a decrease in VF.
Referring to FIG. 24, simulations were performed for the characteristics of a current density JA-a voltage VAK. The figure shows a current density JA3 in the case of the diode in the present embodiment (FIG. 20) and a current density JA0 in the case of the diode in the comparative example (FIG. 26). According to the present embodiment, it is found that the characteristic curve of current density JA-voltage VAK shifts in the direction in which voltage VAK is decreased on the horizontal axis on the graph, as compared to the case in the comparative example. In other words, it is found that VF can be decreased.
Referring to FIG. 25, simulations were performed for the correlation between a depth y of trench structure 26b and VF. Consequently, it is found that VF can be further sufficiently decreased by setting trench depth y to a dimension t2 or more. In other words, it is found that VF can be further sufficiently decreased by providing trench structure 26b so as to extend through region 2 and n layer 15.
According to the present embodiment, when a positive bias is applied to trench structure 26b located on the cathode side, an accumulation layer is formed on the sidewall of the trench, which causes an effect similar to that obtained in the case where n+ region 2 is expanded. Therefore, the electron injection from the cathode side can be facilitated at the time when the device is turned on, and consequently, VF can be decreased.
Furthermore, VF can be further sufficiently decreased by providing trench structure 26b so as to extend through n+ region 2 and n layer 15. In addition, in the modification (FIG. 22), trench structure 26b may be provided so as to extend through n+ region 2.
Although the first and second conductivity types correspond to a p-type and an n-type, respectively, in each of the above-described embodiments, the present invention is not limited thereto, but the first and second conductivity types may correspond to an n-type and a p-type, respectively.
Although the diode has been described as a semiconductor device in each of the above-described embodiments, the semiconductor device according to the present invention is not limited to a diode alone, but may be a power module including a diode. Such a power module may include, for example, an IGBT.
Although the case where p layer 3, n− drift layer 1, n layer 15, and cathode layer CLa are made of Si to which conductive impurities are added has been described, similar effects can be obtained even when a wide band gap material such as SiC or GaN is used in place of Si.
Furthermore, although the case where the semiconductor device of a high breakdown voltage rated at 3300V class has been described as an example, the present invention can also be applied to those of other breakdown voltage classes.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the scope of the present invention being interpreted by the terms of the appended claims.

## Claims

1. A semiconductor device comprising:
a first electrode;
a first layer located on said first electrode and having a first conductivity type;
a second layer located on said first layer and having a second conductivity type different from said first conductivity type;
a third layer located on said second layer;
a second electrode located on said third layer; and
a fourth layer located between said second layer and said third layer, and having said second conductivity type,
said third layer including
a first portion having said second conductivity type and having a peak value of impurity concentration higher than a peak value of impurity concentration in said second layer, and
a second portion having said first conductivity type,

an area of said second portion accounting for not less than 20% and not more than 95% of a total area of said first and second portions,
said fourth layer including
a third portion located on the first portion, and
a fourth portion located on the second portion,

wherein:
a surface of the first portion facing the fourth layer is flush with a surface of the second portion facing the fourth layer,
the third portion of said fourth layer has a peak value of impurity concentration at a position spaced apart from a surface of the third portion that faces the third layer,
the fourth portion of said fourth layer has a peak value of impurity concentration at a position spaced apart from a surface of the fourth portion that faces the third layer, and
the peak value of impurity concentration in said third portion of said fourth layer is higher than the peak value of impurity concentration in said fourth portion of said fourth layer.

2. The semiconductor device according to claim 1, wherein a conductivity type of conductive impurities of said fourth layer is said second conductivity type.

3. The semiconductor device according to claim 1, wherein
a ratio of the peak value of impurity concentration in said fourth portion to a peak value of impurity concentration in said second portion is not less than 0.001 and not more than 0.1.

4. The semiconductor device according to claim 1, further comprising:
a fifth layer located between said first layer and said second layer and having said second conductivity type; and
a trench structure extending through said first and fifth layers.

5. The semiconductor device according to claim 1, wherein:
a peak value of impurity concentration in said fourth layer is higher than a peak value of impurity concentration in said second layer, and lower than the peak value of impurity concentration in said first portion of said third layer,
for every common depth of the second portion and the first portion of the third layer, no portion of the second portion of the third layer has a higher impurity concentration than the first portion of the third layer,
for every common depth of the fourth portion and the third portion of the fourth layer, no portion of the fourth portion of the fourth layer has a higher impurity concentration than the third portion of the fourth layer, and
the peak value of impurity concentration in said first portion is higher than a peak value of impurity concentration in said second portion.