# Patent

## Title
Switching regulator with variable compensation

## Abstract

A switching regulator circuit includes a power stage and a compensation network. The compensation network includes a programmable transconductance (gm), having a first selectable transconductance such a closed loop transfer function of the switching regulator circuit may be characterized by a first transfer function having a having a first DC open loop gain and a first bandwidth, and by a second transfer function having a second DC open loop gain and a second bandwidth.

## Background
CROSS REFERENCE TO RELATED APPLICATIONS
The present disclosure claims priority to U.S. Provisional App. No. 61/511,549 filed Jul. 26, 2011, the content of which is incorporated herein by reference in its entirety for all purposes.


BACKGROUND
Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Step down DC-DC voltage regulators are common components in modern electronic devices. The buck converter is a popular device for converting a higher voltage source to a lower voltage level that can be used by the electronics components in an electronic device. Typical input voltages may range from 4.6V to 16V, and typical output voltages may range from 0.8V to 5V. A buck converter comprises power stage and a feedback compensation network. The power stage generates a switched signal and typically includes an output filter to smooth out the output voltage. The feedback compensation network may regulate the output voltage by varying the duty cycle of the power stage.
The dynamic response of a voltage regulator informs the circuit designer how the circuit will behave. The dynamic response may be represented by the closed loop transfer function of the voltage regulator. The bandwidth, which is sometimes defined from DC to the cutoff frequency, tells how quickly the circuit will respond to changes in the output voltage during operation of the circuit. The DC open loop gain tells how accurate the circuit will be in compensating for changes in the output voltage; for example, whether the circuit will overshoot or undershoot, ringing, and so on. Acceptable performance of the circuit depends on being able to control or otherwise design for these parameters.
SUMMARY
In some embodiments, a circuit comprises a switching power circuit configured for connection to an input voltage. The switching power circuit provides an output that can be supplied as an output voltage to a load. The circuit further comprises a programmable compensation circuit having a selectable transconductance (gm). The compensation circuit is connected to the output voltage and provides feedback to the switching power circuit. The compensation circuit can be configured in a first configuration characterized by a transfer function having a first DC open loop gain and a first bandwidth. The compensation circuit can be configured in a second configuration characterized by a transfer function having a second DC open loop gain and a second bandwidth.
In some embodiments, the compensation circuit includes a programmable transconductance amplifier having a selectable gm. An input value may be provided to select the gm of the transconductance amplifier.
In some embodiments, compensation circuit includes a programmable voltage divider.
In some embodiments, the compensation circuit includes a programmable RC filter.
In some embodiments, the circuit is incorporated in a buck converter.



BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a high level block diagram of a switching regulator circuit in accordance with the present disclosure.
FIG. 2 shows some circuit details of a switching regulator circuit in accordance with some embodiments.
FIG. 2A illustrates an example of a programmable transconductance amplifier.
FIG. 3 shows an equivalent circuit diagram of the circuit illustrated in FIG. 2.
FIG. 4 represents Bode plots of the transfer functions of a power stage and a compensation stage of the circuit illustrated in FIG. 2.
FIG. 5 represents a Bode plot of a closed loop transfer function of the circuit illustrated in FIG. 2.
FIG. 6 represents a Bode plot where the pole P1 and the zero Z2 are made equal.



DETAILED DESCRIPTION
Disclosed embodiments relate to switching regulators having a programmable compensation network. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention as defined by the claims may include some or all of the features in these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.
Referring to FIG. 1, a switching regulator circuit 100 may receive an input voltage Vin and produce an output voltage Vout. The output voltage Vout may be used to drive a load 112. In accordance with embodiments of the present invention, the switching regulator circuit 100 may include a switching power circuit 102 which receives the input voltage Vin. The input voltage Vin may range from 4.5V to 16V; however, other voltage levels are possible of course. The switching power circuit 102 may output a switching signal SW that is supplied, via a filter 106, to the load 112 as the output voltage Vout. In some embodiments, the switching signal SW is a square wave. The switching power circuit 102 and filter 106 may be collectively referred to as the “power stage.”
In accordance with the present disclosure, a programmable compensation network 104 may compensate for variations in the output voltage Vout that may result from variations in the load 112, temperature fluctuation, and so on. In some embodiments, for example, the programmable compensation network 104 may provide a feedback control signal which feeds into the switching power circuit 102 to the control the duty cycle of the switching signal SW, thereby regulating the output voltage Vout.
In some embodiments, the switching regulator circuit 100 is a buck regulator, where the output voltage Vout is less than the input voltage Vin. As will be explained below, the output voltage Vout can be readily programmed by the user to different operating voltages. In accordance with principles of the present disclosure, the programmable compensation network 104 can ensure stable circuit operation for each of the different operating voltages.
Referring to FIG. 2, in some embodiments, the switching regulator circuit 100 comprises two components: device 202 and external filter 206. The device 202 may be provided as an integrated circuit (IC) device. The external filter 206, as the name suggests, comprises components that are typically too large or impractical to fabricate on the IC device 202 and thus may be provided external to the IC device (off-chip). The external filter 206 may be any suitable design. For example, FIG. 2 shows the external filter 206 comprises a diode D (e.g., a Schottky diode), an inductor L, and an output capacitor Co configured in a pi network. The figure also includes a resistor RESR which represents the total equivalent series resistance (ESR) of the output capacitor Co, which is sometimes referred to as the parasitic resistance. The load 112 is represented by resistor Rloadnd.
The device 202 may include the switching power circuit 102 (FIG. 1) and the programmable compensation network 104. In some embodiments, the switching power circuit 102 may be a current mode control switching power circuit. For example, the switching power circuit 102 may comprise a switch M1, a current sense amplifier 212, a summing circuit 214, a comparator 216, and an RS flip-flop 218.
The switch M1 may have an input for a connection to the input voltage Vin. The switch M1 may be controlled by a switching control signal Vswitch to produce the switching signal SW. In an embodiment, for example, the switch M1 may be a field effect transistor (FET) device. A source terminal S of the FET M1 may be connected to the input voltage Vin. A gate terminal G of the FET M1 may be connected to a source of the switching control signal Vswitch to produce the switching signal SW, which may be obtained from the drain terminal D of switch M1.
The current sense amplifier 212 may be connected to the switch M1 to sense the current flow through the inductor L on each switching cycle. For example, the current sense amplifier 212 may be connected to the source S and drain D terminals of the FET M1 to sense current flow through the FET, which effectively senses the current flow through the inductor L. An output resistor Rsense may be provided at an output of the current sense amplifier 212 to produce a current sense voltage Visns. The summing circuit 214 may combine the current sense voltage Visns with a slope compensation signal Vslope obtained from a voltage ramp generator (not shown). In some embodiments, the voltage ramp generator (not shown) may be provided on-chip (i.e., fabricated on the device 202), and in other embodiments the voltage ramp generator may be provided off-chip. The output of the summing circuit 214 is a ramp signal Vramp.
The ramp signal Vramp may be connected to an input of the comparator 216. In some embodiments, for example, the ramp signal Vramp is connected to a non-inverting input of the comparator 216. Since the ramp signal Vramp is based on the current flow through switch M1, the ramp signal represents a current mode feedback signal. Another feedback control signal, produced in the programmable compensation network 104 (discussed below), may connect to another input of the comparator 216 (e.g., an inverting input). As will be explained below, the feedback control signal produced in the programmable compensation network 104 is a voltage mode feedback signal. An output of the comparator 216 may drive an RS flip-flop 218 in accordance with the current mode feedback signal (Vramp) and the voltage mode feedback signal. In particular, the output of the comparator 216 may drive the RESET input of the RS flip-flop. A clock signal CLK may feed into the SET input of the RS flip-flop 218. The clock signal CLK may be provided on-chip or off-chip. An output Q of the RS flip-flop 218 may be connected to the switch M1 to serve as the switching control signal Vswitch for the switch, and in particular the switching control signal controls the duty cycle of the switch. In an embodiment, the output Q may be connected to the gate terminal G of FET Mf.
In some embodiments, the programmable compensation network 104 may comprise a programmable resistor network 222, a programmable transconductance amplifier 224, and a programmable RC filter 226. The programmable resistor network 222 may be configured as a voltage divider, and connected to the output voltage Vout to generate a feedback voltage Vfb that is proportional to Vout. Accordingly, the programmable resistor network 222 may also be referred to as a programmable feedback divider. An input value R-setting may be provided off-chip; e.g., by a user, another circuit, etc. In some embodiments, for example, the input value R-setting may be a four-bit data value used to configure the programmable resistor network 222 with one out of sixteen possible voltage divider ratios (taps), Dr; although more or less bits may be provided. The level of the output voltage Vout may be selected by programming the programmable resistor network 222 using the input value R-setting.
In accordance with principles of the present disclosure, the programmable compensation network 104 includes a programmable transconductance amplifier 224. The programmable transconductance amplifier 224 may include a pair of differential inputs 224a, 224b. The feedback voltage Vfb from the programmable resistor network 222 may be connected to an inverting input 224a. A reference voltage Vref may be connected to a non-inverting input 224b. In some embodiments, the reference voltage Vref may be about 0.8V, and may be provided from an on-chip source or the reference source may be off-chip.
In some embodiments, the programmable transconductance amplifier 224 may be programmed using the input value R-setting, as depicted in FIG. 2. In particular, the transconductance (gm) value of the programmable transconductance amplifier 224 is programmable. In other embodiments, a second input value other than the input value R-setting may be used to program the programmable transconductance amplifier 224. The second input value may have the same, or a different, number of bits of resolution as the input value R-setting.
Referring for a moment to FIG. 2A, an illustrative embodiment of the programmable transconductance amplifier 224 is shown. The particular circuit shown in the figures shows an operational transconductance amplifier (OTA). A steering resistor sets the transconductance gm of the OTA. More particularly, the steering resistor may be programmable thereby allowing the transconductance gm of the OTA to be determined according to the input value R-setting.
Completing the circuit description of FIG. 2, an output Vc of the programmable transconductance amplifier 224 may connect to the programmable RC filter 226. The programmable RC filter 226 may be programmed, for example, via a programmable resistor Rc. Programmable resistors, such as the resistor Rc and the steering resistor in FIG. 2A, are known devices. Any of numerous known suitable designs may be used.
The output Vc of the programmable transconductance amplifier 224 may serve as the feedback control signal that feeds into the comparator 216, as described above. As will be explained below, the programmable compensation network 104 of the present disclosure facilitates selection of the operating output voltage Vout. In addition, the programmable compensation network 104 facilitates improving the bandwidth of the switching regulator circuit 100 (e.g., having a high crossover frequency) thereby improving circuit response time. The programmable compensation network 104 also facilitates improving accuracy of the switching regulator circuit 100 by maximizing the circuit DC open loop gain without creating instability. In accordance with principles of the present disclosure, both bandwidth and DC open loop gain can be improved without trading off one for the other.
As can be seen from FIG. 2, the output voltage Vout can be set by setting the voltage divider ratio Dr of the programmable resistor network 222. Vout relates to Vfb by the relation Vfb=Vout×Dr. By operation of the feedback loop of the programmable compensation network 104, the programmable transconductance amplifier 224 will drive the output voltage Vout to maintain Vfb=Vref. Therefore, the output voltage Vout can be determined from




  
    V
    out
  
  =
  
    
      
        V
        ref
      
      
        D
        r
      
    
    .
  




For example, assuming Vref is 0.8V, Vout can be set to 0.8V, 1.6V, 2V, and 3.2V by providing the programmable resistor network 222 with selectable divider ratios Dr of 1, 0.5, 0.4, and 0.25, respectively. If the input value R-setting is a two-bit value, then the setting “00” may be used to set the divider ratio Dr to 1, the setting “01” may be used to set the divider ratio to 0.5, the setting “10” may be used to set the divider ratio to 0.4, and the setting “11” may be used to set the divider ratio to 0.25.

In operation, the clock signal CLK causes the switch M1 to produce a switching signal SW which is filtered by the external filter 206 to produce the output voltage Vout. The output voltage Vout can then be supplied to the load 112. The output voltage Vout is fed back to the programmable transconductance amplifier 224 via the programmable resistor network 222 as feedback voltage Vfb, and compared against the reference voltage Vref. The programmable transconductance amplifier 224 will produce an output voltage, namely the control voltage Vc. The RC filter 226 smooths out fluctuations in the control voltage Vc. The control voltage Vc feeds into the comparator 216, thus forming a voltage controlled feedback loop.
In the power stage, the current sense amplifier 212 effectively senses the current flow through the inductor L, and produces a voltage level that is proportional to the sensed current, namely, the current sense voltage Visns. The current sense voltage Visns is combined with the slope compensation signal Vslope to produce Vramp, which feeds into the comparator 216 thus forming a current controlled feedback loop.
In the beginning of a switching period, the control voltage Vc is higher than Vramp, since Vfb is 0V. This will cause the output of the comparator 216 to be LO, taking the RS flip-flop 218 out of reset. The clock signal CLK will turn the switch M1 ON. As current begins to flow through switch M1 and inductor L, the current sense voltage Visns (and hence Vramp) will begin to ramp up. At the same time, the current flow will cause Vfb to ramp up as well. When Vfb=Vref, the control voltage Vc will go to 0V. When Vramp≧Vc, the comparator 216 will go HI and put the RS flip-flop 218 in reset, thus turning the switch M1 OFF.
As the current flow through the inductor drops, Vfb will decay and fall below Vref. This will cause the control voltage Vc to once again become higher than Vramp, thus repeating the cycle. Setting the voltage divider ration Dr determines the ON and OFF switching times of the switch M1, and hence the duty cycle of the switching signal SW.
Referring to FIG. 3, the discussion will now consider the bandwidth characteristic of the switching regulator circuit 100 (which relates to circuit response time) and the DC open loop gain of the switching regulator circuit (which relates to accuracy of circuit operation). The diagram in FIG. 3 represents an equivalent circuit of the switching regulator circuit 100. Accordingly, an equivalent circuit of the power stage may be represented by a current source G, (which represents the sense amp 212), the output capacitor Co and its equivalent series resistance RESR, and the load 112. An equivalent circuit of the programmable compensation network 104 may be represented by the programmable resistor network 222, the programmable transconductance amplifier 224, and the programmable RC filter 226.
Consider first, the DC open loop gain of the switching regulator circuit 100. The open loop transfer function TFpower of the power stage may be represented by:




  
    
      
        
          
            TF
            power
          
          =
          
            
              G
              i
            
            ⁢
            
              
                R
                load
              
              ·
              
                
                  1
                  +
                  
                    
                      sC
                      o
                    
                    ⁢
                    
                      R
                      ESR
                    
                  
                
                
                  1
                  +
                  
                    
                      sC
                      o
                    
                    ⁢
                    
                      R
                      load
                    
                  
                
              
            
          
        
        ,
      
    
    
      
        Eqn
        .
        
          
        
        ⁢
        1
      
    
  




where Gi is the current sense gain of the current sense amplifier 212,

Rload is the value of the load 112,
Co is the values of the output capacitor Co, and
RESR is the value of the equivalent series resistance RESR.
The inductor L is associated with an equivalent resistance, sometimes referred to as the DC resistance (DCR). However, its resistance is sufficiently small that it can be ignored for purposes of the following analysis.
The open loop transfer function TFcompensation of the programmable compensation network 104 may be represented by:




  
    
      
        
          
            TF
            compensation
          
          =
          
            
              
                
                  V
                  ref
                
                
                  V
                  out
                
              
              ·
              
                g
                m
              
            
            ⁢
            
              
                r
                o
              
              ·
              
                
                  1
                  +
                  
                    
                      sC
                      c
                    
                    ⁢
                    
                      R
                      c
                    
                  
                
                
                  1
                  +
                  
                    
                      sC
                      c
                    
                    ⁢
                    
                      r
                      o
                    
                  
                
              
            
          
        
        ,
      
    
    
      
        Eqn
        .
        
          
        
        ⁢
        2
      
    
  




where Vref is the voltage level of the reference voltage Vref,

Vout is the voltage level of the output voltage Vout,
gm is the transconductance of the transconductance amplifier 224,
ro is the output resistance of the transconductance amplifier 224,
Cc is the value of the capacitor Cc in the filter 226, and
Rc is the value of the resistor Rc in the filter 226.
Recall from above that




  
    V
    out
  
  =
  
    
      V
      ref
    
    
      D
      r
    
  




so the ratio





  
    V
    ref
  
  
    V
    out
  




represents the voltage divider ratio Dr of the programmable resistor network 222.

The closed loop transfer function TFclosedloop of the switching regulator circuit 100 may be defined according to:




  
    
      
        
          
            TF
            closedloop
          
          =
          
            
              TF
              power
            
            ·
            
              TF
              compensation
            
          
        
        ,
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          3
        
        ⁢
        a
      
    
  
  
    
      
        
          
            TF
            cloasedloop
          
          =
          
            
              G
              i
            
            ⁢
            
              
                R
                load
              
              ·
              
                
                  1
                  +
                  
                    
                      sC
                      o
                    
                    ⁢
                    
                      R
                      ESR
                    
                  
                
                
                  1
                  +
                  
                    
                      sC
                      o
                    
                    ⁢
                    
                      R
                      load
                    
                  
                
              
              ·
              
                
                  V
                  ref
                
                
                  V
                  out
                
              
              ·
              
                g
                m
              
            
            ⁢
            
              
                r
                o
              
              ·
              
                
                  1
                  +
                  
                    
                      sC
                      c
                    
                    ⁢
                    
                      R
                      c
                    
                  
                
                
                  1
                  +
                  
                    
                      sC
                      c
                    
                    ⁢
                    
                      r
                      o
                    
                  
                
              
            
          
        
        ,
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          3
        
        ⁢
        b
      
    
  




where the DC terms can be collected to produce:





  
    
      
        
          TF
          cloasedloop
        
        =
        
          
            G
            i
          
          ⁢
          
            
              R
              load
            
            ·
            
              
                V
                ref
              
              
                V
                out
              
            
            ·
            
              g
              m
            
          
          ⁢
          
            
              r
              o
            
            ·
            
              
                1
                +
                
                  
                    sC
                    o
                  
                  ⁢
                  
                    R
                    ESR
                  
                
              
              
                1
                +
                
                  
                    sC
                    o
                  
                  ⁢
                  
                    R
                    load
                  
                
              
            
            ·
            
              
                
                  1
                  +
                  
                    
                      sC
                      c
                    
                    ⁢
                    
                      R
                      c
                    
                  
                
                
                  1
                  +
                  
                    
                      sC
                      c
                    
                    ⁢
                    
                      r
                      o
                    
                  
                
              
              .
            
          
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          3
        
        ⁢
        c
      
    
  




As can be seen from Eqn. 3c, the closed loop transfer function of the switching regulator circuit 100 has a DC open loop gain ADC given by:





  
    
      
        
          A
          DC
        
        =
        
          
            G
            i
          
          ⁢
          
            
              R
              load
            
            ·
            
              
                V
                ref
              
              
                V
                out
              
            
            ·
            
              g
              m
            
          
          ⁢
          
            
              r
              o
            
            .
          
        
      
    
    
      
        Eqn
        .
        
          
        
        ⁢
        4
      
    
  




Consider next the bandwidth of the switching regulator circuit 100. The discussion begins with the closed loop transfer function TFclosedloop of the switching regulator circuit 100 as expressed in Eqn. 3b. Since the output resistance ro of the transconductance amplifier 224 is typically high (in principle, infinite), Eqn. 3b can be simplified by first rearranging some terms in the equation:




  
    
      
        
          TF
          cloasedloop
        
        =
        
          
            G
            i
          
          ⁢
          
            
              R
              load
            
            ·
            
              
                1
                +
                
                  
                    sC
                    o
                  
                  ⁢
                  
                    R
                    ESR
                  
                
              
              
                1
                +
                
                  
                    sC
                    o
                  
                  ⁢
                  
                    R
                    load
                  
                
              
            
            ·
            
               
              
                
                  
                    V
                    ref
                  
                  
                    V
                    out
                  
                
                ⁣
                
                  ·
                  
                    g
                    m
                  
                  ·
                  
                    (
                    
                      1
                      +
                      
                        
                          sC
                          c
                        
                        ⁢
                        
                          R
                          c
                        
                      
                    
                    )
                  
                  ·
                  
                    
                      
                        r
                        o
                      
                      
                        1
                        +
                        
                          
                            sC
                            c
                          
                          ⁢
                          
                            r
                            o
                          
                        
                      
                    
                    .
                  
                
              
            
          
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          5
        
        ⁢
        
          
        
        ⁢
        a
      
    
  




Then, assuming Ccro>>1, the following approximation can be made:





  
    
      
        
          
            r
            o
          
          
            1
            +
            
              
                sC
                c
              
              ⁢
              
                r
                o
              
            
          
        
        ≈
        
          
            1
            
              sC
              c
            
          
          .
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          5
        
        ⁢
        
          
        
        ⁢
        b
      
    
  




The closed loop transfer function TFclosedloop can then be approximated by:





  
    
      
        
          TF
          cloasedloop
        
        ≈
        
          
            G
            i
          
          ⁢
          
            
              R
              load
            
            ·
            
              
                1
                +
                
                  
                    sC
                    o
                  
                  ⁢
                  
                    R
                    ESR
                  
                
              
              
                1
                +
                
                  
                    sC
                    o
                  
                  ⁢
                  
                    R
                    load
                  
                
              
            
            ·
            
               
              
                
                  
                    V
                    ref
                  
                  
                    V
                    out
                  
                
                ⁣
                
                  ·
                  
                    g
                    m
                  
                  ·
                  
                    
                      
                        1
                        +
                        
                          
                            sC
                            c
                          
                          ⁢
                          
                            R
                            c
                          
                        
                      
                      
                        sC
                        c
                      
                    
                    .
                  
                
              
            
          
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          5
        
        ⁢
        
          
        
        ⁢
        c
      
    
  




Turning for a moment to FIGS. 4-6, FIG. 4 shows Bode plots of the power stage transfer function (Eqn. 1) and the compensation network transfer function (Eqn. 2). From Eqn. 1, the power stage transfer function TFpower has a pole P1 defined at:




  
    
      
        
          P
          1
        
        =
        
          1
          
            
              C
              o
            
            ⁢
            
              R
              load
            
          
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          6
        
        ⁢
        
          
        
        ⁢
        a
      
    
  




and a zero Z1 defined at:





  
    
      
        
          Z
          1
        
        =
        
          
            1
            
              
                C
                o
              
              ⁢
              
                R
                ESR
              
            
          
          .
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          6
        
        ⁢
        
          
        
        ⁢
        b
      
    
  




Likewise, from Eqn. 2, the compensation network transfer function TFcompensation has a pole P2 defined at:





  
    
      
        
          P
          2
        
        =
        
          1
          
            
              C
              o
            
            ⁢
            
              r
              o
            
          
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          7
        
        ⁢
        
          
        
        ⁢
        a
      
    
  




and a zero Z2 defined at:





  
    
      
        
          Z
          2
        
        =
        
          
            1
            
              
                C
                c
              
              ⁢
              
                R
                c
              
            
          
          .
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          7
        
        ⁢
        
          
        
        ⁢
        b
      
    
  




FIG. 5 shows the Bode plot for the closed loop transfer function (Eqn. 3c) of the switching regulator circuit 100. As can be seen in the Bode plot of FIG. 5, between P1 and Z2 there is a −40 dB slope which indicates a range of frequencies, namely




  
    
      f
      
        P
        ⁢
        
          
        
        ⁢
        1
      
    
    =
    
      
        
          
            P
            1
          
          
            2
            ⁢
            
              
            
            ⁢
            π
          
        
        ⁢
        
          
        
        ⁢
        and
        ⁢
        
          
        
        ⁢
        
          f
          
            Z
            ⁢
            
              
            
            ⁢
            2
          
        
      
      =
      
        
          Z
          2
        
        
          2
          ⁢
          
            
          
          ⁢
          π
        
      
    
  
  ,




where the switching regulator circuit 100 may exhibit unstable operation. However, if pole Pi of the power stage transfer function (Eqn. 1) and the zero Z2 of the compensation network transfer function (Eqn. 2) are set equal to each other, then stable operation across the full bandwidth of the switching regulator circuit 100 can be obtained. The resulting Bode plot is shown in FIG. 6, where the zero Z2 has been made equal to the pole P1.

Returning to Eqn. 5c, when P1=Z2, it can be shown from Eqn. 5c that the closed loop DC gain of the switching regulator circuit 100 may be expressed as:




  
    
      
        
          closed
          ⁢
          
            
          
          ⁢
          loop
          ⁢
          
            
          
          ⁢
          DC
          ⁢
          
            
          
          ⁢
          gain
        
        =
        
          
            G
            i
          
          ⁢
          
            
              R
              load
            
            ·
            
              
                V
                ref
              
              
                V
                out
              
            
            ·
            
              g
              m
            
          
          ⁢
          
            
              R
              c
            
            .
          
        
      
    
    
      
        Eqn
        .
        
          
        
        ⁢
        8
      
    
  




It can be further shown that the crossover frequency ω0 may be expressed as:





  
    
      
        
          
            
              ω
              0
            
            
              P
              1
            
          
          =
          
            
              G
              i
            
            ⁢
            
              
                R
                load
              
              ·
              
                
                  V
                  ref
                
                
                  V
                  out
                
              
              ·
              
                g
                m
              
            
            ⁢
            
              R
              c
            
          
        
        ,
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          9
        
        ⁢
        
          
        
        ⁢
        a
      
    
  




and substituting Eqn. 6a:





  
    
      
        
          ω
          0
        
        =
        
          
            G
            i
          
          ⁢
          
            
              R
              load
            
            ·
            
              
                V
                ref
              
              
                V
                out
              
            
            ·
            
              g
              m
            
          
          ⁢
          
            
              R
              c
            
            ·
            
              1
              
                
                  C
                  o
                
                ⁢
                
                  R
                  load
                
              
            
          
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          9
        
        ⁢
        
          
        
        ⁢
        b
      
    
  
  
    
      
        
          ω
          0
        
        =
        
          
            
              G
              i
            
            ·
            
              
                V
                ref
              
              
                V
                out
              
            
            ·
            
              g
              m
            
          
          ⁢
          
            
              R
              c
            
            ·
            
              
                1
                
                  C
                  o
                
              
              .
            
          
        
      
    
    
      
        
          Eqn
          .
          
            
          
          ⁢
          9
        
        ⁢
        
          
        
        ⁢
        c
      
    
  




Eqn. 9c, therefore, represents the bandwidth ω0 of the switching regulator circuit 100.

The switching regulator circuit 100 of the present disclosure may therefore be characterized by a closed loop transfer function that has a DC open loop gain ADC that can be expressed with Eqn. 4 and a bandwidth ω0 that can be expressed with Eqn. 9c, both of which are reproduced below as Eqns. 10 and 11 respectively:




  
    
      
        
          
            A
            DC
          
          =
          
            
              G
              i
            
            ⁢
            
              
                R
                load
              
              ·
              
                
                  V
                  ref
                
                
                  V
                  out
                
              
              ·
              
                g
                m
              
            
            ⁢
            
              r
              o
            
          
        
        ,
      
    
    
      
        Eqn
        .
        
          
        
        ⁢
        10
      
    
  
  
    
      
        
          ω
          0
        
        =
        
          
            
              G
              i
            
            ·
            
              
                V
                ref
              
              
                V
                out
              
            
            ·
            
              g
              m
            
          
          ⁢
          
            
              R
              c
            
            ·
            
              
                1
                
                  C
                  o
                
              
              .
            
          
        
      
    
    
      
        Eqn
        .
        
          
        
        ⁢
        11
      
    
  




Referring back to FIG. 2, since the gm of the programmable transconductance amplifier 224 is programmable, then programming the gm will affect both ADC and ω0. In addition, since the term




  
    V
    ref
  
  
    V
    out
  




is equal to Dr, then programming the voltage divider ratio Dr of the programmable resistor network 222 also will affect both ADC and ω0. FIG. 2 further shows that the input value R-setting may be used to program suitable values for both gm and Dr. In accordance with principles of the present disclosure, values of gm are inversely related to corresponding values of Dr; as gm decreases, corresponding values of Dr increase. Thus, as a lower value of Dr is selected to set a higher output voltage Vout, a higher value for gm is selected for the programmable transconductance amplifier 224. Conversely, as a higher value of Dr is selected to set a lower output voltage Vout, a lower value for gm is selected for the programmable transconductance amplifier 224.

Referring to Eqns. 10 and 11, the inverse relation between gm and Dr is advantageous because setting the input value R-setting to select a higher operating output voltage Vout (hence a lower Dr) will tend to reduce the DC open loop gain ADC of the switching regulator circuit 100 and the bandwidth ω0 of the switching regulator circuit. A lower DC open loop gain results in reduced accuracy in compensating for changes to Vout. A narrower bandwidth results in a slower response time in responding to changes in Vout. However, in accordance with the present disclosure, an R-setting that selects a higher operating output voltage Vout also selects an increased gm value, thereby offsetting the tendency to reduce both ADC and ω0 using the same control, namely, gm.
Conversely, setting the input value R-setting to select a lower operating output voltage Vout (hence a higher Dr) will tend to increase both ADC and ω0. An increased ADC may results in unstable operation when compensating for changes to Vout. However, in accordance with the present disclosure, an R-setting that selects a lower operating output voltage Vout also decreases gm, thereby offsetting the tendency to increase ADC.
The specific selectable values for gm and Dr, and the resolution of the input value R-setting (i.e., number of bits) are design choices that depend on factors not relevant to the present disclosure. Accordingly, a discussion about specific values for gm and Dr are beyond the scope of the present disclosure.
Referring again to FIG. 2, in a typical usage case, a circuit designer may design their switching regulator circuit using an IC device comprising device 202, and providing their own components for external filter 206 to drive load 112. In a particular embodiment, for example, suppose the input value R-setting is a four-bit input. The programmable transconductance amplifier 224 and programmable network resistor 222 will have, respectively, sixteen selectable gm values (e.g., g0 to g15, where g0<g1, g1<g2, . . . g14<g15) and sixteen selectable Dr values (e.g., D0 to D15, where D0>D1, D1>D2, . . . D14>D15). In some embodiments, the programmable resistor Rc in the RC filter 226 may be programmed on-chip, in the factory. For example, the programmable resistor Rc may comprise fusible links that are “blown” at the time of manufacture to obtain a certain fixed resistance value.
The circuit designer may decide on a suitable output voltage level Vout for their design, and suitable component values for the external filter 206. The circuit designer may then select the closest Dr that will give them their designed Vout. For example, the circuit designer may use the relationship




  
    
      V
      out
    
    =
    
      
        V
        ref
      
      
        D
        r
      
    
  
  ,




where Vref is a known value (e.g., 0.8V) to determine Dr and hence the correct value for the input value R-setting. When the circuit designer enters the R-setting value into the device 202, the programmable resistor network 222 may then be configured to provide the selected Dr. In accordance with the present disclosure, the entered R-setting value will also serve to configure the programmable transconductance amplifier 224 with a value for gm that is selected by the entered R-setting value. In a particular embodiment, for example, the entered R-setting value may be stored in a static memory (not shown) on the device 202. When the device 202 is powered, the R-setting value may be read from the static memory and used to program or otherwise configure both the programmable resistor network 222 and the programmable transconductance amplifier 224. Thus, by using one parameter, R-setting, the operating output voltage Vout of the switching regulator circuit can be selected, while at the same time maximizing the DC open loop gain as well as the bandwidth.

The above description illustrates various embodiments of the present invention along with examples of how aspects of the present invention may be implemented. The above examples and embodiments should not be deemed to be the only embodiments, and are presented to illustrate the flexibility and advantages of the present invention as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations and equivalents will be evident to those skilled in the art and may be employed without departing from the spirit and scope of the invention as defined by the claims.

## Claims

1. A circuit comprising:
a switching power circuit having a first input for a connection to an input voltage and having a second input, the switching power circuit further having an output to supply an output voltage to a load; and
a programmable compensation circuit having a selectable transconductance (gm) and comprising an input section for a connection to the load to receive the output voltage across the load and an output section connected to the second input of the switching power circuit to provide a control signal to the switching power circuit,
the programmable compensation circuit having a first selectable gm wherein a closed loop transfer function of the circuit is represented by a first transfer function having a first DC open loop gain and a first bandwidth,
the programmable compensation circuit having at least a second selectable gm wherein the closed loop transfer function of the circuit is represented by a second transfer function having a second DC open loop gain and a second bandwidth.

2. The circuit of claim 1 wherein the programmable compensation circuit further comprises a programmable transconductance amplifier having a gm that sets the gm of the programmable compensation circuit, wherein the gm of the programmable transconductance amplifier is selectable.

3. The circuit of claim 2 further comprising an input to receive an input value to select the gm of the programmable transconductance amplifier.

4. The circuit of claim 3 wherein the input section of the programmable compensation circuit comprises a programmable voltage divider, wherein the input value serves to select the gm and a voltage divider ratio of the programmable voltage divider.

5. The circuit of claim 1 wherein the input section of the programmable compensation circuit comprises a programmable resistor network.

6. The circuit of claim 5 wherein the programmable resistor network is a voltage divider, the circuit further comprising an input to receive an input value to program a voltage divider ratio of the voltage divider.

7. The circuit of claim 6 wherein the input value is further to program a transconductance (gm) of the programmable compensation circuit.

8. The circuit of claim 1 wherein the output section of the programmable compensation circuit comprises a programmable RC filter.

9. The circuit of claim 1 further comprising a filter circuit connected between the output of the switching power circuit and the load, wherein the filter circuit filters an output of the switching power circuit to produce the output voltage supplied to the load.

10. The circuit of claim 1, wherein the circuit is configured as a buck converter.

11. A method in a circuit comprising:
receiving an input voltage at a switching power circuit;
producing an output of the switching power circuit to be supplied to a load as an output voltage;
accessing a user-provided input value;
using the input value to configure a programmable compensation network with a selectable transconductance (gm);
receiving at an input section of the programmable compensation network the output voltage across the load; and
providing an output from an output section of the programmable compensation network as a control signal to the switching power circuit,
wherein the programmable compensation circuit has a first selectable gm wherein a closed loop transfer function of the circuit is represented by a first transfer function having a first DC open loop gain and a first bandwidth,
wherein the programmable compensation circuit has at least a second selectable gm wherein the closed loop transfer function of the circuit is represented by a second transfer function having a second DC open loop gain and a second bandwidth.

12. The method of claim 11 wherein the programmable compensation circuit further comprises a programmable transconductance amplifier having a selectable gm that sets the gm of the programmable compensation circuit, the method further comprising selecting a gm of the programmable transconductance amplifier using the input value.

13. The method of claim 12 wherein the input section of the programmable compensation circuit comprises a programmable voltage divider, the method further comprising also using the input value to select a voltage divider ratio of the programmable voltage divider.

14. The method of claim 11 wherein the input section of the programmable compensation circuit comprises a programmable resistor network.

15. The method of claim 14 wherein the programmable resistor network is a voltage divider, the method further comprising programming a voltage divider ratio of the voltage divider using the input value.

16. The method of claim 11 wherein the output section of the programmable compensation circuit comprises a programmable RC filter.

17. The method of claim 11 further comprising providing the output of the switching power circuit to a filter circuit and supplying an output of the filter circuit as the output voltage to the load.