# Patent

## Title
Switchable signal routing circuit

## Abstract

A switchable signal routing circuit for routing a signal between at least one input port and at least one output port is provided. The ports are connected via variable resistors to a common node, wherein the switchable signal routing circuit is configured to set resistance values of the variable resistors in dependence on a number of active ports.

## Background
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of copending International Application No. PCT/EP2013/054303, filed Mar. 4, 2013, which is incorporated herein by reference in its entirety.
Embodiments of the present invention relate to a switchable signal routing circuit for routing a signal between at least one input port and at least one output port. Further embodiments relate to a method for operating a switchable signal routing circuit. Some embodiments relate to a combined RF variable splitter+switch (RF=radio frequency).


BACKGROUND OF THE INVENTION
It would be desirable to have a distributing network that is designed to send the signal of one input port to N output ports simultaneously, with the following additional requirements (or constraints):

    1. The distributing network should be broadband, ideally from DC to infinite frequency (DC=direct current).
    2. Each of the N output ports of the distributing network should be individually selectable as transmitting or not transmitting one.
    3. As minimum requirement, the input port and all the M (1≦M≦N) output ports of the distributing network selected to transmit should be impedance matched.
    4. As additional requirement, not only the M transmitting ports but also the remaining ones should be impedance matched, i.e. all the N+1 ports of the distributing network should be impedance matched, independently on which port(s) is(are) transmitting.
    5. The insertion loss of the distributing network should be reduced (or even minimized).
    6. The temperature dependency of the distributing network should be reduced (or even minimized).
    7. The linearity of the distributing network should be increased (or even maximized).
    8. The sensitivity of the distributing network to manufacturing process variations and the requirement of postproduction alignment should be reduced (or even minimized).


One possible structure that holds some—but not all—of the requirements listed above is the single pole N throw (SPNT) switch, wherein within this context, N is an integer multiple and stands for “multiple”. A detailed description of the SPNT switch can be found in Roberto Sorrentino, Giovanni Bianchi: Microwave and RF Engineering, Ch. 10, pp. 363-389. The main drawback of the SPNT switch is that only one output port at the time can be selected among the available N output ports.
Thus, at least requirement 2 stating that each of the N output ports should be individually selectable as transmitting or not transmitting one is not satisfied.
One other circuit which satisfies some—but again not all—the requirements listed above is the N-output splitter 10, schematized in FIG. 1. It consists of N+1 equal valued resistors, indicated in FIG. 1 as R1 to RN+1, and N+1 Ports, indicated in FIG. 1 as P1 to PN+1. The N+1 equal valued R1 to RN+1 resistors connect the N+1 Ports P1 to PN+1 to a common node 12. Thereby, the equal valued resistors R1 to RN+1 comprise fixed or constant resistance values.
The condition for simultaneously matching all of the N+1 ports P1 to PN+1 (i.e., for fulfilling requirement 3 stating that the input port and all of the M output ports selected to transmit should be impedance matched and requirement 4 stating that not only the M transmitting ports but also the remaining ones should be impedance matched) is:




  
    
      
        
          R
          k
        
        =
        
          
            
              N
              -
              1
            
            
              N
              +
              1
            
          
          ⁢
          
            R
            0
          
          ⁢
          
            
          
          ⁢
          
            (
            
              1
              ≤
              k
              ≤
              
                N
                +
                1
              
            
            )
          
        
      
    
    
      
        (
        1
        )
      
    
  




where R0 is the reference impedance, normally equal to 50Ω.

Under the condition described by equation (1) the scattering parameters of the network in FIG. 1 are




  
    
      
        
          s
          hk
        
        =
        
          
            1
            N
          
          ⁢
          
            
          
          ⁢
          
            (
            
              
                1
                ≤
                h
              
              ,
              
                k
                ≤
                
                  N
                  +
                  1
                
              
              ,
              
                h
                ≠
                k
              
            
            )
          
        
      
    
    
      
        (
        2
        )
      
    
  
  
    
      
        
          s
          hk
        
        =
        
          0
          ⁢
          
            
          
          ⁢
          
            (
            
              1
              ≤
              k
              ≤
              
                N
                +
                1
              
            
            )
          
        
      
    
    
      
        (
        3
        )
      
    
  




as all the ports are totally equivalent.

Equation (3) confirms the impedance matching of the structure and needs no further comments. Equation (2) states that the splitter 10 transmits the input power to each of its N output ports P2 to PN+1 with an attenuation in linear units equal to the reciprocal of the number N of output ports P2 to PN+1 itself. From equation (2) it also follows that the ratio between the input power PIN (present at the input port P1) and the output power POUT globally transmitted to the output ports P2 to PN+1 is




  
    
      
        
          
            P
            OUT
          
          
            P
            IN
          
        
        =
        
          
            
              ∑
              
                k
                =
                2
              
              
                N
                +
                1
              
            
            ⁢
            
              
                
                
                  s
                  
                    k
                    ,
                    1
                  
                
                
              
              2
            
          
          =
          
            
              
                ∑
                
                  k
                  =
                  2
                
                
                  N
                  +
                  1
                
              
              ⁢
              
                
                  
                  
                    1
                    N
                  
                  
                
                2
              
            
            =
            
              1
              N
            
          
        
      
    
    
      
        (
        4
        )
      
    
  




In other words, only 1/N of the available input power PIN is shared between the output ports P2 to PN+1, where the remaining (N−1)/N of the available input power PIN is dissipated inside the structure 10. That could be in contrast with requirement 5 stating that the insertion loss of the distribution network should be reduced (or even minimized). On the other side, the only way to realize a non-dissipative N-way power divider structure is by using reactive elements instead of resistors. One of such possibility's is based on the so called Wilkinson power divider, as described in Giovanni Bianchi: Microwave and RF Engineering, Ch. 7, pp. 205-209. Unfortunately, reactive elements are inherently frequency-depending. Therefore, non-dissipative distributed networks can only be realized with relative bandwidth of relatively few octaves.
FIG. 2 lists in a table resistance values and transmission coefficients of N-way power splitters. In other words, FIG. 2 lists in a table the resistance values of the fixed equal valued resistors (assuming R0=50Ω) and the input-output transmission coefficients for power splitters having a number of output ports from 1 to 16 (the 1-output power splitter is a trivial structure consisting of a direct input-output connection).
An additional requirement not fulfilled by the structure shown in FIG. 1 is requirement 2 stating that each of the N output ports P2 to PN+1 should be individually selectable as transmitting or not transmitting one.
SUMMARY
An embodiment may have a switchable signal routing circuit for routing a signal between at least one input port and at least one output port, wherein the ports are connected via variable resistors to a common node, wherein the switchable signal routing circuit is configured to set resistance values of the variable resistors in dependence on a number of active ports.
According to another embodiment, a method for operating a switchable signal routing circuit for muting a signal between at least one input port and at least one output port, wherein the ports are connected by means of variable resistors to a common node, may have the step of: setting resistance values of the variable resistors in dependence on a number of active ports.
Another embodiment may have a computer program having a program code for performing, when running on a computer or microprocessor, a method according to claim 17.
A switchable signal routing circuit for routing a signal between at least one input port and at least one output port is provided. The ports are connected via variable resistors to a common node, wherein the switchable signal routing circuit is configured to set resistance values of the variable resistors in dependence on a number of active ports.
Further, a method for operating a switchable signal routing circuit for routing a signal between at least one input port and at least one output port is provided. The ports are connected by means of variable resistors to a common node. The method comprises setting resistance values of the variable resistors in dependence on a number of active ports.



BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the present invention will be detailed subsequently referring to the appended drawings, in which:
FIG. 1 shows a block diagram of a passive N-way splitter.
FIG. 2 lists in a table resistance values and transmission coefficients of N-way power splitters.
FIG. 3 shows a block diagram of a passive switchable power splitter.
FIG. 4a shows a block diagram of an absorptive SPST with series elements.
FIG. 4b shows a block diagram of an absorptive SPST with shunt elements.
FIG. 5 shows a block diagram of a switchable signal routing circuit according to an embodiment of the present invention.
FIG. 6a shows a block diagram of a variable resistor.
FIG. 6b shows a PIN diode based implementation of the variable resistor shown in FIG. 6a. 
FIG. 6c shows a FET based implementation of the variable resistor shown in FIG. 6a. 
FIG. 7a shows a block diagram of a variable resistor.
FIG. 7b shows a block diagram of an implementation of the variable resistor shown in FIG. 7a, according to an embodiment of the present invention.
FIG. 7c shows a block diagram of an implementation of the variable resistor shown in FIG. 7a, according to a further embodiment of the present invention.
FIG. 7d shows a block diagram of an implementation of the variable resistor shown in FIG. 7a, according to a further embodiment of the present invention.
FIG. 7e shows a block diagram of an implementation of the variable resistor shown in FIG. 7a, according to a further embodiment of the present invention.
FIG. 8 lists in a table different resistance values which the variable resistor shown in FIG. 7b and the variable resistor shown in FIG. 7c can provide.
FIG. 9 compares in a table the number of resistor units which may use the variable resistor shown in FIG. 7b and the number of resistor units which may use the variable resistor shown in FIG. 7c for providing the same number of different resistance values.



DETAILED DESCRIPTION OF THE INVENTION
Equal or equivalent elements or elements with equal or equivalent functionality are denoted in the following description by equal or equivalent reference numerals.
Before embodiments of the present invention are described, a passive switchable power splitter which fulfills requirement 2 (stating that each of the N output ports should be individually selectable as transmitting or not transmitting one) by introducing additional SPST switches at the outputs is presented.
FIG. 3 shows a block diagram of a passive switchable power splitter 20. Note that, the structure shown in FIG. 3 is based on the structure shown in FIG. 1 with the addition of N single pole single throw (SPST) switches 222 to 22N+1 at the N output ports, denoted with P2 to PN+1. Thereby, the SPST switch is a special and simplified case of the SPNT switch with N=1.
In other words, the passive switchable power splitter 20 comprises a passive splitter 21 comprising the N+1 equal valued resistors R1 to RN+1 and N single pole single throw (SPST) switches 222 to 22N+1 connected between the equal valued resistors R2 to RN+1 and the output ports P2 to PN+1.
The SPST switches 222 to 22N+1 used in FIG. 3 are absorptive in that they present an ideally perfect impedance match to both of their ports, independent on whether the respective port is transmitting (i.e., active) or not transmitting (i.e., inactive), or in other word, independently from the setting status. This way, the passive splitter 20 shown in FIG. 3 works as in the normal case (all its ports are impedance-matched), while all of the output ports P2 to PN+1 can be individually selected to transmit or not.
FIGS. 4a and 4b show two alternative structures for an absorptive SPST switch with impedance matching in the non-transmitting state. More precisely, FIG. 4a shows a realization of an absorptive SPST switch with series elements (SWA with R0 and SWC with R0), where FIG. 4b shows a realization of an absorptive SPST switch with shunt elements (SWD with R0 and SWH with R0).
The absorptive SPST switch 22 shown in FIG. 4a comprises, an input port Pk′, an output port Pk, a reference terminal 24, a first switch SWA, a second switch SWB, a third switch SWC, a first reference impedance R0 and a second reference impedance R0.
The first switch SWA and the second switch SWB are connected in series between the input port Pk′ and the output port Pk. A common node 23 between the first switch SWA and the second switch SWB is connected via the third switch SWC to the reference terminal 24. The reference terminal 24 can be configured to provide a reference potential, e.g., ground potential. Thus, the reference terminal 24 can be a ground terminal.
In other words, the first switch SWA, the second switch SWB and the third switch SWC form a star connection between the input port Pk′, the output port Pk and the reference terminal 24.
The first reference impedance R0 is connected in parallel to the first switch SWA, wherein the second reference impedance R0 is connected in parallel to the second switch SWB.
The absorptive SPST switch 22 shown in FIG. 4b comprise an input port Pk′, an output port Pk, reference terminal(s) 24, a fourth switch SWD, a fifth switch SWE, a sixth switch SWE, a seventh switch SWG, an eighth switch SWH, a first reference impedance R0 and a second reference impedance R0.
The fifth switch SWE and the seventh switch SWG are connected in series between the input port Pk′ and the output port Pk. A common node 23 between the fifth switch SWE and the seventh switch SWG is connected via a sixth switch SWF to (one of) the reference terminal(s) 24. In other words, the fifth switch SWE, the sixth switch SWF and the seventh switch SWG form a star connection between the input port Pk′, the output port Pk and (one of) the reference terminal(s) 24.
The fourth switch SWD and the first reference impedance R0 are connected in series between the input port Pk′ (one of) the reference terminal(s) 24. The eighth switch SWH and the second reference impedance R0 are connected in series between the output port Pk and (one of) the reference terminal(s) 24.
Note that the reference terminal(s) 24 can be ground terminal(s) providing a ground potential.
As already mentioned, either the absorptive SPST switch 22 shown in FIG. 4a or the absorptive SPST switch 22 shown in FIG. 4b can be added to each of the outputs of the passive N-way splitter 10 shown in FIG. 1 to obtain the passive switchable power splitter 20 shown in FIG. 2.
Thereby, each SPST switch 22 has series and shunt switching devices which could assume very high (ideally infinite) or very low (ideally zero) impedance values. When the switches SWA, SWB, SWE and SWG are short circuited, the SPST switch 22 connects its two RF ports Pk′ and Pk to each other. When the switches SWC, SWD, SWF and SWH are short circuited, the SPST switch 22 isolates its two RF ports Pk′ and Pk from each other. Transmitting or not, the SPST switch 22 presents matched ports Pk′ and Pk to the passive splitter 21 and to the external output ports P2 to PN+1.
The main inconvenience of the structure shown in FIG. 3 is its insertion loss, which is depending on the number N of available output ports P2 to PN+1, and not on the number M (M≦N) of actually selected or active output ports P1 to PM+1. Since the transmission coefficient is inversely proportional to the number N of output ports P2 to PN+1, the minimum possible insertion loss is not realized when less than the available output ports are selected, i.e., when M<N. The following example may clarify this.
Thereby, it is assumed that the network comprises four (N=4) output ports with R0=50Ω. From equations (1) and (3) the values of the fourth row of the table shown in FIG. 2 are obtained, namely a resistance Rk of 30Ω for each of the equal valued resistors R1 to R5, and an input-output transmission coefficient (20·log10(|sk1|)) of −12.04 dB.
If only two of the four output ports are selected as transmitting, anyway an input-output transmission coefficient (20·log10(|sk1|)) of −12.04 dB is obtained, while the second row of the table shown in FIG. 2 states that the transmission coefficient for a passive splitter comprising two output ports should only be −6.02 dB.
Thus, the structure shown in FIG. 3 does not exploit the opportunity offered by the splitter to realize lower insertion loss values in case of reduced number of active output ports. All that is in strong contrast with requirement 5 stating that the insertion loss of the distributing network should be reduced (or even minimized).
Subsequently, embodiments of the present invention are described which reduce or even avoid the above mentioned disadvantages.
In the following description a plurality of details are set forth to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring embodiments of the present invention. In addition, features of different embodiments described hereinafter may be combined with each other, unless specifically noted otherwise.
FIG. 5 shows a block diagram of a switchable signal routing circuit 100 according to an embodiment of the present invention. The switchable signal routing circuit 100 is configured to route a signal between at least one input port and at least one output port, wherein the ports P1 to PN+1 are connected via variable resistors R1 to RN+1 to a common node 102. The switchable signal routing circuit 100 is configured to set resistance values of the variable resistors R1 to RN+1 in dependence on a number L of active ports P1 to PL.
According to the concept of the present invention, the switchable signal routing circuit 100 comprises variable resistors R1 to RN+1 instead of fixed equal valued resistors as it is the case in FIG. 1. In other words, the fixed equal valued resistors R1 to RN+1 of the passive N-way splitter shown in FIG. 1 are replaced by variable resistors R1 to RN+1. Furthermore, the switchable signal routing circuit 100 is configured to set the resistance values of the variable resistors R1 to RN+1 in dependence on the number L of active ports P1 to PL.
Thereby, N can be a natural number greater than or equal to two (N≧2), wherein L can be a natural number greater than or equal to two, and smaller than or equal to N+1 (2≦L≦N+1).
For example, the switchable signal routing circuit 100 can comprise 3, 4, 5, 10, 20, 30, 40, 50, 100 or even more ports P1 to PN+1.
Note that the switchable signal routing circuit 100 can comprise a plurality of input/output ports P1 to PN+1, wherein at least one of the plurality of input/output ports P1 to PN+1 is used as input port, and wherein at least another of the plurality of input/output ports P1 to PN+1 is used as output port.
For example, the switchable signal routing circuit 100 can comprise one input port P1 and a plurality of output ports P2 to PN+1. In that case, the switchable signal routing circuit 100 can be referred to as signal splitter.
Furthermore, the switchable signal routing circuit can comprise a plurality of input ports P2 to PN+1 and one output port P1. In that case, the switchable signal routing circuit 100 can be referred to as signal combiner.
Naturally, the switchable signal routing circuit 100 can also comprise a plurality of input ports and a plurality of output ports at the same time. Or in other words, the switchable signal routing circuit 100 can also comprise more than one input port (e.g., 2, 3, 5, 10, 20, 30, 50 or even more input ports) and more than one output port (e.g., 2, 3, 5, 10, 20, 30, 50 or even more output ports) at the same time.
In some embodiments, the switchable signal routing circuit 100 can be configured to receive a control information describing the number L, of active ports P1 to PL and to automatically set the resistance values of the variable resistors R1 to RN+1 in response to the control information.
Thereby, the switchable signal routing circuit 100 can be configured to set the resistance values of all the variable resistors R1 to RN+1. Further, the switchable signal routing circuit 100 can be configured to set only the resistance values of variable resistors R1 to RL connected to active ports P1 to PL.
Further, the switchable signal routing circuit 100 can be configured to individually set the resistance value of each variable resistors R1 to RN+1, or each variable resistor R1 to RL connected to an active port P1 to PL.
Moreover, the switchable signal routing circuit 100 can be configured to set the resistance values of the variable resistors R1 to RN+1, or the resistance values of the resistors R1 to RL connected to active ports P1 to PL to the same value.
For example, the switchable signal routing circuit 100 can be configured to set the resistance value R of each of the variable resistors R1 to RN+1 within a tolerance of 10% (or 5%, or 3%, or 1%) based on the formula:




  
    
      
        R
        =
        
          
            R
            0
          
          ⁢
          
            
              M
              -
              1
            
            
              M
              +
              1
            
          
        
      
    
    
      
        (
        5
        )
      
    
  




wherein M=L−1, wherein L is the number of active ports, and wherein R0 is a reference impedance, e.g., having a resistance of 50Ω (or 60Ω, or 70Ω, or 110Ω).

Further, the switchable signal routing circuit 100 can be configured to terminate inactive ports PL+1 to PN+1 with a termination resistor.
The termination resistor may provide a reference impedance at the inactive ports PL+1 to PN+1. For example, the termination resistor may have a reference impedance R0 of 50Ω (or 60Ω, or 70Ω, or 10Ω).
Moreover, the switchable signal routing circuit 100 can be configured to disconnect inactive ports PL+1 to PN+1 from the common node 102.
The switchable signal routing circuit 100 (N+1 port network) can be used to either distribute one input signal present at one input port to M selectable output ports or to combine M sources connected to M selectable input ports to a common output port. In the first case, the port P1 of the network 100 can be the input port, and the remaining N ports P2 to PN+1 can be the output ports. In the second case, the port Pt of the network 100 can be the output port, where the remaining N ports P2 to PN+1 can be the input ports.
The reconfigurable distribution network 100 can be purely passive and ideally or almost linear. From this, it follows, that in practice the network 100 is also reciprocal. Therefore, the use cases as source distributer (or splitter) or source combiner are totally equivalent.
Therefore, the following considerations referring to the use case as source distributer may also apply to the use case as source combiner.
In other words, in the following it is assumed that the switchable signal routing circuit 100 comprises one input port P1 and a plurality of output ports P2 to PN+1. Thereby, the number of selected or active output ports is denoted with M, wherein M is equal to the number L of active ports (i.e., active input and output ports) minus one (M=L−1).
As already indicated, the basic idea behind this invention is to replace the fixed resistors Rk (1≦k≦N+1) of the passive splitter 10 shown in FIG. 1 with variable controlled ones. More precisely, the L=M+1 resistors connected with the input port P1 and the selected output ports P2 to PL=M+1 will assume the value R0·(M−1)/(M+1), where M (1≦M≦N) is the number of selected (or active) output ports. The remaining N−M resistors RL+1 to RN+1, connected with the non-selected output ports PL+1 to PN+1 will ideally be open-circuit.
The classical implementation of current (voltage) controlled resistors at radio frequency (RF) employs PIN (positive intrinsic negative) diodes or field effect transistors (FET) as described in Giovanni Bianchi: Microwave and RF Engineering, Ch. 10, pp. 389-400.
FIG. 6a to 6c summarize the resulting structures. Thereby, FIG. 6a shows a block diagram of a variable resistor Rk (1≦k≦N+1), wherein FIG. 6b shows a PIN diode based (current controlled) implementation of the variable resistor R& shown in FIG. 6a, and wherein FIG. 6c shows a FET based (voltage controlled) implementation of the variable resistor Rk shown in FIG. 6a. 
The following problems are the main drawbacks of the variable resistance implementations shown in FIGS. 6a to 6c. 

    9. The resulting RF resistance could have a critical dependency on the value of the control quantity (current or voltage).
    10. The resulting RF resistance also changes with the temperature.
    11. The resulting RF resistance for a given control quantity and temperature is changing from piece to piece.
    12. The resulting network is inherently non-linear, particularly when the variable resistance is set to the intermediate states (close to its neither lowest nor highest possible impedance).


Problems 9 to 11 are in strong contrast with requirements 6 (stating that the temperature dependency of the distributing network should be reduced (or even minimized)) and requirement 8 (stating that the sensitivity of the distributing network to the manufacturing process variations and the requirement of postproduction alignment should be reduced (or even minimized)). Thereby, particularly problem 10 is in strong contrast with requirement 6.
Moreover, problem 12 tends to prevent the achievement of requirement 7 (stating that the linearity of the distributing network should be increased (or even maximized)).
These consideration suggest the implementation of “digitally” controlled variable resistors, using the schemes of FIGS. 7a to 7c. The switching elements of FIGS. 7a to 7c can be realized with either PIN diodes or FETs, with circuit solutions of the type shown in FIG. 4a or 4b respectively. The peculiarity in the cases of FIGS. 7b and 7c is that the semiconductor devices (PIN diode or FET) is not used at its intermediate resistance, but only at the extreme states, i.e., ideally open or short circuit. That solution removes the problem 9 and strongly reduces problems 10, 11, and 12. Indeed PIN (FET) need a driving current (voltage) above or below given limits for the minimum or maximum resistance status. Moreover, non-linearity, temperature dependency, and parameter variations from piece to piece are typically much smaller in the extreme than in the intermediate impedance regions.
FIG. 7a shows a block diagram of a variable resistor according to an embodiment of the present invention. The variable resistor Rk shown in FIG. 7a may be used for implementing the variable resistors R1 to RN+1 of the switchable signal routing circuit 100 shown in FIG. 5, wherein k is a natural number greater than or equal to one, and smaller than or equal to N+1 (1≦k≦N+1).
FIG. 7b shows a block diagram of an implementation of the variable resistor Rk shown in FIG. 7a, according to an embodiment of the present invention.
The variable resistor Rk shown in FIG. 7b can be connected between the common node 102 and one of the plurality of ports P1 to PN+1. Thus, the switchable signal routing circuit 100 may comprise a plurality of the variable resistors Rk connected between the plurality of ports P1 to PN+1 and the common node 102.
Each of the variable resistors Rk can comprise a switch SW0 in order to disconnect the respective port when it is in the inactive state from the common node 102. Note that although shown in FIG. 7b as being part of the switchable resistor Rk, the switch SW0 may also be implemented externally to the variable resistor Rk. In that case, the switch SW0 may be connected in series with the variable resistor Rk between the common node 102 and the respective port, in order to disconnect the port when it is in inactive state from the common node 102 (and to connect the port when it is in an active state to the common node).
Moreover, each variable resistor Rk can comprise a plurality of switchable resistor units 1041 to 104N−1 connected in series, wherein the switchable resistor units 1041 to 104N−1 are switchable between active and inactive.
Note that a resistor unit may be in its active state when its resistance is being effective, where the switchable resistor unit may be in its inactive state when its resistance is being ineffective, e.g. bypassed.
The plurality of switchable resistor units 1041 to 104N−1 may comprise different resistance values, wherein the switchable signal routing circuit 100 can be configured to set the resistance value of the respective variable resistor Rk by selectively activating one or more respective resistor units 1041 to 104N−1.
Each of the plurality of switchable resistor units 1041 to 104N−1 may comprise a parallel connection of a resistor element and a switch.
As indicated in FIG. 7b, each variable resistor Rk of the plurality of variable resistors R1 to RN+1 can comprise N switchable resistor units 1041 to 104N−1, wherein the resistance value Rj of the j-th switchable resistor unit of the N switchable resistor units 1041 to 104N−1 is given within a tolerance of ±10% (or 5%, or 3%, or 1%) by the formula:




  
    
      
        
          R
          j
        
        =
        
          
            R
            0
          
          ⁢
          
            
              j
              -
              1
            
            
              j
              +
              1
            
          
          ⁢
          
            
          
          ⁢
          
            (
            
              1
              ≤
              j
              ≤
              N
            
            )
          
        
      
    
    
      
        (
        6
        )
      
    
  




wherein j is an index of the switchable resistor unit 1041 to 104N−1, wherein N is a number of ports P1 to NN+1 of the switchable signal routing circuit 100 minus one, and wherein R0 is a reference impedance, such as 50Ω (or 60Ω, or 70Ω, or 110Ω).

Thereby, the switchable signal routing circuit 100 can be configured to activate the switchable resistor unit 104j having the index j=M=L−1 and to deactivate the other switchable resistor units.
In other words, the solution of FIG. 7b comprises N+1 switching elements SW1 to SWN bypassing N resistors The 0th switching element, denoted with SW0, can be used to prevent the variable resistance structure (which is anyway terminated with R0 at the respective output port when its inactive, or at the terminal of the variable resistor connected to the respective inactive output port) to load the resistor common node 102, when the output port corresponding to the resistance itself is not transmitting. The remaining N switching elements are all short-circuited but one, which is SWj=M if M output ports are selected (1≦M≦N) to transmit. In the special case of one single selected output port (M=1), all the switching elements of the resistors relative to that port and to the input are short circuited, while all the others are open-circuited.
A positive side-effect of the switch SW0 is that the non selected output is (at least ideally) now isolated from the splitter. Therefore, the corresponding output SPST switch 22 does not need to be absorptive on the splitter side any more, i.e., SWA or SWD in FIG. 4a or 4b can be removed, together with the associated R0. This will simplify the structure while simultaneously improving insertion and return-loss.
Note that the resistance distribution of FIG. 7b is not unique. Other possible implementations with different switch actuation strategies are possible, such as R0·1⁄3 for SW1, R0·( 2/4−1⁄3) for SW2, R0·(3⁄5− 2/4−1⁄3) for SW3, and so on. In this case, all the M switching elements from SW1 to SWM will be open, while the remaining N−M switching elements from SWM+1 to SWN will be short-circuited.
FIG. 7c shows a block diagram of an implementation of the variable resistor Rk shown in FIG. 7a, according to a further embodiment of the present invention.
Each variable resistor Rk can comprise a plurality of switchable resistor units 1041 to 104N−1 connected in series, wherein the switchable resistor units 1041 to 104N−1 are switchable between active and inactive.
Note that a resistor unit may be in its active state when its resistance is being effective, where the switchable resistor unit may be in its inactive state when its resistance is being ineffective, e.g. bypassed.
The plurality of switchable resistor units 1041 to 104N−1 may comprise different resistance values, wherein the switchable signal routing circuit 100 can be configured to set the resistance value of the respective variable resistor Rk by selectively activating one or more respective resistor units 1041 to 104N−1.
Each of the plurality of switchable resistor units 1041 to 104N−1 may comprise a parallel connection of a resistor element and a switch.
As shown in FIG. 7c, each resistor Rk of the variable resistors R1 to RN+1 can comprise Q switchable resistor units 1041 to 104Q, wherein the resistance value Ri of the i-th switchable resistor unit of the Q switchable resistor 1041 to 104Q units is given within a tolerance of ±10% (or 5%, or 7%, or 10%) by the formula:

Ri=2I-1RX(1≦I≦Q)  (7)

wherein i is an index of the switchable resistor unit, wherein Q=log2N, wherein N is a number of ports P1 to PN+1 of the switchable signal routing 100 circuit minus one, and wherein Rx is a given impedance.

In other words, the various resistance values that may be used for different numbers of selected output ports can be approximated with the binary structure shown in FIG. 7c. This simplifies the structure, although at the expense of a lower accuracy in the realized resistance value, at least in the ideal case.
In practice, the consistently lower number of switching elements Q=└log2(N)┘ gives much lower RF parasitics, which probably overcompensates the lack of accuracy.
FIG. 7d shows a block diagram shows a block diagram of an implementation of the variable resistor Rk shown in FIG. 7a, according to a further embodiment of the present invention.
Moreover, each variable resistor Rk can comprise a plurality of switchable resistor units 1041 to 104N−1 connected in parallel, wherein the switchable resistor units 1041 to 104N−1 are switchable between active and inactive.
Note that a resistor unit may be in its active state when its resistance is being effective, where the switchable resistor unit may be in its inactive state when its resistance is being ineffective, e.g. bypassed.
The plurality of switchable resistor units 1041 to 104N−1 may comprise different resistance values, wherein the switchable signal routing circuit 100 can be configured to set the resistance value of the respective variable resistor Rk by selectively activating one or more respective resistor units 1041 to 104N−1.
Each of the plurality of switchable resistor units 1041 to 104N−1 may comprise a series connection of a resistor element and a switch.
As indicated in FIG. 74, each variable resistor Rk of the plurality of variable resistors R1 to RN+1 can comprise N switchable resistor units 1041 to 104N−1, wherein the resistance value Rj of the j-th switchable resistor unit of the N switchable resistor units 1041 to 104N−1 is given within a tolerance of ±10% (or 5%, or 3%, or 1%) by the formula:




  
    
      
        
          R
          j
        
        =
        
          
            R
            0
          
          ⁢
          
            
              j
              -
              1
            
            
              j
              +
              1
            
          
          ⁢
          
            
          
          ⁢
          
            (
            
              1
              ≤
              j
              ≤
              N
            
            )
          
        
      
    
    
      
        (
        6
        )
      
    
  




wherein j is an index of the switchable resistor unit 1041 to 104N−1, wherein N is a number of ports P1 to PN+1 of the switchable signal muting circuit 100 minus one, and wherein R0 is a reference impedance, such as 50Ω (or 60Ω, or 70Ω, or 110Ω).

Thereby, the switchable signal routing circuit 100 can be configured to activate the switchable resistor unit 104j having the index j=M=L−1 and to deactivate the other switchable resistor units.
FIG. 7e shows a block diagram of an implementation of the variable resistor Rk shown in FIG. 7a, according to a further embodiment of the present invention.
Each variable resistor Rk can comprise a plurality of switchable resistor units 1041 to 104N−1 connected in parallel, wherein the switchable resistor units 1041 to 104N−1 are switchable between active and inactive.
Note that a resistor unit may be in its active state when its resistance is being effective, where the switchable resistor unit may be in its inactive state when its resistance is being ineffective, e.g. bypassed.
The plurality of switchable resistor units 1041 to 104N−1 may comprise different resistance values, wherein the switchable signal routing circuit 100 can be configured to set the resistance value of the respective variable resistor Rk by selectively activating one or more respective resistor units 1041 to 104N−1.
Each of the plurality of switchable resistor units 1041 to 104N−1 may comprise a series connection of a resistor element and a switch.
As shown in FIG. 7e, each resistor Rk of the variable resistors R1 to RN+1 can comprise Q switchable resistor units 1041 to 104Q, wherein the resistance value Ri of the i-th switchable resistor unit of the Q switchable resistor 1041 to 104Q units is given within a tolerance of ±10% (or 5%, or 7%, or 10%) by the formula:

Ri=2I-1RX(1≦I≦Q)  (7)

wherein i is an index of the switchable resistor unit, wherein Q=log2N, wherein N is a number of ports P1 to PN+1 of the switchable signal routing 100 circuit minus one, and wherein Rx is a given impedance.

To summarize, the circuit implementation of FIG. 7b uses N+1 series cells each comprising one FET with one shunt resistor (the apparent exception is SW0, which has no shunt resistor but that cell can be considered as one FET with infinite resistance in shunt). A totally (at least by principle) equivalent implementation is shown in FIG. 7d. The network in FIG. 7d can realize exactly the same resistance values [0, R0/3, . . . R0·(N−1)/(N+1), ∞] as the one in FIG. 7b, just with a different actuation strategy of the switching FETs.
Similarly, the circuit of FIG. 7c can be also implemented as the one of FIG. 7e, i.e. the latter also realizes 20 different resistance values (plus of course open and short-circuit). The calculation strategy is identical to the case of the network in FIG. 7c, just with different resistance values in the various states (Remember that the networks of FIGS. 7c and 7d as well do not exactly realize the resistance that may be used in the various states. Both give approximated values, the values of the two networks are not the same, but the resulting reflection coefficients (9) could be made identical for the two networks).
FIG. 8 lists in a table the resistance values which the variable resistor Rk shown in FIG. 7b and the variable resistor Rk shown in FIG. 7c can provide. Thereby, the structure shown in FIG. 7b realizes the resistance values listed in the first row of the table shown in FIG. 8, wherein the structure shown in FIG. 5c realizes the resistance values listed in the second row of the table shown in FIG. 8.
FIG. 9 compares in a table the number N of resistor units 1041 to 104N which may use the variable resistor Rk shown in FIG. 7b and the number Q of resistor units 1041 to 104Q which may use the variable resistor Rk shown in FIG. 7c for providing the same number of different resistance values.
In other words, FIG. 9 lists in a table the number of switching elements that may be used for the exact (FIG. 7b) and binary (FIG. 7c) realization on the first and second column, respectively.
In the following, the component values (or resistance values) realized with the binary digitally variable resistor Rk shown in FIG. 7c are discussed. The resistance of any resistor Rk=R(M) assumes the value among the 2Q possible ones, i.e., 0, Rx, 2·Rx, 3·Rx, . . . (2Q−1)·RX. The resistance presented at the input port P1 is:




  
    
      
        
          R
          IN
        
        =
        
          
            R
            
              (
              M
              )
            
          
          +
          
            
              
                R
                
                  (
                  M
                  )
                
              
              +
              
                R
                0
              
            
            M
          
        
      
    
    
      
        (
        8
        )
      
    
  




The resulting reflection coefficient is:




  
    
      
        
          ρ
          IN
        
        =
        
          
            
              
                R
                IN
              
              -
              
                R
                0
              
            
            
              
                R
                IN
              
              +
              
                R
                0
              
            
          
          =
          
            
              
                
                  R
                  
                    (
                    M
                    )
                  
                
                +
                
                  
                    
                      R
                      
                        (
                        M
                        )
                      
                    
                    +
                    
                      R
                      0
                    
                  
                  M
                
                -
                
                  R
                  0
                
              
              
                
                  R
                  
                    (
                    M
                    )
                  
                
                +
                
                  
                    
                      R
                      
                        (
                        M
                        )
                      
                    
                    +
                    
                      R
                      0
                    
                  
                  M
                
                +
                
                  R
                  0
                
              
            
            =
            
              
                
                  
                    (
                    
                      1
                      +
                      M
                    
                    )
                  
                  ⁢
                  
                    
                      R
                      
                        (
                        M
                        )
                      
                    
                    
                      R
                      0
                    
                  
                
                +
                1
                -
                M
              
              
                
                  
                    (
                    
                      1
                      +
                      M
                    
                    )
                  
                  ⁢
                  
                    
                      R
                      
                        (
                        M
                        )
                      
                    
                    
                      R
                      0
                    
                  
                
                +
                1
                +
                M
              
            
          
        
      
    
    
      
        (
        9
        )
      
    
  




A possible design method may comprise choosing the bit resistance RX and N among the 2Q available states of the binary stepped variable resistor Rk, in order to minimize the amplitude of the reflection coefficient (8). To that regard, one possible degree of freedom is the value to consider, i.e., the worst case among the different number of selected ports, or the average between the values, er different combinations.
For example, if N=4 then the optimum bit resistance for the best worst-case return-loss is RX a 12.1Ω, which gives a worst case return-loss of about 22.67 dB for M=2.
In the special (but frequent) case of an integer power of two number of outputs (N=2N_INTEGER, where N_INTEGER is an integer number, for instance N=2, 4, 8, . . . ) the number of available states is not larger than the one that may be used. In that case, the design procedure is limited to the choice of RX, unless, more stages are introduced in the binary stepped variable resistor, in order to gain flexibility and better impedance matching.
To summarize, the above described switchable signal routing circuit 100 (linear N+1 port network) can, but is not limited to, split a signal present at a common input port to M selectable output ports, or to combine signals present at M selectable input ports to a common output port. Thereby, the switchable signal routing circuit 100 fulfills (at least some) of the following requirements (or constraints):

    1. The switchable signal routing circuit is broadband, (ideally from DC to infinite frequency). The lower frequency limit of the circuit can be DC (0 Hz). The upper frequency limit can be ideally infinite (in the case of ideal FET). A practical value for the maximum usable frequency results from the combination of several factors, i.e. number of ports (N+1 in denotation herein, the higher N the lower the maximum frequency), acceptable performance degradation respect to the ideal case. FET technology (i.e. the real FETs behaves not as ideal controlled switches, rather they present finite on resistance, parasitic reactance in both ON and OFF states), type of assembly technology (which also adds parasitic reactance). Typical numbers could be N=4, Gallium Arsenide Monolithic Microwave Integrated Circuit (Ga—As MMIC) technology, 1-2 dB of degradation on the insertion loss at the highest frequency [compared to the ideal case of equation (2), which gives s21=0.25 i.e. −12 dB], maximum frequency=10 GHz.
    2. Each of the N output ports P2 to PN+1 can be individually selected as transmitting or not transmitting one.
    3. The input port P1 and all of the M output ports P2 to PM+1 selected to transmit can be impedance matched.
    4. Not only the M transmitting ports P2 to PM+1 but also the remaining output ports PM+2 to PN+1 can be impedance matched, i.e. all of the N+1 ports of the device 100 can be impedance matched, independently of which port(s) is(are) transmitting.
    5. The insertion loss of the switchable signal routing circuit 100 is reduced (or even minimized).
    6. The temperature dependency of the switchable signal routing circuit 100 is reduced (or even minimized).
    7. The linearity of the switchable signal routing circuit 100 is increased (or even maximized).
    8. The sensitivity of the switchable signal muting circuit to the manufacturing process variations and the requirement of post-production alignment is reduced (or even minimized).


Further embodiments provide a method for operating a switchable signal routing circuit for routing a signal between at least one input port and at least one output port, wherein the ports are connected by means of variable resistors to a common node. The method comprises setting resistance values of the variable resistors in dependence on a number of active ports.
Thereby, the method may comprise varying the number of active ports, and automatically setting the resistance values of the variable resistors in response to the varying of the number of active ports.
Further embodiments provide a variable minimum-insertion loss power combiner structure (switchable signal routing circuit), i.e. FIG. 1 or FIG. 2 with fixed resistors R1 to RN+1 replaced with variable controlled ones. The variable resistors R1 to RN+1 can be implemented as shown in FIG. 7b or 7c. 
Although some aspects have been described in the context of an apparatus, it is clear that these aspects also represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Analogously, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus. Some or all of the method steps may be executed by (or using) a hardware apparatus, like for example, a microprocessor, a programmable computer or an electronic circuit. In some embodiments, some one or more of the most important method steps may be executed by such an apparatus.
Depending on certain implementation requirements, embodiments of the invention can be implemented in hardware or in software. The implementation can be performed using a digital storage medium, for example a floppy disk, a DVD, a Blu-Ray, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, having electronically readable control signals stored thereon, which cooperate (or are capable of cooperating) with a programmable computer system such that the respective method is performed. Therefore, the digital storage medium may be computer readable.
Some embodiments according to the invention comprise a data carrier having electronically readable control signals, which are capable of cooperating with a programmable computer system, such that one of the methods described herein is performed.
Generally, embodiments of the present invention can be implemented as a computer program product with a program code, the program code being operative for performing one of the methods when the computer program product runs on a computer. The program code may for example be stored on a machine readable carrier.
Other embodiments comprise the computer program for performing one of the methods described herein, stored on a machine readable carrier.
In other words, an embodiment of the inventive method is, therefore, a computer program having a program code for performing one of the methods described herein, when the computer program runs on a computer.
A further embodiment of the inventive methods is, therefore, a data carrier (or a digital storage medium, or a computer-readable medium) comprising, recorded thereon, the computer program for performing one of the methods described herein. The data carrier, the digital storage medium or the recorded medium are typically tangible and/or non-transitionary.
A further embodiment of the inventive method is, therefore, a data stream or a sequence of signals representing the computer program for performing one of the methods described herein. The data stream or the sequence of signals may for example be configured to be transferred via a data communication connection, for example via the Internet.
A further embodiment comprises a processing means, for example a computer, or a programmable logic device, configured to or adapted to perform one of the methods described herein.
A further embodiment comprises a computer having installed thereon the computer program for performing one of the methods described herein.
A further embodiment according to the invention comprises an apparatus or a system configured to transfer (for example, electronically or optically) a computer program for performing one of the methods described herein to a receiver. The receiver may, for example, be a computer, a mobile device, a memory device or the like. The apparatus or system may, for example, comprise a file server for transferring the computer program to the receiver.
In some embodiments, a programmable logic device (for example a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor in order to perform one of the methods described herein. Generally, the methods are advantageously performed by any hardware apparatus.
While this invention has been described in terms of several embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and compositions of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations and equivalents as fall within the true spirit and scope of the present invention.

## Claims

1. A switchable signal routing circuit comprising:
a plurality of ports including at least one input port and at least one output port;
a common node; and
a plurality of variable resistors,
wherein each of the variable resistors is coupled between a respective one of the plurality of ports and the common node, and
wherein the switchable signal routing circuit is configured to set resistance values of the variable resistors in dependence on a number of active ones of the plurality of ports, and wherein the switchable signal routing circuit is configured to terminate inactive ports with a termination resistor.

2. The switchable signal routing circuit according to claim 1, wherein the switchable signal routing circuit is configured to receive a control information describing the number of active ports and to automatically set the resistance values of the variable resistors in response to the control information.

3. The switchable signal routing circuit according to claim 1, wherein the switchable signal routing circuit is configured to disconnect the inactive ports from the common node.

4. The switchable signal routing circuit according to claim 3, wherein the switchable signal routing circuit comprises switches connected in series with the variable resistors between the common node and the ports, in order to disconnect the inactive ports from the common node.

5. The switchable signal routing circuit according to claim 1, wherein each of the variable resistors comprises a plurality of switchable resistor units connected in series, wherein the switchable resistor units are switchable between active and inactive.

6. The switchable signal routing circuit according to claim 5, wherein each of the plurality of switchable resistor units comprises a parallel connection of a resistor element and a switch.

7. The switchable signal routing circuit according to claim 1, wherein each of the variable resistors comprises a plurality of switchable resistor units connected in parallel, wherein the switchable resistor units are switchable between active and inactive.

8. The switchable signal routing circuit according to claim 7, wherein each of the plurality of switchable resistor units comprises a series connection of a resistor element and a switch.

9. The switchable signal routing circuit according to claim 5, wherein the plurality of switchable resistor units comprise different resistance values, wherein the switchable signal routing circuit is configured to set the resistance value of the respective variable resistor of the plurality of variable resistors by selectively activating one or more respective resistor units.

10. The switchable signal routing circuit according to claim 1, wherein the switchable signal routing circuit is configured to set the resistance value of each of the variable resistors within a tolerance of ±10% based on the formula:




  R
  =
  
    
      R
      0
    
    ⁢
    
      
        M
        -
        1
      
      
        M
        +
        1
      
    
  



wherein M=L−1, wherein L is the number of active ports, and wherein R0 is a reference impedance.

11. The switchable signal routing circuit according to claim 5, wherein each of the variable resistors comprises N switchable resistor units, wherein the resistance value Rj of the j-th switchable resistor unit of the N switchable resistor units is given within a tolerance of ±10% by the formula:




  
    R
    j
  
  =
  
    
      R
      0
    
    ⁢
    
      
        j
        -
        1
      
      
        j
        +
        1
      
    
    ⁢
    
      
    
    ⁢
    
      (
      
        1
        ≤
        j
        ≤
        N
      
      )
    
  



wherein j is an index of the switchable resistor unit, wherein N is a number of ports of the switchable signal routing circuit minus one, and wherein R0 is a reference impedance.

12. The switchable signal routing circuit according to claim 11, wherein the switchable signal routing circuit is configured to activate the switchable resistor unit comprising the index j=L−1 and to deactivate the other switchable resistor units, wherein L is the number of active ports.

13. The switchable signal routing circuit according to claim 5, wherein each of the variable resistors comprises Q switchable resistor units, wherein the resistance value Ri of the i-th switchable resistor unit of the Q switchable resistor units is given within a tolerance of ±10% by the formula:


Ri=2I-1Rx(1≦I≦Q)

wherein i is an index of the switchable resistor unit, wherein Q=log2N, wherein N is a number of ports of the switchable signal routing circuit minus one, and wherein Rx is a given impedance.

14. The switchable signal routing circuit according to claim 1, wherein the switchable signal routing circuit comprises one input port and a plurality of output ports.

15. The switchable signal routing circuit according to claim 1, wherein the switchable signal routing circuit comprises a plurality of input ports and one output port.

16. A method for operating a switchable signal routing circuit for routing a signal between at least one input port and at least one output port, the method comprising:
coupling a plurality of ports together each through a respective one of a plurality of variable resistors, wherein a number of the plurality of ports are active and any other ports are inactive, wherein the switchable signal routing circuit is configured to terminate inactive ports with a termination resistor; and
setting resistance values of the plurality of variable resistors in dependence on the number of active ports.

17. The method according to claim 16, wherein the method comprises:
varying the number of active ports; and
automatically setting the resistance values of the variable resistors in response to the varying of the number of active ports.

18. A computer program comprising a program code for performing, when running on a computer or microprocessor, a method according to claim 16.

19. A device comprising:
a plurality of ports;
a common node;
a plurality of variable resistors each coupled between a respective one of the plurality of ports and the common node, wherein each variable resistor includes a plurality of switchable resistor units adapted to selectively set a resistance value of the variable resistors in dependence on a number of active ones of the plurality of ports in response to control information; and
a termination resistor that terminates inactive ports of the plurality of ports.